CN115828805A

CN115828805A - Method, apparatus and storage medium for split logic system design

Info

Publication number: CN115828805A
Application number: CN202211295804.XA
Authority: CN
Inventors: 齐正华; 请求不公布姓名
Original assignee: Core Huazhang Technology Beijing Co ltd
Current assignee: Core Huazhang Technology Beijing Co ltd
Priority date: 2022-10-21
Filing date: 2022-10-21
Publication date: 2023-03-21

Abstract

The application provides a method, equipment and a storage medium for designing a split logic system. The method comprises the following steps: obtaining a description of the logic system design, the logic system design comprising a plurality of modules; analyzing the description of the logic system design to determine a connectivity relationship and a first dependency relationship of the plurality of modules, wherein the connectivity relationship comprises an attribution relationship between the plurality of modules, and the first dependency relationship comprises a reference relationship between the plurality of modules; partitioning the logical system design into a plurality of partitions according to the connectivity relationships and the first dependency relationships, wherein each of the plurality of partitions includes at least one of the plurality of modules; and outputting a description of the plurality of partitions.

Description

Method, apparatus and storage medium for split logic system design

Technical Field

The present application relates to the field of computer software technologies, and in particular, to a method, a device, and a storage medium for partitioning a logic system design.

Background

In the field of verification of integrated circuits, simulation may refer to compiling a logic system design and then running it using a simulation tool to perform simulation tests on various functions of the design. The design may be, for example, a design for an Application Specific Integrated Circuit (ASIC) or a System-On-Chip (SOC) for a Specific Application. Therefore, a Design to be tested or verified in simulation may also be referred to as a Design Under Test (DUT). As the scale of logic system designs becomes larger, the compilation time of the designs by simulation tools becomes longer.

In the field of software systems, split compilation is ubiquitous. In general, a compiler may compile different source code files in parallel. For example, A.c, b.c, C.c, and D.c are compiled separately and then recombined into a complete binary file. However, for chip design, the compiler cannot directly divide the design by design files due to the physical connections between hardware modules and the virtual signal connections between the DUT and the TB.

Therefore, how to divide the chip design to speed up the compiling of the chip design is an urgent problem to be solved.

Disclosure of Invention

A first aspect of the present application provides a method of partitioning a logic system design, the method comprising: obtaining a description of the logic system design, the logic system design comprising a plurality of modules; analyzing the description of the logic system design to determine a connectivity relationship and a first dependency relationship of the plurality of modules, wherein the connectivity relationship comprises an affiliation relationship between the plurality of modules and the first dependency relationship comprises a reference relationship between the plurality of modules; partitioning the logical system design into a plurality of partitions according to the connectivity relationships and the first dependencies, wherein each of the plurality of partitions includes at least one of the plurality of modules; and outputting a description of the plurality of partitions.

A second aspect of the present application provides an electronic device comprising: a memory for storing a set of instructions; and at least one processor configured to execute the set of instructions to cause the electronic device to perform the method of the first aspect.

A third aspect of the application provides a non-transitory computer readable storage medium storing a set of instructions of a computer for, when executed, causing the computer to perform the method of the first aspect.

The method, the device and the storage medium for partitioning the logic system design provided by the application partition the logic system design through the communication relation and the dependency relation in the logic system design. In this way, the compiler can compile the design in the partitioned multiple partitions in parallel, thereby speeding up the compilation of the logic system design.

Drawings

In order to more clearly illustrate the technical solutions in the present application or related technologies, the drawings required for the embodiments or related technologies in the following description are briefly introduced, and it is obvious that the drawings in the following description are only the embodiments of the present application, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without creative efforts.

Fig. 1 shows a schematic structural diagram of an exemplary electronic device according to an embodiment of the present application.

FIG. 2A shows a schematic diagram of an exemplary simulation system according to an embodiment of the present application.

FIG. 2B illustrates a schematic diagram of an exemplary compiler, according to an embodiment of the present application.

FIG. 3A shows a schematic diagram of an exemplary segmentation design in accordance with an embodiment of the present application.

FIG. 3B shows a schematic diagram of another exemplary segmentation design in accordance with an embodiment of the present application.

FIG. 4 shows a schematic diagram of a description of an exemplary partition according to an embodiment of the present application.

FIG. 5 illustrates a flow diagram of a method of an exemplary split logic system design in accordance with an embodiment of the present application.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is further described in detail below with reference to the accompanying drawings in combination with specific embodiments.

It is to be noted that, unless otherwise defined, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this application belongs. As used in this application, the terms "first," "second," and the like, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. The word "comprising" and similar words are intended to mean that the elements or items listed before they occur in the word "comprise" and the equivalents thereof, without excluding other elements or items. "connected," and like terms, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

Fig. 1 shows a schematic structural diagram of an electronic device 100 according to an embodiment of the present application. The electronic device 100 may be an electronic device running a simulation system. As shown in fig. 1, the electronic device 100 may include: a processor 102, a memory 104, a network interface 106, a peripheral interface 108, and a bus 110. Wherein the processor 102, the memory 104, the network interface 106, and the peripheral interface 108 are communicatively coupled to each other within the electronic device via a bus 110.

The processor 102 may be a Central Processing Unit (CPU), an image processor, a neural Network Processor (NPU), a Microcontroller (MCU), a programmable logic device, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), or one or more Integrated circuits. Processor 102 may be used to perform functions associated with the techniques described herein. In some embodiments, processor 102 may also include multiple processors integrated into a single logic component. As shown in FIG. 1, the processor 102 may include a plurality of processors 102a, 102b, and 102c.

The memory 104 may be configured to store data (e.g., a set of instructions, computer code, intermediate data, etc.). In some embodiments, the simulation test system for simulating a test design may be a computer program stored in memory 104. As shown in fig. 1, the data stored by the memory may include program instructions (e.g., for implementing the methods of the split logic system design of the present application) as well as data to be processed (e.g., the memory may store temporary code generated during the compilation process). The processor 102 may also access memory-stored program instructions and data and execute the program instructions to operate on the data to be processed. The memory 104 may include volatile memory devices or non-volatile memory devices. In some embodiments, the memory 104 may include Random Access Memory (RAM), read Only Memory (ROM), optical disks, magnetic disks, hard disks, solid State Disks (SSDs), flash memory, memory sticks, and the like.

The network interface 106 may be configured to provide communications with other external devices to the electronic device 100 via a network. The network may be any wired or wireless network capable of transmitting and receiving data. For example, the network may be a wired network, a local wireless network (e.g., bluetooth, wiFi, near Field Communication (NFC), etc.), a cellular network, the internet, or a combination of the above. It is to be understood that the type of network is not limited to the specific examples described above. In some embodiments, network interface 106 may include any combination of any number of Network Interface Controllers (NICs), radio frequency modules, transceivers, modems, routers, gateways, adapters, cellular network chips, and the like.

The peripheral interface 108 may be configured to connect the electronic device 100 with one or more peripheral devices to enable input and output of information. For example, the peripheral devices may include input devices such as keyboards, mice, touch pads, touch screens, microphones, various sensors, and output devices such as displays, speakers, vibrators, indicator lights, and the like.

The bus 110 may be configured to transfer information between various components of the electronic device 100 (e.g., the processor 102, the memory 104, the network interface 106, and the peripheral interface 108), such as an internal bus (e.g., a processor-memory bus), an external bus (a USB port, a PCI-E bus), and so forth.

It should be noted that although the electronic device architecture only shows the processor 102, the memory 104, the network interface 106, the peripheral interface 108 and the bus 110, in a specific implementation, the electronic device architecture may also include other components necessary for normal operation. In addition, those skilled in the art will appreciate that the above-described electronic device architecture may also include only the components necessary to implement the embodiments of the present application, and need not include all of the components shown in the figures.

FIG. 2A shows a schematic diagram of an exemplary simulation tool 200 according to an embodiment of the present disclosure. The simulation tool 200 may be a computer program running on the electronic device 100.

In the field of chip design, a design may be simulated using a simulation tool. The simulation tool may be, for example, a GalaxSim simulation tool available from Chihua chapter science and technology, inc. The exemplary simulation tool 200 shown in FIG. 2A may include a compiler 210 and a simulator 220. Compiler 210 can receive source code 204 (e.g., a hardware description language such as VHDL, verilog, systemveilog, etc.) and compile into execution code 206 (e.g., machine code, assembly code, software code, etc.). It is understood that the description of the logic system design may be described in a Hardware Description Language (HDL), a Register Transfer Level (RTL) language, binary code, assembly code, or machine code, among others. The simulator 220 may simulate according to the execution code 206 and output the simulation result 208. For example, simulation tool 200 may output simulation results 208 to an output device (e.g., displayed on a display) via peripheral interface 108 of FIG. 1.

Fig. 2B is a diagram of an exemplary compiler 210 according to an embodiment of the present application. As shown in FIG. 2B, compiler 210 may include a front end 212, a middle end 214, and a back end 216.

Front end 212 may be used to analyze the lexical, grammatical, semantic meaning of the source code according to a particular source language.

After lexical, grammatical, and semantic analysis of the source code is complete, the middle-end 214 may convert the source code into an intermediate representation (or intermediate code) and may optimize the intermediate representation. An intermediate language (intermediate code) is a syntax-oriented, equivalent internal representation code that is easily translated into source code for a target program. The intelligibility and the ease of generating the execution code are intermediate between the source code and the execution code. Commonly used intermediate codes are represented by inverse wave, quaternary, ternary, tree, etc. For example, the middle end 214 may remove useless code, remove inaccessible code, clear unused variables, and the like. The optimization may include machine dependent optimization and machine independent optimization. Among other things, machine-related optimization, for example, may be optimization of a Testbench (TB), and may utilize some of the Testbench's characteristics to assist in the optimization. The machine-independent optimization may be, for example, an optimization of a Design Under Test (DUT). The optimized intermediate representation may then be passed to the back end 126 for further processing.

The back end 216 may further optimize the intermediate representation according to the architecture of the target processor (e.g., processor 102 of FIG. 1) and generate the execution code. Typically, the executing code is machine code.

It is to be understood that the structure of the compiler is not limited to the example of fig. 2B. For example, front end 212 and middle end 214 may be collectively referred to as the front end of a compiler.

The compiler 210 may generate execution code based on the computer code to be compiled. The computer code to be compiled may also be referred to as source code, such as a written logic system design. Typically, the source language in which the source code is written is a high level programming language. The high-level programming language may be a software programming language or a hardware programming language as described above. The execution code may be, for example, assembly code, machine code, or the like. In general, the compiler 210 may be stored in the memory 104 shown in FIG. 1 and executed by the processor 102 to compile a logic system design into executable code. Compiler 210 may translate the description of the logic system design from a high-level language description (e.g., HDL language) to a lower-level description (e.g., RTL language or binary code) so that the underlying hardware may run the logic system design.

As described above, it takes a relatively long compiling time to compile a large-scale logic system design. With the scale of logic system design getting larger and larger, the compile time becomes too long. In the technical field of traditional software, split compilation is a method for improving compilation efficiency. The time for compilation may be reduced by splitting the design and compiling the split sub-designs in parallel. However, unlike conventional software, the logic system design of the present application is essentially a chip design, and there are signal dependencies and driving relationships between multiple modules in the logic system design. This makes the partitioning techniques in the conventional software technology field unsuitable for partitioning compilation of logic system designs. How to realize the division of the logic system design under the condition of considering the hardware essence of the logic system design is an urgent problem to be solved in the industry. In order to solve the above problems, the present application provides a method for designing a partitioned logic system.

FIG. 3A shows a schematic diagram of an exemplary segmentation design 300 according to an embodiment of the present application.

The compiler 210 may obtain a Register Transfer Level (RTL) description of the logic system design. The RTL description is an abstraction level for describing the operation of synchronous digital circuits. In this description, a logic system design may include multiple modules. As shown in FIG. 3A, a logic system design may include a number of elements, such as a Top module, a TB module, a DUT module, a CPU module, a Memory Device (MEM) module, and r signals. The Top module is the uppermost module of the whole logic system design and comprises a DUT module and a TB module; the DUT module is a representation of a chip design, and the TB module is used for providing a stimulus signal to the DUT and reading a return signal of the DUT in simulation to judge whether the DUT operates according to design requirements; the DUT module further includes a MEM module and a CPU module, the MEM module further including an r signal. It is common practice for the compiler 210 to compile the entire logic system design including these multiple elements directly, which takes a relatively long time.

Compiler 210 may analyze a logic system design to determine connectivity and dependencies between modules according to its RTL level description.

Compiler 210 may analyze the logic system design in a global analysis. In the GalaxSim simulation tool of Chihua chapter, the compiler 210 can perform a global analysis by, for example, running the command line "GalaxSim-gobal _ analysis-frtl. The global analysis may be by analyzing the source code 204 of the logic system design.

Connectivity here may include affiliations between modules. Compiler 210 may distinguish between DUT modules and TB modules by analyzing code. For example, compiler 210 may distinguish a DUT module from a TB module by analyzing the number of instances (instances) in the module, which may be significantly higher than the number of instances in the TB module. Compiler 210 may also distinguish between DUT modules and TB modules by determining whether synthesizable code statements are included in the modules. In general, the DUT module may include synthesizable code statements and not non-synthesizable code statements. For example, the "initial block" statement is not included in the DUT module. The TB module may include non-synthesizable code statements, e.g., system task $ dsiplay (), initial statements, etc. Based on the differentiated DUT modules and TB modules, the compiler 210 can determine that the DUT modules and TB modules belong to Top modules. Similarly, compiler 210 may determine that the CPU module and the MEM module are attributed to the DUT module; and compiler 210 may determine that the r signal belongs to the MEM module.

Dependencies herein may include reference relationships between modules. The compiler 210 can analyze the TB block to have a cross-module reference (XMR) pointing to the r signal. For example, an XMR described as "force top.dut.mem.r =1' b1" may be present in the TB module. In addition to referencing such references across modules, compiler 210 may also determine dependencies between modules via interface (interface), import (import), etc. information.

The compiler 210 may segment the logic system design according to the analyzed connectivity and dependency between the modules. Generally, the compiler 210 may handle the TB module and the DUT module separately. That is, the compiler 210 may divide the TB module into a first partition 301 and the DUT module into a second partition 302. The compiler 210 may divide the CPU module and the MEM module into the second partition 302 where the DUT module is located according to the connection relationship between the CPU module and the MEM module. Similarly, the compiler 210 may divide the r signal into the second partition 302 where the MEM module is located according to the connectivity relationship of the r signal belonging to the MEM module.

Generally, due to the relatively large design size of the DUT modules, no other modules may be scribed into the second partition 302. Compiler 210 may partition Top modules and TB modules into first partition 301. It is understood that compiler 210 may also divide the Top module into other partitions (not shown in fig. 3A) outside of first partition 301 and second partition 302 according to the needs of the actual compiling process.

While partitioning the logic system design, compiler 210 may preserve dependency information between the TB module and the DUT module. The dependency information may be used in a subsequent compilation integration process.

FIG. 3B illustrates a schematic diagram of another exemplary segmentation design 302 according to an embodiment of the present application.

The DUT module may be a System-on-Chip (SOC) design and may include a CPU module and a MEM module. In some embodiments, the design scale of the DUT module is quite large, so in the second partition 302 in which the DUT module is located, the compiler 210 may further divide the DUT module into a first sub-partition 3021 in which the MEM module is located and a second sub-partition 3022 in which the CPU module is located. According to the communication relationship between the r signal and the MEM module obtained by the foregoing analysis, the compiler 210 may divide the r signal into the first sub-partition 3021 where the MEM module is located.

FIG. 4 shows a schematic diagram of a description 400 of an exemplary partition according to an embodiment of the present application.

According to the dependency of XMR in the TB module pointing to the r signal, the compiler 210 may determine the dependency of the first partition 301 in which the TB module is located with respect to the second partition 302 in which the r signal is located. This dependency can be denoted as "p1_ dep". It will be appreciated that the dependency "p1_ dep" may comprise the dependency of the TB module in the first partition 301 on the r signal in the second partition 302. For example, a module dependency described as "$ xmr _ info (" top.dut.mem.r ")" may be included in the dependency "p1_ dep". Since the compiler 210 can only obtain information of the currently compiled first partition 301 and cannot obtain information of other partitions, such as the second partition 302, during the compilation process, the dependency relationship across partitions is described in a "$ xmr _ info" manner.

The compiler 210 may output the description "P1" of the first partition 301 as shown in fig. 3A according to the partition result. The description of the first partition 301 may include an RTL description of the first partition 301, denoted as "p1_ source". The description of the first partition 301 may also include the dependency "p1_ dep" of the first partition 301 on the second partition 302. Similarly, for the second partition 302, the compiler 210 may output the RTL description "p2_ source" of the second partition 302 and the dependency "p2_ dep" of the second partition 302 on other partitions.

As shown in fig. 4, compiler 210 may output a description 400 of the plurality of partitions. Where "Pn" may represent a description of the nth partition, "Pn _ source" may represent an RTL description of the nth partition, and "Pn _ dep" may represent a dependency of the nth partition on other partitions.

In this way, the compiler 210 may determine the connectivity and dependency relationship between multiple modules in the logic system design by global analysis, and further segment the logic system design. The compiler 210 may analyze the sub-designs in the partitioned partitions in parallel, speeding up the compilation.

Because the first partition 301 and the second partition 302 obtained by partitioning the logic system design have a dependency relationship, in order to ensure execution of the simulation process, the simulator 220 may reserve a linking function in the interface for linking the compiling result of the first partition 301 and the compiling result of the second partition 302 during simulation, thereby implementing complete simulation of the logic system design. That is, simulator 220 may implement the simulation of different partitions with dependencies through linking.

FIG. 5 illustrates a flow diagram of a method 500 of an exemplary split logic system design in accordance with embodiments of the present application. The method 500 may be implemented by the electronic device 100 shown in fig. 1, and more specifically, by a compiler (e.g., the compiler 210 in fig. 2A or fig. 2B) running on the electronic device 100. The method 500 may include the following steps.

At step 502, compiler 210 may obtain a description of the logic system design. In some embodiments, the description of the logic system design may include a Register Transfer Level (RTL) description. The logic system design may include a plurality of modules (e.g., top module, TB module, DUT module, CPU module, MEM module, and r-signal in fig. 3A).

At step 504, compiler 210 may analyze the description of the logic system design to determine connectivity and first dependencies of the plurality of modules. Wherein the connectivity includes affiliations between the modules (e.g., as in fig. 3A, the DUT module and the TB module are affiliated with the Top module, the CPU module and the MEM module are affiliated with the DUT module, and the r signal is affiliated with the MEM module). The first dependency may include a reference relationship between the plurality of modules (e.g., a cross-module reference (XMR) in fig. 3A where the TB module points to the r signal).

In some embodiments, compiler 210 may perform a global analysis of the logic system design based on the register transfer level description; and determining the communication relation and the first dependency relation of the plurality of modules according to the result of the global analysis. In some embodiments, the compiler 210 may run a command line (e.g., command line "gallaxsim-gobal _ analysis-frtl. List") to implement a global analysis of the logic system design. The manner of global analysis may be to analyze the source code of the logic system design (e.g., source code 204 in fig. 2A or fig. 2B).

At step 506, compiler 210 may partition the logic system design into a plurality of partitions (e.g., first partition 301 and second partition 302 in fig. 3A) according to the connectivity and the first dependency, wherein each of the plurality of partitions includes at least one of the plurality of modules (e.g., first partition 301 of fig. 3A includes a Top module and a TB module, and second partition 302 includes a DUT module, a MEM module, a CPU module, and r-signals).

In some embodiments, the plurality of modules may include a first module (e.g., the DUT module in fig. 3A). Compiler 210 may partition the first module into a plurality of sub-partitions (e.g., first sub-partition 3021 and second sub-partition 3022 in fig. 3B) based on the design size of the first module.

In some embodiments, the plurality of partitions includes a first partition (e.g., first partition 301 in fig. 3A) and a second partition (e.g., second partition 302 in fig. 3A), the first module is a Design Under Test (DUT), and the plurality of modules further includes a test platform (TB). Since the compiler 210 may generally process the DUT module and the TB module separately, each of the plurality of partitions including at least one of the plurality of modules may further include: the first partition includes the design under test; and the second partition includes the test platform.

At step 508, compiler 210 may output a description of the plurality of partitions (e.g., description 400 in FIG. 4).

In some embodiments, compiler 210 may determine an RTL description (e.g., "p1_ source" in FIG. 4) for the first partition. Compiler 210 may determine, from a first dependency of the plurality of modules (e.g., XMR of TB Module pointing to r signal in FIG. 3A), a second dependency (e.g., "p1_ dep" in FIG. 4) of the first partition (e.g., first partition 301 in FIG. 3A) on other partitions (e.g., second partition 302 in FIG. 3A) of the plurality of partitions. Compiler 210 may output the RTL description of the first partition and the second dependency.

In some embodiments, the second dependency may include a dependency of a module in the first partition (e.g., a TB module in the first partition 301 in fig. 3A) on a module in the other partition (e.g., an r signal in the second partition 302 in fig. 3A) (e.g., a module dependency described as "$ xmr _ info (" top.dut.mem.r ")).

The embodiment of the application further provides the electronic equipment. The electronic device may be the electronic device 100 of fig. 1. The electronic device 100 may include a memory for storing a set of instructions; and at least one processor configured to execute the set of instructions to cause the electronic device to perform method 500.

Embodiments of the present application also provide a non-transitory computer-readable storage medium. The non-transitory computer-readable storage medium stores a set of instructions of a computer for causing the electronic device to perform the method 500 when executed.

Some embodiments of the present application are described above. Other embodiments are within the scope of the following claims. In some cases, the actions or steps recited in the claims may be performed in a different order than in the embodiments and still achieve desirable results. In addition, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some embodiments, multitasking and parallel processing may also be possible or may be advantageous.

Those of ordinary skill in the art will understand that: the discussion of any embodiment above is meant to be exemplary only, and is not intended to intimate that the scope of the disclosure, including the claims, is limited to these examples; within the context of the present application, features from the above embodiments or from different embodiments may also be combined, steps may be implemented in any order, and there are many other variations of the different aspects of the present application as described above, which are not provided in detail for the sake of brevity.

While the present application has been described in conjunction with specific embodiments thereof, many alternatives, modifications, and variations of these embodiments will be apparent to those of ordinary skill in the art in light of the foregoing description. For example, other memory architectures, such as Dynamic RAM (DRAM), may use the discussed embodiments.

The present application is intended to embrace all such alternatives, modifications and variances which fall within the broad scope of the appended claims. Therefore, any omissions, modifications, substitutions, improvements, and the like that may be made without departing from the spirit and principles of the application are intended to be included within the scope of the application.

Claims

1. A method of partitioning a logic system design, comprising:

obtaining a description of the logic system design, the logic system design comprising a plurality of modules;

analyzing the description of the logic system design to determine a connectivity relationship and a first dependency relationship of the plurality of modules, wherein the connectivity relationship comprises an affiliation relationship between the plurality of modules and the first dependency relationship comprises a reference relationship between the plurality of modules;

partitioning the logical system design into a plurality of partitions according to the connectivity relationships and the first dependency relationships, wherein each of the plurality of partitions includes at least one of the plurality of modules; and

outputting a description of the plurality of partitions.

2. The method of claim 1, wherein the plurality of modules comprises a first module, the method further comprising:

and dividing the first module into a plurality of sub-partitions according to the design scale of the first module.

3. The method of claim 2, wherein the description of the logical system design comprises a Register Transfer Level (RTL) description.

4. The method of claim 3, wherein analyzing the description of the logic system design to determine connectivity and first dependencies for the plurality of modules further comprises:

performing global analysis on the logic system design according to the register transmission level description; and

and determining the communication relation and the first dependency relation of the plurality of modules according to the result of the global analysis.

5. The method of claim 4, wherein globally analyzing the logic system design further comprises:

a command line is run to implement a global analysis of the logic system design.

6. The method of claim 2, wherein the plurality of partitions includes a first partition and a second partition, the first module is a Design Under Test (DUT), the plurality of modules further includes a Test platform (TB), each of the plurality of partitions includes at least one of the plurality of modules further includes:

the first partition includes the design under test; and

the second partition includes the test platform.

7. The method of claim 6, wherein outputting the description of the plurality of partitions further comprises:

determining an RTL description for the first partition;

determining second dependencies of the first partition on other partitions of the plurality of partitions according to the first dependencies of the plurality of modules; and

outputting the RTL description and the second dependency of the first partition.

8. The method of claim 7, wherein the second dependencies comprise dependencies of modules in the first partition on modules in the other partitions.

9. An electronic device, comprising:

a memory for storing a set of instructions; and

at least one processor configured to execute the set of instructions to cause the electronic device to perform the method of any of claims 1-8.

10. A non-transitory computer readable storage medium storing a set of instructions of an electronic device, which when executed, cause the electronic device to perform the method of any of claims 1 to 8.