CN115827547A - Multi-core processor dynamic cache partition isolation system and control method thereof - Google Patents
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Abstract
The invention discloses a multi-core processor dynamic cache partition isolation system and a control method thereof, wherein the system comprises a multi-core processor, a shared timer interrupt module and a shared secondary cache, the shared secondary cache comprises a cache access management unit, a cache control unit, a cache access switching unit and a cache access pool, dynamic partition management is carried out on a cache channel through the cache access management unit, the cache control unit and the cache access switching unit, and a dynamically configurable shared secondary cache is provided for the multi-core processor, so that the shared secondary cache can be efficiently used by each core, inter-core cache interference is avoided, correct operation of processor tasks is ensured to a certain extent, and system performance is improved. The invention can be widely applied to the technical field of multi-core processors.
Description
Technical Field
The invention relates to the technical field of multi-core processors, in particular to a multi-core processor dynamic cache partition isolation system and a control method thereof.
Background
With the termination of moore's law, the performance increase of the computer processor single core bottleneck is limited, and current processor designs are increasingly turning to multi-core platforms. To mitigate the high latency of off-chip memory, multi-core processor system on chip (MPSoC) architectures are typically equipped with a hierarchical cache subsystem. This complex cache hierarchy can make the behavior of the shared cache difficult to predict and analyze. For example, a task running on one core may evict useful L2 cache space that may be being used by another task in another core. These inter-core cache interferences will result in an increase in miss rate and thus a corresponding performance degradation. Meanwhile, inter-core cache interference is difficult to analyze accurately, thus making it difficult to estimate the worst-case execution time of an application. Currently, most of the multi-core cache management of real-time systems uses a page coloring technology, that is, a software cache partitioning method at an operating system level, to partition a cache according to settings. However, the problem with the page coloring technique is that the coloring time overhead is large, and on one hand, the time overhead prohibits frequent changes of page colors, and on the other hand, the color change of a task with execution time smaller than the page change overhead is not cost-effective, thereby affecting the performance of the multi-core processor system.
Disclosure of Invention
In order to solve the above technical problems, the present invention aims to: the invention provides a multi-core processor dynamic cache partition isolation system and a control method thereof, which avoid inter-core cache interference and improve system performance.
The first technical scheme adopted by the invention is as follows:
a multi-core processor dynamic cache partition isolation system, comprising:
the system comprises a multi-core processor and a cache management module, wherein the multi-core processor comprises a plurality of cores, and each core is mutually independent and shares a corresponding first-level cache;
a shared timer interrupt module to synchronize and trigger tasks on each of the cores;
the shared second-level cache comprises a cache access management unit, a cache control unit, a cache access switching unit and a cache access pool, wherein the cache access pool comprises a plurality of cache accesses, the cache access management unit is used for reconfiguring the cache accesses occupied by the cache accesses according to cache instructions sent by the cores and issuing corresponding cache control signals, the cache access switching unit is used for dynamically connecting the cores and the corresponding cache accesses according to the cache control signals, and the cache control unit is used for controlling the access of the cores to the corresponding cache accesses according to the cache control signals.
Further, the shared timer interrupt module includes a global timer and decrementers corresponding to the cores one to one, where the global timer is configured to generate a trigger signal at a preset time interval, and the trigger signal causes each of the decrementers to decrement once in sequence.
Further, each core is connected with the cache path management unit, each core is provided with a corresponding code, the cache instruction comprises the code and an instruction type, and the cache path management unit identifies the corresponding core according to the code and determines the corresponding cache path configuration operation according to the instruction type.
Further, the cache control unit includes a plurality of cache controllers, and the cache controllers correspond to the cores one to one.
Further, the cache access is composed of memory blocks, and is provided with a plurality of cache partitions, and each cache partition can be occupied by a different core.
Further, the multi-core processor dynamic cache partition isolation system further comprises a cache way replacement module, and the cache way replacement module is used for selecting an occupied cache way for cache replacement when the core needs to store data in the shared secondary cache and each cache way is occupied.
Further, the cache way replacement module includes a memory and a selector, the memory is configured to store a reference way queue, the reference way queue is a queue of cache ways to be replaced formed based on a first-in first-out replacement policy, the selector is configured to select a corresponding cache way according to the reference way queue and an enable signal queue for cache replacement, the enable signal queue is generated by the cache way management unit, and the enable signal queue includes a plurality of enable signals corresponding to the cache ways to be replaced one to one.
The second technical scheme adopted by the invention is as follows:
a control method of a multi-core processor dynamic cache partition isolation system is used for being realized by the multi-core processor dynamic cache partition isolation system and comprises the following steps:
receiving a cache instruction sent by each core through a cache path management unit, reconfiguring a cache path occupied by the core according to the cache instruction, and generating a corresponding cache control signal according to a reconfiguration result;
receiving the cache control signal through a cache access switching unit, dynamically connecting each core and the corresponding cache access according to the cache control signal, and returning a connection state to the cache control unit;
and receiving the cache control signal and the connection state through the cache control unit, and starting or interrupting the access of each core to the corresponding cache access according to the cache control signal and the connection state.
Further, the system for isolating the dynamic cache partition of the multi-core processor further comprises a cache way replacement module, wherein the cache way replacement module comprises a memory and a selector, and the control method further comprises the following steps:
when the cache ways are all occupied, selecting a plurality of cache ways with the front occupation time as cache ways to be replaced through the cache way management unit, generating a reference way queue according to the cache ways to be replaced, and further storing the reference way queue in the memory;
when the cache path management unit receives the cache instruction of the core, generating a corresponding enable signal queue according to the cache instruction, and sending the enable signal queue to the selector, wherein the enable signal queue comprises a plurality of enable signals which are in one-to-one correspondence with the cache paths to be replaced;
selecting corresponding buffer path for buffer replacement through the selector according to the enable signal queue and the reference path queue
The invention has the beneficial effects that: the invention provides a multi-core processor dynamic cache partition isolation system and a control method thereof, which perform dynamic partition management on a cache channel through a cache access management unit, a cache control unit and a cache access switching unit, and provide a dynamically configurable shared secondary cache for a multi-core processor, so that the shared secondary cache can be efficiently used by each core, the inter-core cache interference is avoided, the correct operation of processor tasks is ensured to a certain extent, and the system performance is improved.
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Fig. 1 is a schematic structural diagram of a dynamic cache partition isolation system of a multi-core processor according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a shared secondary cache according to an embodiment of the present invention;
fig. 3 is a schematic partition diagram of a cache channel according to an embodiment of the present invention;
fig. 4 is a flowchart illustrating steps of a control method of a dynamic cache partition isolation system of a multi-core processor according to an embodiment of the present invention.
Detailed Description
The invention is described in further detail below with reference to the figures and the specific embodiments. For the step numbers in the following embodiments, they are set for convenience of illustration only, the order between the steps is not limited at all, and the execution order of each step in the embodiments can be adapted according to the understanding of those skilled in the art.
In the description of the present invention, the meaning of a plurality is more than two, if there are first and second described for the purpose of distinguishing technical features, but not for indicating or implying relative importance or implicitly indicating the number of indicated technical features or implicitly indicating the precedence of the indicated technical features. Furthermore, unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art. The terminology used in the description herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.
Referring to fig. 1 and 2, an embodiment of the present invention provides a system for isolating a dynamic cache partition of a multicore processor, including:
the multi-core processor comprises a plurality of cores, and each core is mutually independent and shares a corresponding first-level cache;
the shared timer interrupt module is used for synchronizing and triggering tasks on each core;
the shared second-level cache comprises a cache access management unit, a cache control unit, a cache access switching unit and a cache access pool, wherein the cache access pool comprises a plurality of cache accesses, the cache access management unit is used for reconfiguring the cache accesses occupied by the cache accesses according to cache instructions sent by the cores and sending corresponding cache control signals, the cache access switching unit is used for dynamically connecting the cores and the corresponding cache accesses according to the cache control signals, and the cache control unit is used for controlling the access of the cores to the corresponding cache accesses according to the cache control signals.
Specifically, in the embodiment of the present invention, different cores of the multi-core processor share one level of cache and are independent of each other; the shared timer interrupt module is used for synchronizing and triggering tasks on different processors; the shared level two cache is shared by multiple cores and is allocated and used by the multiple cores in a configurable dynamic cache partitioning manner.
As a further alternative, the shared timer interrupt module includes a global timer and decrementers corresponding to the cores one to one, where the global timer is configured to generate a trigger signal at a preset time interval, and the trigger signal causes each decrementer to decrement once in sequence.
In an embodiment of the invention, the shared timer interrupt module provides a dedicated decrementer for each core, decrementing based on the shared global timer, the shared global timer generating a trigger signal within a fixed time interval such that each decrementer is decremented once.
Referring to fig. 2, as a further alternative implementation, each core is connected to a cache way management unit, each core is provided with a corresponding code, a cache instruction includes a code and an instruction type, and the cache way management unit identifies the corresponding core according to the code and determines a corresponding cache way configuration operation according to the instruction type.
Specifically, the cache way management unit is configured to centrally manage the cache ways. Through the cache way management unit, each core may send commands to reconfigure the cache ways it occupies. The cache path management unit is connected to the N cores, can identify codes of different cores, and operates corresponding cache paths in the cache path pool according to different instruction types. Based on the uniform scheduling scheme, the cores do not need to inquire the state of the cache access before allocating the memory, and meanwhile, the interference among the cores of the multi-core processor is avoided.
Further as an optional implementation, the cache control unit includes a plurality of cache controllers, and the cache controllers are in one-to-one correspondence with the cores.
Specifically, the cache control unit includes a plurality of cache controllers, which are arranged in a one-to-one correspondence with the plurality of cores to ensure access of each core to the shared second-level cache.
Referring to fig. 3, as a further alternative embodiment, the cache way is composed of memory blocks, and a plurality of cache partitions are provided, and each cache partition may be occupied by a different core.
Specifically, as shown in fig. 3, which is a schematic diagram of a partition of a cache channel provided in the embodiment of the present invention, different fills in the partition indicate that memories of corresponding cache partitions are occupied by different cores. The dynamic partition cache management of the embodiment of the invention is realized based on the cache partition mode.
Referring to fig. 1, as a further optional implementation manner, the system for isolating a dynamic cache partition of a multi-core processor further includes a cache way replacement module, where the cache way replacement module is configured to select an occupied cache way for cache replacement when a core needs to store data in a shared secondary cache and each cache way is occupied.
Specifically, when new data must be stored in the shared secondary cache and all cache ways are occupied, an occupied cache way needs to be selected for replacement, and the embodiment of the invention adopts a first-in first-out replacement strategy, namely, preferentially replacing the cache channel which is occupied earliest. In order to maintain the discontinuous cache way partition occupying mode, the embodiment of the invention deploys a cache way replacing module.
Referring to fig. 1, as a further alternative embodiment, the buffer way replacement module includes a memory and a selector, where the memory is configured to store a reference way queue, the reference way queue is a queue of buffer ways to be replaced formed based on a first-in first-out replacement policy, the selector is configured to select corresponding buffer ways according to the reference way queue and an enable signal queue for buffer replacement, the enable signal queue is generated by a buffer way management unit, and the enable signal queue includes a plurality of enable signals corresponding to the buffer ways to be replaced one to one.
Specifically, the embodiment of the invention stores the cache ways to be replaced in the dual-port memory in a form of a queue based on a first-in first-out replacement strategy, and forms a reference way queue. When a cache way is released, the information in the reference way queue should be cleared as the initial reference way in one clock. To achieve this objective, the embodiment of the present invention uses the control manner of the enable signal, and constructs a 1-bit enable signal for each reference path in the reference path queue and stores the enable signal in the form of a queue to control the output of the selector, so as to achieve the purpose of resetting the reference path queue in one clock cycle.
The system structure and the operation principle of the embodiment of the present invention are explained above. It can be understood that the cache channel is dynamically partitioned and managed by the cache path management unit, the cache control unit and the cache path switching unit, and a dynamically configurable shared secondary cache is provided for the multi-core processor, so that the shared secondary cache can be efficiently used by each core, the inter-core cache interference is avoided, the correct operation of processor tasks is ensured to a certain extent, and the system performance is improved.
The following further describes embodiments of the present invention with reference to a control method.
Referring to fig. 4, an embodiment of the present invention provides a control method for a dynamic cache partition isolation system of a multi-core processor, which is implemented by the dynamic cache partition isolation system of the multi-core processor, and includes the following steps:
s101, receiving a cache instruction sent by each core through a cache path management unit, reconfiguring a cache path occupied by the core according to the cache instruction, and generating a corresponding cache control signal according to a reconfiguration result;
s102, receiving a cache control signal through a cache access switching unit, dynamically connecting each core and a corresponding cache access according to the cache control signal, and returning a connection state to the cache control unit;
s103, receiving the cache control signal and the connection state through the cache control unit, and starting or interrupting access of each core to the corresponding cache access according to the cache control signal and the connection state.
As a further optional implementation manner, the system for isolating a dynamic cache partition of a multi-core processor further includes a cache way replacement module, where the cache way replacement module includes a memory and a selector, and the control method further includes the following steps:
s104, when the cache paths are all occupied, selecting a plurality of cache paths with front occupation time as cache paths to be replaced through a cache path management unit, generating a reference path queue according to the cache paths to be replaced, and storing the reference path queue in a memory;
s105, when the cache path management unit receives a core cache instruction, generating a corresponding enable signal queue according to the cache instruction, and sending the enable signal queue to the selector, wherein the enable signal queue comprises a plurality of enable signals which are in one-to-one correspondence with the cache paths to be replaced;
and S106, selecting a corresponding buffer path for buffer replacement through the selector according to the enable signal queue and the reference path queue.
It can be understood that the contents in the system embodiments are all applicable to the method embodiments, the functions specifically implemented by the method embodiments are the same as the system embodiments, and the beneficial effects achieved by the method embodiments are also the same as the beneficial effects achieved by the system embodiments.
It should be recognized that embodiments of the present invention can be realized and implemented by computer hardware, a combination of hardware and software, or by computer instructions stored in a non-transitory computer readable memory. The above-described methods may be implemented in a computer program using standard programming techniques, including a non-transitory computer-readable storage medium configured with the computer program, where the storage medium so configured causes a computer to operate in a specific and predefined manner, according to the methods and figures described in the detailed description. Each program may be implemented in a high level procedural or object oriented programming language to communicate with a computer system. However, the program(s) can be implemented in assembly or machine language, if desired. In any case, the language may be a compiled or interpreted language. Furthermore, the program can be run on a programmed application specific integrated circuit for this purpose.
Further, the operations of processes described herein can be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by context. The processes described herein (or variations and/or combinations thereof) may be performed under the control of one or more computer systems configured with executable instructions, and may be implemented as code (e.g., executable instructions, one or more computer programs, or one or more applications) collectively executed on one or more processors, by hardware, or combinations thereof. The computer program includes a plurality of instructions executable by one or more processors.
Further, the above-described methods may be implemented in any type of computing platform operatively connected to a suitable connection, including but not limited to a personal computer, mini computer, mainframe, workstation, networked or distributed computing environment, separate or integrated computer platform, or in communication with a charged particle tool or other imaging device, and the like. Aspects of the invention may be embodied in machine-readable code stored on a non-transitory storage medium or device, whether removable or integrated into a computing platform, such as a hard disk, optically read and/or write storage medium, RAM, ROM, or the like, such that it may be read by a programmable computer, which when read by the storage medium or device, is operative to configure and operate the computer to perform the procedures described herein. Further, the machine-readable code, or portions thereof, may be transmitted over a wired or wireless network. The invention described herein includes these and other different types of non-transitory computer-readable storage media when such media include instructions or programs that implement the steps described above in conjunction with a microprocessor or other data processor. The invention also includes the computer itself when programmed according to the methods and techniques described herein.
A computer program can be applied to input data to perform the functions described herein to transform the input data to generate output data that is stored to non-volatile memory. The output information may also be applied to one or more output devices, such as a display. In a preferred embodiment of the invention, the transformed data represents physical and tangible objects, including particular visual depictions of physical and tangible objects produced on a display.
The above description is only a preferred embodiment of the present invention, and the present invention is not limited to the above embodiment, and any modifications, equivalent substitutions, improvements, etc. within the spirit and principle of the present invention should be included in the protection scope of the present invention as long as the technical effects of the present invention are achieved by the same means. The invention is capable of other modifications and variations in its technical solution and/or its implementation, within the scope of protection of the invention.
Claims (9)
1. A multi-core processor dynamic cache partition isolation system, comprising:
the system comprises a multi-core processor and a cache management module, wherein the multi-core processor comprises a plurality of cores, and each core is mutually independent and shares a corresponding first-level cache;
a shared timer interrupt module to synchronize and trigger tasks on each of the cores;
the shared second-level cache comprises a cache access management unit, a cache control unit, a cache access switching unit and a cache access pool, wherein the cache access pool comprises a plurality of cache accesses, the cache access management unit is used for reconfiguring the cache accesses occupied by the cache accesses according to cache instructions sent by the cores and issuing corresponding cache control signals, the cache access switching unit is used for dynamically connecting the cores and the corresponding cache accesses according to the cache control signals, and the cache control unit is used for controlling the access of the cores to the corresponding cache accesses according to the cache control signals.
2. The system of claim 1, wherein the system is configured to perform dynamic cache partition isolation for the multi-core processor: the shared timer interrupt module comprises a global timer and decrementers corresponding to the cores one by one, wherein the global timer is used for generating a trigger signal at a preset time interval, and the trigger signal enables the decrementers to decrement once in sequence.
3. The system of claim 1, wherein the system is configured to perform dynamic cache partition isolation for the multi-core processor: each core is connected with the cache access management unit, each core is provided with a corresponding code, the cache instruction comprises the code and an instruction type, and the cache access management unit identifies the corresponding core according to the code and determines the corresponding cache access configuration operation according to the instruction type.
4. The system of claim 1, wherein the system is configured to perform dynamic cache partition isolation for the multi-core processor: the cache control unit comprises a plurality of cache controllers, and the cache controllers are in one-to-one correspondence with the cores.
5. The system of claim 1, wherein the system comprises: the cache path is composed of memory blocks and is provided with a plurality of cache partitions, and each cache partition can be occupied by different cores respectively.
6. The system according to any of claims 1 to 5, wherein: the multi-core processor dynamic cache partition isolation system further comprises a cache path replacement module, wherein the cache path replacement module is used for selecting one occupied cache path for cache replacement when the core needs to store data in the shared secondary cache and each cache path is occupied.
7. The system of claim 6, wherein the system is configured to perform dynamic cache partition isolation for the multi-core processor: the buffer path replacing module comprises a memory and a selector, wherein the memory is used for storing a reference path queue, the reference path queue is a queue of buffer paths to be replaced, which is formed based on a first-in first-out replacement strategy, the selector is used for selecting corresponding buffer paths according to the reference path queue and an enabling signal queue to perform buffer replacement, the enabling signal queue is generated by the buffer path management unit, and the enabling signal queue comprises a plurality of enabling signals which are in one-to-one correspondence with the buffer paths to be replaced.
8. A control method of a multi-core processor dynamic cache partition isolation system, for being implemented by the multi-core processor dynamic cache partition isolation system of any one of claims 1 to 7, comprising the steps of:
receiving a cache instruction sent by each core through a cache path management unit, reconfiguring a cache path occupied by the core according to the cache instruction, and generating a corresponding cache control signal according to a reconfiguration result;
receiving the cache control signal through a cache access switching unit, dynamically connecting each core and the corresponding cache access according to the cache control signal, and returning a connection state to the cache control unit;
and receiving the cache control signal and the connection state through the cache control unit, and starting or interrupting the access of each core to the corresponding cache access according to the cache control signal and the connection state.
9. The method for controlling the multi-core processor dynamic cache partition isolation system according to claim 8, wherein the multi-core processor dynamic cache partition isolation system further comprises a cache way replacement module, the cache way replacement module comprises a memory and a selector, and the method further comprises the following steps:
when the cache ways are all occupied, selecting a plurality of cache ways with the front occupation time as cache ways to be replaced through the cache way management unit, generating a reference way queue according to the cache ways to be replaced, and further storing the reference way queue in the memory;
when the cache path management unit receives the cache instruction of the core, generating a corresponding enable signal queue according to the cache instruction, and sending the enable signal queue to the selector, wherein the enable signal queue comprises a plurality of enable signals which are in one-to-one correspondence with the cache paths to be replaced;
and selecting a corresponding buffer access for buffer replacement through the selector according to the enabling signal queue and the reference access queue.
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| CN202211438477.9A CN115827547A (en) | 2022-11-16 | 2022-11-16 | Multi-core processor dynamic cache partition isolation system and control method thereof |
| PCT/CN2023/095559 WO2024103666A1 (en) | 2022-11-16 | 2023-05-22 | Dynamic cache-partition isolation system for multi-core processor, and control method therefor |
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| WO2024103666A1 (en) * | 2022-11-16 | 2024-05-23 | 中山大学 | Dynamic cache-partition isolation system for multi-core processor, and control method therefor |
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| US7076609B2 (en) * | 2002-09-20 | 2006-07-11 | Intel Corporation | Cache sharing for a chip multiprocessor or multiprocessing system |
| CN101571843A (en) * | 2008-04-29 | 2009-11-04 | 国际商业机器公司 | Method, apparatuses and system for dynamic share high-speed cache in multi-core processor |
| US9529719B2 (en) * | 2012-08-05 | 2016-12-27 | Advanced Micro Devices, Inc. | Dynamic multithreaded cache allocation |
| CN105426319B (en) * | 2014-08-19 | 2019-01-11 | 超威半导体产品（中国）有限公司 | Dynamic buffering zone devices and method |
| US12066945B2 (en) * | 2020-12-22 | 2024-08-20 | Intel Corporation | Dynamic shared cache partition for workload with large code footprint |
| CN115098431A (en) * | 2022-05-27 | 2022-09-23 | 北京奕斯伟计算技术股份有限公司 | Processor, shared cache allocation method and device |
| CN115827547A (en) * | 2022-11-16 | 2023-03-21 | 中山大学 | Multi-core processor dynamic cache partition isolation system and control method thereof |
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