CN115827547A - A multi-core processor dynamic cache partition isolation system and control method thereof - Google Patents

Abstract

The invention discloses a multi-core processor dynamic cache partition isolation system and a control method thereof. The system includes a multi-core processor, a shared timer interrupt module, and a shared secondary cache. The shared secondary cache includes a cache path management unit, a cache control unit, The cache path switching unit and the cache path pool, through the cache path management unit, the cache control unit and the cache path switching unit, perform dynamic partition management on the cache path, and provide a dynamically configurable shared secondary cache for multi-core processors, so that the shared secondary cache It can be efficiently used by each core, avoiding inter-core cache interference, ensuring the correct operation of processor tasks to a certain extent, and improving system performance. The invention can be widely applied in the technical field of multi-core processors.

Description

A multi-core processor dynamic cache partition isolation system and control method thereof

technical field

The invention relates to the technical field of multi-core processors, in particular to a multi-core processor dynamic cache partition isolation system and a control method thereof.

Background technique

With the end of Moore's Law, the performance improvement of the single-core bottleneck of computer processors is limited, and current processor designs are increasingly shifting to multi-core platforms. To mitigate the high latency of off-chip memory, multicore processor system-on-chip (MPSoC) architectures are often equipped with a hierarchical cache subsystem. This complex cache hierarchy makes the behavior of shared caches difficult to predict and analyze. For example, a task running on one core may evict useful L2 cache space that may be in use by another task in another core. These inter-core cache interferences will lead to an increase in the miss rate, resulting in a corresponding performance degradation. At the same time, inter-core cache interference is difficult to analyze accurately, thus making it difficult to estimate the worst-case execution time of an application. At present, most of the multi-core cache management in real-time systems use page coloring technology, that is, the software cache partition method at the operating system level, and the cache is partitioned according to the settings. However, the problem with the page coloring technique is that the coloring time is very expensive. On the one hand, this time overhead prohibits frequent page color changes; Multi-core processor system performance.

Contents of the invention

In order to solve the above technical problems, the object of the present invention is: the present invention proposes a multi-core processor dynamic cache partition isolation system and its control method, which avoids inter-core cache interference and improves system performance.

The first technical scheme adopted in the present invention is:

A multi-core processor dynamic cache partition isolation system, comprising:

A multi-core processor, the multi-core processor includes a plurality of cores, each of which is independent of each other and has a corresponding level-1 cache;

A shared timer interrupt module, the shared timer interrupt module is used to synchronize and trigger tasks on each of the cores;

A shared secondary cache, the shared secondary cache includes a cache path management unit, a cache control unit, a cache path switching unit, and a cache path pool, the cache path pool includes multiple cache paths, and the cache path management unit is used to The cache instructions sent by each of the cores reconfigure the cache paths they occupy, and issue corresponding cache control signals, and the cache path switching unit is used to control each of the cores and the corresponding cache paths according to the cache control signals Dynamic connection, the cache control unit is used to control the access of each core to the corresponding cache path according to the cache control signal.

Further, the shared timer interrupt module includes a global timer and a decrementer corresponding to each of the cores, the global timer is used to generate a trigger signal at a preset time interval, and the trigger signal makes each of the cores The decrementer decrements one by one.

Further, each of the cores is connected to the cache path management unit, and each of the cores is provided with a corresponding code, the cache instruction includes the code and the instruction type, and the cache path management unit identifies according to the code the corresponding core, and determine the corresponding cache path configuration operation according to the instruction type.

Further, the cache control unit includes a plurality of cache controllers corresponding to the cores one by one.

Further, the cache path is composed of memory blocks, and a plurality of cache partitions are provided, and each of the cache partitions can be occupied by different cores.

Further, the multi-core processor dynamic cache partition isolation system also includes a cache path replacement module, the cache path replacement module is used when the core needs to store data in the shared L2 cache and each of the cache paths is When occupied, select an occupied cache path for cache replacement.

Further, the cache path replacement module includes a memory and a selector, the memory is used to store a reference path queue, the reference path queue is a queue of cache paths to be replaced based on a first-in-first-out replacement strategy, and the selection The device is used to select a corresponding cache path for cache replacement according to the reference path queue and the enable signal queue, the enable signal queue is generated by the cache path management unit, and the enable signal queue includes multiple One-to-one corresponding enable signal of cache path.

The second technical solution adopted in the present invention is:

A control method for a multi-core processor dynamic cache partition isolation system, which is implemented by the above-mentioned multi-core processor dynamic cache partition isolation system, includes the following steps:

receiving the cache instruction sent by each core through the cache path management unit, and reconfiguring the cache path occupied by the core according to the cache instruction, and then generating a corresponding cache control signal according to the reconfiguration result;

receiving the cache control signal through the cache path switching unit, and dynamically connecting each of the cores with the corresponding cache path according to the cache control signal, and then returning the connection state to the cache control unit;

The cache control unit receives the cache control signal and the connection status, and enables or disables each core's access to the corresponding cache path according to the cache control signal and the connection status.

Further, the multi-core processor dynamic cache partition isolation system also includes a cache path replacement module, the cache path replacement module includes a memory and a selector, and the control method further includes the following steps:

When the cache paths are all occupied, the cache path management unit selects a plurality of cache paths with a higher occupation time as the cache paths to be replaced, and generates a reference path queue according to the cache paths to be replaced, and then the reference a pass queue is stored in said memory;

When the cache path management unit receives the cache instruction of the core, it generates a corresponding enable signal queue according to the cache instruction, and sends the enable signal queue to the selector, and the enable signal The queue includes a plurality of enabling signals corresponding to the cache paths to be replaced;

The selector selects the corresponding cache path according to the enable signal queue and the reference path queue for cache replacement

The beneficial effects of the present invention are: the present invention provides a multi-core processor dynamic cache partition isolation system and its control method, through the cache path management unit, the cache control unit and the cache path switch unit to dynamically partition the cache path management, for multi-core The processor provides a dynamically configurable shared L2 cache, so that the shared L2 cache can be efficiently used by each core, avoiding inter-core cache interference, ensuring the correct operation of processor tasks to a certain extent, and improving system performance.

Description of drawings

FIG. 1 is a schematic structural diagram of a multi-core processor dynamic cache partition isolation system provided by an embodiment of the present invention;

FIG. 2 is a schematic structural diagram of a shared L2 cache provided by an embodiment of the present invention;

FIG. 3 is a schematic partition diagram of a cache channel provided by an embodiment of the present invention;

FIG. 4 is a flowchart of steps of a control method of a multi-core processor dynamic cache partition isolation system provided by an embodiment of the present invention.

Detailed ways

The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. For the step numbers in the following embodiments, it is only set for the convenience of illustration and description, and the order between the steps is not limited in any way. The execution order of each step in the embodiments can be adapted according to the understanding of those skilled in the art sexual adjustment.

In the description of the present invention, multiple means more than two. If the first and second are described only for the purpose of distinguishing technical features, it cannot be understood as indicating or implying relative importance or implicitly indicating what is indicated The number of technical features or implicitly indicates the order of the indicated technical features. Also, unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art. The terms used in the specification herein are for describing specific embodiments only, and are not intended to limit the present invention.

Referring to Figures 1 and 2, an embodiment of the present invention provides a multi-core processor dynamic cache partition isolation system, including:

Multi-core processors, multi-core processors include multiple cores, each core is independent of each other and has a corresponding level-1 cache;

Shared timer interrupt module, which is used to synchronize and trigger tasks on each core;

The shared L2 cache includes a cache path management unit, a cache control unit, a cache path switching unit, and a cache path pool. The cache path pool includes multiple cache paths, and the cache path management unit is used to send cache instructions according to each core. Reconfigure the cache path occupied by it, and issue the corresponding cache control signal, the cache path switching unit is used to dynamically connect each core and the corresponding cache path according to the cache control signal, and the cache control unit is used to control each core according to the cache control signal Core access to the corresponding cache way.

Specifically, in the embodiment of the present invention, the different cores of the multi-core processor exclusively share the first-level cache and are independent of each other; the shared timer interrupt module is used to synchronize and trigger tasks on different processors; the shared second-level cache is used by multiple cores Shared, allocated and used by multiple cores in a configurable dynamic cache partition.

Further as an optional implementation, the shared timer interrupt module includes a global timer and a decrementer corresponding to each core one by one, the global timer is used to generate a trigger signal at a preset time interval, and the trigger signal makes each decrementer decrement in turn once.

In the embodiment of the present invention, the shared timer interrupt module provides a dedicated decrementer for each core, decrements based on the shared global timer, and the shared global timer generates a trigger signal within a fixed time interval, so that each decrement decrements once.

Referring to Fig. 2, further as an optional embodiment, each core is connected to the cache path management unit, each core is provided with a corresponding code, the cache instruction includes code and instruction type, and the cache path management unit identifies the corresponding core according to the code, And determine the corresponding cache path configuration operation according to the instruction type.

Specifically, the cache path management unit is used for centralized management of cache paths. Through the cache path management unit, each core can send commands to reconfigure the cache paths it occupies. The cache path management unit is connected to the N cores, and can identify codes of different cores, and operate corresponding cache paths in the cache path pool according to different instruction types. Based on this unified scheduling scheme, the core does not need to query the state of the cache path before allocating memory, and also avoids interference between cores of the multi-core processor.

As a further optional implementation manner, the cache control unit includes multiple cache controllers, and the cache controllers correspond to the cores one by one.

Specifically, the cache control unit includes multiple cache controllers, which are set in one-to-one correspondence with multiple cores, so as to ensure that each core can access the shared L2 cache.

Referring to FIG. 3 , further as an optional implementation manner, the cache path is composed of memory blocks, and multiple cache partitions are provided, and each cache partition can be occupied by different cores.

Specifically, FIG. 3 is a schematic partition diagram of a cache channel provided by an embodiment of the present invention, and different fillings in the figure indicate that the memory of the corresponding cache partition is being occupied by different cores. The dynamic partition cache management in the embodiment of the present invention is implemented based on the cache partition method.

Referring to Fig. 1, further as an optional embodiment, the multi-core processor dynamic cache partition isolation system also includes a cache path replacement module, and the cache path replacement module is used to store data in the shared L2 cache when the core needs and each cache path is When occupied, select an occupied cache path for cache replacement.

Specifically, when new data must be stored in the shared L2 cache and all cache paths are occupied, it is necessary to select an occupied cache path for replacement. Replace the buffer channel that started occupying the earliest. In order to maintain a discontinuous cache way partition occupation mode, the embodiment of the present invention deploys a cache way replacement module.

Referring to Fig. 1, further as an optional embodiment, the cache path replacement module includes a memory and a selector, the memory is used to store a reference path queue, and the reference path queue is a queue of cache paths to be replaced based on a first-in-first-out replacement strategy , the selector is used to select the corresponding cache path for cache replacement according to the reference path queue and the enable signal queue, the enable signal queue is generated by the cache path management unit, and the enable signal queue includes multiple enable signal.

Specifically, in the embodiment of the present invention, based on a first-in-first-out replacement policy, cache paths to be replaced are stored in a queue in a dual-port memory to form a reference path queue. When a buffered way is released, the information in the reference way queue should be cleared as the original reference way within one clock. In order to achieve this goal, the embodiment of the present invention adopts the control mode of the enable signal, and constructs a 1-bit enable signal for each reference path in the reference path queue and stores it in the form of a queue to control the output of the selector. In this way, the purpose of resetting the reference path queue in one clock cycle is achieved.

The above is the description of the system structure and working principle of the embodiment of the present invention. It can be understood that, through the cache path management unit, the cache control unit and the cache path switching unit, the cache path is dynamically partitioned and managed, and a dynamically configurable shared L2 cache is provided for the multi-core processor, so that the shared L2 cache can be efficiently provided. The use of each core avoids inter-core cache interference, ensures the correct operation of processor tasks to a certain extent, and improves system performance.

The embodiments of the present invention will be further described below in conjunction with the control method.

Referring to FIG. 4 , an embodiment of the present invention provides a control method for a multi-core processor dynamic cache partition isolation system, which is implemented by the above-mentioned multi-core processor dynamic cache partition isolation system, including the following steps:

S101. Receive the cache instruction sent by each core through the cache path management unit, reconfigure the cache path occupied by the core according to the cache instruction, and then generate a corresponding cache control signal according to the reconfiguration result;

S102. Receive the cache control signal through the cache path switching unit, and dynamically connect each core with the corresponding cache path according to the cache control signal, and then return the connection state to the cache control unit;

S103. Receive the cache control signal and the connection state through the cache control unit, and enable or stop each core's access to the corresponding cache path according to the cache control signal and the connection state.

Further as an optional implementation, the multi-core processor dynamic cache partition isolation system also includes a cache path replacement module, the cache path replacement module includes a memory and a selector, and the control method further includes the following steps:

S104. When the cache paths are all occupied, the cache path management unit selects a plurality of cache paths with a higher occupying time as the cache paths to be replaced, and generates a reference path queue according to the cache paths to be replaced, and then stores the reference path queue in in memory;

S105. When the cache path management unit receives the cache instruction of the core, it generates a corresponding enable signal queue according to the cache instruction, and sends the enable signal queue to the selector. The enable signal queue includes a plurality of cache paths to be replaced One-to-one corresponding enable signal;

S106 , select a corresponding cache path to perform cache replacement according to the enable signal queue and the reference path queue through the selector.

It can be understood that the content in the above-mentioned system embodiment is applicable to this method embodiment, the functions realized by this method embodiment are the same as those of the above-mentioned system embodiment, and the beneficial effects achieved are the same as those achieved by the above-mentioned system embodiment The beneficial effects are also the same.

It should be appreciated that embodiments of the invention may be realized or implemented by computer hardware, a combination of hardware and software, or by computer instructions stored in a non-transitory computer readable memory. The above methods can be implemented in a computer program using standard programming techniques—including a non-transitory computer-readable storage medium configured with a computer program, wherein the storage medium so configured causes the computer to operate in a specific and predefined manner—according to the specific implementation Methods and figures described in the examples. Each program can be implemented in a high-level procedural or object-oriented programming language to communicate with the computer system. However, the programs can be implemented in assembly or machine language, if desired. In any case, the language may be a compiled or interpreted language. Furthermore, the program can be run on an application specific integrated circuit programmed for this purpose.

In addition, operations of processes described herein may be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by context. The processes described herein (or variations and/or combinations thereof) can be performed under the control of one or more computer systems configured with executable instructions, and as code that collectively executes on one or more processors (e.g. , executable instructions, one or more computer programs or one or more applications), hardware or a combination thereof. The computer program described above includes a plurality of instructions executable by one or more processors.

Further, the above method can be implemented in any type of computing platform operably connected to suitable, including but not limited to personal computer, minicomputer, main frame, workstation, network or distributed computing environment, separate or integrated computer platform , or communicate with charged particle tools or other imaging devices, etc. Aspects of the invention can be implemented as machine-readable code stored on a non-transitory storage medium or device, whether removable or integrated into a computing platform, such as a hard disk, optically read and/or written storage medium, RAM, ROM, etc., such that they are readable by a programmable computer, when the storage medium or device is read by the computer, can be used to configure and operate the computer to perform the processes described herein. Additionally, the machine-readable code, or portions thereof, may be transmitted over a wired or wireless network. The invention described herein includes these and other various types of non-transitory computer-readable storage media when such media include instructions or programs that implement the steps described above in conjunction with a microprocessor or other data processor. The invention also includes the computer itself when programmed according to the methods and techniques described herein.

Computer programs can be applied to input data to perform the functions described herein, transforming the input data to generate output data stored to non-volatile memory. Output information may also be applied to one or more output devices such as a display. In a preferred embodiment of the invention, the transformed data represents physical and tangible objects, including specific visual depictions of physical and tangible objects produced on a display.

The above is only a preferred embodiment of the present invention, and the present invention is not limited to the above-mentioned implementation, as long as it achieves the technical effect of the present invention by the same means, within the spirit and principles of the present invention, any Any modification, equivalent replacement, improvement, etc., shall be included within the protection scope of the present invention. Various modifications and changes may be made to the technical solutions and/or implementations within the protection scope of the present invention.

Claims (9)

1. A multi-core processor dynamic cache partition isolation system, comprising:

the system comprises a multi-core processor and a cache management module, wherein the multi-core processor comprises a plurality of cores, and each core is mutually independent and shares a corresponding first-level cache;

a shared timer interrupt module to synchronize and trigger tasks on each of the cores;

the shared second-level cache comprises a cache access management unit, a cache control unit, a cache access switching unit and a cache access pool, wherein the cache access pool comprises a plurality of cache accesses, the cache access management unit is used for reconfiguring the cache accesses occupied by the cache accesses according to cache instructions sent by the cores and issuing corresponding cache control signals, the cache access switching unit is used for dynamically connecting the cores and the corresponding cache accesses according to the cache control signals, and the cache control unit is used for controlling the access of the cores to the corresponding cache accesses according to the cache control signals.

2. The system of claim 1, wherein the system is configured to perform dynamic cache partition isolation for the multi-core processor: the shared timer interrupt module comprises a global timer and decrementers corresponding to the cores one by one, wherein the global timer is used for generating a trigger signal at a preset time interval, and the trigger signal enables the decrementers to decrement once in sequence.

3. The system of claim 1, wherein the system is configured to perform dynamic cache partition isolation for the multi-core processor: each core is connected with the cache access management unit, each core is provided with a corresponding code, the cache instruction comprises the code and an instruction type, and the cache access management unit identifies the corresponding core according to the code and determines the corresponding cache access configuration operation according to the instruction type.

4. The system of claim 1, wherein the system is configured to perform dynamic cache partition isolation for the multi-core processor: the cache control unit comprises a plurality of cache controllers, and the cache controllers are in one-to-one correspondence with the cores.

5. The system of claim 1, wherein the system comprises: the cache path is composed of memory blocks and is provided with a plurality of cache partitions, and each cache partition can be occupied by different cores respectively.

6. The system according to any of claims 1 to 5, wherein: the multi-core processor dynamic cache partition isolation system further comprises a cache path replacement module, wherein the cache path replacement module is used for selecting one occupied cache path for cache replacement when the core needs to store data in the shared secondary cache and each cache path is occupied.

7. The system of claim 6, wherein the system is configured to perform dynamic cache partition isolation for the multi-core processor: the buffer path replacing module comprises a memory and a selector, wherein the memory is used for storing a reference path queue, the reference path queue is a queue of buffer paths to be replaced, which is formed based on a first-in first-out replacement strategy, the selector is used for selecting corresponding buffer paths according to the reference path queue and an enabling signal queue to perform buffer replacement, the enabling signal queue is generated by the buffer path management unit, and the enabling signal queue comprises a plurality of enabling signals which are in one-to-one correspondence with the buffer paths to be replaced.

8. A control method of a multi-core processor dynamic cache partition isolation system, for being implemented by the multi-core processor dynamic cache partition isolation system of any one of claims 1 to 7, comprising the steps of:

receiving a cache instruction sent by each core through a cache path management unit, reconfiguring a cache path occupied by the core according to the cache instruction, and generating a corresponding cache control signal according to a reconfiguration result;

receiving the cache control signal through a cache access switching unit, dynamically connecting each core and the corresponding cache access according to the cache control signal, and returning a connection state to the cache control unit;

and receiving the cache control signal and the connection state through the cache control unit, and starting or interrupting the access of each core to the corresponding cache access according to the cache control signal and the connection state.

9. The method for controlling the multi-core processor dynamic cache partition isolation system according to claim 8, wherein the multi-core processor dynamic cache partition isolation system further comprises a cache way replacement module, the cache way replacement module comprises a memory and a selector, and the method further comprises the following steps:

when the cache ways are all occupied, selecting a plurality of cache ways with the front occupation time as cache ways to be replaced through the cache way management unit, generating a reference way queue according to the cache ways to be replaced, and further storing the reference way queue in the memory;

when the cache path management unit receives the cache instruction of the core, generating a corresponding enable signal queue according to the cache instruction, and sending the enable signal queue to the selector, wherein the enable signal queue comprises a plurality of enable signals which are in one-to-one correspondence with the cache paths to be replaced;

and selecting a corresponding buffer access for buffer replacement through the selector according to the enabling signal queue and the reference access queue.

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