CN115827257B

CN115827257B - CPU capacity prediction method and system for processor system

Info

Publication number: CN115827257B
Application number: CN202310133156.6A
Authority: CN
Inventors: 尹俊文; 廖海宁; 尹鹏
Original assignee: Tengyun Chuangwei Information Technology Weihai Co ltd
Current assignee: Tengyun Chuangwei Information Technology Weihai Co ltd
Priority date: 2023-02-20
Filing date: 2023-02-20
Publication date: 2023-05-05
Anticipated expiration: 2043-02-20
Also published as: CN115827257A

Abstract

The application relates to the field of intelligent prediction, and particularly discloses a CPU capacity prediction method and a CPU capacity prediction system for a processor system. Therefore, the CPU capacity can be accurately predicted, so that the CPU capacity is better controlled, overload is prevented, or the performance of the CPU can not meet the processing task requirement, and the performance stability and reliability of a processor system are maintained.

Description

CPU capacity prediction method and system for processor system

Technical Field

The present application relates to the field of intelligent prediction, and more particularly, to a method and system for CPU capacity prediction for a processor architecture.

Background

With the increasing concentration of data processing, IBM Z-series Mainframe (Mainframe) has become the first choice for banking core business processing platforms. The financial market has the characteristics of large traffic, various types and complex processing flow, so the performance of the computer system is monitored, particularly the performance of the CPU is monitored, and the reasonable configuration of computer resources and the effective operation of the computer system are ensured.

Along with the increase of the user quantity of the system platform, before the bottleneck of the processor system appears, how to reasonably allocate CPU resources to ensure the smooth operation of the processor system and ensure that the processor system can meet the processing task requirements is a difficult problem which puzzles most operation and maintenance personnel to carry out capacity planning. The capacity planning of the traditional data center mainly takes experience as a main part, and in order to ensure the performance of a processor system, a mode of excessive allocation of resources is often adopted, which can lead to very low overall utilization rate of resources of a data center server and cause resource waste.

Accordingly, an optimized CPU capacity prediction scheme for a processor architecture is desired.

Disclosure of Invention

The present application has been made in order to solve the above technical problems. The embodiment of the application provides a CPU capacity prediction method and a CPU capacity prediction system for a processor system, which excavate dynamic association characteristics of the residual CPU capacities of all CPU units in a time dimension and association relations among the residual CPU capacities of all CPU units by adopting a deep neural network model based on deep learning. Therefore, the CPU capacity can be accurately predicted, so that the CPU capacity is better controlled, overload is prevented, or the performance of the CPU can not meet the processing task requirement, and the performance stability and reliability of a processor system are maintained.

According to one aspect of the present application, there is provided a CPU capacity prediction method for a processor architecture, comprising: obtaining residual CPU capacities of a plurality of CPU units in a processor system at a plurality of preset time points in a preset time period; residual CPU capacity of each CPU unit at a plurality of preset time points in a preset time period is arranged into an input vector according to a time dimension, and then a plurality of residual CPU capacity feature vectors are obtained through a multi-scale neighborhood feature extraction module; calculating transfer matrixes between every two residual CPU capacity feature vectors in the residual CPU capacity feature vectors to obtain a plurality of transfer matrixes; the transfer matrixes are aggregated into three-dimensional input tensors according to channel dimensions, and then a convolutional neural network model serving as a feature extractor is used for obtaining a CPU residual capacity correlation feature map; the CPU residual capacity associated feature map is passed through a non-local neural network model to obtain a decoding feature map; performing feature distribution modulation on the decoding feature map to obtain an optimized decoding feature map; and performing decoding regression on the optimized decoding characteristic map through a decoder to obtain a decoding value used for representing the predicted value of the CPU capacity of the processor system.

In the above method for predicting CPU capacity of a processor architecture, the multi-scale neighborhood feature extraction module includes: the device comprises a first convolution layer, a second convolution layer parallel to the first convolution layer and a cascade layer connected with the first convolution layer and the second convolution layer, wherein the first convolution layer uses a one-dimensional convolution kernel with a first scale, and the second convolution layer uses a one-dimensional convolution kernel with a second scale.

In the above method for predicting CPU capacity of a processor system, the arranging the remaining CPU capacities of the CPU units at a plurality of predetermined time points in a predetermined time period as input vectors according to a time dimension, and then obtaining a plurality of remaining CPU capacity feature vectors by a multi-scale neighborhood feature extraction module, includes: inputting the residual CPU capacity input vector into a first convolution layer of the multi-scale neighborhood feature extraction module to obtain a first neighborhood scale residual CPU capacity feature vector, wherein the first convolution layer is provided with a first one-dimensional convolution kernel with a first length; inputting the residual CPU capacity input vector into a second convolution layer of the multi-scale neighborhood feature extraction module to obtain a second neighborhood scale residual CPU capacity feature vector, wherein the second convolution layer is provided with a second one-dimensional convolution kernel with a second length, and the first length is different from the second length; and cascading the first neighborhood scale residual CPU capacity feature vector and the second neighborhood scale residual CPU capacity feature vector to obtain the plurality of residual CPU capacity feature vectors.

In the above method for predicting CPU capacity of a processor architecture, the inputting the remaining CPU capacity input vector into the first convolution layer of the multi-scale neighborhood feature extraction module to obtain a first neighborhood-scale remaining CPU capacity feature vector includes: performing one-dimensional convolution coding on the residual CPU capacity input vector by using a first convolution layer of the multi-scale neighborhood feature extraction module according to the following formula to obtain a residual CPU capacity feature vector of the first neighborhood scale; wherein, the formula is:

，

wherein ,ais the first convolution kernelxThe width in the direction of the sheet is,

for the first convolution kernel parameter vector,

for a local vector matrix that operates with a convolution kernel,wfor the size of the first convolution kernel,Xrepresenting the remaining CPU capacity input vector; and inputting the residual CPU capacity input vector into a second convolution layer of the multi-scale neighborhood feature extraction module to obtain a second neighborhood-scale residual CPU capacity feature vector, including: performing one-dimensional convolution coding on the residual CPU capacity input vector by using a second convolution layer of the multi-scale neighborhood feature extraction module according to the following formula to obtain a residual CPU capacity feature vector of the second neighborhood scale; wherein, the formula is:

，

Wherein b is the second convolution layerxThe width in the direction of the sheet is,

for the second convolution layer parameter vector,

for the local vector matrix to operate with the convolution kernel, m is the size of the second convolution layer,Xrepresenting the remaining CPU capacity input vector.

In the above method for predicting CPU capacity of a processor system, the calculating a transfer matrix between each two remaining CPU capacity feature vectors of the plurality of remaining CPU capacity feature vectors to obtain a plurality of transfer matrices includes: calculating transfer matrices between every two residual CPU capacity feature vectors in the residual CPU capacity feature vectors to obtain a plurality of transfer matrices according to the following formula; wherein, the formula is:

，

wherein

and />

Representing every two of the plurality of residual CPU capacity feature vectorsResidual CPU capacity feature vector,>

representing the plurality of transfer matrices.

In the above method for predicting CPU capacity of a processor system, the aggregating the plurality of transfer matrices according to channel dimensions into a three-dimensional input tensor, and then obtaining a CPU residual capacity correlation feature map by using a convolutional neural network model as a feature extractor, includes: each layer of the convolutional neural network model using the feature extractor performs, in forward transfer of the layer, input data: carrying out convolution processing on input data to obtain a convolution characteristic diagram; pooling the convolution feature images based on the local feature matrix to obtain pooled feature images; performing nonlinear activation on the pooled feature map to obtain an activated feature map; the output of the last layer of the convolutional neural network serving as the feature extractor is the CPU residual capacity associated feature map, and the input of the first layer of the convolutional neural network serving as the feature extractor is the three-dimensional input tensor.

In the above method for predicting CPU capacity of a processor system, the step of passing the CPU residual capacity correlation feature map through a non-local neural network model to obtain a decoded feature map includes: respectively inputting the CPU residual capacity associated feature map into a first point convolution layer, a second point convolution layer and a third point convolution layer of the non-local neural network model to obtain a first feature map, a second feature map and a third feature map; calculating a weighted sum of the first feature map and the second feature map according to positions to obtain an intermediate fusion feature map; inputting the intermediate fusion feature map into a Softmax function to normalize feature values of each position in the intermediate fusion feature map so as to obtain a normalized intermediate fusion feature map; calculating a weighted sum of the normalized intermediate fusion feature map and the third feature map by position to obtain a re-fusion feature map; embedding a Gaussian similarity function into the re-fusion feature map to calculate the similarity between feature values of each position in the re-fusion feature map so as to obtain a global perception feature map; passing the global perception feature map through a fourth point convolution layer of the non-local neural network model to obtain a channel-adjustment global perception feature map; and calculating a weighted sum of the channel adjustment global perception feature map and the CPU residual capacity association feature map according to positions to obtain the decoding feature map.

In the above method for predicting CPU capacity of a processor system, the performing feature distribution modulation on the decoding feature map to obtain an optimized decoding feature map includes: performing feature distribution modulation on the decoding feature map by using the following formula to obtain the optimized decoding feature map; wherein, the formula is:

，

wherein

Is a predetermined characteristic value of said decoding profile, for example>

Is a feature value other than the predetermined feature value of the decoding feature map, and +.>

Is the mean value of all feature values of the decoded feature map, and +.>

Is the scale of the decoding profile, +.>

Is an exponential operation of a value representing a natural exponential function value raised to a power by said value, +>

Is a predetermined feature value of the optimized decoding feature map.

In the above CPU capacity prediction method for a processor architecture, the optimizing decoding feature map is decoded by a decoder to obtain a prediction result for the processor architectureA decoded value representing a predicted value of CPU capacity of the processor architecture, comprising: performing decoding regression on the optimized decoding feature map by a decoder using the decoder in the following formula to obtain a decoded value representing a predicted value of the CPU capacity of the processor architecture; wherein, the formula is:

, wherein />

Representing the optimized decoding profile, +_>

Is the decoded value,/->

Is a weight matrix, < >>

Representing matrix multiplication.

According to another aspect of the present application, there is provided a CPU capacity prediction system for a processor architecture, comprising: the capacity information acquisition module is used for acquiring the residual CPU capacities of a plurality of CPU units in the processor system at a plurality of preset time points in a preset time period; the multi-scale neighborhood feature extraction module is used for arranging the residual CPU capacity of each CPU unit at a plurality of preset time points in a preset time period into an input vector according to a time dimension and then obtaining a plurality of residual CPU capacity feature vectors through the multi-scale neighborhood feature extraction module; the transfer module is used for calculating transfer matrixes between every two residual CPU capacity feature vectors in the residual CPU capacity feature vectors to obtain a plurality of transfer matrixes; the convolution module is used for aggregating the transfer matrixes into a three-dimensional input tensor according to channel dimensions and then obtaining a CPU residual capacity correlation characteristic diagram through a convolution neural network model serving as a characteristic extractor; the non-local neural network module is used for enabling the CPU residual capacity associated feature map to pass through a non-local neural network model to obtain a decoding feature map; the feature distribution modulation module is used for carrying out feature distribution modulation on the decoding feature map so as to obtain an optimized decoding feature map; and a decoding regression module for performing decoding regression on the optimized decoding feature map through a decoder to obtain a decoding value for representing the predicted value of the CPU capacity of the processor architecture.

According to still another aspect of the present application, there is provided an electronic apparatus including: a processor; and a memory having stored therein computer program instructions that, when executed by the processor, cause the processor to perform the CPU capacity prediction method for a processor architecture as described above.

According to yet another aspect of the present application, there is provided a computer readable medium having stored thereon computer program instructions which, when executed by a processor, cause the processor to perform a CPU capacity prediction method for a processor architecture as described above.

Compared with the prior art, the CPU capacity prediction method and the CPU capacity prediction system for the processor system provided by the application have the advantages that the dynamic correlation characteristics of the residual CPU capacities of all the CPU units in the time dimension and the correlation relation among the residual CPU capacities of all the CPU units are excavated by adopting a deep neural network model based on deep learning. Therefore, the CPU capacity can be accurately predicted, so that the CPU capacity is better controlled, overload is prevented, or the performance of the CPU can not meet the processing task requirement, and the performance stability and reliability of a processor system are maintained.

Drawings

The foregoing and other objects, features and advantages of the present application will become more apparent from the following more particular description of embodiments of the present application, as illustrated in the accompanying drawings. The accompanying drawings are included to provide a further understanding of embodiments of the application and are incorporated in and constitute a part of this specification, illustrate the application and not constitute a limitation to the application. In the drawings, like reference numerals generally refer to like parts or steps.

FIG. 1 is a flow chart of a method for CPU capacity prediction for a processor architecture according to an embodiment of the present application.

Fig. 2 is a schematic architecture diagram of a CPU capacity prediction method for a processor architecture according to an embodiment of the present application.

FIG. 3 is a flow chart of multi-scale neighborhood feature extraction in a CPU capacity prediction method for a processor architecture according to an embodiment of the present application.

Fig. 4 is a flowchart of convolutional neural network coding in a CPU capacity prediction method for a processor architecture according to an embodiment of the present application.

Fig. 5 is a flow chart of non-local neural network encoding in a CPU capacity prediction method for a processor architecture according to an embodiment of the present application.

FIG. 6 is a block diagram of a CPU capacity prediction system for a processor architecture according to an embodiment of the present application.

Fig. 7 is a block diagram of an electronic device according to an embodiment of the present application.

Detailed Description

Hereinafter, example embodiments according to the present application will be described in detail with reference to the accompanying drawings. It should be apparent that the described embodiments are only some of the embodiments of the present application and not all of the embodiments of the present application, and it should be understood that the present application is not limited by the example embodiments described herein.

Scene overview: as described in the background art, the capacity planning of the traditional data center is mainly based on experience, and in order to ensure the performance of the processor system, a mode of excessive allocation of resources is often adopted, which results in very low overall utilization rate of resources of the data center server and resource waste. Accordingly, an optimized CPU capacity prediction scheme for a processor architecture is desired.

Accordingly, considering that the capacity of the CPU needs to be predicted in order to better control the capacity of the CPU, when the capacity of the CPU is actually predicted, the prediction can be performed by performing dynamic change analysis on the remaining CPU capacities of a plurality of CPU units in the processor system in a time dimension. However, since the processor system is composed of a plurality of CPU units, the remaining CPU capacity of each CPU unit has not only a characteristic of constantly changing in the time dimension, but also a correlation relationship between the remaining CPU capacities of the respective CPU units, which makes it difficult to predict the CPU capacity of the processor system in real time. Therefore, in the process of predicting the CPU capacity of the processor system, the difficulty is how to accurately predict the CPU capacity in order to better control the CPU capacity, prevent overload or performance failure to meet the processing task requirements, so as to maintain the performance stability and reliability of the processor system.

In recent years, deep learning and neural networks have been widely used in the fields of computer vision, natural language processing, text signal processing, and the like. In addition, deep learning and neural networks have also shown levels approaching and even exceeding humans in the fields of image classification, object detection, semantic segmentation, text translation, and the like.

The development of deep learning and neural networks provides new solutions and schemes for mining time sequence association relationships among the remaining CPU capacities of each CPU unit of the processor system. Those of ordinary skill in the art will appreciate that deep learning based deep neural network models may adjust parameters of the deep neural network model by appropriate training strategies, such as by gradient descent back-propagation algorithms, to enable modeling of complex nonlinear correlations between things, which is obviously suitable for modeling and establishing complex timing correlations between the remaining CPU capacities of the various CPU units of the processor architecture.

Specifically, in the technical scheme of the present application, first, the remaining CPU capacities of a plurality of CPU units in a processor system at a plurality of predetermined time points within a predetermined period of time are acquired. Then, considering that the residual CPU capacity of each CPU unit in the processor system has fluctuation in the time dimension, and has different variation characteristics under different time period spans in the predetermined time period, in order to accurately extract the time sequence dynamic variation characteristics to accurately predict the CPU capacity, in the technical scheme of the application, the residual CPU capacities of each CPU unit at a plurality of predetermined time points in the predetermined time period are further arranged as input vectors according to the time dimension, and then feature mining is performed in a multi-scale neighborhood feature extraction module, so as to extract dynamic multi-scale neighborhood associated features of the residual CPU capacity of each CPU unit under different time spans in the predetermined time period, thereby obtaining a plurality of residual CPU capacity feature vectors corresponding to a plurality of CPU units.

Then, it is considered that in the processor system, the CPU capacity of the processor system is related to the remaining CPU capacities of the plurality of CPU units therein, and that there is also an associative relationship between the remaining CPU capacities of the respective CPU units. That is, the correlation between the remaining CPU capacities of the respective CPU units determines the overall CPU capacity of the processor system, and if it is desired to accurately predict the CPU capacity of the processor system, it is necessary to perform feature mining of the correlation between the remaining CPU capacities of the respective CPU units. Specifically, in the technical scheme of the application, a transfer matrix between every two residual CPU capacity feature vectors in the multiple residual CPU capacity feature vectors is calculated, so as to represent relevance feature distribution information between residual CPU capacities of every two CPU units in the multiple CPU units, thereby obtaining multiple transfer matrices.

Further, after obtaining the relevance feature distribution information between the residual CPU capacities of each two CPU units in the plurality of CPU units, in order to explore the influence of the relevance feature of the residual CPU capacities of each CPU unit on the CPU capacity change of the processor system, in the technical scheme of the application, the plurality of transfer matrices are further aggregated into a three-dimensional input tensor according to the channel dimension, and then feature mining is performed in a convolutional neural network model serving as a feature extractor, so as to obtain a CPU residual capacity relevance feature map. In particular, here, the convolutional neural network model is a convolutional neural network model having a three-dimensional convolutional kernel, which is a three-dimensional convolutional kernel having W (width), H (height) and C (channel dimension), and the correlation of the remaining CPU capacities of the respective CPU units can be extracted using the convolutional neural network model having a three-dimensional convolutional kernel in a sample dimension with respect to the correlation variation characteristics of the CPU capacities of the processor system as a whole.

Then, again, consider that since convolution is a typical local operation, it can only extract feature correlations of the remaining CPU capacity local to the processor architecture, and cannot be focused on global, affecting the CPU capacity prediction accuracy for the processor architecture. For the residual CPU capacity of each CPU unit, the correlation characteristic of the residual CPU capacity of each CPU unit forms the CPU capacity characteristic of the whole processor system, the residual CPU capacity characteristics of each CPU unit are not isolated, and the correlation among the residual CPU capacity characteristic distribution of each CPU unit generates a prospect target. Therefore, in the technical solution of the present application, in order to more accurately predict the CPU capacity of the processor system, a non-local neural network is used to further perform the CPU residual capacity related feature extraction of each CPU unit. That is, the CPU residual capacity correlation feature map is passed through a non-local neural network model to expand the feature receptive field through the non-local neural network model, thereby obtaining a decoded feature map. In particular, here, the non-local neural network captures hidden dependency information by calculating the similarity between the CPU residual capacity features of each CPU unit, so as to model the context features, so that the network focuses on global overall content between the CPU residual capacity features of each CPU unit, and further, the feature extraction capability of the backbone network is improved in decoding and prediction tasks.

And then, further carrying out decoding regression on the optimized decoding characteristic map through a decoder to obtain a decoding value used for representing the predicted value of the CPU capacity of the processor system. In this way, the CPU capacity of the processor system can be accurately predicted to prevent overload or performance failure to meet processing task requirements, so that the performance stability and reliability of the processor system can be maintained.

In particular, in the technical solution of the present application, the multiple transfer matrices are aggregated into the three-dimensional input tensor according to the channel dimension, the CPU residual capacity correlation feature map is obtained through a convolutional neural network model serving as a feature extractor, and the decoding feature map is obtained through a non-local neural network model, so that the decoding feature map includes rich local and global features in the channel arrangement dimension between the time sequence transfer features of each CPU unit, that is, local and global correlation features in the instant transfer-channel cross dimension.

But on the other hand, the decoding feature map expresses rich local and global associated features in the cross dimension, so that the fitting burden between the decoding feature map and the weight matrix of the decoder is heavy when the decoding regression is carried out through the decoder, and the training speed of the decoder and the accuracy of the decoding regression result are affected.

Thus, the decoded feature map is preferably subjected to regression characterization flattening, specifically expressed as:

，

is a predetermined characteristic value of said decoding profile, for example>

Is the mean value of all feature values of the decoded feature map, and +.>

Is the scale of the decoded feature map, i.e. width times height times channel number.

Here, the flattening of the regression characterization of the decoded feature map flattens the finite polyhedral manifold for the regression characterization of the feature distribution in the high-dimensional feature space while maintaining the inherent distance between the planes of the manifold and intuitively avoiding intersection based on space, which essentially decomposes the finite polyhedral manifold into a cube lattice based on right-angle plane intersection and with vertices, thereby obtaining flattened "slice" aggregations of the regression planes, i.e., aggregations of the feature distribution of the decoded feature map along each dimension. Therefore, the fitting performance of the decoding feature map to the weight matrix of the decoder is enhanced, and the training speed of the decoding regression of the decoding feature map through the decoder and the accuracy of the decoding result are improved. Therefore, the CPU capacity of the processor system can be accurately predicted, so that the CPU capacity is better controlled, overload of the CPU is prevented, or the performance of the CPU cannot meet the processing task requirement, and the performance stability and reliability of the processor system are maintained.

Based on this, the present application proposes a CPU capacity prediction method for a processor architecture, comprising: obtaining residual CPU capacities of a plurality of CPU units in a processor system at a plurality of preset time points in a preset time period; residual CPU capacity of each CPU unit at a plurality of preset time points in a preset time period is arranged into an input vector according to a time dimension, and then a plurality of residual CPU capacity feature vectors are obtained through a multi-scale neighborhood feature extraction module; calculating transfer matrixes between every two residual CPU capacity feature vectors in the residual CPU capacity feature vectors to obtain a plurality of transfer matrixes; the transfer matrixes are aggregated into three-dimensional input tensors according to channel dimensions, and then a convolutional neural network model serving as a feature extractor is used for obtaining a CPU residual capacity correlation feature map; the CPU residual capacity associated feature map is passed through a non-local neural network model to obtain a decoding feature map; performing feature distribution modulation on the decoding feature map to obtain an optimized decoding feature map; and performing decoding regression on the optimized decoding characteristic map through a decoder to obtain a decoding value used for representing the predicted value of the CPU capacity of the processor system.

Having described the basic principles of the present application, various non-limiting embodiments of the present application will now be described in detail with reference to the accompanying drawings.

An exemplary method is: FIG. 1 is a flow chart of a method for CPU capacity prediction for a processor architecture according to an embodiment of the present application. As shown in fig. 1, a CPU capacity prediction method for a processor architecture according to an embodiment of the present application includes the steps of: s110, acquiring residual CPU capacities of a plurality of CPU units in a processor system at a plurality of preset time points in a preset time period; s120, arranging the residual CPU capacity of each CPU unit at a plurality of preset time points in a preset time period into an input vector according to a time dimension, and then obtaining a plurality of residual CPU capacity feature vectors through a multi-scale neighborhood feature extraction module; s130, calculating transfer matrixes among every two residual CPU capacity feature vectors in the residual CPU capacity feature vectors to obtain a plurality of transfer matrixes; s140, aggregating the transfer matrixes into a three-dimensional input tensor according to channel dimensions, and then obtaining a CPU residual capacity correlation characteristic diagram through a convolutional neural network model serving as a characteristic extractor; s150, the CPU residual capacity associated feature map is passed through a non-local neural network model to obtain a decoding feature map; s160, performing feature distribution modulation on the decoding feature map to obtain an optimized decoding feature map; and S170, carrying out decoding regression on the optimized decoding characteristic map through a decoder to obtain a decoding value used for representing the predicted value of the CPU capacity of the processor system.

Fig. 2 is a schematic architecture diagram of a CPU capacity prediction method for a processor architecture according to an embodiment of the present application. As shown in fig. 2, in the network configuration, first, remaining CPU capacities of a plurality of CPU units in a processor system at a plurality of predetermined time points within a predetermined period of time are acquired; the residual CPU capacity of each CPU unit at a plurality of preset time points in a preset time period is arranged into an input vector according to a time dimension, and then a plurality of residual CPU capacity feature vectors are obtained through a multi-scale neighborhood feature extraction module; secondly, calculating transfer matrixes among every two residual CPU capacity feature vectors in the residual CPU capacity feature vectors to obtain a plurality of transfer matrixes; the transfer matrixes are aggregated into three-dimensional input tensors according to channel dimensions, and then a convolutional neural network model serving as a feature extractor is used for obtaining a CPU residual capacity correlation feature map; then, the CPU residual capacity associated feature map is passed through a non-local neural network model to obtain a decoding feature map; then, carrying out feature distribution modulation on the decoding feature map to obtain an optimized decoding feature map; further, the optimized decoding feature map is subjected to decoding regression by a decoder to obtain a decoded value representing a predicted value of the CPU capacity of the processor architecture.

Specifically, in step S110, the remaining CPU capacities of a plurality of CPU units in the processor architecture at a plurality of predetermined time points within a predetermined period of time are acquired. In view of the fact that the capacity of the CPU needs to be predicted in order to better control the capacity of the CPU, when the capacity of the CPU is actually predicted, the prediction can be performed by performing dynamic change analysis on the time dimension of the remaining CPU capacities of a plurality of CPU units in the processor system, in the technical scheme of the present application, first, the remaining CPU capacities of a plurality of predetermined time points of a plurality of CPU units in the processor system in a predetermined time period are obtained.

Specifically, in step S120, the remaining CPU capacities of the respective CPU units at a plurality of predetermined time points within a predetermined period of time are arranged as input vectors according to a time dimension, and then the input vectors are passed through a multi-scale neighborhood feature extraction module to obtain a plurality of remaining CPU capacity feature vectors. In the technical scheme of the application, the residual CPU capacities of the CPU units at a plurality of preset time points in the preset time period are further arranged into input vectors according to the time dimension and then subjected to feature mining in a multi-scale neighborhood feature extraction module, so that dynamic multi-scale neighborhood associated features of the residual CPU capacities of the CPU units in different time spans in the preset time period are extracted, and a plurality of residual CPU capacity feature vectors corresponding to the CPU units are obtained. In the technical solution of the present application, the arranging the remaining CPU capacities of the CPU units at a plurality of predetermined time points in a predetermined time period according to a time dimension into an input vector, and then obtaining a plurality of remaining CPU capacity feature vectors by using a multi-scale neighborhood feature extraction module includes: inputting the residual CPU capacity input vector into a first convolution layer of the multi-scale neighborhood feature extraction module to obtain a first neighborhood scale residual CPU capacity feature vector, wherein the first convolution layer is provided with a first one-dimensional convolution kernel with a first length; inputting the residual CPU capacity input vector into a second convolution layer of the multi-scale neighborhood feature extraction module to obtain a second neighborhood scale residual CPU capacity feature vector, wherein the second convolution layer is provided with a second one-dimensional convolution kernel with a second length, and the first length is different from the second length; and cascading the first neighborhood scale residual CPU capacity feature vector and the second neighborhood scale residual CPU capacity feature vector to obtain the plurality of residual CPU capacity feature vectors. Wherein, the multiscale neighborhood feature extraction module comprises: the device comprises a first convolution layer, a second convolution layer parallel to the first convolution layer and a cascade layer connected with the first convolution layer and the second convolution layer, wherein the first convolution layer uses a one-dimensional convolution kernel with a first scale, and the second convolution layer uses a one-dimensional convolution kernel with a second scale. More specifically, the inputting the residual CPU capacity input vector into the first convolution layer of the multi-scale neighborhood feature extraction module to obtain a first neighborhood-scale residual CPU capacity feature vector includes: performing one-dimensional convolution coding on the residual CPU capacity input vector by using a first convolution layer of the multi-scale neighborhood feature extraction module according to the following formula to obtain a residual CPU capacity feature vector of the first neighborhood scale; wherein, the formula is:

，

is a first convolution kernel parameter vector,

For a local vector matrix that operates with a convolution kernel,wfor the size of the first convolution kernel,Xrepresenting the remaining CPU capacity input vector; andthe step of inputting the residual CPU capacity input vector into the second convolution layer of the multi-scale neighborhood feature extraction module to obtain a second neighborhood-scale residual CPU capacity feature vector, includes: performing one-dimensional convolution coding on the residual CPU capacity input vector by using a second convolution layer of the multi-scale neighborhood feature extraction module according to the following formula to obtain a residual CPU capacity feature vector of the second neighborhood scale; wherein, the formula is:

，

for the second convolution layer parameter vector,

for the local vector matrix to operate with the convolution kernel, m is the size of the second convolution layer,Xrepresenting the remaining CPU capacity input vector; more specifically, in a specific example of the present application, the first neighborhood-scale residual CPU capacity feature vector and the second neighborhood-scale residual CPU capacity feature vector may be cascaded in a cascading manner to obtain the plurality of residual CPU capacity feature vectors, specifically: fusing the first neighborhood scale residual CPU capacity feature vector and the second neighborhood scale residual CPU capacity feature vector to obtain the plurality of residual CPU capacity feature vectors by the following formula; wherein, the formula is: / >

, wherein ,/>

Representing the first neighborhood scale residual CPU capacity feature vector,>

representing the second neighborhood scale residual CPU capacity feature vector,

representing a cascade function->

Representing the plurality of remaining CPU capacity feature vectors.

FIG. 3 is a flow chart of multi-scale neighborhood feature extraction in a CPU capacity prediction method for a processor architecture according to an embodiment of the present application. As shown in fig. 3, in the multi-scale neighborhood feature extraction process, the method includes: s210, inputting the residual CPU capacity input vector into a first convolution layer of the multi-scale neighborhood feature extraction module to obtain a first neighborhood scale residual CPU capacity feature vector, wherein the first convolution layer is provided with a first one-dimensional convolution kernel with a first length; s220, inputting the residual CPU capacity input vector into a second convolution layer of the multi-scale neighborhood feature extraction module to obtain a second neighborhood scale residual CPU capacity feature vector, wherein the second convolution layer is provided with a second one-dimensional convolution kernel with a second length, and the first length is different from the second length; and S230, cascading the first neighborhood scale residual CPU capacity feature vector and the second neighborhood scale residual CPU capacity feature vector to obtain a plurality of residual CPU capacity feature vectors.

Specifically, in step S130, a transfer matrix between every two remaining CPU capacity feature vectors of the plurality of remaining CPU capacity feature vectors is calculated to obtain a plurality of transfer matrices. It is contemplated that in the processor architecture, the CPU capacity of the processor architecture is related to the remaining CPU capacities of the plurality of CPU units therein, and that the remaining CPU capacities of the respective CPU units also have an associative relationship therebetween. That is, the correlation between the remaining CPU capacities of the respective CPU units determines the overall CPU capacity of the processor system, and if it is desired to accurately predict the CPU capacity of the processor system, it is necessary to perform feature mining of the correlation between the remaining CPU capacities of the respective CPU units. Specifically, in the technical scheme of the application, a transfer matrix between every two residual CPU capacity feature vectors in the multiple residual CPU capacity feature vectors is calculated, so as to represent relevance feature distribution information between residual CPU capacities of every two CPU units in the multiple CPU units, thereby obtaining multiple transfer matrices. Specifically, the calculating a transfer matrix between each two remaining CPU capacity feature vectors of the plurality of remaining CPU capacity feature vectors to obtain a plurality of transfer matrices includes: calculating transfer matrices between every two residual CPU capacity feature vectors in the residual CPU capacity feature vectors to obtain a plurality of transfer matrices according to the following formula; wherein, the formula is:

, wherein />

and />

Representing each two remaining CPU capacity feature vectors of the plurality of remaining CPU capacity feature vectors,/for each remaining CPU capacity feature vector>

Representing the plurality of transfer matrices.

Specifically, in step S140, the transfer matrices are aggregated into a three-dimensional input tensor according to the channel dimension, and then a convolutional neural network model serving as a feature extractor is used to obtain a CPU residual capacity correlation feature map. Further, after obtaining the relevance feature distribution information between the residual CPU capacities of each two CPU units in the plurality of CPU units, in order to explore the influence of the relevance feature of the residual CPU capacities of each CPU unit on the CPU capacity change of the processor system, in the technical scheme of the application, the plurality of transfer matrices are further aggregated into a three-dimensional input tensor according to the channel dimension, and then feature mining is performed in a convolutional neural network model serving as a feature extractor, so as to obtain a CPU residual capacity relevance feature map. In particular, here, the convolutional neural network model is a convolutional neural network model having a three-dimensional convolutional kernel, which is a three-dimensional convolutional kernel having W (width), H (height) and C (channel dimension), and the correlation of the remaining CPU capacities of the respective CPU units can be extracted using the convolutional neural network model having a three-dimensional convolutional kernel in a sample dimension with respect to the correlation variation characteristics of the CPU capacities of the processor system as a whole. Specifically, each layer of the convolutional neural network performs input data in forward transfer of the layer: using a convolution module to carry out three-dimensional convolution coding on input data by using a three-dimensional convolution check to obtain a convolution characteristic diagram; carrying out pooling treatment on the convolution feature map by using a pooling module to obtain a pooled feature map; using an activation module to perform nonlinear activation on the characteristic values of each position of the pooled characteristic map so as to obtain a CPU residual capacity associated characteristic map; the input of the first layer of the convolutional neural network is a three-dimensional input tensor obtained by aggregating the plurality of transfer matrixes according to channel dimensions, and the output of the last layer of the convolutional neural network is the CPU residual capacity correlation characteristic diagram.

Fig. 4 is a flowchart of convolutional neural network coding in a CPU capacity prediction method for a processor architecture according to an embodiment of the present application. As shown in fig. 4, in the encoding process of the convolutional neural network, the method includes: each layer of the convolutional neural network model using the feature extractor performs, in forward transfer of the layer, input data: s310, carrying out convolution processing on input data to obtain a convolution characteristic diagram; s320, pooling the convolution feature map based on a local feature matrix to obtain a pooled feature map; s330, performing nonlinear activation on the pooled feature map to obtain an activated feature map; the output of the last layer of the convolutional neural network serving as the feature extractor is the CPU residual capacity associated feature map, and the input of the first layer of the convolutional neural network serving as the feature extractor is the three-dimensional input tensor.

Specifically, in step S150, the CPU residual capacity related feature map is passed through a non-local neural network model to obtain a decoded feature map. It will be appreciated that since convolution is a typical local operation, it can only extract feature correlations of the remaining CPU capacity local to the processor architecture, and cannot be focused on global, affecting the CPU capacity prediction accuracy for the processor architecture. For the residual CPU capacity of each CPU unit, the correlation characteristic of the residual CPU capacity of each CPU unit forms the CPU capacity characteristic of the whole processor system, the residual CPU capacity characteristics of each CPU unit are not isolated, and the correlation among the residual CPU capacity characteristic distribution of each CPU unit generates a prospect target. Therefore, in the technical solution of the present application, in order to more accurately predict the CPU capacity of the processor system, a non-local neural network is used to further perform the CPU residual capacity related feature extraction of each CPU unit. That is, the CPU residual capacity correlation feature map is passed through a non-local neural network model to expand the feature receptive field through the non-local neural network model, thereby obtaining a decoded feature map. In particular, here, the non-local neural network captures hidden dependency information by calculating the similarity between the CPU residual capacity features of each CPU unit, so as to model the context features, so that the network focuses on global overall content between the CPU residual capacity features of each CPU unit, and further, the feature extraction capability of the backbone network is improved in decoding and prediction tasks.

Fig. 5 is a flow chart of non-local neural network encoding in a CPU capacity prediction method for a processor architecture according to an embodiment of the present application. As shown in fig. 5, in the non-local neural network encoding process, it includes: s410, respectively inputting the CPU residual capacity associated feature map into a first point convolution layer, a second point convolution layer and a third point convolution layer of the non-local neural network model to obtain a first feature map, a second feature map and a third feature map; s420, calculating a weighted sum of the first feature map and the second feature map according to positions to obtain an intermediate fusion feature map; s430, inputting the intermediate fusion feature map into a Softmax function to normalize feature values of each position in the intermediate fusion feature map so as to obtain a normalized intermediate fusion feature map; s440, calculating a weighted sum of the normalized intermediate fusion feature map and the third feature map according to positions to obtain a re-fusion feature map; s450, embedding a Gaussian similarity function into the re-fusion feature map to calculate the similarity between feature values of each position in the re-fusion feature map so as to obtain a global perception feature map; s460, passing the global perception feature map through a fourth point convolution layer of the non-local neural network model to obtain a channel-adjustment global perception feature map; and S470, calculating a weighted sum of the channel adjustment global perception feature map and the CPU residual capacity association feature map according to positions to obtain the decoding feature map.

Specifically, in step S160, the decoding profile is modulated to obtain an optimized decoding profile. In particular, in the technical solution of the present application, the multiple transfer matrices are aggregated into the three-dimensional input tensor according to the channel dimension, the CPU residual capacity correlation feature map is obtained through a convolutional neural network model serving as a feature extractor, and the decoding feature map is obtained through a non-local neural network model, so that the decoding feature map includes rich local and global features in the channel arrangement dimension between the time sequence transfer features of each CPU unit, that is, local and global correlation features in the instant transfer-channel cross dimension. But on the other hand, the decoding feature map expresses rich local and global associated features in the cross dimension, so that the fitting burden between the decoding feature map and the weight matrix of the decoder is heavy when the decoding regression is carried out through the decoder, and the training speed of the decoder and the accuracy of the decoding regression result are affected. Thus, the decoded feature map is preferably subjected to regression characterization flattening, specifically expressed as:

，

wherein

Is a predetermined characteristic value of said decoding profile, for example>

Is the mean value of all feature values of the decoded feature map, and +.>

Is the scale of the decoding profile, +.>

Is a predetermined feature value of the optimized decoding feature map. Here, the flattening of the regression characterization of the decoded feature map flattens the finite polyhedral manifold for the regression characterization of the feature distribution in the high-dimensional feature space while maintaining the inherent distance between the planes of the manifold and intuitively avoiding intersection based on space, which essentially decomposes the finite polyhedral manifold into a cube lattice based on right-angle plane intersection and with vertices, thereby obtaining flattened "slice" aggregations of the regression planes, i.e., aggregations of the feature distribution of the decoded feature map along each dimension. Therefore, the fitting performance of the decoding feature map to the weight matrix of the decoder is enhanced, and the training speed of the decoding regression of the decoding feature map through the decoder and the accuracy of the decoding result are improved. Therefore, the CPU capacity of the processor system can be accurately predicted, so that the CPU capacity is better controlled, overload of the CPU is prevented, or the performance of the CPU cannot meet the processing task requirement, and the performance stability and reliability of the processor system are maintained.

Specifically, in step S170, the optimized decoding feature map is subjected to decoding regression by a decoder to obtain a decoded value representing a predicted value of the CPU capacity of the processor architecture. In the technical scheme of the application, the optimized decoding characteristic diagram is subjected to decoding regression in a decoder to obtain the useful characteristic diagramDecoding values representing predicted values of CPU capacities of the processor architecture. In this way, the CPU capacity of the processor system can be accurately predicted to prevent overload or performance failure to meet processing task requirements, so that the performance stability and reliability of the processor system can be maintained. In a specific example, said performing a decoding regression on said optimized decoding profile by a decoder to obtain a decoded value representing a predicted value of CPU capacity of said processor architecture comprises: performing decoding regression on the optimized decoding feature map by a decoder using the decoder in the following formula to obtain a decoded value representing a predicted value of the CPU capacity of the processor architecture; wherein, the formula is:

, wherein />

Representing the optimized decoding profile, +_>

Is the value of the said decoding which is to be used,

is a weight matrix, < > >

Representing matrix multiplication.

In summary, a CPU capacity prediction method for a processor architecture according to an embodiment of the present application is explained, which mines a dynamic correlation feature of the remaining CPU capacities of respective CPU units in a time dimension and a correlation relationship between the remaining CPU capacities of the respective CPU units by using a deep neural network model based on deep learning. Therefore, the CPU capacity can be accurately predicted, so that the CPU capacity is better controlled, overload is prevented, or the performance of the CPU can not meet the processing task requirement, and the performance stability and reliability of a processor system are maintained.

Exemplary System: FIG. 6 is a block diagram of a CPU capacity prediction system for a processor architecture according to an embodiment of the present application. As shown in fig. 6, a CPU capacity prediction system 300 for a processor architecture according to an embodiment of the present application includes: a capacity information acquisition module 310; a multi-scale neighborhood feature extraction module 320; a transfer module 330; a convolution module 340; a non-local neural network module 350; a feature distribution modulation module 360; and, a decode regression module 370.

The capacity information obtaining module 310 is configured to obtain remaining CPU capacities of a plurality of CPU units in the processor system at a plurality of predetermined time points within a predetermined time period; the multi-scale neighborhood feature extraction module 320 is configured to arrange the remaining CPU capacities of the CPU units at a plurality of predetermined time points within a predetermined time period into input vectors according to a time dimension, and then obtain a plurality of remaining CPU capacity feature vectors through the multi-scale neighborhood feature extraction module; the transfer module 330 is configured to calculate a transfer matrix between every two remaining CPU capacity feature vectors in the plurality of remaining CPU capacity feature vectors to obtain a plurality of transfer matrices; the convolution module 340 is configured to aggregate the plurality of transfer matrices into a three-dimensional input tensor according to a channel dimension, and then obtain a CPU residual capacity correlation feature map through a convolutional neural network model serving as a feature extractor; the non-local neural network module 350 is configured to pass the CPU residual capacity correlation feature map through a non-local neural network model to obtain a decoding feature map; the feature distribution modulation module 360 is configured to perform feature distribution modulation on the decoded feature map to obtain an optimized decoded feature map; and the decoding regression module 370 is configured to perform decoding regression on the optimized decoding feature map through a decoder to obtain a decoded value that is used to represent the predicted value of the CPU capacity of the processor architecture.

In one example, in the above CPU capacity prediction system 300 for a processor architecture, the multi-scale neighborhood feature extraction module 320 is further configured to: inputting the residual CPU capacity input vector into a first convolution layer of the multi-scale neighborhood feature extraction module to obtain a first neighborhood scale residual CPU capacity feature vector, wherein the first convolution layer is provided with a first one-dimensional convolution kernel with a first length; inputting the residual CPU capacity input vector into the multi-scale neighborhood feature extractionA second convolution layer of the module is used for obtaining a residual CPU capacity characteristic vector of a second neighborhood scale, wherein the second convolution layer is provided with a second one-dimensional convolution kernel of a second length, and the first length is different from the second length; and cascading the first neighborhood scale residual CPU capacity feature vector and the second neighborhood scale residual CPU capacity feature vector to obtain the plurality of residual CPU capacity feature vectors. Wherein, the multiscale neighborhood feature extraction module comprises: the device comprises a first convolution layer, a second convolution layer parallel to the first convolution layer and a cascade layer connected with the first convolution layer and the second convolution layer, wherein the first convolution layer uses a one-dimensional convolution kernel with a first scale, and the second convolution layer uses a one-dimensional convolution kernel with a second scale. More specifically, the inputting the residual CPU capacity input vector into the first convolution layer of the multi-scale neighborhood feature extraction module to obtain a first neighborhood-scale residual CPU capacity feature vector includes: performing one-dimensional convolution coding on the residual CPU capacity input vector by using a first convolution layer of the multi-scale neighborhood feature extraction module according to the following formula to obtain a residual CPU capacity feature vector of the first neighborhood scale; wherein, the formula is:

，

for the first convolution kernel parameter vector,

for a local vector matrix that operates with a convolution kernel,wfor the size of the first convolution kernel,Xrepresenting the remaining CPU capacity input vector; and inputting the residual CPU capacity input vector into a second convolution layer of the multi-scale neighborhood feature extraction module to obtain a second neighborhood-scale residual CPU capacity feature vector, including: a second convolution layer using the multi-scale neighborhood feature extraction module pairs the residual C with the following formulaCarrying out one-dimensional convolution coding on the PU capacity input vector to obtain a residual CPU capacity characteristic vector of the second neighborhood scale; wherein, the formula is:

，

for the second convolution layer parameter vector,

In one example, in the above CPU capacity prediction system 300 for a processor architecture, the transfer module 330 is further configured to: calculating transfer matrices between every two residual CPU capacity feature vectors in the residual CPU capacity feature vectors to obtain a plurality of transfer matrices according to the following formula; wherein, the formula is:

, wherein

and />

Representing the plurality of transfer matrices.

In one example, in the above CPU capacity prediction system 300 for a processor architecture, the convolution module 340 is further configured to: each layer of the convolutional neural network model using the feature extractor performs, in forward transfer of the layer, input data: carrying out convolution processing on input data to obtain a convolution characteristic diagram; pooling the convolution feature images based on the local feature matrix to obtain pooled feature images; performing nonlinear activation on the pooled feature map to obtain an activated feature map; the output of the last layer of the convolutional neural network serving as the feature extractor is the CPU residual capacity associated feature map, and the input of the first layer of the convolutional neural network serving as the feature extractor is the three-dimensional input tensor.

In one example, in the above CPU capacity prediction system 300 for a processor architecture, the non-local neural network module 350 is further configured to: respectively inputting the CPU residual capacity associated feature map into a first point convolution layer, a second point convolution layer and a third point convolution layer of the non-local neural network model to obtain a first feature map, a second feature map and a third feature map; calculating a weighted sum of the first feature map and the second feature map according to positions to obtain an intermediate fusion feature map; inputting the intermediate fusion feature map into a Softmax function to normalize feature values of each position in the intermediate fusion feature map so as to obtain a normalized intermediate fusion feature map; calculating a weighted sum of the normalized intermediate fusion feature map and the third feature map by position to obtain a re-fusion feature map; embedding a Gaussian similarity function into the re-fusion feature map to calculate the similarity between feature values of each position in the re-fusion feature map so as to obtain a global perception feature map; passing the global perception feature map through a fourth point convolution layer of the non-local neural network model to obtain a channel-adjustment global perception feature map; and calculating a weighted sum of the channel adjustment global perception feature map and the CPU residual capacity association feature map according to positions to obtain the decoding feature map.

In one example, in the above CPU capacity prediction system 300 for a processor architecture, the feature distribution modulation module 360 is further configured to: performing feature distribution modulation on the decoding feature map by using the following formula to obtain the optimized decoding feature map; wherein, the formula is:

，

wherein

Is a predetermined characteristic value of said decoding profile, for example>

Is the mean value of all feature values of the decoded feature map, and +.>

Is the scale of the decoding profile, +.>

Is a predetermined feature value of the optimized decoding feature map.

In one example, in the above CPU capacity prediction system 300 for a processor architecture, the decoding regression module 370 is further configured to: performing decoding regression on the optimized decoding feature map by a decoder using the decoder in the following formula to obtain a decoded value representing a predicted value of the CPU capacity of the processor architecture; wherein, the formula is:

, wherein />

Representing the optimized decoding profile, +_ >

Is the decoded value,/->

Is a weight matrix, < >>

Representing matrix multiplication.

In summary, the CPU capacity prediction system 300 for a processor architecture according to the embodiment of the present application is illustrated by mining the dynamic correlation characteristics of the remaining CPU capacities of the respective CPU units in the time dimension and the correlation relationship between the remaining CPU capacities of the respective CPU units by using a deep neural network model based on deep learning. Therefore, the CPU capacity can be accurately predicted, so that the CPU capacity is better controlled, overload is prevented, or the performance of the CPU can not meet the processing task requirement, and the performance stability and reliability of a processor system are maintained.

As described above, the CPU capacity prediction system for a processor architecture according to the embodiments of the present application can be implemented in various terminal devices. In one example, the CPU capacity prediction system 300 for a processor architecture according to embodiments of the present application may be integrated into a terminal device as one software module and/or hardware module. For example, the CPU capacity prediction system 300 for a processor architecture may be a software module in the operating system of the terminal device, or may be an application developed for the terminal device; of course, the CPU capacity prediction system 300 for a processor architecture could equally be one of the numerous hardware modules of the terminal device.

Alternatively, in another example, the CPU capacity prediction system 300 for a processor architecture and the terminal device may be separate devices, and the CPU capacity prediction system 300 for a processor architecture may be connected to the terminal device through a wired and/or wireless network and transmit the interactive information in a agreed data format.

Exemplary electronic device: next, an electronic device according to an embodiment of the present application is described with reference to fig. 7.

Fig. 7 illustrates a block diagram of an electronic device according to an embodiment of the present application.

As shown in fig. 7, the electronic device 10 includes one or more processors 11 and a memory 12.

The processor 11 may be a Central Processing Unit (CPU) or other form of processing unit having data processing and/or instruction execution capabilities, and may control other components in the electronic device 10 to perform desired functions.

Memory 12 may include one or more computer program products that may include various forms of computer-readable storage media, such as volatile memory and/or non-volatile memory. The volatile memory may include, for example, random Access Memory (RAM) and/or cache memory (cache), and the like. The non-volatile memory may include, for example, read Only Memory (ROM), hard disk, flash memory, and the like. One or more computer program instructions may be stored on the computer readable storage medium that can be executed by the processor 11 to implement the functions in the CPU capacity prediction method for a processor architecture and/or other desired functions of the various embodiments of the present application as described above. Various content, such as an optimized classification characteristic map, may also be stored in the computer-readable storage medium.

In one example, the electronic device 10 may further include: an input device 13 and an output device 14, which are interconnected by a bus system and/or other forms of connection mechanisms (not shown).

The input means 13 may comprise, for example, a keyboard, a mouse, etc.

The output device 14 can output various information including a decoded value and the like to the outside. The output means 14 may include, for example, a display, speakers, a printer, and a communication network and remote output devices connected thereto, etc.

Of course, only some of the components of the electronic device 10 that are relevant to the present application are shown in fig. 7 for simplicity, components such as buses, input/output interfaces, etc. are omitted. In addition, the electronic device 10 may include any other suitable components depending on the particular application.

Exemplary computer program product and computer readable storage Medium: in addition to the methods and apparatus described above, embodiments of the present application may also be a computer program product comprising computer program instructions which, when executed by a processor, cause the processor to perform steps in the functions described in the above "exemplary methods" section of the present specification in a CPU capacity prediction method for a processor architecture according to various embodiments of the present application.

The computer program product may write program code for performing the operations of embodiments of the present application in any combination of one or more programming languages, including an object oriented programming language such as Java, C++ or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computing device, partly on the user's device, as a stand-alone software package, partly on the user's computing device, partly on a remote computing device, or entirely on the remote computing device or server.

Furthermore, embodiments of the present application may also be a computer-readable storage medium, having stored thereon computer program instructions that, when executed by a processor, cause the processor to perform steps in the functions in the CPU capacity prediction method for a processor architecture according to various embodiments of the present application described in the "exemplary method" section of the present specification.

The computer readable storage medium may employ any combination of one or more readable media. The readable medium may be a readable signal medium or a readable storage medium. The readable storage medium may include, for example, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or a combination of any of the foregoing. More specific examples (a non-exhaustive list) of the readable storage medium would include the following: an electrical connection having one or more wires, a portable disk, a hard disk, random Access Memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

The basic principles of the present application have been described above in connection with specific embodiments, however, it should be noted that the advantages, benefits, effects, etc. mentioned in the present application are merely examples and not limiting, and these advantages, benefits, effects, etc. are not to be considered as necessarily possessed by the various embodiments of the present application. Furthermore, the specific details disclosed herein are for purposes of illustration and understanding only, and are not intended to be limiting, as the application is not intended to be limited to the details disclosed herein as such.

The block diagrams of the devices, apparatuses, devices, systems referred to in this application are only illustrative examples and are not intended to require or imply that the connections, arrangements, configurations must be made in the manner shown in the block diagrams. As will be appreciated by one of skill in the art, the devices, apparatuses, devices, systems may be connected, arranged, configured in any manner. Words such as "including," "comprising," "having," and the like are words of openness and mean "including but not limited to," and are used interchangeably therewith. The terms "or" and "as used herein refer to and are used interchangeably with the term" and/or "unless the context clearly indicates otherwise. The term "such as" as used herein refers to, and is used interchangeably with, the phrase "such as, but not limited to.

It is also noted that in the apparatus, devices and methods of the present application, the components or steps may be disassembled and/or assembled. Such decomposition and/or recombination should be considered as equivalent to the present application.

The previous description of the disclosed aspects is provided to enable any person skilled in the art to make or use the present application. Various modifications to these aspects will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other aspects without departing from the scope of the application. Thus, the present application is not intended to be limited to the aspects shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

The foregoing description has been presented for purposes of illustration and description. Furthermore, this description is not intended to limit the embodiments of the application to the form disclosed herein. Although a number of example aspects and embodiments have been discussed above, a person of ordinary skill in the art will recognize certain variations, modifications, alterations, additions, and subcombinations thereof.

Claims

1. A method for CPU capacity prediction for a processor architecture, comprising:

obtaining residual CPU capacities of a plurality of CPU units in a processor system at a plurality of preset time points in a preset time period;

Residual CPU capacity of each CPU unit at a plurality of preset time points in a preset time period is arranged into an input vector according to a time dimension, and then a plurality of residual CPU capacity feature vectors are obtained through a multi-scale neighborhood feature extraction module;

calculating transfer matrixes between every two residual CPU capacity feature vectors in the residual CPU capacity feature vectors to obtain a plurality of transfer matrixes;

the transfer matrixes are aggregated into three-dimensional input tensors according to channel dimensions, and then a convolutional neural network model serving as a feature extractor is used for obtaining a CPU residual capacity correlation feature map;

the CPU residual capacity associated feature map is passed through a non-local neural network model to obtain a decoding feature map;

performing feature distribution modulation on the decoding feature map to obtain an optimized decoding feature map; and

performing decoding regression on the optimized decoding feature map through a decoder to obtain a decoding value used for representing a predicted value of the CPU capacity of the processor system;

wherein, the CPU residual capacity associated feature map is passed through a non-local neural network model to obtain a decoding feature map, comprising:

respectively inputting the CPU residual capacity associated feature map into a first point convolution layer, a second point convolution layer and a third point convolution layer of the non-local neural network model to obtain a first feature map, a second feature map and a third feature map;

Calculating a weighted sum of the first feature map and the second feature map according to positions to obtain an intermediate fusion feature map;

inputting the intermediate fusion feature map into a Softmax function to normalize feature values of each position in the intermediate fusion feature map so as to obtain a normalized intermediate fusion feature map;

calculating a weighted sum of the normalized intermediate fusion feature map and the third feature map by position to obtain a re-fusion feature map;

embedding a Gaussian similarity function into the re-fusion feature map to calculate the similarity between feature values of each position in the re-fusion feature map so as to obtain a global perception feature map;

passing the global perception feature map through a fourth point convolution layer of the non-local neural network model to obtain a channel-adjustment global perception feature map; and

and calculating a weighted sum of the channel adjustment global perception feature map and the CPU residual capacity association feature map according to positions to obtain the decoding feature map.

2. The CPU capacity prediction method for a processor architecture of claim 1, wherein the multi-scale neighborhood feature extraction module comprises: the device comprises a first convolution layer, a second convolution layer parallel to the first convolution layer and a cascade layer connected with the first convolution layer and the second convolution layer, wherein the first convolution layer uses a one-dimensional convolution kernel with a first scale, and the second convolution layer uses a one-dimensional convolution kernel with a second scale.

3. The method for predicting CPU capacity of a processor architecture according to claim 2, wherein the arranging the remaining CPU capacities of each of the CPU units at a plurality of predetermined time points within a predetermined time period as an input vector according to a time dimension and then passing through a multi-scale neighborhood feature extraction module to obtain a plurality of remaining CPU capacity feature vectors comprises:

inputting the residual CPU capacity input vector into a first convolution layer of the multi-scale neighborhood feature extraction module to obtain a first neighborhood scale residual CPU capacity feature vector, wherein the first convolution layer is provided with a first one-dimensional convolution kernel with a first length;

inputting the residual CPU capacity input vector into a second convolution layer of the multi-scale neighborhood feature extraction module to obtain a second neighborhood scale residual CPU capacity feature vector, wherein the second convolution layer is provided with a second one-dimensional convolution kernel with a second length, and the first length is different from the second length; and

and cascading the first neighborhood scale residual CPU capacity feature vector and the second neighborhood scale residual CPU capacity feature vector to obtain a plurality of residual CPU capacity feature vectors.

4. The method for CPU capacity prediction for a processor architecture according to claim 3, wherein,

The inputting the residual CPU capacity input vector into the first convolution layer of the multi-scale neighborhood feature extraction module to obtain a first neighborhood-scale residual CPU capacity feature vector includes: performing one-dimensional convolution coding on the residual CPU capacity input vector by using a first convolution layer of the multi-scale neighborhood feature extraction module according to the following formula to obtain a residual CPU capacity feature vector of the first neighborhood scale;

wherein, the formula is:

，

wherein ,ais the first convolution kernelxWidth in the direction,

For the first convolution kernel parameter vector, +.>

For a local vector matrix that operates with a convolution kernel,wfor the size of the first convolution kernel,Xrepresenting the remaining CPU capacity input vector; and inputting the residual CPU capacity input vector into a second convolution layer of the multi-scale neighborhood feature extraction module to obtain a second neighborhood-scale residual CPU capacity feature vector, including: performing one-dimensional convolution coding on the residual CPU capacity input vector by using a second convolution layer of the multi-scale neighborhood feature extraction module according to the following formula to obtain a residual CPU capacity feature vector of the second neighborhood scale;

wherein, the formula is:

，

wherein b is the second convolution kernel xWidth in the direction,

For a second convolution kernel parameter vector, +.>

For the local vector matrix to operate with the convolution kernel function, m is the size of the second convolution kernel,Xrepresenting the remaining CPU capacity input vector.

5. The method of CPU capacity prediction for a processor architecture as claimed in claim 4, wherein said calculating a transition matrix between each two of said plurality of remaining CPU capacity feature vectors to obtain a plurality of transition matrices comprises: calculating transfer matrices between every two residual CPU capacity feature vectors in the residual CPU capacity feature vectors to obtain a plurality of transfer matrices according to the following formula;

wherein, the formula is:

，

wherein

and />

Representing each two remaining CPU capacity feature vectors of the plurality of remaining CPU capacity feature vectors,

representing the plurality of transfer matrices.

6. The method for predicting CPU capacity of a processor architecture according to claim 5, wherein the aggregating the plurality of transfer matrices into a three-dimensional input tensor according to a channel dimension and then obtaining a CPU residual capacity correlation feature map by using a convolutional neural network model as a feature extractor comprises: each layer of the convolutional neural network model using the feature extractor performs, in forward transfer of the layer, input data:

Carrying out convolution processing on input data to obtain a convolution characteristic diagram;

pooling the convolution feature images based on the local feature matrix to obtain pooled feature images; and

non-linear activation is carried out on the pooled feature map so as to obtain an activated feature map;

the output of the last layer of the convolutional neural network serving as the feature extractor is the CPU residual capacity associated feature map, and the input of the first layer of the convolutional neural network serving as the feature extractor is the three-dimensional input tensor.

7. The method for CPU capacity prediction in a processor architecture according to claim 6, wherein said performing feature distribution modulation on said decoded feature map to obtain an optimized decoded feature map comprises:

performing feature distribution modulation on the decoding feature map by using the following formula to obtain the optimized decoding feature map;

wherein, the formula is:

，

wherein

Is a predetermined characteristic value of said decoding profile, for example>

Is the mean value of all feature values of the decoded feature map, and +.>

Is the scale of the decoding profile, +.>

Is an exponential operation of a value representing a natural exponential function value raised to a power by said value, + >

Is a predetermined feature value of the optimized decoding feature map.

8. The CPU capacity prediction method for a processor architecture according to claim 7, wherein said performing decoding regression on the optimized decoding profile by a decoder to obtain a decoded value representing a predicted value of the CPU capacity of the processor architecture comprises: performing decoding regression on the optimized decoding feature map by a decoder using the decoder in the following formula to obtain a decoded value representing a predicted value of the CPU capacity of the processor architecture;

wherein, the formula is:

, wherein />

Representing the optimized decoding profile, +_>

Is the decoded value,/->

Is a weight matrix, < >>

Representing matrix multiplication.

9. A CPU capacity prediction system for a processor architecture, comprising:

the capacity information acquisition module is used for acquiring the residual CPU capacities of a plurality of CPU units in the processor system at a plurality of preset time points in a preset time period;

the multi-scale neighborhood feature extraction module is used for arranging the residual CPU capacity of each CPU unit at a plurality of preset time points in a preset time period into an input vector according to a time dimension, and then obtaining a plurality of residual CPU capacity feature vectors through the multi-scale neighborhood feature extraction module;

The transfer module is used for calculating transfer matrixes between every two residual CPU capacity feature vectors in the residual CPU capacity feature vectors to obtain a plurality of transfer matrixes;

the convolution module is used for aggregating the transfer matrixes into a three-dimensional input tensor according to channel dimensions and then obtaining a CPU residual capacity correlation characteristic diagram through a convolution neural network model serving as a characteristic extractor;

the non-local neural network module is used for enabling the CPU residual capacity associated feature map to pass through a non-local neural network model to obtain a decoding feature map;

the feature distribution modulation module is used for carrying out feature distribution modulation on the decoding feature map so as to obtain an optimized decoding feature map; and

the decoding regression module is used for carrying out decoding regression on the optimized decoding characteristic diagram through a decoder so as to obtain a decoding value used for representing the predicted value of the CPU capacity of the processor system;

wherein, the non-local neural network module is used for: respectively inputting the CPU residual capacity associated feature map into a first point convolution layer, a second point convolution layer and a third point convolution layer of the non-local neural network model to obtain a first feature map, a second feature map and a third feature map; calculating a weighted sum of the first feature map and the second feature map according to positions to obtain an intermediate fusion feature map; inputting the intermediate fusion feature map into a Softmax function to normalize feature values of each position in the intermediate fusion feature map so as to obtain a normalized intermediate fusion feature map; calculating a weighted sum of the normalized intermediate fusion feature map and the third feature map by position to obtain a re-fusion feature map; embedding a Gaussian similarity function into the re-fusion feature map to calculate the similarity between feature values of each position in the re-fusion feature map so as to obtain a global perception feature map; passing the global perception feature map through a fourth point convolution layer of the non-local neural network model to obtain a channel-adjustment global perception feature map; and calculating a weighted sum of the channel adjustment global perception feature map and the CPU residual capacity association feature map according to positions to obtain the decoding feature map.