CN115810638A

CN115810638A - Display substrate and display module

Info

Publication number: CN115810638A
Application number: CN202310025499.0A
Authority: CN
Inventors: 王梦奇; 吴建鹏; 于子阳; 张跳梅; 陈文波; 蒋志亮; 胡明; 邱海军
Original assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd
Priority date: 2023-01-09
Filing date: 2023-01-09
Publication date: 2023-03-17

Abstract

A display substrate and a display module are provided. The display substrate comprises a display area and a binding area positioned on one side of the display area; the binding area comprises a bending area and a binding pin area which are sequentially arranged along the direction far away from the display area; the bending area is configured to bend the binding area to the back of the display area, the binding pin area comprises a plurality of binding pads, and the binding pads are configured to be bound and connected with the flexible circuit board; the display substrate includes a second power line configured to supply a low-level signal to the display substrate, the second power line including a first sub power line and a second sub power line; the first sub power line is positioned in the bending area and comprises a plurality of first sub lines arranged in parallel and a plurality of second sub lines arranged in parallel, and the first sub lines and the second sub lines are mutually connected in a cross mode to form a grid-shaped structure; the second sub power line is configured to connect the first sub power line and the bonding pad.

Description

Display substrate and display module

Technical Field

The embodiment of the disclosure relates to the technical field of display, in particular to a display substrate and a display module.

Background

With the development of Display technology, the types of Display products are increasing, for example, liquid Crystal Displays (LCDs), organic Light-Emitting diodes (OLEDs), plasma Display Panels (PDPs), field Emission Displays (FEDs), and the like. The display substrate is provided with power lines including a first power line for providing a high level signal and a second power line for providing a low level signal.

The inventor of the present application finds that the voltage Drop (IR Drop) of the second power line on the display substrate is large, which is not favorable for reducing the display power consumption.

Disclosure of Invention

The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

The embodiment of the disclosure provides a display substrate and a display module to solve the problem that the voltage drop of a second power line on the display substrate is large.

In a first aspect, an embodiment of the present disclosure provides a display substrate, including a display area and a binding area located on one side of the display area; the binding area comprises a bending area and a binding pin area which are sequentially arranged along the direction far away from the display area; the bending area is configured to bend the binding area to the back of the display area, the binding pin area comprises a plurality of binding pads, and the binding pads are configured to be in binding connection with the flexible circuit board; the display substrate includes a second power line configured to provide a low-level signal to the display substrate, the second power line including a first sub power line and a second sub power line; the first sub power line is positioned in the bending area and comprises a plurality of first sub lines arranged in parallel and a plurality of second sub lines arranged in parallel, and the first sub lines and the second sub lines are mutually connected in a cross mode to form a grid-shaped structure; the second sub power line is configured to connect the first sub power line and the bonding pad.

In an exemplary embodiment, the first sub line extends in a first direction, the second sub line extends in a second direction, the first direction is perpendicular to the second direction, and the binding region is located at one side of the display region in the second direction.

In an exemplary embodiment, the second sub-line includes a second sub-connection line and a second sub-grid line, the second sub-connection line is configured to be connected to the second sub-power supply line, and the second sub-grid line is configured to be connected to the plurality of first sub-lines.

In an exemplary embodiment, the number of the second sub-connection lines is greater than the number of the second sub-grid lines.

In an exemplary embodiment, an orthographic projection of the second sub-grid line on the display substrate is located in an area surrounded by orthographic projections of the first sub-lines on the display substrate.

In an exemplary embodiment, the bonding area further includes a unit test area and a driving chip area, the unit test area is located on a side of the bending area away from the display area, and the driving chip area is located on a side of the unit test area away from the display area; the second sub power line is located in at least one of the first region and the second region; the orthographic projection of the first area on the display substrate is not overlapped with the orthographic projection of the unit test area and the orthographic projection of the driving chip area on the display substrate; the orthographic projection of the second area on the display substrate at least partially overlaps with the orthographic projection of the unit test area on the display substrate, and the orthographic projection of the second area on the display substrate at least partially overlaps with the orthographic projection of the driving chip area on the display substrate.

In an exemplary embodiment, the first region includes at least one of a first sub-region and a second sub-region; in the first direction, the first sub-area and the second sub-area are located at two opposite ends of the binding region, and the second region is located between the first sub-area and the second sub-area.

In an exemplary embodiment, the binding region further includes a routing region, and the routing region is located at a side of the bending region close to the display region; the bonding pads comprise a first bonding pad and a second bonding pad; one end of the second power line is connected with the second binding pad, and the other end of the second power line extends to the wiring area; the display substrate further comprises a first power line configured to provide a high-level signal to the display substrate, one end of the first power line is connected with the first bonding pad, and the other end of the first power line extends to the wiring area; and the orthographic projection of the first power line on the bending area does not overlap with the orthographic projection of the second sub-line on the bending area.

In an exemplary embodiment, an orthographic projection of the second sub-line on the bending area is located outside an area surrounded by an orthographic projection of the first power line on the bending area.

In an exemplary embodiment, the other end of the second power line extends to the routing area, and includes: one end of the second sub-connecting line extends to the wiring area.

In an exemplary embodiment, the second sub-line further includes a second sub-transmission line; the other end of second power cord extends to walk the line district, still includes: the other end of the second sub-transmission line extends to the wiring area.

In an exemplary embodiment, the first power line is located in at least one of a third area and a fourth area, and an orthographic projection of the third area on the display substrate does not overlap with an orthographic projection of the unit test area and the orthographic projection of the driving chip area on the display substrate; the orthographic projection of the fourth area on the display substrate at least partially overlaps with the orthographic projection of the unit test area on the display substrate, and the orthographic projection of the fourth area on the display substrate at least partially overlaps with the orthographic projection of the driving chip area on the display substrate.

In an exemplary embodiment, the third region includes at least one of a third sub-region and a fourth sub-region; in the first direction, the third sub-area and the fourth sub-area are located at two opposite ends of the binding area, and the fourth area is located between the third sub-area and the fourth sub-area; the fourth region includes at least one of fifth and sixth sub-regions adjacent to and on either side of the second region in the first direction.

In an exemplary embodiment, the display substrate further includes a data transmission line, one end of the data transmission line is connected to the driving chip region, and the other end of the data transmission line extends to the wiring region and is connected to a data signal line of the display region; the orthographic projection of the second sub-line on the bending area is positioned between the orthographic projections of the adjacent data transmission lines on the bending area.

In a second aspect, an embodiment of the present disclosure provides a display module including the display substrate as described above.

According to the display substrate provided by the embodiment of the disclosure, the second power line is arranged in the bending area, so that the area of the second power line on the display substrate is increased, the resistance of the second power line is reduced, the voltage drop of the second power line is further reduced, and the display power consumption of the display substrate is favorably reduced. The first sub power line located in the bending area is set to be the first sub power lines and the second sub power lines, the diameter of each sub power line is smaller, the sub power lines are not prone to breaking when the bending area bends, moreover, the first sub power lines and the second sub power lines are in cross connection, stability of signal transmission is guaranteed, and stable and normal work of the display substrate is guaranteed. The problem of the great voltage drop of the second power line on the display substrate is solved.

Other aspects will be apparent upon reading and understanding the attached drawings and detailed description.

Drawings

The accompanying drawings are included to provide a further understanding of the disclosed embodiments and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the example serve to explain the principles of the disclosure and not to limit the disclosure.

FIG. 1 is a schematic diagram of a display device;

FIG. 2 is a schematic diagram of an equivalent circuit of a pixel driving circuit;

FIG. 3 is a schematic view of a display substrate;

FIG. 4 is a schematic plan view of a display substrate;

FIG. 5 is a schematic diagram illustrating a top view of a display substrate in an exemplary embodiment;

FIG. 6 is a schematic diagram of a second sub-link line and a second sub-power line connected by a via in an exemplary embodiment;

fig. 7 is a schematic diagram illustrating a trace of a display substrate in an exemplary embodiment.

Reference numerals:

21-a first sub-line; 22-a second sub-power line; 23-a second sub-connection line;

24-a second sub-grid line; 25-a second sub-transmission line; 30-a first power line;

40-a data transmission line; 100-a display area; 200-a binding region;

201-an insulating layer; 202-a via; 210-a routing area;

220-a bending zone; 230-unit test area; 240-driving chip area;

250-binding a pin area; 251-a first sub-pad; 252-a second sub-pad;

253-a third sub-pad; 254-fourth sub-pad; 255-fifth sub-pad;

256-sixth sub-pad; 257 — seventh sub-pad; 300-bezel area 300;

310-second power supply loop line.

Detailed Description

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. Note that the embodiments may be implemented in a plurality of different forms. Those skilled in the art can readily appreciate the fact that the forms and details may be varied into a variety of forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be construed as being limited to the contents described in the following embodiments. The embodiments and features of the embodiments in the present disclosure may be arbitrarily combined with each other without conflict.

The scale of the drawings in this disclosure may be referenced in actual processing, but is not limited to such. For example: the width-length ratio of the channel, the thickness and the interval of each film layer and the width and the interval of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the drawings, and the drawings described in the present disclosure are only schematic structural views, and one embodiment of the present disclosure is not limited to the shapes, numerical values, and the like shown in the drawings.

The ordinal numbers such as "first", "second", and "third" in the present specification are provided to avoid confusion of the constituent elements, and are not limited in number.

In this specification, for convenience, the terms "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicating the orientation or positional relationship are used to explain the positional relationship of the constituent elements with reference to the drawings only for the convenience of description and simplification of description, but not to indicate or imply that the device or element referred to must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present disclosure. The positional relationship of the components is changed as appropriate in accordance with the direction in which each component is described. Therefore, the words described in the specification are not limited to the words described in the specification, and may be replaced as appropriate.

In this specification, the terms "mounted," "connected," and "connected" are to be construed broadly unless otherwise explicitly specified or limited. For example, it may be a fixed connection, or a removable connection, or an integral connection; can be a mechanical connection, or an electrical connection; either directly or indirectly through intervening components, or both may be interconnected. The specific meaning of the above terms in the present disclosure can be understood in specific instances by those of ordinary skill in the art.

In this specification, "electrically connected" includes a case where constituent elements are connected together by an element having some kind of electrical action. The "element having a certain electric function" is not particularly limited as long as it can transmit and receive an electric signal between connected components. Examples of the "element having some kind of electric function" include not only an electrode and a wiring but also a switching element such as a transistor, a resistor, an inductor, a capacitor, other elements having various functions, and the like.

In the present specification, "film" and "layer" may be interchanged with each other. For example, the "conductive layer" may be sometimes replaced with a "conductive film". Similarly, the "insulating film" may be replaced with an "insulating layer".

In the present specification, "parallel" means a state in which an angle formed by two straight lines is-10 ° or more and 10 ° or less, and therefore, includes a state in which the angle is-5 ° or more and 5 ° or less. The term "perpendicular" refers to a state in which the angle formed by two straight lines is 80 ° or more and 100 ° or less, and therefore includes a state in which the angle is 85 ° or more and 95 ° or less.

In this specification, a triangle, a rectangle, a trapezoid, a pentagon, a hexagon and the like are not strictly defined, and may be an approximate triangle, a rectangle, a trapezoid, a pentagon, a hexagon and the like, some small deformations caused by tolerances may exist, and a lead angle, an arc edge, deformation and the like may exist.

"about" in this disclosure means that the limits are not strictly defined, and that the numerical values are within the tolerances allowed for the process and measurement.

Fig. 1 is a schematic structural diagram of a display device. As shown in fig. 1, the display device may include a timing controller connected to the data driver, the scan driver and the light emitting driver, respectively, the data driver connected to the plurality of data signal lines (D1 to Dn), respectively, the scan driver connected to the plurality of scan signal lines (S1 to Sm), respectively, and the light emitting driver connected to the plurality of light emitting signal lines (E1 to Eo), respectively. The pixel array may include a plurality of sub-pixels Pxij, i and j may be natural numbers, at least one of the sub-pixels Pxij may include a circuit unit and a light emitting device connected to the circuit unit, and the circuit unit may include at least a pixel driving circuit connected to the scan signal line, the light emitting signal line and the data signal line, respectively. In an exemplary embodiment, the timing controller may supply a gray value and a control signal suitable for the specification of the data driver to the data driver, may supply a clock signal, a scan start signal, etc. suitable for the specification of the scan driver to the scan driver, and may supply a clock signal, an emission stop signal, etc. suitable for the specification of the light emitting driver to the light emitting driver. The data driver may generate data voltages to be supplied to the data signal lines D1, D2, D3, \8230; \8230, and Dn using the gray scale value and the control signal received from the timing controller. For example, the data driver may sample a gray value using a clock signal and apply a data voltage corresponding to the gray value to the data signal lines D1 to Dn in units of pixel rows, n may be a natural number. The scan driver may generate scan signals to be supplied to the scan signal lines S1, S2, S3, \8230 \ 8230;, and Sm by receiving a clock signal, a scan start signal, and the like from the timing controller. For example, the scan driver may sequentially supply scan signals having on-level pulses to the scan signal lines S1 to Sm. For example, the scan driver may be constructed in the form of a shift register, and may generate the scan signals in such a manner that scan start signals provided in the form of on-level pulses are sequentially transmitted to the next stage circuit under the control of a clock signal, and m may be a natural number. The light emitting driver may generate an emission signal to be supplied to the light emitting signal lines E1, E2, E3, \8230;, and Eo by receiving a clock signal, an emission stop signal, and the like from the timing controller. For example, the light emission driver may sequentially supply emission signals having off-level pulses to the light emission signal lines E1 to Eo. For example, the light emitting driver may be configured in the form of a shift register, and the emission signal may be generated in such a manner that the emission stop signal provided in the form of an off-level pulse is sequentially transmitted to the next stage circuit under the control of a clock signal, and o may be a natural number.

Fig. 2 is an equivalent circuit diagram of a pixel driving circuit. In an exemplary embodiment, the pixel driving circuit may be a 3T1C, 4T1C, 5T2C, 6T1C, or 7T1C structure. As shown in fig. 2, the pixel driving circuit may include 7 transistors (first to seventh transistors T1 to T7), and 1 storage capacitor C, and the pixel driving circuit includes a data signal terminal D, a first scan signal terminal S1, a second scan signal terminal S2, a light emitting signal terminal E, an initialization signal terminal INIT, a first power supply terminal VDD, and a second power supply terminal VSS, each of which is connected to a corresponding signal line or power supply line, respectively.

In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, and a third node N3. The first node N1 is respectively connected to a first pole of the third transistor T3, a second pole of the fourth transistor T4, and a second pole of the fifth transistor T5, the second node N2 is respectively connected to a second pole of the first transistor, a first pole of the second transistor T2, a control pole of the third transistor T3, and a second end of the storage capacitor C, and the third node N3 is respectively connected to a second pole of the second transistor T2, a second pole of the third transistor T3, and a first pole of the sixth transistor T6.

In an exemplary embodiment, a first terminal of the storage capacitor C is connected to the first power line VDD, and a second terminal of the storage capacitor C is connected to the second node N2, that is, the second terminal of the storage capacitor C is connected to the control electrode of the third transistor T3.

A control electrode of the first transistor T1 is connected to the second scanning signal line S2, a first electrode of the first transistor T1 is connected to the initial signal line INIT, and a second electrode of the first transistor is connected to the second node N2. When the on-level scan signal is applied to the second scan signal line S2, the first transistor T1 transfers an initialization voltage to the control electrode of the third transistor T3 to initialize the charge amount of the control electrode of the third transistor T3.

A control electrode of the second transistor T2 is connected to the first scan signal line S1, a first electrode of the second transistor T2 is connected to the second node N2, and a second electrode of the second transistor T2 is connected to the third node N3. When the on-level scan signal is applied to the first scan signal line S1, the second transistor T2 connects the control electrode of the third transistor T3 with the second electrode.

A control electrode of the third transistor T3 is connected to the second node N2, that is, the control electrode of the third transistor T3 is connected to the second end of the storage capacitor C, a first electrode of the third transistor T3 is connected to the first node N1, and a second electrode of the third transistor T3 is connected to the third node N3. The third transistor T3 may be referred to as a driving transistor, and the third transistor T3 determines an amount of driving current flowing between the first power supply line VDD and the second power supply line VSS according to a potential difference between a control electrode and a first electrode thereof.

A control electrode of the fourth transistor T4 is connected to the first scan signal line S1, a first electrode of the fourth transistor T4 is connected to the data signal terminal D, and a second electrode of the fourth transistor T4 is connected to the first node N1. When the on-level scan signal is applied to the first scan signal line S1, the fourth transistor T4 causes the data voltage of the data signal line D to be input to the pixel driving circuit.

A control electrode of the fifth transistor T5 is connected to the light emitting signal line E, a first electrode of the fifth transistor T5 is connected to the first power supply line VDD, and a second electrode of the fifth transistor T5 is connected to the first node N1. A control electrode of the sixth transistor T6 is connected to the light emitting signal line E, a first electrode of the sixth transistor T6 is connected to the third node N3, and a second electrode of the sixth transistor T6 is connected to the first electrode of the light emitting device. When the on-level light emission signal is applied to the light emission signal line E, the fifth transistor T5 and the sixth transistor T6 cause the light emitting device to emit light by forming a driving current path between the first power line VDD and the second power line VSS.

A control electrode of the seventh transistor T7 is connected to the second scanning signal line S2, a first electrode of the seventh transistor T7 is connected to the initialization signal line INIT, and a second electrode of the seventh transistor T7 is connected to the first electrode of the light emitting device. When the on-level scan signal is applied to the second scan signal line S2, the seventh transistor T7 transmits an initialization voltage to the first pole of the light emitting device to initialize or release the amount of charges accumulated in the first pole of the light emitting device.

In an exemplary embodiment, the light emitting device may be an OLED including a first electrode (anode), an organic light emitting layer, and a second electrode (cathode) stacked, or may be a QLED including a first electrode (anode), a quantum dot light emitting layer, and a second electrode (cathode) stacked.

In an exemplary embodiment, the second pole of the light emitting device is connected to a second power line VSS, the second power line VSS being a low level signal, and the first power line VDD being a high level signal. The first scanning signal end S1 is a scanning signal line in the pixel driving circuit of the display line, the second scanning signal end S2 is a scanning signal line in the pixel driving circuit of the previous display line, that is, for the nth display line, the first scanning signal end S1 is S (n), the second scanning signal end S2 is S (n-1), the second scanning signal end S2 of the display line and the first scanning signal end S1 in the pixel driving circuit of the previous display line are the same signal line, which can reduce the signal lines of the display panel and realize the narrow frame of the display panel.

In an exemplary embodiment, the first to seventh transistors T1 to T7 may be P-type transistors, or may be N-type transistors. The same type of transistors are adopted in the pixel driving circuit, so that the process flow can be simplified, the process difficulty of the display panel is reduced, and the yield of products is improved. In some possible implementations, the first to seventh transistors T1 to T7 may include P-type transistors and N-type transistors.

In an exemplary embodiment, the first to seventh transistors T1 to T7 may employ a low temperature polysilicon thin film transistor, or may employ an oxide thin film transistor, or may employ both a low temperature polysilicon thin film transistor and an oxide thin film transistor. The active layer of the Low Temperature polysilicon thin film transistor adopts Low Temperature polysilicon (LTPS for short), and the active layer of the Oxide thin film transistor adopts Oxide semiconductor (Oxide). The Low-Temperature Polycrystalline silicon thin film transistor has the advantages of high mobility, high charging speed and the like, the Oxide thin film transistor has the advantages of Low leakage current and the like, the Low-Temperature Polycrystalline silicon thin film transistor and the Oxide thin film transistor are integrated on one display substrate to form a Low-Temperature Polycrystalline Oxide (LTPO) display substrate, the advantages of the Low-Temperature Polycrystalline Oxide and the Oxide thin film transistor can be utilized, low-frequency driving can be realized, power consumption can be reduced, and display quality can be improved.

In an exemplary embodiment, taking the example that 7 transistors in the pixel driving circuit shown in fig. 2 are all P-type transistors, the working process of the pixel driving circuit may include:

in the first phase A1, referred to as a reset phase, the signal of the second scanning signal line S2 is a low-level signal, and the signals of the first scanning signal line S1 and the light-emitting signal line E are high-level signals. The signal of the second scanning signal terminal S2 is a low level signal, so that the first transistor T1 is turned on, the signal of the initial signal terminal INIT is provided to the second node N2, the storage capacitor C is initialized, and the original data voltage in the storage capacitor is cleared. The signals of the first scan signal terminal S1 and the light emitting signal terminal E are high level signals, so that the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 are turned off, and the OLED does not emit light at this stage.

In the second phase A2, referred to as a data writing phase or a threshold compensation phase, the signal of the first scan signal terminal S1 is a low level signal, the signals of the second scan signal terminal S2 and the light emitting signal terminal E are high level signals, and the data signal terminal D outputs a data voltage. At this stage, the second terminal of the storage capacitor C is at a low level, so the third transistor T3 is turned on. The signal of the first scan signal terminal S1 is a low level signal to turn on the second transistor T2, the fourth transistor T4, and the seventh transistor T7. The second transistor T2 and the fourth transistor T4 are turned on, so that the data voltage output by the data signal terminal D is provided to the second node N2 through the first node N1, the turned-on third transistor T3, the turned-on third node N3, and the turned-on second transistor T2, and a difference between the data voltage output by the data signal terminal D and the threshold voltage of the third transistor T3 is charged into the storage capacitor C, the voltage of the second terminal (the second node N2) of the storage capacitor C is Vd- | Vth |, vd is the data voltage output by the data signal terminal D, and Vth is the threshold voltage of the third transistor T3. The seventh transistor T7 is turned on to supply the initial voltage of the initial signal terminal INIT to the first electrode of the OLED, initialize (reset) the first electrode of the OLED, clear the pre-stored voltage therein, complete the initialization, and ensure that the OLED does not emit light. The signal of the second scan signal terminal S2 is a high level signal, turning off the first transistor T1. The signal of the emission signal terminal E is a high level signal, turning off the fifth transistor T5 and the sixth transistor T6.

In the third phase A3, referred to as a light-emitting phase, the signal of the light-emitting signal terminal E is a low-level signal, and the signals of the first scanning signal terminal S1 and the second scanning signal terminal S2 are high-level signals. The signal of the light-emitting signal terminal E is a low level signal, so that the fifth transistor T5 and the sixth transistor T6 are turned on, and the power voltage output by the first power terminal VDD provides a driving voltage to the first electrode of the OLED through the turned-on fifth transistor T5, the turned-on third transistor T3, and the turned-on sixth transistor T6, so as to drive the OLED to emit light.

During driving of the pixel driving circuit, the driving current flowing through the third transistor T3 (driving transistor) is determined by a voltage difference between the gate electrode and the first electrode thereof. Since the voltage of the second node N2 is Vd- | Vth |, the driving current of the third transistor T3 is:

I＝K*(Vgs-Vth) ² ＝K*[(Vdd-Vd+|Vth|)-Vth] ² ＝K*(Vdd-Vd) ²

where I is a driving current flowing through the third transistor T3, that is, a driving current driving the OLED, K is a constant, vgs is a voltage difference between the gate electrode and the first electrode of the third transistor T3, vth is a threshold voltage of the third transistor T3, vd is a data voltage output from the data signal terminal D, and Vdd is a power voltage received by the first power source terminal Vdd from the first power source line.

Fig. 3 is a schematic structural diagram of a display substrate. As shown in fig. 3, the display substrate may include a display area 100, a binding area 200 located at one side of the display area 100, and a bezel area 300 located at the other side of the display area 100. In an exemplary embodiment, the display area 100 may be a flat area including a plurality of subpixels Pxij constituting a pixel array, the plurality of subpixels Pxij being configured to display a moving picture or a still image, and the display area 100 may be referred to as an effective area (AA). In an exemplary embodiment, the display substrate may be a flexible substrate, and thus the display substrate may be deformable, such as rolled, bent, folded, or rolled.

In an exemplary embodiment, the bonding region 200 may include a routing region 210, a bending region 220, a Cell Test (CT) region 230, a driving chip region 240, and a bonding pin region 250, which are sequentially disposed in a direction away from the display region. The routing area 210 may be connected to the display area 100, and may include at least a plurality of data transmission lines configured to connect data signal lines of the display area. The bending region 220 is connected to the routing region 210, and may include a composite insulating layer provided with a groove configured to bend the binding region to the rear surface of the display region 100. The driving chip region 240 may include an Integrated Circuit (IC) configured to be connected to a plurality of data transmission lines. The Bonding Pad area 250 may include a Bonding Pad (Bonding Pad) configured to be bonded and connected to an external Flexible Printed Circuit (FPC).

Fig. 4 is a schematic plan view of a display substrate. As shown in fig. 4, the display substrate may include a plurality of pixel units P regularly arranged, at least one pixel unit P of the plurality of pixel units P may include a first subpixel P1 emitting light of a first color, a second subpixel P2 emitting light of a second color, and a third subpixel P3 emitting light of a third color, each of the subpixels may include a circuit unit and a light emitting device, the circuit unit may include a pixel driving circuit, and a scanning signal line, a data signal line, a light emitting signal line, and the like connected to the pixel driving circuit, and the pixel driving circuit may be configured to receive a data voltage transmitted from the data signal line and output a corresponding current to the light emitting device under the control of the scanning signal line and the light emitting signal line. The light emitting device in each sub-pixel is connected to the pixel driving circuit of the sub-pixel, and the light emitting device is configured to emit light with corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel.

In an exemplary embodiment, the first subpixel P1 may be a red subpixel (R) emitting red light, the second subpixel P2 may be a blue subpixel (B) emitting blue light, and the third subpixel P3 may be a green subpixel (G) emitting green light. In an exemplary embodiment, the shape of the sub-pixel in the pixel unit may be a rectangular shape, a diamond shape, a pentagonal shape, or a hexagonal shape. When the pixel unit includes three sub-pixels, the three sub-pixels may be arranged in a horizontal parallel manner, a vertical parallel manner, or a delta manner, which is not limited in this disclosure.

In an exemplary embodiment, a fourth sub-pixel may be further included in the pixel unit P, and the fourth sub-pixel may be a green sub-pixel (G) emitting green light, or the fourth sub-pixel may be a white sub-pixel (B) emitting white light. When the pixel unit includes four sub-pixels, the four sub-pixels may be arranged in a horizontal parallel manner, a vertical parallel manner, a Square (Square) manner, or a Diamond (Diamond) manner, and the disclosure is not limited thereto.

The embodiment of the disclosure provides a display substrate, which includes a display area and a binding area located at one side of the display area; the binding area comprises a bending area and a binding pin area which are sequentially arranged along the direction far away from the display area; the bending area is configured to bend the binding area to the back of the display area, the binding pin area comprises a plurality of binding pads, and the binding pads are configured to be in binding connection with the flexible circuit board; the display substrate includes a second power line configured to supply a low-level signal to the display substrate, the second power line including a first sub power line and a second sub power line; the first sub power line is positioned in the bending area and comprises a plurality of first sub lines arranged in parallel and a plurality of second sub lines arranged in parallel, and the plurality of first sub lines and the plurality of second sub lines are mutually connected in a cross mode to form a grid-shaped structure; the second sub power line is configured to connect the first sub power line and the bonding pad.

According to the display substrate provided by the embodiment of the disclosure, the second power line is arranged in the bending area, so that the area of the second power line on the display substrate is increased, the resistance of the second power line is reduced, the voltage drop of the second power line is further reduced, and the display power consumption of the display substrate is favorably reduced. The first sub power line located in the bending area is set to be the first sub lines and the second sub lines, so that the diameter of each sub line is smaller, the sub lines are not prone to breaking when being bent in the bending area, the first sub lines and the second sub lines are in cross connection with each other, the stability of signal transmission is guaranteed, and the display substrate can be guaranteed to work stably and normally.

In order to reduce the width of the frame of the display product, some technologies have proposed a structure in which data connection lines are located in a display area (FIAA), one end of each of the data connection lines is connected to a corresponding data signal line in the display area, and the other end of each of the data connection lines extends to a bonding area and is connected to an integrated circuit in the bonding area. In the technology, the fan-shaped oblique line does not need to be arranged in the binding region, so that the width of the fan-out region is reduced, and the width of the lower frame is effectively reduced. However, due to the narrowing of the lower frame, the area occupied by the second power line near the lower frame is small, so that the voltage drop of the second power line in the middle of the display substrate is large. By adopting the display substrate provided by the embodiment of the disclosure, a low potential signal can be directly provided to the second power line positioned in the middle of the display substrate through the latticed second power line arranged in the bending area, the voltage drop of the second power line in the middle of the display substrate can be effectively reduced, and a better effect is achieved on the display substrate adopting a FIAA structure.

In this embodiment, through setting up first sub-line and extending along first direction, the second sub-line extends along the second direction, and first direction perpendicular to second direction binds the regional one side that is located the display area along the second direction, and the axis of buckling of bending zone is parallel with first direction for first sub-line is parallel with the axis of buckling of bending zone, and first sub-line is difficult to break when buckling.

In an exemplary embodiment, the second sub-line includes a second sub-connection line and a second sub-grid line, the second sub-connection line is disposed to be connected to the second sub-power line, and the second sub-grid line is disposed to be connected to the plurality of first sub-lines.

In this embodiment, the second sub-link lines are connected to the plurality of first sub-lines and need to receive low-level signals from the bonding pads, and the provision of a larger number of second sub-link lines helps to ensure stable reception of low-level signals from the bonding pads. The second sub-grid lines can transmit signals among the plurality of first sub-lines, the task of directly receiving signals from the binding pads is not undertaken, the number of the wires in the bending area can be reduced by setting the second sub-grid lines with smaller number, the bending area is facilitated to be bent, and the risk of wire breakage can be reduced. The number of the second sub-connection lines and the number of the second sub-grid lines may be set as needed, which is not limited by the present disclosure.

In an exemplary embodiment, the orthographic projection of the second sub-grid line on the display substrate is located in an area surrounded by the orthographic projections of the first sub-lines on the display substrate.

In an exemplary embodiment, the first sub line and the second sub line are disposed in the same layer in a direction perpendicular to the display substrate, and the second sub line and the second sub power line are connected through a via hole.

In an exemplary embodiment, in a direction perpendicular to a display substrate, the display substrate includes a first source drain electrode layer and a second source drain electrode layer, the first sub-line and the second sub-line are located on the first source drain electrode layer, and the second sub-power line is located on the second source drain electrode layer; or the first sub-line and the second sub-line are positioned on the second source drain electrode layer, and the second sub-power line is positioned on the first source drain electrode layer.

In other embodiments, the display substrate may include other film layers, and the first sub power line and the second sub power line may be positioned as needed, which is not limited in the present disclosure.

In an exemplary embodiment, the bonding area further includes a unit test area and a driving chip area, the unit test area is located on one side of the bending area away from the display area, and the driving chip area is located on one side of the unit test area away from the display area; the second sub power line is positioned in at least one of the first area and the second area, and the orthographic projection of the first area on the display substrate is not overlapped with the orthographic projection of the unit test area and the orthographic projection of the driving chip area on the display substrate; the orthographic projection of the second area on the display substrate at least partially overlaps with the orthographic projection of the unit test area on the display substrate, and the orthographic projection of the second area on the display substrate at least partially overlaps with the orthographic projection of the driving chip area on the display substrate.

In an exemplary embodiment, the first region includes at least one of a first sub-region and a second sub-region; in the first direction, the first sub-area and the second sub-area are located at two opposite ends of the binding area, and the second area is located between the first sub-area and the second sub-area.

In an exemplary embodiment, the binding region further includes a routing region, and the routing region is located at a side of the bending region close to the display region; the bonding pads comprise a first bonding pad and a second bonding pad; one end of the second power line is connected with the second binding pad, and the other end of the second power line extends to the wiring area; the display substrate further comprises a first power line, the first power line is configured to provide a high-level signal to the display substrate, one end of the first power line is connected with the first binding pad, and the other end of the first power line extends to the wiring area; the orthographic projection of the first power line in the bending area does not overlap with the orthographic projection of the second sub-line in the bending area.

In this embodiment, there is not the overlap through setting up the orthographic projection of first power cord in the district of buckling and the orthographic projection of second sub-line in the district of buckling for in the direction of perpendicular to district of buckling, there is not the second sub-line in the position that first power cord passes through, has reduced the line quantity of walking in perpendicular to district of buckling, not only helps buckling the district of buckling, also can reduce the line and take place cracked risk in the district of buckling.

In an exemplary embodiment, an orthographic projection of the second sub-line on the bending region is located outside an area surrounded by an orthographic projection of the first power line on the bending region.

In an exemplary embodiment, the other end of the second power line extends to a wiring region, and includes: one end of the second sub-connecting line extends to the wiring area.

In an exemplary embodiment, the second sub-line further includes a second sub-transmission line; the other end of second power cord extends to the region of walking about the line, still includes: the other end of the second sub-transmission line extends to the wiring area. The second sub-transmission lines may be connected to the plurality of first sub-lines and extend to the routing area.

In this embodiment, through setting up the second sub transmission line for the position that the second power cord got into the region of walking is more nimble, is convenient for walk the line design, arranges more possibilities for walking on the display substrate. The number and distribution of the second sub-transmission lines may be set as desired, which is not limited by the present disclosure.

In an exemplary embodiment, the first power line is located in at least one of a third area and a fourth area, and an orthographic projection of the third area on the display substrate does not overlap with orthographic projections of the unit test area and the driving chip area on the display substrate; the orthographic projection of the fourth area on the display substrate at least partially overlaps with the orthographic projection of the unit test area on the display substrate, and the orthographic projection of the fourth area on the display substrate at least partially overlaps with the orthographic projection of the driving chip area on the display substrate.

In an exemplary embodiment, the third region includes at least one of a third sub-region and a fourth sub-region; in the first direction, the third sub-area and the fourth sub-area are located at two opposite ends of the binding area, and the fourth area is located between the third sub-area and the fourth sub-area.

In an exemplary embodiment, the third and fourth sub-regions are located between the first and second sub-regions.

In an exemplary embodiment, the fourth area includes at least one of a fifth sub-area and a sixth sub-area, which are adjacent to and located on both sides of the second area in the first direction.

In other embodiments, the third region and the fourth region may include more sub-regions, which the present disclosure does not limit.

In an exemplary embodiment, the display substrate further includes a data transmission line, one end of the data transmission line is connected to the driving chip region, and the other end of the data transmission line extends to the wiring region and is connected to the data signal line of the display region; the orthographic projection of the second sub-line in the bending area is positioned between the orthographic projections of the adjacent data transmission lines in the bending area.

In this embodiment, data transmission line can extend along the second direction in the district of buckling, and the orthographic projection through setting up the second sub-line in the district of buckling is located between the orthographic projection of adjacent data transmission line in the district of buckling, has reduced the line quantity of walking in perpendicular to district of buckling orientation, helps buckling the district of buckling, can reduce the line and take place cracked risk in the district of buckling.

In an exemplary embodiment, the display substrate may include a first gate metal layer and a second gate metal layer, the data transmission line may include a first data transmission line and a second data transmission line, the first data transmission line may be located at the first gate metal layer, and the second data transmission line may be located at the second gate metal layer.

In an exemplary embodiment, the first data transmission line and the second data transmission line are disposed to be spaced apart from each other.

Fig. 5 is a schematic top view of a display substrate in an exemplary embodiment. As shown in fig. 5, the display substrate includes a display area 100 and a binding area located at one side of the display area 100 along a second direction Y, and the first direction X and the second direction Y may cross each other. The display substrate further includes a bezel area 300 located at the other side of the display area 100. The binding region includes a bending region 220 and a binding pin region 250 sequentially arranged in a direction away from the display region 100 (i.e., the second direction Y); the bending region 210 is configured to bend the bonding region to the back surface of the display region 100, and the bonding pin region 250 includes a plurality of bonding pads configured to be bonded with a flexible wiring board (not shown) which can provide various signals to the display substrate through the bonding pads. The display substrate includes a second power line configured to supply a low-level signal to the display substrate, the second power line including a first sub power line and a second sub power line 22; the first sub power line is located in the bending area 220 and comprises a plurality of first sub lines 21 arranged in parallel and a plurality of second sub lines arranged in parallel, and the plurality of first sub lines 21 and the plurality of second sub lines are mutually connected in a cross mode to form a grid-shaped structure; the second sub power line 22 is provided to connect the first sub power line and the bonding pad. The second power line is arranged in the bending area, so that the area of the second power line on the display substrate is increased, the resistance of the second power line is reduced, the voltage drop of the second power line is reduced, and the display power consumption of the display substrate is reduced. The first sub power line located in the bending area is set to be the first sub lines and the second sub lines, so that the diameter of each sub line is smaller, the sub lines are not prone to breaking when being bent in the bending area, the first sub lines and the second sub lines are in cross connection with each other, the stability of signal transmission is guaranteed, and the display substrate can be guaranteed to work stably and normally.

In an exemplary embodiment, the first sub line 21 may extend in a first direction X, the second sub line may extend in a second direction Y, and the first direction X may be perpendicular to the second direction Y. Under the condition that the first direction X is perpendicular to the second direction Y, the bending region 220 bends along the axis of the first direction X, and the first sub-line 21 extends along the first direction X, so that the extending direction of the first sub-line 21 is parallel to the bending axis of the bending region, and the first sub-line 21 is not easy to break.

In an exemplary embodiment, the second sub-line includes a second sub-connection line 23 and a second sub-grid line 24, the second sub-connection line 23 is disposed to be connected to the second sub-power line 22, and the second sub-grid line 24 is disposed to be connected to the plurality of first sub-lines 21.

In an exemplary embodiment, the orthographic projection of the second sub-grid lines 24 on the display substrate is located within an area surrounded by the orthographic projections of the plurality of first sub-lines 21 on the display substrate. That is, the second sub-grid line 24 is connected to the plurality of first sub-lines 21, and the second sub-grid line 24 is located between two first sub-lines 21 at opposite ends in the second direction Y.

In an exemplary embodiment, the number of the second sub-connection lines 23 may be more than the second sub-grid lines 24. Since the second sub-link 23 is connected to not only the plurality of first sub-wires 21 but also needs to receive the low level signal from the bonding pad, by providing a greater number of second sub-link 23, it is helpful to ensure stable reception of the low level signal from the bonding pad. The second sub-grid lines 24 can transmit signals among the plurality of first sub-lines 21, but the second sub-grid lines 24 do not undertake the task of directly receiving signals from the bonding pads, and by arranging the second sub-grid lines 24 with smaller number, the number of the wires in the bending area 220 can be reduced, so that the bending area 220 can be bent, and the risk of wire breakage can be reduced.

In an exemplary embodiment, the first sub line 21 and the second sub line are disposed in the same layer in a direction perpendicular to the display substrate, and the second sub line and the second sub power line 22 may be connected through a via hole.

Fig. 6 is a schematic diagram of the connection of the second sub-connection line and the second sub-power line through the via hole in an exemplary embodiment, and other structures are omitted. As shown in fig. 6, an insulating layer 201 may be disposed between the second sub-link line 23 and the second sub-power line 22, a via hole 202 may be formed on the insulating layer 201, and the second sub-link line 23 and the second sub-power line 22 may be connected through the via hole 202. In an exemplary embodiment, in a direction perpendicular to the display substrate, the display substrate may include a first source drain electrode layer (SD 1) and a second source drain electrode layer (SD 2), the first sub-line 21 and the second sub-line may be located on the first source drain electrode layer, and the second sub-power line 22 may be located on the second source drain electrode layer; alternatively, the first sub line 21 and the second sub line may be located on the second source/drain electrode layer, and the second sub power line 22 may be located on the first source/drain electrode layer. In other embodiments, the display substrate may include other film layers, and the first and second sub power lines 22 may be positioned as needed, which is not limited by the present disclosure.

In an exemplary embodiment, the bonding area further includes a unit test region 230 and a driving chip region 240, the unit test region 230 may be located on a side of the bending region 220 away from the display area 100, and the driving chip region 240 may be located on a side of the unit test region 230 away from the display area 100. The second sub power line 22 may be located in at least one of a first region and a second region, and an orthographic projection of the first region on the display substrate does not overlap with an orthographic projection of the unit test region 230 and the driving chip region 240 on the display substrate; an orthogonal projection of the second area on the display substrate and an orthogonal projection of the unit test area 230 on the display substrate may at least partially overlap, and an orthogonal projection of the second area on the display substrate and an orthogonal projection of the driving chip area 240 on the display substrate may at least partially overlap. In an exemplary embodiment, the first region may include at least one of a first sub-region and a second sub-region; in the first direction X, the first sub-area and the second sub-area may be located at opposite ends of the binding region, and the second region may be located between the first sub-area and the second sub-area.

As shown in fig. 5, the binding pin zone 250 may include at least a plurality of first binding pads and a plurality of second binding pads, the first binding pads may be configured to provide a high-level signal to the first power line, and the second binding pads may be configured to provide a low-level signal to the second power line. The second bonding pad may include at least a first sub-pad 251, a second sub-pad 252, and a third sub-pad 253, the first sub-pad 251 may be connected to the plurality of second sub-power lines 22 located at the first sub-area, the second sub-pad 252 may be connected to the plurality of second sub-power lines 22 located at the second sub-area, and the first and second sub-pads 251 and 252 may be located at opposite ends of the bonding pin area 250 along the first direction X. The third sub-pad 253 may be connected to a plurality of second sub-power lines 22 located in a second region, and in an exemplary embodiment, the second region may be located in a middle portion of the bonding region along the first direction X, and the plurality of second sub-power lines 22 located in the second region may start from the third sub-pad 253, sequentially pass through the driving chip region 240 and the unit test region 230, and then enter the bending region 220. In fig. 5, three second sub power lines 22 are respectively disposed in the first sub area, the second sub area, and the second area, and the three second sub power lines 22 are connected to a single second bonding pad, in practical applications, the number of the second sub power lines 22, the number of the second bonding pads, the number of the second sub power lines 22 connected to a single second bonding pad, and the like in each area may be set as needed, which is not limited by the disclosure. In fig. 5, it is illustrated that the second sub power line 22 directly extends to the bending region 220 along the second direction Y, such a straight routing is helpful to reduce the routing length and save the routing space, in practical applications, the extending direction of the second sub power line 22 may be set as required, for example, a serpentine routing, which is not limited by the present disclosure. In practical applications, the first region may include more sub-regions, and the second region may also include more sub-regions, which is not limited by the present disclosure.

In an exemplary embodiment, the bonding area may further include a routing area 210, and the routing area 210 may be located at a side of the bending area 220 close to the display area 100. The display substrate further includes a first power line 30, the first power line 30 is configured to provide a high level signal to the display substrate, one end of the first power line 30 is connected to the first bonding pad, and the other end of the first power line 30 extends to the routing area 210. There is no overlap between the orthographic projection of the first power line 30 at the inflection region 220 and the orthographic projection of the second sub-line at the inflection region 220. By arranging the orthographic projection of the first power line 30 in the bending area 220 and the orthographic projection of the second sub-line in the bending area 220 to be not overlapped, the second sub-line does not exist at the position where the first power line 30 passes in the direction perpendicular to the bending area 220, the number of the wires running in the direction perpendicular to the bending area 220 is reduced, the bending area 220 is favorably bent, and the risk of breakage of the wires in the bending area 220 can be reduced.

In an exemplary embodiment, an orthogonal projection of the second sub-line on the bending region 220 is located outside an area surrounded by an orthogonal projection of the first power line 30 on the bending region 220.

In an exemplary embodiment, the second sub-line may further include a second sub-transmission line 25, one end of the second sub-transmission line 25 is connected to the first sub-line 21, and the other end of the second sub-transmission line 25 extends to the routing region 210. By providing the second sub-transmission line 25, the position where the second power line enters the wiring area 210 is more flexible, the wiring design is facilitated, and more possibilities are provided for wiring arrangement on the display substrate.

In an exemplary embodiment, the first power line 30 may be located in at least one of a third region and a fourth region, and an orthographic projection of the third region on the display substrate does not overlap with an orthographic projection of the unit test region 230 and the driving chip region 240 on the display substrate; the orthographic projection of the fourth area on the display substrate at least partially overlaps the orthographic projection of the unit test area 230 on the display substrate, and the orthographic projection of the fourth area on the display substrate at least partially overlaps the orthographic projection of the driving chip area 240 on the display substrate.

In an exemplary embodiment, the third region may include at least one of a third sub-region and a fourth sub-region; in the first direction X, the third sub-area and the fourth sub-area are located at opposite ends of the binding region, and the fourth region is located between the third sub-area and the fourth sub-area.

In an exemplary embodiment, the fourth area includes at least one of a fifth sub-area and a sixth sub-area, the fifth sub-area and the sixth sub-area being adjacent to and located on both sides of the second area in the first direction.

As shown in fig. 5, the first bonding pad may include at least a fourth sub-pad 254, a fifth sub-pad 255, a sixth sub-pad 256, and a seventh sub-pad 257. The fourth sub-pad 254 may be connected to the plurality of first power lines 30 located at the third sub-area, the fifth sub-pad 255 may be connected to the plurality of first power lines 30 located at the fourth sub-area, the fourth and fifth sub-pads 254 and 255 may be located at opposite ends of the bonding pin area 250 along the first direction X, and the fourth and fifth sub-pads 254 and 255 may be located between the first and second sub-pads 251 and 252. The sixth sub-pad 256 may be connected to the plurality of first power lines 30 located in the fifth sub-area, the seventh sub-pad 257 may be connected to the plurality of first power lines 30 located in the sixth sub-area, in an exemplary embodiment, the fifth and sixth sub-areas may be adjacent to the second area and located at two sides of the second area along the first direction X, and the plurality of first power lines 30 located in the fourth area may start from the corresponding pad and sequentially pass through the driver chip area 240 and the unit test area 230 and then enter the routing area 210. In fig. 5, two first power lines 30 are respectively disposed in the third sub-area, the fourth sub-area, the fifth sub-area and the sixth sub-area, and the two first power lines 30 are connected to a single first bonding pad, and in practical applications, the number of the first power lines 30 located in each area, the number of the first bonding pads, the number of the single first bonding pad connected to the first power line 30, and the like may be set as needed, which is not limited by the present disclosure. In fig. 5, it is illustrated that the first power line 30 directly extends to the routing area 210 along the second direction Y, such straight routing is helpful to reduce the routing length and save the routing space, in practical applications, the extending direction of the first power line 30 may be set as required, for example, a serpentine routing, and the disclosure does not limit this. In practical applications, the third region may include more sub-regions, and the fourth region may also include more sub-regions, which is not limited by the present disclosure.

In fig. 5, the routing in the routing area 210 is not illustrated, and in practical application, the routing arrangement in the routing area 210 may be set as needed, for example, a part of the routing in the routing area 210 may enter the frame area 300 first and then be connected to the routing in the display area 100, or a part of the routing in the routing area 210 may be directly connected to the routing in the display area 100, which is not limited by the present disclosure.

In an exemplary embodiment, the display substrate further includes a data transmission line 40, one end of the data transmission line 40 is connected to the driving chip region 240, and the other end of the data transmission line 40 extends to the wiring region 210 and is connected to a data signal line (not shown) of the display region 100; the orthographic projection of the second sub-line on the bending region 220 is positioned between the orthographic projections of the adjacent data transmission lines 40 on the bending regions 220. As shown in fig. 5, the data transmission line 40 may extend in the second direction Y in the bending region 220, and the orthographic projection of the second sub-line on the bending region 220 is located between the orthographic projections of the adjacent data transmission lines 40 on the bending region 220, so that the number of the routing lines in the direction perpendicular to the bending region 220 is reduced, the bending region 220 is facilitated, and the risk of breakage of the routing lines in the bending region 220 can be reduced. The data transmission lines 40 are shown by two dotted lines in fig. 5, and in practical applications, the number of the data transmission lines 40 may be as many as needed, which is not limited by the present disclosure.

In an exemplary embodiment, the data transmission line 40 may include a first data transmission line and a second data transmission line, which are located at different film layers in a direction perpendicular to the display substrate.

In an exemplary embodiment, the display substrate may include a first Gate metal layer (Gate 1) and a second Gate metal layer (Gate 2), the first data transmission line may be located at the first Gate metal layer, and the second data transmission line may be located at the second Gate metal layer, which is not limited by the present disclosure.

In an exemplary embodiment, the first data transmission line and the second data transmission line are disposed at intervals from each other along the first direction X, which is not limited by the present disclosure.

Fig. 7 is a schematic diagram illustrating traces of a display substrate in an exemplary embodiment. Fig. 7 increases the illustration of the power and data lines entering the display area compared to fig. 5. As shown in fig. 7, in an exemplary embodiment, a second power supply loop line 310 may be disposed around the display area 100, both ends of the second power supply loop line 310 may be located at both ends of the display substrate opposite in the first direction X, the second sub-link line 23 connected to the first sub-pad 251 may be connected to one end of the second power supply loop line 310, and the second sub-link line 23 connected to the second sub-pad 252 may be connected to the other end of the second power supply loop line 310. The second sub-connection line 23 connected to the third sub-pad 253 may be connected to the second power supply loop line 310 after passing through the display area 100. The second sub-transmission line 25 may pass through the display area 100 and then be connected to the second power loop line 310. The data transmission line 40 may be connected to the data signal line located in the display area 100 after passing through the routing area 210.

In an exemplary embodiment, a plurality of parallel second transverse lines (not shown) may be disposed in the display area 100 along the first direction X, and both ends of the plurality of parallel second transverse lines may be connected to the second power loop line 310 to form second power lines distributed in a grid shape in the display area 100, and since the second sub-connection lines 23 connected to the third sub-pads 253 may directly provide low-level signals to the second transverse lines in the middle of the display area 100, a voltage drop of signals transferred from both ends of the display substrate to the middle of the display substrate is avoided, which helps to reduce display power consumption of the display substrate.

In other embodiments, the second power ring line 310 may not be provided, the second sub-connection line 23 may be directly connected to a plurality of second transverse lines provided in the display area 100, the second power lines are distributed in a grid shape in the display area, and a plurality of second longitudinal lines parallel to each other may be provided in the display area 100 along the second direction Y as required to form a second power line grid with a higher density in the display area 100, which is not limited by the present disclosure.

In an exemplary embodiment, the first power line 30 located in the third and fourth sub-regions, i.e., the first power line 30 connected to the fourth and fifth sub-pads 254 and 255, may enter the display region 100 after passing through the bending region 220, the routing layer 210. The first power line 30 located in the fifth and sixth sub-regions, i.e., the first power line 30 connected to the sixth and

seventh sub-pads

256 and 257, may enter the display area 100 after passing through the driving chip region 240, the unit test region 230, the bending region 220, and the routing layer 210. Thereby realizing the supply of a high level signal to the display area of the display substrate.

In an exemplary embodiment, a plurality of parallel first transverse lines (not shown) may be disposed in the first direction X in the display area 100, and the plurality of first transverse lines may be connected to a plurality of first power lines 30 extending from the routing area 210 to the display area 100 to form the first power lines 30 distributed in a grid shape in the display area 100, and a plurality of parallel first longitudinal lines may be disposed in the second direction Y in the display area 100 to form a first power line grid with a greater density in the display area 100, if necessary, which is not limited by the present disclosure.

In an exemplary embodiment, as shown in fig. 7, in a direction perpendicular to the display substrate, the first sub line 21, the second sub connection line 23, the second sub mesh line 24, and the second sub transmission line 25 may be located at the first source-drain electrode layer and connected to each other, the second sub power line 22 may be located at the second source-drain electrode layer, and the second sub power line 22 may be connected to the first sub power line through a via hole. The first power line 30 may be located at the second source-drain electrode layer, and there is no connection relationship between the first power line 30 and the second power line. The data transmission line 40 may include a first data transmission line and a second data transmission line sequentially spaced from each other along the first direction X, the first data transmission line may be located in a first gate metal layer, the second data transmission line may be located in a second gate metal layer, and there is no connection relationship between the data transmission line 40 and a second power line. In other embodiments, the positions of different lines on different film layers can be set according to needs, and the disclosure does not limit this.

The embodiment of the disclosure further provides a display module comprising the display substrate in any one of the embodiments. The display module can be: the OLED display, the mobile phone, the tablet computer, the television, the display, the notebook computer, the digital photo frame, the navigator and other products or components with display functions, which is not limited in the embodiments of the present disclosure.

In an exemplary embodiment, the display module may further include one or more film layers, such as an encapsulation layer, a touch layer, a polarizing layer, and a cover plate layer, on the display substrate, which is not limited in this disclosure.

Although the embodiments of the present invention have been described above, the above description is only for the convenience of understanding the present invention, and is not intended to limit the present invention. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. The display substrate is characterized by comprising a display area and a binding area positioned on one side of the display area; the binding area comprises a bending area and a binding pin area which are sequentially arranged along the direction far away from the display area; the bending area is configured to bend the binding area to the back of the display area, the binding pin area comprises a plurality of binding pads, and the binding pads are configured to be in binding connection with the flexible circuit board;

the display substrate includes a second power line configured to provide a low-level signal to the display substrate, the second power line including a first sub power line and a second sub power line;

the first sub power line is positioned in the bending area and comprises a plurality of first sub lines arranged in parallel and a plurality of second sub lines arranged in parallel, and the first sub lines and the second sub lines are mutually connected in a cross mode to form a grid-shaped structure; the second sub power line is configured to connect the first sub power line and the bonding pad.

2. The display substrate of claim 1, wherein the first sub-line extends in a first direction, wherein the second sub-line extends in a second direction, wherein the first direction is perpendicular to the second direction, and wherein the bonding region is located at one side of the display region in the second direction.

3. The display substrate according to claim 2, wherein the second sub-line includes a second sub-connection line and a second sub-grid line, the second sub-connection line is configured to be connected to the second sub-power supply line, and the second sub-grid line is configured to be connected to the plurality of first sub-lines.

4. The display substrate of claim 3, wherein the number of the second sub-connection lines is greater than the number of the second sub-grid lines.

5. The display substrate according to claim 3, wherein an orthographic projection of the second sub-grid line on the display substrate is located in an area surrounded by orthographic projections of the first sub-lines on the display substrate.

6. The display substrate of claim 3, wherein the bonding area further comprises a unit test area and a driving chip area, the unit test area is located on a side of the bending area away from the display area, and the driving chip area is located on a side of the unit test area away from the display area;

the second sub power line is located in at least one of the first region and the second region; the orthographic projection of the first area on the display substrate is not overlapped with the orthographic projection of the unit test area and the orthographic projection of the driving chip area on the display substrate; the orthographic projection of the second area on the display substrate at least partially overlaps with the orthographic projection of the unit test area on the display substrate, and the orthographic projection of the second area on the display substrate at least partially overlaps with the orthographic projection of the driving chip area on the display substrate.

7. The display substrate according to claim 6, wherein the first region comprises at least one of a first sub-region and a second sub-region; in the first direction, the first sub-area and the second sub-area are located at two opposite ends of the binding region, and the second region is located between the first sub-area and the second sub-area.

8. The display substrate of claim 7, wherein the bonding area further comprises a routing area, and the routing area is located on a side of the bending area close to the display area; the bonding pads comprise a first bonding pad and a second bonding pad; one end of the second power line is connected with the second binding pad, and the other end of the second power line extends to the wiring area;

the display substrate further comprises a first power line, the first power line is configured to provide a high-level signal to the display substrate, one end of the first power line is connected with the first binding pad, and the other end of the first power line extends to the wiring area; and the orthographic projection of the first power line on the bending area does not overlap with the orthographic projection of the second sub-line on the bending area.

9. The display substrate of claim 8, wherein an orthographic projection of the second sub-line on the bending area is outside an area surrounded by an orthographic projection of the first power line on the bending area.

10. The display substrate according to claim 8, wherein the other end of the second power line extends to the routing area, and comprises:

one end of the second sub-connecting line extends to the wiring area.

11. The display substrate of claim 10, wherein the second sub-line further comprises a second sub-transmission line; the other end of the second power line extends to the wiring area, and the power line further comprises:

the other end of the second sub-transmission line extends to the wiring area.

12. The display substrate according to claim 8, wherein the first power line is located in at least one of a third area and a fourth area, and an orthogonal projection of the third area on the display substrate does not overlap with an orthogonal projection of the unit test area and the driving chip area on the display substrate; the orthographic projection of the fourth area on the display substrate at least partially overlaps with the orthographic projection of the unit test area on the display substrate, and the orthographic projection of the fourth area on the display substrate at least partially overlaps with the orthographic projection of the driving chip area on the display substrate.

13. The display substrate according to claim 12, wherein the third region comprises at least one of a third sub-region and a fourth sub-region; in the first direction, the third sub-area and the fourth sub-area are located at two opposite ends of the binding area, and the fourth area is located between the third sub-area and the fourth sub-area;

the fourth region includes at least one of fifth and sixth sub-regions adjacent to and on either side of the second region in the first direction.

14. The display substrate of claim 8, further comprising a data transmission line, wherein one end of the data transmission line is connected to the driving chip region, and the other end of the data transmission line extends to the wiring region and is connected to a data signal line of the display region; the orthographic projection of the second sub-line in the bending area is positioned between the orthographic projections of the adjacent data transmission lines in the bending area.

15. A display module comprising the display substrate according to any one of claims 1 to 14.