CN115810551A - Manufacturing method of package substrate, package structure and manufacturing method thereof - Google Patents
Manufacturing method of package substrate, package structure and manufacturing method thereof Download PDFInfo
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- CN115810551A CN115810551A CN202111070057.5A CN202111070057A CN115810551A CN 115810551 A CN115810551 A CN 115810551A CN 202111070057 A CN202111070057 A CN 202111070057A CN 115810551 A CN115810551 A CN 115810551A
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Abstract
The application provides a manufacturing method of a packaging substrate, which comprises the steps of providing a circuit substrate, wherein the circuit substrate comprises a substrate layer, an embedded circuit and a first connecting pad, the embedded circuit is arranged in the substrate layer, the first connecting pad is arranged on the surface of the substrate layer, and the first connecting pad is electrically connected with the embedded circuit. And a covering layer is arranged on the base material layer, a plurality of openings are formed in the covering layer corresponding to the first connecting pads, and the first connecting pads are exposed at the bottoms of the openings. And filling a resistor body in the opening, wherein one side of the resistor body is electrically connected with the first connecting pad, a connecting layer is arranged on the covering layer, and the other side of the resistor body is electrically connected with the connecting layer. In addition, the application also provides a packaging structure and a manufacturing method of the packaging structure.
Description
Technical Field
The application relates to a manufacturing method of a package substrate, a package structure and a manufacturing method thereof.
Background
Generally, the system integration technology integrates a chip and passive elements such as a resistor, an inductor, a capacitor, etc. on the surface of a circuit substrate, so as to adapt to the development trend of light, thin, short and small electronic products. However, the passive element occupies a part of the surface area of the circuit substrate, which reduces the area available for the chip to be mounted, and is not favorable for the chip to be mounted.
Disclosure of Invention
To solve the problems in the background art, the present application provides a method for manufacturing a package substrate.
In addition, it is necessary to provide a manufacturing method of the package structure.
In addition, it is necessary to provide a package structure.
A method for manufacturing a package substrate includes the steps of: the circuit substrate comprises a substrate layer, an embedded circuit and a first connecting pad, wherein the embedded circuit is arranged in the substrate layer, the first connecting pad is arranged on the surface of the substrate layer, and the first connecting pad is electrically connected with the embedded circuit. And arranging a covering layer on the base material layer, wherein the covering layer is provided with a plurality of openings, and the first connecting pads are exposed in the openings. And arranging a resistor body in the opening, so that one side of the resistor body is electrically connected with the first connecting pad, and arranging a connecting layer on the covering layer, so that the other side of the resistor body is electrically connected with the connecting layer.
Further, before providing the resistor body, the manufacturing method may further include: and arranging an insulator in each opening, wherein each opening comprises a first space and a second space, the insulator is positioned in the first space, part of the first connecting pad is exposed in the second space, and the resistor is arranged in the second space.
Further, the insulator is a hollow structure and includes a through hole, and the through hole forms the second space after the insulator is disposed in each of the openings.
Further, after the resistor body is provided, the manufacturing method may further include: and oxidizing the surface of the resistor body to form an oxide layer, wherein the resistor body is electrically connected with the connecting layer through the oxide layer.
Further, the connecting layer comprises an anisotropic conductive adhesive layer which covers and is connected with each resistor body.
Furthermore, the connection layer comprises a plurality of second connection pads, and the second connection pads are in one-to-one correspondence with and connected with the resistor bodies.
A manufacturing method of a package structure includes the steps: the circuit substrate comprises a substrate layer, an embedded circuit and a first connecting pad, wherein the embedded circuit is arranged in the substrate layer, the first connecting pad is arranged on the surface of the substrate layer, and the first connecting pad is electrically connected with the embedded circuit. The cover layer is arranged on the base material layer and provided with a plurality of openings, and the first connecting pads are exposed in the openings. And arranging a resistor body in the opening, so that one side of the resistor body is electrically connected with the first connecting pad. And arranging a connecting layer on the covering layer, and electrically connecting the other side of the resistor body with the connecting layer. And arranging a chip element on the connecting layer to obtain the packaging structure.
A packaging structure comprises a packaging substrate and a chip element arranged on the packaging substrate. The packaging substrate comprises a circuit substrate, a covering layer, a resistor body and a connecting layer, wherein the circuit substrate comprises a substrate layer, a first connecting pad embedded in a buried line structure of the substrate layer and arranged on the surface of the substrate layer, the first connecting pad is electrically connected with the buried line structure, the covering layer is arranged on the substrate layer, the covering layer is provided with a plurality of openings, the first connecting pad is exposed in the openings, the resistor body is arranged in the openings, one side of the resistor body is electrically connected with the first connecting pad, the connecting layer is arranged on the covering layer, and the other side of the resistor body is electrically connected with the connecting layer. The chip element is arranged on the connecting layer and electrically connected with the connecting layer.
Furthermore, the connection layer comprises an anisotropic conductive adhesive layer, the chip element comprises a chip and a connection pin, one side of the connection pin is electrically connected with the chip, and the other side of the connection pin is connected with the anisotropic conductive adhesive layer.
Furthermore, the connection layer includes a plurality of second connection pads, the package structure further includes a plurality of solder balls and a protection layer disposed on the second connection pads, and the solder balls are disposed between the connection pins and the protection layer.
Compared with the prior art, the manufacturing method of the package substrate provided by the application buries the resistor body in the opening of the covering layer, and the first connecting pad and the connecting layer are respectively arranged on the two opposite sides of the resistor body and are electrically connected with the resistor body to form the resistor element, so that the occupation of the resistor element on the surface area of the package substrate is reduced, and more and larger chip elements can be arranged on the surface of the package substrate.
Drawings
Fig. 1 is a schematic view of a circuit substrate according to an embodiment of the present disclosure.
Fig. 2 is a schematic view of the circuit board shown in fig. 1 after an insulator is provided.
Fig. 3 is a schematic view of the circuit board shown in fig. 2 after a resistor is provided.
Fig. 4 is a schematic view of the circuit substrate shown in fig. 3 after a connection layer is disposed.
Fig. 5 is a schematic diagram of a package structure according to an embodiment of the present application.
Fig. 6 is a schematic view of a package substrate according to another embodiment of the present disclosure.
Fig. 7 is a schematic view of the package substrate shown in fig. 6 after a protective layer is disposed thereon.
Fig. 8 is a schematic diagram of a package structure according to another embodiment of the present application.
Description of the main elements
Buried wiring structure 12
Buried wiring layer 121
Connecting layer 50
Anisotropic conductive adhesive layer 51
Thickness direction H
The following detailed description will further illustrate the present application in conjunction with the above-described figures.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments.
It will be understood that when an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. When an element is referred to as being "disposed on" another element, it can be directly on the other element or intervening elements may also be present.
Referring to fig. 1 to 4, an embodiment of the present application provides a method for manufacturing a package substrate 100, including the steps of:
s1, referring to fig. 1, a circuit substrate 10 is provided, where the circuit substrate 10 includes a substrate layer 11, an embedded circuit structure 12, and a plurality of first connection pads 13. The embedded circuit structure 12 is arranged in the substrate layer 11, the first connecting pad 13 is arranged on the surface of the substrate layer 11, and the first connecting pad 13 is electrically connected with the embedded circuit structure 12.
In this embodiment, the embedded circuit structure 12 includes a plurality of embedded circuit layers 121 and a plurality of embedded vias 122, the embedded vias 122 are connected between every two adjacent embedded circuit layers 121 to realize the conduction of the plurality of embedded circuit layers 121, and the embedded vias 122 are further connected to the first connection pads 13 to realize the conduction between the first connection pads 13 and the embedded circuit layers 121.
S2, referring to fig. 1, a cover layer 20 is disposed on a surface of the substrate layer 11 having the first connection pads 13, a plurality of openings 21 are disposed at positions of the cover layer 20 corresponding to the first connection pads 13, the first connection pads 13 are exposed at bottoms of the openings 21, each of the openings 21 includes a first space 211 and a second space 212 except the first space 211, and at least a portion of the first connection pads 13 are exposed in the second space 212.
S3, referring to fig. 2, an insulator 30 is disposed in the first space 211, such that the insulator 30 occupies a portion of the opening 21, and the size of the insulator 30 can be adjusted according to requirements.
In this embodiment, the insulator 30 is a hollow cylindrical structure, the insulator 30 is disposed in the opening 21 to occupy a portion of the opening 21, and a central region of the first connection pad 13 is partially exposed at a bottom of the opening 21.
S4, referring to fig. 3, a resistor 40 is disposed in the second space 212, and one side of the resistor 40 is electrically connected to the first connection pad 13. The side of the resistor 40 away from the first connection pad 13 is flush with the side of the cover layer 20 away from the substrate layer 11, an insulator 30 is arranged in the opening 21 to occupy part of the opening 21, so that the opening 21 of the other part where the resistor 40 can be arranged is reduced, and the resistance of the resistor 40 can be adjusted by adjusting the size of the insulator 30.
In the present embodiment, the material of the resistor 40 includes any one of a nickel-phosphorus composition, a conductive metal, a conductive alloy, and a conductive nonmetal. In some embodiments, the resistor 40 is disposed in the opening 21 by electroplating, electroless plating or coating.
In another embodiment of the present application, after the resistor 40 is formed, the surface of the resistor 40 may be oxidized to form an oxide layer (not shown), and the oxide layer may be used to prevent the resistor 40 from being oxidized and protect the resistor 40.
And S5, referring to FIG. 4, a connecting layer 50 is arranged on the covering layer 20, and the connecting layer 50 is electrically connected to the resistor body 40 to obtain the packaging substrate 100.
In the present embodiment, referring to fig. 4, the connection layer 50 includes an anisotropic conductive adhesive layer 51, the anisotropic conductive adhesive layer 51 has a thickness direction H, along the thickness direction H, the anisotropic conductive adhesive layer 51 is electrically connected to the resistor 40, and along other directions (for example, perpendicular to the thickness direction H, etc.), the anisotropic conductive adhesive layer 51 is electrically isolated from the resistor 40, so that a plurality of the resistor 40 connected to the same anisotropic conductive adhesive layer 51 are not directly electrically conducted, and thus, the connection layer 50 does not need to be hollowed, drilled, and other processes, thereby saving processing flows and processing materials, and improving processing efficiency.
Referring to fig. 4 to 5, the present application further provides a method for manufacturing a package structure 200, including the steps of:
s6, referring to fig. 4, providing one package substrate 100, where the package substrate 100 includes a circuit substrate 10, a cover layer 20, a resistor 40, and a connection layer 50, the circuit substrate 10 includes a substrate layer 11, an embedded circuit structure 12 embedded in the substrate layer 11, and a first connection pad 13 disposed on a surface of the substrate layer 11, the first connection pad 13 is electrically connected to the embedded circuit structure 12, the cover layer 20 is disposed on the substrate layer 11, the cover layer 20 is provided with a plurality of openings 21, the first connection pad 13 is exposed at a bottom of the opening 21, the resistor 40 is disposed in the opening 21, one side of the resistor 40 is electrically connected to the first connection pad 13, the connection layer 50 is disposed on the cover layer 20, and the other side of the resistor 40 is electrically connected to the connection layer 50.
Referring to fig. 5, a chip element 60 is disposed on the connection layer 50, wherein the chip element 60 includes a chip 61 and a connection pin 62, one side of the connection pin 62 is electrically connected to the chip 61, and the other side of the connection pin 62 is electrically connected to the connection layer 50.
Referring to fig. 6 to 8, in another embodiment of the present invention, the connection layer 50 includes a plurality of second connection pads 52 disposed at intervals, and each of the second connection pads 52 is disposed on one of the resistors 40 and electrically connected to the resistor 40. The manufacturing method of the package structure 200 includes:
s70, referring to fig. 7, a protective layer 521 is disposed on the second connecting pad 52, the protective layer 521 is made of a nickel-gold alloy, and the protective layer 521 is used to improve the conductivity of the second connecting pad 52 and prevent the second connecting pad 52 from being corroded.
S72, referring to fig. 8, solder balls 522 are disposed on the passivation layer 521 by reflow soldering.
S73, referring to fig. 8, the connection pins 62 are disposed on the solder balls 522, and the second connection pads 52 are electrically connected to the solder balls 522 through the protection layer 521.
Compared with the prior art, the manufacturing method of the package substrate 100 provided by the present application has the following advantages:
the resistor 40 is embedded in the opening 21 of the cover layer 20, and the first connection pads 13 and the connection layers 50 are respectively disposed on two opposite sides of the resistor 40, and the first connection pads 13 and the connection layers 50 are electrically connected to the resistor 40 to form a resistor element, so that the occupation of the resistor element on the surface area of the package substrate 100 is reduced, and more and larger chip elements 60 can be disposed on the surface of the package substrate 100.
Second, the chip element 60 and the resistor 40 are electrically connected by the anisotropic conductive adhesive layer 51, so that the anisotropic conductive adhesive layer 51 does not need to be hollowed or drilled, and the anisotropic conductive adhesive 41 does not need to be subjected to chemical gold processing, thereby saving processing flow and processing materials and improving processing efficiency.
And thirdly, the chip element 60 and the resistor 40 are electrically connected through the anisotropic conductive adhesive layer 51 without using solder paste or solder ball connection, which is beneficial to reducing inductance.
Referring to fig. 5, the present application further provides a package structure 200, where the package structure 200 includes a package substrate 100 and a chip element 60 disposed on the package substrate 100. The package substrate 100 includes a circuit substrate 10, a cover layer 20, a resistor 40 and a connection layer 50, the circuit substrate 10 includes a substrate layer 11, a buried circuit structure 12 embedded in the substrate layer 11 and a first connection pad 13 disposed on the surface of the substrate layer 11, the first connection pad 13 is electrically connected to the buried circuit structure 12, the cover layer 20 is disposed on the substrate layer 11, the cover layer 20 is provided with a plurality of openings 21, the first connection pad 13 is exposed at the bottom of the opening 21, the resistor 40 is disposed in the opening 21, one side of the resistor 40 is electrically connected to the first connection pad 13, the connection layer 50 is disposed on the cover layer 20, and the other side of the resistor 40 is electrically connected to the connection layer 50. The chip element 60 is disposed on the connection layer 50 and electrically connected to the connection layer 50.
In this embodiment, the connection layer 50 includes an anisotropic conductive adhesive layer 51, the chip component 60 includes a chip 61 and connection pins 62, one side of the connection pins 62 is electrically connected to the chip 61, and the other side is connected to the anisotropic conductive adhesive layer 51.
Referring to fig. 8, in another embodiment of the present application, the connection layer 50 includes a second connection pad 52 and a protection layer 521 disposed on the second connection pad 52, and the package structure 200 further includes a plurality of solder balls 522, wherein the solder balls 522 are disposed between the connection pins 62 and the protection layer 521.
In addition, other changes may be made by those skilled in the art within the spirit of the application, and it is understood that such changes are encompassed within the scope of the invention as claimed.
Claims (10)
1. A method for manufacturing a package substrate includes the steps of:
providing a circuit substrate, wherein the circuit substrate comprises a substrate layer, an embedded line and a first connecting pad, the embedded line is arranged in the substrate layer, the first connecting pad is arranged on the surface of the substrate layer, and the first connecting pad is electrically connected with the embedded line;
a covering layer is arranged on the base material layer, the covering layer is provided with a plurality of openings, and the first connecting pads are exposed in the openings;
arranging a resistor body in the opening hole, and electrically connecting one side of the resistor body with the first connecting pad; and
and arranging a connecting layer on the covering layer, so that the other side of the resistor body is electrically connected with the connecting layer.
2. The manufacturing method according to claim 1, wherein before providing the resistor body, the manufacturing method further comprises:
arranging an insulator in each opening, wherein each opening comprises a first space and a second space, the insulator is positioned in the first space, and part of the first connecting pad is exposed in the second space;
wherein the resistor is disposed in the second space.
3. The method according to claim 2, wherein the insulator has a hollow structure and includes a through hole, and the through hole forms the second space after the insulator is disposed in each of the openings.
4. The manufacturing method according to claim 1, further comprising, after providing the resistor body, a step of:
and oxidizing the surface of the resistor body to form an oxide layer, wherein the resistor body is electrically connected with the connecting layer through the oxide layer.
5. The manufacturing method according to claim 1, wherein the connection layer includes an anisotropic conductive adhesive layer covering and connecting each of the resistor bodies.
6. The method according to claim 1, wherein the connection layer includes a plurality of second connection pads, and the second connection pads are connected to the resistor bodies in a one-to-one correspondence.
7. A method for manufacturing a package structure, comprising the steps of:
providing a circuit substrate, wherein the circuit substrate comprises a substrate layer, an embedded circuit and a first connecting pad, the embedded circuit is arranged in the substrate layer, the first connecting pad is arranged on the surface of the substrate layer, and the first connecting pad is electrically connected with the embedded circuit;
a covering layer is arranged on the base material layer, the covering layer is provided with a plurality of openings, and the first connecting pads are exposed in the openings;
arranging a resistor body in the opening hole, and electrically connecting one side of the resistor body with the first connecting pad;
arranging a connecting layer on the covering layer to enable the other side of the resistor body to be electrically connected with the connecting layer;
and arranging a chip element on the connecting layer to obtain the packaging structure.
8. A package structure comprises a package substrate and a chip element disposed on the package substrate,
the packaging substrate comprises a circuit substrate, a covering layer, a resistor body and a connecting layer, wherein the circuit substrate comprises a substrate layer, an embedded line structure embedded in the substrate layer and a first connecting pad arranged on the surface of the substrate layer, the first connecting pad is electrically connected with the embedded line structure, the covering layer is arranged on the substrate layer, the covering layer is provided with a plurality of openings, the first connecting pad is exposed out of the openings, the resistor body is arranged in the openings, one side of the resistor body is electrically connected with the first connecting pad, the connecting layer is arranged on the covering layer, and the other side of the resistor body is electrically connected with the connecting layer,
the chip element is arranged on the connecting layer and electrically connected with the connecting layer.
9. The package structure of claim 8, wherein the connection layer comprises an anisotropic conductive adhesive layer, the chip component comprises a chip and connection pins, one side of the connection pins is electrically connected to the chip, and the other side of the connection pins is connected to the anisotropic conductive adhesive layer.
10. The package structure of claim 8, wherein the connection layer comprises a plurality of second connection pads, the package structure further comprising a plurality of solder balls and a passivation layer disposed on the second connection pads, the solder balls being disposed between the connection pins and the passivation layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111070057.5A CN115810551A (en) | 2021-09-13 | 2021-09-13 | Manufacturing method of package substrate, package structure and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111070057.5A CN115810551A (en) | 2021-09-13 | 2021-09-13 | Manufacturing method of package substrate, package structure and manufacturing method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN115810551A true CN115810551A (en) | 2023-03-17 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111070057.5A Pending CN115810551A (en) | 2021-09-13 | 2021-09-13 | Manufacturing method of package substrate, package structure and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115810551A (en) |
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2021
- 2021-09-13 CN CN202111070057.5A patent/CN115810551A/en active Pending
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