CN115809067A

CN115809067A - Model conversion method and device, electronic equipment and storage medium

Info

Publication number: CN115809067A
Application number: CN202211653510.XA
Authority: CN
Inventors: 宋佩; 魏琼; 赵健; 周国鹏; 蔡宗霖; 严晓; 赵恩海; 吴运凯; 马妍; 冯洲武
Original assignee: Shanghai MS Energy Storage Technology Co Ltd
Current assignee: Shanghai MS Energy Storage Technology Co Ltd
Priority date: 2022-12-21
Filing date: 2022-12-21
Publication date: 2023-03-17

Abstract

The application discloses a model conversion method and device, electronic equipment and a storage medium, wherein the method comprises the following steps: and acquiring a target mathematical model compiled based on a preset compiling rule. And reading out function content data of each function in the target mathematical model. The function content data mainly comprises a function name, a function parameter and a function statement. According to the set constraint conditions, the function name, the function parameters and the function are decomposed and converted, and list information capable of forming a VerilogHDL module, namely the name of an output module, the input and output interfaces and the corresponding bit length of the module, register variables or linear variables in the module, the flow of a state machine, the type of a floating point operator, the number to be instantiated and the like, is output. And finally, generating a VerilogHDL text and outputting the VerilogHDL text according to the set generation template and the IP information of the floating point operation of the manufacturer based on the list information obtained by conversion.

Description

Model conversion method and device, electronic equipment and storage medium

Technical Field

The present application relates to the field of model design technologies, and in particular, to a model transformation method and apparatus, an electronic device, and a storage medium.

Background

In the field of communication systems and the like, a large number of complex calculation model simulations and fixed-point designs are often required. When the model design is realized, a mathematical model is usually established by using a C language to quickly perform simulation and test to verify the correctness of the model, and then the model is designed into a corresponding circuit module by using hardware description languages such as verilog hdl.

After the mathematical model is simulated and the correctness of the model is verified at present, an engineer writes a corresponding VerilogHDL text by using a hardware description language of VerilogHDL based on the previously established mathematical model.

This approach, however, requires repeated labor among engineers and requires a large amount of code to be written, and is therefore relatively inefficient and prone to error.

Disclosure of Invention

Based on the defects of the prior art, the application provides a model conversion method and device, electronic equipment and a storage medium, so as to solve the problems that the existing conversion mode is low in efficiency and easy to generate errors.

In order to achieve the above object, the present application provides the following technical solutions:

a first aspect of the present application provides a model conversion method, including:

acquiring a target mathematical model compiled based on a preset compiling rule;

reading function content data of each function in the target mathematical model; the function content data at least comprises a function name, a function parameter and a function statement;

converting to obtain a module unit corresponding to each function based on the function name of each function;

respectively aiming at each function, converting each function form parameter into an input interface or an output interface of a module unit corresponding to the function based on the type of each function form parameter of the function;

resolving the variables in each function into register-type variables based on the type of the variables in each function, and converting the constants in each function into corresponding identifiers;

analyzing an operator in each function functional statement of the function and an input variable and an output variable in the operator;

allocating operation resources of each operational character based on preset constraint conditions, and generating state machine information based on the operation resources of each operational character and input variables and output variables in each operational character;

and generating a VerilogHDL text corresponding to the target mathematical model according to a preset generation template and factory floating point operation IP information based on the state machine information, the basic information of the module unit corresponding to each function and the information of the interface of the module unit corresponding to each function.

Optionally, in the above model conversion method, after the obtaining of the target mathematical model written based on the preset writing rule, the method further includes:

reading each target numerical value and related information thereof in a function in the target mathematical model, and respectively forming each target numerical dictionary set by using each numerical value and related information thereof; the target numerical dictionary set comprises a constant dictionary set, a variable dictionary set, a structural body dictionary set and an array dictionary set; keys of key-value pairs in the constant dictionary set are constant names, and values are numerical value types and numerical values; keys of key-value pairs in the variable dictionary set are variable names, and values are numerical value types and numerical values; the key of the key value pair in the structure dictionary set is a structure name, and the value is a numerical value type, a variable name in the structure and a corresponding numerical value; the key of the key value pair in the array dictionary set is an array name, and the value is an array length, an array type and an array value.

Optionally, in the above model conversion method, the resolving variables in each function into register-type variables based on the type of the variables in each function, and converting constants in each function into corresponding identifiers includes:

respectively searching out the numerical values and the types corresponding to the variables from the target numerical value dictionary set according to the names of the variables aiming at each variable in each function;

converting the numerical value corresponding to the variable into a register type variable with bit length corresponding to the type of the variable;

if the variable is a local variable, the converted variable is placed in a module unit corresponding to the function to which the variable belongs;

if the variable is a global variable, the converted variable is placed in a top module unit;

finding out the numerical value corresponding to the constant from the target numerical value dictionary set according to the name of each constant in each function;

and based on the name and the corresponding numerical value of each constant, macro definition is carried out on the constant, the constant is converted into a corresponding identifier, and the identifier is stored in an independent callable file.

Optionally, in the above model conversion method, the converting, for each function, each function parameter into an input interface or an output interface of a module unit corresponding to the function based on a type of each function parameter of the function includes:

respectively aiming at each function form parameter in each function, if the function form parameter is a read-only input parameter, converting the function form parameter into a linear network type input interface of a module unit corresponding to the function according to the length corresponding to the type of the function form parameter; the length of the interface corresponding to the function parameters of the array type is the length of the array multiplied by the bit length corresponding to the type of the data in the array;

if the function form parameter is a write-only output parameter, converting the function form parameter into a register type output interface of a module unit corresponding to the function according to the length corresponding to the type of the function form parameter;

and if the function form parameter is a readable and writable parameter, converting the function form parameter into an output interface and an input interface of the module unit corresponding to the function according to the length corresponding to the type of the function form parameter.

Optionally, in the above model conversion method, the converting, based on the function name of each function, to obtain the module unit corresponding to each function includes:

respectively aiming at each function, if the prefix of the function name of the function is a top-level character, converting the function into a top-level module unit corresponding to the function;

and if the prefix of the function name of the function is a function character, converting the function into a general module unit corresponding to the function.

Optionally, in the above model conversion method, the constraint condition includes resource maximization, resource minimization and directional resource minimization, and the allocating operation resources of each of the operators based on a preset constraint condition includes:

if the preset constraint condition is that the resource is maximized, respectively allocating corresponding operation resources for each operational character in different function functional statements without coupling relation and each operational character without coupling relation in a single function functional statement;

allocating a corresponding operation resource for each operation of the same type in different functional statements having a coupling relationship, and allocating a corresponding operation resource for each operation of the same type having a coupling relationship in a single functional statement;

if the preset constraint condition is that the resource is minimized, distributing a corresponding operation resource for each operational character of each type in all the function functional statements;

if the preset constraint condition is that the directional resource is maximized, allocating a corresponding operation resource to each operational character of the directional type in all the function functional statements, and allocating a corresponding operation resource to each operational character which does not belong to the directional type based on the resource maximization.

Optionally, in the above model conversion method, the method further includes:

and generating a comprehensive resource use report file based on the VerilogHDL text corresponding to the target mathematical model.

A second aspect of the present application provides a model conversion apparatus, including:

the model obtaining unit is used for obtaining a target mathematical model compiled based on a preset compiling rule;

the first reading unit is used for reading out function content data of each function in the target mathematical model; the function content data at least comprises a function name, a function parameter and a function statement;

the name conversion unit is used for converting the function name of each function to obtain a module unit corresponding to each function;

the interface conversion unit is used for respectively aiming at each function and converting each function form parameter into an input interface or an output interface of the module unit corresponding to the function based on the type of each function form parameter of the function;

a function parameter conversion unit, configured to resolve variables in each function into register-type variables based on the type of the variables in each function, and convert constants in each function into corresponding identifiers;

the information analysis unit is used for analyzing the operational characters in the functional statements of the functions and the input variables and the output variables in the operational characters;

a statement conversion unit, configured to allocate operation resources of each of the operators based on a preset constraint condition, and generate state machine information based on the operation resources of each of the operators and input variables and output variables in each of the operators;

and the result generating unit is used for generating a VerilogHDL text corresponding to the target mathematical model according to a preset generating template and manufacturer floating point operation IP information based on the state machine information, the basic information of the module unit corresponding to each function and the information of the interface of the module unit corresponding to each function.

Optionally, in the above model conversion apparatus, further comprising:

the second reading unit is used for reading each target numerical value and related information thereof in the function in the target mathematical model and respectively forming each target numerical value dictionary set by using each numerical value and related information thereof; the target numerical dictionary set comprises a constant dictionary set, a variable dictionary set, a structural body dictionary set and an array dictionary set; keys of key-value pairs in the constant dictionary set are constant names, and values are numerical value types and numerical values; keys of key-value pairs in the variable dictionary set are variable names, and values are numerical value types and numerical values; keys of key value pairs in the structure dictionary set are structure names, and values are numerical value types, variable names in the structures and corresponding numerical values; the key of the key value pair in the array dictionary set is an array name, and the values are array length, array type and array value.

Optionally, in the above model conversion apparatus, the function parameter conversion unit includes:

the first searching unit is used for respectively searching the corresponding numerical value and the type of the variable from the target numerical value dictionary set according to the name of the variable aiming at each variable in each function;

a first conversion unit, configured to convert a numerical value corresponding to the variable into a register-type variable having a bit length corresponding to a type to which the variable belongs;

the first placing unit is used for placing the converted variable into a module unit corresponding to the function to which the variable belongs when the variable is a local variable;

the second placement unit is used for placing the converted variable into the top module unit when the variable is a global variable;

the second searching unit is used for searching out the numerical value corresponding to the constant from the target numerical value dictionary set according to the name of each constant in each function;

and the second conversion unit is used for carrying out macro definition on the constants based on the names and the corresponding numerical values of the constants, converting the constants into corresponding identifiers and storing the identifiers in an independent calling file.

Optionally, in the above model conversion apparatus, the interface conversion unit includes:

an input interface conversion unit, configured to respectively aim at each function parameter in each function, and if the function parameter is a read-only input parameter, convert the function parameter into a linear network type input interface of a module unit corresponding to the function according to a length corresponding to a type of the function parameter; the length of the interface corresponding to the function parameters of the array type is the length of the array multiplied by the bit length corresponding to the type of the data in the array;

an output interface conversion unit, configured to convert the function parameters into register-type output interfaces of the module units corresponding to the functions according to the lengths corresponding to the types of the function parameters when the function parameters are write-only output parameters;

and the dual-interface conversion unit is used for converting the function form parameters into the output interface and the input interface of the module unit corresponding to the function according to the lengths corresponding to the types of the function form parameters when the function form parameters are readable and writable parameters.

Optionally, in the above model conversion apparatus, the name conversion unit includes:

the top conversion unit is used for converting the function into a top module unit corresponding to the function if the prefix of the function name of the function is a top character aiming at each function;

and the general conversion unit is used for converting the function into a general module unit corresponding to the function when the prefix of the function name of the function is a function character.

Optionally, in the above model conversion apparatus, the constraint condition includes resource maximization, resource minimization and directional resource minimization, and when the statement conversion unit executes the operation resource allocation of each of the operators based on the preset constraint condition, the statement conversion unit is configured to:

if the preset constraint condition is that the resource is maximized, respectively allocating corresponding operation resources to each operational character in different functional statements without coupling relation and each operational character without coupling relation in a single functional statement;

if the preset constraint condition is that the resource is minimized, distributing a corresponding operation resource for each operator of each type in all the function functional statements respectively;

if the preset constraint condition is that the directed resource is maximized, allocating a corresponding operation resource for each operator of the directed type in all the function statements, and allocating a corresponding operation resource for each operator not belonging to the directed type based on the resource maximization.

Optionally, in the above model conversion apparatus, further comprising:

and the report generation unit is used for generating a comprehensive resource use report file based on the VerilogHDL text corresponding to the target mathematical model.

A third aspect of the present application provides an electronic device, comprising:

a memory and a processor;

wherein the memory is used for storing programs;

the processor is configured to execute the program, and when the program is executed, the program is specifically configured to implement the model transformation method according to any one of the above items.

A fourth aspect of the present application provides a computer storage medium for storing a computer program which, when executed, is adapted to implement a model transformation method as defined in any one of the preceding claims.

The application provides a model conversion method, which is used for obtaining a target mathematical model compiled based on a preset compiling rule. And then reading out the function content data of each function in the target mathematical model. The function content data at least comprises a function name, a function parameter and a function statement. And then converting the function parameters into input interfaces or output interfaces of the module units corresponding to the functions respectively aiming at each function based on the type of the function parameters of the function. Then, the variables in each function are analyzed into register type variables based on the types of the variables in each function, the constants in each function are converted into corresponding identifiers, operators in each function statement of the function and input variables and output variables in the operators are analyzed, then, operation resources of each operator are allocated based on preset constraint conditions, and state machine information is generated based on the operation resources of each operator and the input variables and the output variables in each operator, thereby realizing the conversion of the function statement. And finally, generating a VerilogHDL text corresponding to the target mathematical model according to a preset generation template and manufacturer floating point operation IP information based on the state machine information, the basic information of the module unit corresponding to each function and the information of the interface of the module unit corresponding to each function. Therefore, the method for automatically converting the mathematical model written in the C language into the model written in the Verilog HDL language is realized, manual compiling is not needed, the conversion efficiency is improved, and errors are avoided.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the embodiments or the prior art descriptions will be briefly described below, it is obvious that the drawings in the following description are only the embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.

Fig. 1 is a flowchart of a model transformation method according to an embodiment of the present application;

FIG. 2 is a diagram illustrating an example of a sub-function in a mathematical model provided by an embodiment of the present application;

FIG. 3 is a diagram illustrating an example of a principal function in a mathematical model provided by an embodiment of the present application;

FIG. 4 is a schematic diagram of an example of a structure provided in an embodiment of the present application;

fig. 5 is a schematic diagram of an example of interface conversion provided in an embodiment of the present application;

FIG. 6 is a diagram illustrating an example of local variable transformation provided by an embodiment of the present application;

fig. 7 is a schematic diagram of an example of state machine information obtained by conversion under a constraint condition of resource maximization according to an embodiment of the present application;

fig. 8 is a schematic diagram of an example of state machine information obtained by conversion under a constraint condition of resource minimization according to an embodiment of the present application;

FIG. 9 is a diagram illustrating an example of a generated template provided by an embodiment of the present application;

FIG. 10 is a schematic diagram of a portion of data of a fill module in a generation template according to an embodiment of the present application;

FIG. 11 is a schematic diagram of data of another fill module in a generation template according to an embodiment of the present application;

FIG. 12 is a schematic diagram illustrating an architecture of a model transformation apparatus according to an embodiment of the present application;

fig. 13 is an architectural view of an electronic device according to an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be described clearly and completely with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only some embodiments of the present application, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

In this application, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrases "comprising one of 8230; \8230;" 8230; "does not exclude the presence of additional like elements in a process, method, article, or apparatus that comprises the element.

The embodiment of the application provides a model conversion method, as shown in fig. 1, including the following steps:

s101, obtaining a target mathematical model compiled based on a preset compiling rule.

In order to enhance the efficiency and accuracy of model conversion, it is required in the embodiment of the present application that when a mathematical model is expressed by using C language, the mathematical model needs to be written according to a preset writing rule.

Optionally, the preset composition rule may include the following items:

1. because the verilog hdl language describes a digital circuit module, it does not support the high level syntax in the C language, so that when writing the C function, it is required to specify the high level syntax such as the dynamic memory, the pointer to the pointer, the pointer to the function, and the linked list.

2. When writing a function, aiming at the definition of the parameters in the interface name, different types of parameters are required to have corresponding prefixes so as to determine the types of the parameters, and therefore the parameters are converted into corresponding interfaces. For example, a read-only input parameter prefixed "in _", a write-only output parameter prefixed "out _", and a readable and writable parameter prefixed "inout _"; the function has no return value, the output value is realized in the interface, but the function flow can be finished in advance by using 'return' in the function statement.

3. When defining a structure, it is defined as a set of variables of the same type and cannot contain pointer variables.

4. In the C language, the pointer can point to the initial address of the array, so that more distinguishing judgment is made in the conversion program for avoiding, the pointer is forbidden to point to the array, and the array configuration parameters are selected to be directly used for representing the transmission of the array.

5. In the assignment calculation of the function, a library function defined in the (math.h) is referred to realize mathematical operation, such as log, pow, sqrt and the like, so that more distinguishing judgment is carried out in the conversion program for avoiding, the printing output needs to be shielded in the final output file, and only the library function call related to the operation is reserved.

6. The function name maximum length is a preset number of characters, for example, 50 characters.

7. The module written by VerilogHDL has a hierarchical calling characteristic, namely other functional module calls are called in a top-level module to realize complete functions, and call nesting exists among C functions to realize complete functions, so that the specified function name needs to have a corresponding prefix to distinguish a main function from a sub-function, for example, the prefix of the main function can be 'top', and the prefix of the sub-function can be 'fun'.

8. When a constant value is used in any function, the function is defined as a global constant to facilitate subsequent analysis.

And S102, reading function content data of each function in the target mathematical model.

The function content data at least comprises a function name, a function parameter and a function statement. Function arguments refer to the individual parameters defined in the function name.

In the conversion process, the corresponding module unit is mainly converted according to the function name, the corresponding interface is converted according to the function form, and the function statement corresponds to the execution logic of the module unit, so that the function statement needs to be analyzed, and finally, the information set, the module name, the module input and output interfaces and the corresponding bit length of the VerilogHDL module unit, the register variable or linear variable in the module, the flow of a state machine, the type of the floating point operator, the number of needed instantiations and the like are obtained. Therefore, it is necessary to read the function name, function argument, and function statement of each function.

Of course, for the function content data, local variables within the function and global constants within the function may also be included. And the function content data can be stored in a dictionary set mode, wherein keys in each key value pair in the dictionary are function names, and values are function names, function parameters, local variables in the functions and global constants in the functions.

Optionally, in another embodiment of the present application, in order to facilitate searching and converting each numerical value in the function subsequently, in this embodiment of the present application, after performing step S101, not only the function content is read, but also the following steps may be further performed:

reading each target numerical value and related information thereof in the function in the target mathematical model, and respectively forming each target numerical value dictionary set by using each numerical value and related information thereof.

The target numerical dictionary set comprises a constant dictionary set, a variable dictionary set, a structural body dictionary set and an array dictionary set. The keys of the key-value pairs in the constant dictionary set are constant names, and the values are value types and values. The key of the key-value pair in the variable dictionary set is the variable name, and the value is the value type and the value. The key of the key value pair in the structure dictionary set is a structure name, and the value is a numerical value type, a variable name in the structure and a corresponding numerical value. The key of the key-value pair in the array dictionary set is the array name, and the values are the array length, the array type and the array value.

And S103, converting to obtain the module unit corresponding to each function based on the function name of each function.

Specifically, each mathematical model implements a function of a certain function, that is, a module unit in verilog hdl, so that the module unit corresponding to each function can be obtained through conversion based on the function name of each function.

Optionally, in another embodiment of the present application, a specific implementation manner of step S103 includes:

and respectively aiming at each function, if the prefix of the function name of the function is a top-level character, converting the function into a top-level module unit corresponding to the function, and if the prefix of the function name of the function is the function character, converting the function into a general module unit corresponding to the function.

Where the top character may be "top" and the function character may be "fun". The top module unit is used for calling the general module unit to realize all functions, and the general module unit realizes the function of a certain sub-function.

And S104, respectively aiming at each function, converting each function parameter into an input interface or an output interface of the module unit corresponding to the function based on the type of each function parameter of the function.

Specifically, for each function parameter in each function, if the function parameter is a read-only input parameter, the function parameter is converted into an input interface of a wire mesh type (wire type) of the module unit corresponding to the function according to the length corresponding to the type of the function parameter.

And if the function form parameter is the write-only output parameter, converting the function form parameter into a register type (reg type) output interface of the module unit corresponding to the function according to the length corresponding to the type of the function form parameter.

And if the function parameters are readable and writable parameters, converting the function parameters into output interfaces and input interfaces of the module units corresponding to the functions according to the lengths corresponding to the types of the function parameters.

The length of the interface corresponding to the function parameters of the array type is the length of the array multiplied by the bit length corresponding to the type of the data in the array. That is, for other integer type function parameters, the corresponding bit length is fixed, and only the array is more specific.

Specifically, 32 bits are specified for Int32 type, 16 bits for Int16 type, 8 bits for Int8 type, 32 bits for float type, and 64 bits for double type. And for the structure body type, resolving into corresponding input interfaces or output interfaces one by one according to the variable name and the variable type in the structure body. For array types, and as input variables, the length of the corresponding net to be converted is equal to the product of the array length and the bit length corresponding to the data type. When used as an output variable, it is converted into a register set of corresponding array length.

For example, for the sub-function "void fun _ calu _ matrix" shown in fig. 2, the functional arguments following it are subjected to interface conversion, and since the arguments are all of float type, they can be correspondingly converted into respective 32-bit wire-type input interfaces in "fun _ calu _ matrix _ input" and 32-bit reg-type output interfaces in "fun _ calu _ matrix _ output" in fig. 5. And the function in the main function "void _ module" output to fig. 3 is referred to as a structural body, and the definition of the specific structural body is shown in fig. 4. Therefore, when the function parameters are converted, each parameter in the structure is converted, so that "top _ module _ input" and "top _ module _ output" in fig. 5 can be obtained.

And S105, resolving the variables in the functions into register type variables based on the types of the variables in the functions, and converting the constants in the functions into corresponding identifiers.

It should be noted that, when parsing the function functional statement, the variables and constants may be converted first. For the transformation process of the variable, the method is consistent with the way of the function argument, and only the function argument is transformed into the debit, and the debit is transformed into the corresponding variable. For example, after converting the local variables of the main function shown in fig. 3, the variables shown in fig. 6 can be obtained.

Specifically, in the embodiment of the present application, a specific implementation manner of step S105 includes:

and respectively searching the corresponding value and the type of each variable in each function from the target value dictionary set according to the name of the variable.

And converting the value corresponding to the variable into a register type variable with a bit length corresponding to the type of the variable.

And if the variable is a local variable, placing the converted variable in a module unit corresponding to the function to which the variable belongs.

And if the variable is a global variable, placing the converted variable in the top module unit.

And searching the numerical value corresponding to each constant from the target numerical value dictionary set according to the name of each constant in each function.

And based on the name and the corresponding numerical value of each constant, macro-defining the constant, converting the constant into a corresponding identifier, and storing the identifier in an independent callable file.

That is, for a constant, "# define" is used to process it, so as to convert it into a corresponding identifier, and separately generate a callable file for reference by a module file generated by other functions.

And S106, analyzing the operational characters in the functional sentences of the functions and the input variables and the output variables in the operational characters.

Specifically, the assignment statement, the judgment statement, the loop statement, the sub-function call statement, and the like in the function can be read in sequence, and then all the operators in the function statements, and the input variables and the output variables in the operators can be analyzed from the function statements. The operator may be a mathematical operator, a four-way operator, a judgment operator, a for loop number, or the like.

After the step, a relation is established with actual operation or other operations, and preparation is made for filling the interface parameters of the real floating point number IP or other self-defined function modules during the later conversion.

And S107, distributing the operation resources of each operator based on preset constraint conditions, and generating state machine information based on the operation resources of each operator and the input variables and the output variables in each operator.

The constraint condition is a constraint condition for resource use, and can be selected according to requirements.

Optionally, in another embodiment of the present application, the constraint condition includes resource maximization, resource minimization, and directional resource minimization. Correspondingly, in this embodiment of the present application, allocating operation resources of each operator based on a preset constraint condition includes:

if the preset constraint condition is that the resource is maximized, corresponding operation resources are respectively allocated to each operator in different function statements without coupling relation and each operator in a single function statement without coupling relation, that is, each operator is allocated with one corresponding operation resource for the operation of the operator.

And allocating a corresponding operation resource for each operator of the same type in different function statements having a coupling relationship, and allocating a corresponding operation resource for each operation of the same type having a coupling relationship in a single function statement. Because of the coupling relationship, multiple operators of the same type share one operation resource, and thus, the multiple operators of the same type only allocate one corresponding operation resource,

and if the preset constraint condition is that the resource is minimized, respectively allocating a corresponding operation resource for each operator of each type in all the function functional statements.

And if the preset constraint condition is the maximization of the directional resources, allocating a corresponding operation resource for each operational character of the directional type in all the function functional statements, and allocating the corresponding operation resource for each operational character which does not belong to the directional type based on the resource maximization.

In addition, in the embodiment of the present application, by generating a corresponding state machine, a specific implementation logic of a function functional statement is recorded. After the constraint condition is selected, the state of the state machine starts from the binary code b1, and then is increased according to the states of the unique codes, namely b1, b10, b100 and b1000 \8230 \ 8230, until all the function codes are analyzed. And, the default minimum bit length of the state machine state code is 8 bits, and the maximum bit length is 32 bits, namely when the state code is increased to exceed 32 bits, an error is reported and the conversion is terminated.

It should be further noted that, under the resource maximization condition, the state machine state transition condition is: 1. there is a coupling relationship between the upper and lower sentences, i.e. the input of equation 2 is the output of equation 1. 2. And other functional function modules are called. Under the condition of resource minimization or oriented resource minimization, besides 2 conditions specified under the condition of resource maximization, an operator used by two adjacent sentences is also a transformation condition.

For example, the state machine information shown in fig. 7 can be obtained by analyzing the function body statement of the main function in fig. 3 under the constraint of resource maximization, and the state machine information shown in fig. 8 can be obtained under the constraint of resource minimization.

And the loop statement is realized in a state machine by adopting a mode of accumulating a local register to judge whether the loop times are reached.

After the statement is parsed, information of each functional step executed by the state machine, that is, the state machine information, may be stored in a corresponding list for subsequent generation of a final verilog hd execution code from the template.

And S108, generating a VerilogHDL text corresponding to the target mathematical model according to a preset generation template and manufacturer floating point operation IP information based on the state machine information, the basic information of the module unit corresponding to each function and the information of the interface of the module unit corresponding to each function.

The floating point operation IP information and the generation template of different manufacturers can be preset by engineers.

Specifically, the floating point operation IP information includes a module function name, a main input port, a main output port, an input valid signal, an output valid signal, a clock signal, a reset signal, a consumed LUT, and FF resources. Different JSON texts can be written by software engineers according to manufacturers for calling and are subjected to consistency processing, namely, unified names are added in the texts aiming at the problem of inconsistent names of different manufacturers, and port signals are conveniently filled in during instantiation.

The generated template may include common interface signals, such as a global clock clk signal, a reset signal rst _ n, and a chip select signal cs _ n. And, include the conversion sequential logic between the present state "current _ state" and the next state "next _ state" of the internal state machine of the module unit, initialize the reset or chip selection logic statement. The generation is the same for each function, the difference is the type and the number of the called floating point number IP, and the called custom module and the content of the state machine need to be dynamically generated.

For example, as shown in fig. 9, it can be seen that the framework of verilog hdl has specified that the program only needs to dynamically generate code to fill in the content of "fillblock" according to different functions of different functions. For example, the function shown in fig. 3 is converted, and the converted data of the part of "fill block4" in fig. 9 may be as shown in fig. 10, while the converted data of "fill block5" in fig. 9 may be as shown in fig. 11, and the same applies to the data of the other parts.

Optionally, after the conversion is completed, the file of the ". V" suffix of VerilogHDL and the comprehensive resource usage report file in ". Html" format are output by function name. The number of the floating point number IP types used by the current module and other resource consumption information, such as FF, LUT, reg, etc., are also described in the report.

Therefore, in another embodiment of the present application, after step S108 is executed, the following steps may be further executed:

The embodiment of the application provides a model conversion method, and a target mathematical model compiled based on a preset compiling rule is obtained. And then reading out the function content data of each function in the target mathematical model. The function content data at least comprises a function name, a function parameter and a function statement. And then converting the function parameters into input interfaces or output interfaces of the module units corresponding to the functions respectively aiming at each function based on the type of the function parameters of the function. Then, the variables in each function are analyzed into register type variables based on the types of the variables in each function, the constants in each function are converted into corresponding identifiers, operators in each function statement of the function and input variables and output variables in the operators are analyzed, then, operation resources of each operator are allocated based on preset constraint conditions, and state machine information is generated based on the operation resources of each operator and the input variables and the output variables in each operator, thereby realizing the conversion of the function statement. And finally, generating a VerilogHDL text corresponding to the target mathematical model according to a preset generation template and manufacturer floating point operation IP information based on the state machine information, the basic information of the module unit corresponding to each function and the information of the interface of the module unit corresponding to each function. Therefore, the method for automatically converting the mathematical model written in the C language into the model written in the Verilog HDL language is realized, manual compiling is not needed any more, the conversion efficiency is improved, and errors are avoided.

Another embodiment of the present application provides a model transformation apparatus, as shown in fig. 12, including:

the model obtaining unit 1201 is configured to obtain a target mathematical model written based on a preset writing rule.

A first reading unit 1202, configured to read out function content data of each function in the target mathematical model.

The function content data at least comprises a function name, a function parameter and a function statement.

A name conversion unit 1203, configured to obtain a module unit corresponding to each function through conversion based on the function name of each function.

An interface conversion unit 1204, configured to convert, for each function, each function parameter into an input interface or an output interface of the module unit corresponding to the function based on the type of each function parameter of the function.

A function parameter conversion unit 1205 is used to resolve the variables in each function into register type variables based on the type of the variables in each function, and convert the constants in each function into corresponding identifiers.

And the information parsing unit 1206 is used for parsing out the operational characters in the functional statements of the functions and the input variables and the output variables in the operational characters.

A statement conversion unit 1207, configured to allocate operation resources of each operator based on a preset constraint condition, and generate state machine information based on the operation resources of each operator and input variables and output variables in each operator.

And a result generating unit 1208, configured to generate, based on the state machine information, the basic information of the module unit corresponding to each function, and the information of the interface of the module unit corresponding to each function, a verilog hdl text corresponding to the target mathematical model according to a preset generating template and the manufacturer floating point operation IP information.

Optionally, in a model transformation apparatus provided in another embodiment of the present application, the apparatus further includes:

and the second reading unit is used for reading each target numerical value and related information thereof in the function in the target mathematical model and respectively forming each target numerical value dictionary set by using each numerical value and related information thereof.

The target numerical dictionary set comprises a constant dictionary set, a variable dictionary set, a structural body dictionary set and an array dictionary set. The key of a key-value pair in the constant dictionary set is a constant name, and the value is a numeric value type and a numeric value. The key of the key-value pair in the variable dictionary set is the variable name, and the value is the value type and the value. The key of the key value pair in the structure dictionary set is a structure name, and the value is a numerical value type, a variable name in the structure and a corresponding numerical value. The key of the key-value pair in the array dictionary set is the array name, and the value is the array length, the array type and the array value.

Optionally, in a model conversion apparatus provided in another embodiment of the present application, the function parameter conversion unit includes:

and the first searching unit is used for respectively searching the corresponding numerical value and the type of the variable from the target numerical value dictionary set according to the name of the variable aiming at each variable in each function.

And the first conversion unit is used for converting the numerical value corresponding to the variable into a register type variable with the bit length corresponding to the type of the variable.

And the first placing unit is used for placing the converted variable into the module unit corresponding to the function to which the variable belongs when the variable is the local variable.

And the second placement unit is used for placing the converted variable into the top module unit when the variable is the global variable.

And the second searching unit is used for searching the numerical value corresponding to the constant from the target numerical dictionary set according to the name of each constant in each function.

Optionally, in a model conversion apparatus provided in another embodiment of the present application, the interface conversion unit includes:

and the input interface conversion unit is used for respectively aiming at each function parameter in each function, and if the function parameter is a read-only input parameter, converting the function parameter into the line network type input interface of the module unit corresponding to the function according to the length corresponding to the type of the function parameter. The length of the interface corresponding to the function parameters of the array type is the length of the array multiplied by the bit length corresponding to the type of the data in the array.

And the output interface conversion unit is used for converting the function form parameter into a register type output interface of the module unit corresponding to the function according to the length corresponding to the type of the function form parameter when the function form parameter is the write-only output parameter.

And the double-interface conversion unit is used for converting the function parameters into the output interface and the input interface of the module unit corresponding to the function according to the lengths corresponding to the types of the function parameters when the function parameters are readable and writable parameters.

Optionally, in a model conversion apparatus provided in another embodiment of the present application, the name conversion unit includes:

and the top conversion unit is used for respectively aiming at each function, and if the prefix of the function name of the function is a top character, converting the function into a top module unit corresponding to the function.

Optionally, in a model conversion apparatus provided in another embodiment of the present application, the constraint condition includes resource maximization, resource minimization and directional resource minimization, and when the statement conversion unit executes the operation resource allocation for each operator based on the preset constraint condition, the statement conversion unit is configured to:

and if the preset constraint condition is that the resources are maximized, respectively allocating corresponding operation resources to each operational character in different function functional statements without coupling relation and each operational character in a single function functional statement without coupling relation.

And allocating a corresponding operation resource for each operator of the same type in different function statements with coupling relation, and allocating a corresponding operation resource for each operation of the same type with coupling relation in a single function statement.

Optionally, in a model conversion apparatus provided in another embodiment of the present application, the apparatus further includes:

It should be noted that, in the specific working process of each unit provided in the foregoing embodiment of the present application, reference may be made to the specific implementation process of the corresponding step in the foregoing method embodiment, and details are not described here again.

Another embodiment of the present application provides an electronic device, as shown in fig. 13, including:

memory 1301 and processor 1302.

The memory 1301 is used to store programs.

The processor 1302 is configured to execute a program stored in the memory 1302, and when executed, the program is specifically configured to implement the model transformation method provided in any of the embodiments described above.

Another embodiment of the present application provides a computer storage medium for storing a computer program, wherein when the computer program is executed, the computer program is used for implementing the model conversion method provided in any one of the above embodiments.

Computer storage media, including permanent and non-permanent, removable and non-removable media, may implement the information storage by any method or technology. The information may be computer readable instructions, data structures, modules of a program, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static Random Access Memory (SRAM), dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), read Only Memory (ROM), electrically Erasable Programmable Read Only Memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD-ROM), digital Versatile Discs (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices, or any other non-transmission medium that can be used to store information that can be accessed by a computing device. As defined herein, a computer readable medium does not include a transitory computer readable medium such as a modulated data signal and a carrier wave.

Those of skill would further appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative components and steps have been described above generally in terms of their functionality in order to clearly illustrate this interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the technical solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method of model conversion, comprising:

resolving variables in each function into register-type variables based on the type of the variables in each function, and converting constants in each function into corresponding identifiers;

and generating a VerilogHDL text corresponding to the target mathematical model according to a preset generation template and manufacturer floating point operation IP information based on the state machine information, the basic information of the module unit corresponding to each function and the information of the interface of the module unit corresponding to each function.

2. The method according to claim 1, wherein after obtaining the target mathematical model written based on the preset writing rule, the method further comprises:

reading each target numerical value and related information thereof in a function in the target mathematical model, and respectively forming each target numerical value dictionary set by using each numerical value and related information thereof; the target numerical dictionary set comprises a constant dictionary set, a variable dictionary set, a structure dictionary set and an array dictionary set; keys of key-value pairs in the constant dictionary set are constant names, and values are numerical value types and numerical values; keys of key-value pairs in the variable dictionary set are variable names, and values are numerical value types and numerical values; keys of key value pairs in the structure dictionary set are structure names, and values are numerical value types, variable names in the structures and corresponding numerical values; the key of the key value pair in the array dictionary set is an array name, and the value is an array length, an array type and an array value.

3. The method of claim 2, wherein the resolving variables in each of the functions into register-type variables based on the type of the variables in each of the functions, and converting constants in each of the functions into corresponding identifiers comprises:

converting the numerical value corresponding to the variable into a register type variable with a bit length corresponding to the type of the variable;

4. The method according to claim 1, wherein the converting, for each function, each function parameter into an input interface or an output interface of a module unit corresponding to the function based on a type of each function parameter of the function, respectively comprises:

if the function parameters are write-only output parameters, converting the function parameters into register type output interfaces of the module units corresponding to the functions according to the lengths corresponding to the types of the function parameters;

5. The method according to claim 1, wherein the converting to obtain the module unit corresponding to each function based on the function name of each function comprises:

6. The method according to claim 1, wherein the constraints include resource maximization, resource minimization and directional resource minimization, and the allocating operation resources of each of the operators based on the preset constraints comprises:

allocating a corresponding operation resource for each of the operators of the same type in different functional statements having a coupling relationship, and allocating a corresponding operation resource for each of the operations of the same type having a coupling relationship in a single functional statement;

7. The method of claim 1, further comprising:

8. A model conversion apparatus, comprising:

the information analysis unit is used for analyzing an operational character in each function functional statement of the function and an input variable and an output variable in the operational character;

9. An electronic device, comprising:

a memory and a processor;

wherein the memory is used for storing programs;

the processor is configured to execute the program, which when executed is specifically configured to implement the model transformation method as claimed in any one of claims 1 to 7.

10. A computer storage medium for storing a computer program which, when executed, is adapted to implement the model transformation method of any one of claims 1 to 7.