CN115803651A

CN115803651A - Radar signal processing device and method, radar system and mobile platform

Info

Publication number: CN115803651A
Application number: CN202080102739.7A
Authority: CN
Inventors: 徐江丰; 荆涛
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2020-07-31
Filing date: 2020-07-31
Publication date: 2023-03-14
Also published as: WO2022021436A1

Abstract

The radar signal processing device (200, 1602, 2001) comprises at least two RSPU chips (201), the at least two RSPU chips (201) are interconnected in one or more cascade connection modes, and signals output by the microwave signal processing device are subjected to cascade connection processing by the at least two RSPU chips (201). The provided radar signal processing device (200, 1602, 2001) improves the data processing capability of the radar signal processing device (200, 1601, 1602, 2001) and can improve the processing efficiency of a radar system (103) by performing cascade expansion on an RSPU chip (201) according to the dimension of a signal processing unit or according to the dimension of a data processing unit included in the signal processing unit; in addition, the RSPU chip (201) included in the radar signal processing device (200, 1602, 2001) can be flexibly expanded according to the requirements of intelligent driving of all levels and the increasing signal processing algorithm requirements of the vehicle-mounted radar.

Description

Radar signal processing device and method, radar system and mobile platform

Technical Field

The application relates to the technical field of radars, in particular to a radar signal processing device and method, a radar system and a mobile platform.

Background

With the rapid development of internet technology and artificial intelligence technology, the era of intelligent driving has come. In the smart driving, it is necessary to sense an external environment and detect information of a vehicle itself through various sensors, for example, a three-dimensional coordinate and a speed of a 4D radar detection target object having high resolution and high accuracy.

Among them, the 4D radar is mainly directed to automatic driving, and is an important direction of current research. In the working process of the 4D radar, the antenna unit of the 4D radar is required to be matched with a radar system for use. The radar system of the 4D radar generally includes a chip for processing radar radio frequency signals and analog signals and a chip for processing radar baseband data, and the conventional radar system has low processing efficiency.

Disclosure of Invention

The embodiment of the application provides a radar signal processing device and method, a radar system and a mobile platform, so that the processing efficiency of the radar system is improved.

In a first aspect, an embodiment of the present application provides a radar signal processing apparatus applied to a radar system, including: the system comprises at least two Radar Signal Processing Units (RSPUs), wherein the at least two RSPUs are interconnected in a cascade mode;

wherein, adopt cascade mode interconnection between at least two RSPUs, include:

an input interface of a first RSPU in the at least two RSPUs is coupled with an output interface of a microwave signal processing device, and the input interface of the first RSPU is used for receiving a signal output by the microwave signal processing device; the at least two RSPUs are used for performing cascade processing on the signals output by the microwave signal processing device;

the other RSPU in the at least two RSPUs is coupled with the first RSPU, and the output interface of the first RSPU is used for outputting the signal after the cascade processing; or, the other RSPUs of the at least two RSPUs are sequentially coupled to the output interface of the first RSPU, and the output interface of the last RSPU is used for outputting the concatenated signal.

According to the radar signal processing device provided by the embodiment, the RSPU is subjected to cascade expansion according to the dimensionality of the signal processing unit or the dimensionality of the data processing unit included by the signal processing unit, so that the data processing capacity of the radar signal processing device is improved, and the processing efficiency of a radar system can be improved; in addition, the RSPU included in the radar signal processing device can be flexibly expanded according to the requirements of intelligent driving of all levels, the increasing signal processing algorithm requirements of the vehicle-mounted radar and the like.

In some possible designs, when the at least two RSPUs are interconnected in a parallel cascade manner, the at least two RSPUs are used for performing parallel cascade processing on a signal output by the microwave signal processing device;

the input ends of at least two first RSPUs are respectively coupled with the output interface of the microwave signal processing device, and the input interfaces of the at least two first RSPUs are respectively used for receiving signals output by the microwave signal processing device; in the at least two first RSPUs, a signal output end of a last data processing unit of each first RSPU is coupled to a same output interface, and the output interface is used for outputting a signal after parallel cascade processing.

At least two RSPUs are connected in a parallel cascade mode, each RSPU can have the same or equivalent data processing capacity, and the at least two RSPUs can share the operation amount approximately in a balanced mode according to the data processing capacity, so that the same amount of data are approximately processed by each RSPU, and the basic synchronization of the processing time delay is further ensured on the basis of the parallel processing relation among the RSPUs.

In some possible designs, the input interface of each of the at least two first RSPUs is respectively coupled with the output interface of the monolithic microwave integrated circuit MMIC of one or more of the microwave signal processing devices.

In some possible designs, each of the at least two first RSPUs includes a plurality of data processing units coupled in sequence, the plurality of data processing units including a first data processing unit and a second data processing unit coupled in sequence;

the output interface of the first data processing unit in each of the at least two first RSPUs is coupled with the input interface of the second data processing unit of the remaining first RSPUs of the at least two first RSPUs;

the input interface of the second data processing unit in each of the first RSPUs is configured to receive signals output by the first data processing units of the remaining first RSPUs of the at least two first RSPUs.

When the parallel cascade connection mode is adopted for connection, the first data processing unit included by each first RSPU is mutually coupled with the second data processing units of other first RSPUs, so that the second data processing unit of each first RSPU can acquire all data output by the microwave signal processing device, and the second data processing unit of each first RSPU can share the computation amount based on the data processing capacity of the second data processing unit, and further ensures that the processing time delay is basically synchronous on the basis of the parallel processing relation between the RSPUs.

In some possible designs, the first data processing unit is a distance dimension fourier transform unit and the second data processing unit is a doppler dimension fourier transform unit.

When parallel cascade connection is adopted, each first RSPU in at least two first RSPUs can acquire data output by distance dimension Fourier transform units included by all the first RSPUs, namely data output by the microwave signal processing device after distance dimension Fourier transform; and then, the Doppler dimension Fourier transform unit of each first RSPU can share data of all antenna units in a balanced manner based on the distance dimension, and the basic synchronization of the processing time delay is further ensured on the basis of realizing the parallel processing relationship among the RSPUs.

In some possible designs, the first data processing unit is a CFAR unit and the second data processing unit is a DOA calculation unit.

When parallel cascade connection is adopted, in at least two first RSPUs, each first RSPU can acquire data processed and output by CFAR units included in all the first RSPUs, namely data after all data output by the microwave signal processing device pass through CFAR; and then, the DOA computing unit of each first RSPU can share the data of all the antenna units in a balanced manner based on the dimensionality of the target number after CFAR, and the basic synchronization of the processing time delay is further ensured on the basis of realizing the parallel processing relationship among the RSPUs.

In some possible designs, the first data processing unit is a DOA calculation unit and the second data processing unit is a data trace unit.

When parallel cascade connection is adopted, in at least two first RSPUs, each first RSPU can acquire data output by a DOA (direction of arrival) calculation unit included in the first RSPU, namely data after all data output by the microwave signal processing device pass through the DOA; and then, the data tracking unit of each first RSPU can share the data of all the antenna units in a balanced manner based on the dimensionality of the target number calculated by the DOA, and the basic synchronization of the processing time delay is further ensured on the basis of realizing the parallel processing relationship among the RSPUs.

In addition, in practical application, the at least two first RSPUs may simultaneously support a plurality of tandem nodes on a hardware structure, and control the state of one or more tandem nodes between the at least two first RSPUs through software according to actual requirements. Therefore, the flexibility of parallel cascade connection of at least two first RSPUs is realized, and the radar signal processing device can flexibly meet the requirements of different signal processing algorithms.

In some possible designs, further comprising: and the input interface of the third RSPU is coupled with the output interfaces of the at least two first RSPUs, and the third RSPU is used for correspondingly processing the signals output by the at least two first RSPUs and outputting the processed signals through the output interface of the third RSPU.

The third RSPU is coupled to the output interfaces of the at least two RSPUs in a serial cascade mode, and the third RSPU can be used for realizing algorithm expansion, so that the radar signal processing device can flexibly adapt to the requirements of different signal processing algorithms.

In some possible designs, further comprising: a fourth RSPU; the fourth RSPU is coupled between two data processing units sequentially coupled in any of the first RSPUs; or the fourth RSPU is coupled between two data processing units sequentially coupled in the third RSPU; or the input interface of the fourth RSPU is coupled to the input interface of any data processing unit in any of the first RSPUs, and the output interface of the fourth RSPU is coupled to the output interface of any other data processing unit in the first RSPU; alternatively, the input interface of the fourth RSPU is coupled to the input interface of any of the data processing units in the third RSPU, and the output interface of the fourth RSPU is coupled to the output interface of any of the other data processing units in the third RSPU.

The fourth RSPU is coupled to any one of the at least two RSPUs in a cooperative processing cascade mode, or coupled to the third RSPU, the fourth RSPU can be used for realizing an intermediate algorithm node or a branch algorithm node, and the fourth RSPU can be used for realizing algorithm expansion, so that the radar signal processing device can flexibly adapt to the requirements of different signal processing algorithms.

In some possible designs, when the at least two RSPUs are interconnected in a serial cascade manner, the at least two RSPUs are used for performing serial cascade processing on a signal output by the microwave signal processing device;

an input interface of the first RSPU of the at least two RSPUs is coupled to an output interface of the microwave signal processing apparatus, other RSPUs of the at least two RSPUs are sequentially coupled to an output interface of the first RSPU, and an output interface of the last RSPU is used for outputting a serial cascade processed signal;

the at least two RSPUs comprise completely different data processing units.

At least two RSPUs are connected in a serial cascade mode, the RSPUs are in a serial relation, namely after the RSPU of the previous stage processes data, the processed data are output to the RSPU of the next stage, and each RSPU serially processes the data corresponding to all the antenna units. For the small-specification radar device, the connection can be realized in a serial cascade mode, loose coupling is realized among the RSPUs, and independent algorithm expansion is favorably carried out on different data processing units included by different RSPUs.

In some possible designs, the at least two RSPUs each include: one or more of a distance dimensional Fourier transform unit, a Doppler dimensional Fourier transform unit, a CFAR unit, a DOA computation unit, a data tracking unit, and the at least two RSPUs are completely different.

In some possible designs, further comprising: a fifth RSPU;

wherein an input interface of the fifth RSPU is coupled to an output interface of any one of the at least two RSPUs, or an input interface of the fifth RSPU is coupled to an output interface of one or more MMICs in the microwave signal processing device; an output interface of the fifth RSPU is coupled to an output interface of any remaining RSPU of the at least two RSPUs;

the fifth RSPU is configured to receive a signal from an RSPU coupled to an input interface of the fifth RSPU or the microwave signal processing apparatus, perform corresponding processing on the received signal, and output the processed signal through an output interface of the fifth RSPU.

The fifth RSPU is coupled between the output interface of the microwave signal processing device and the output interfaces of the at least two RSPUs in a parallel cascade connection mode, and when the specification of the radar device is expanded, for example, an antenna unit is added, the fifth RSPU can be used for processing data of the newly added antenna unit, so that the radar device can meet the requirement of an intelligent driving level.

In some possible designs, further comprising: a sixth RSPU; the sixth RSPU is coupled between two data processing units sequentially coupled in any one of the RSPUs; or the sixth RSPU is coupled between two data processing units sequentially coupled in the fifth RSPU; or the input interface of the sixth RSPU is coupled to the input interface of any data processing unit in any RSPU, and the output interface of the sixth RSPU is coupled to the output interface of any other data processing unit in the RSPU; alternatively, the input interface of the sixth RSPU is coupled to the input interface of any one of the data processing units in the fifth RSPU, and the output interface of the sixth RSPU is coupled to the output interface of any other one of the data processing units in the fifth RSPU.

The sixth RSPU is coupled to any one of the at least two RSPUs in a cooperative processing cascade mode, or coupled to the fifth RSPU, the sixth RSPU can be used for realizing an intermediate algorithm node or a branch algorithm node, and the sixth RSPU can be used for realizing algorithm expansion, so that the radar signal processing device can flexibly adapt to the requirements of different signal processing algorithms.

In some possible designs, when the at least two RSPUs are coupled in a cooperative cascade manner, the at least two RSPUs are configured to perform a cooperative cascade process on the signal output by the microwave signal processing apparatus;

wherein an input interface of the first RSPU of the at least two RSPUs is coupled to an output interface of the microwave signal processing apparatus, other RSPUs of the at least two RSPUs are coupled to the first RSPU, and an output interface of the first RSPU is configured to output a cooperatively cascaded processed signal.

When the at least two RSPUs are connected in a cooperative processing cascade mode, some RSPUs can be intermediate algorithm points or branch algorithm points of the RSPUs connected with the microwave signal processing device, so that the at least two RSPUs can perform cooperative processing on data output by the microwave signal processing device, and the requirement of signal processing algorithm expansion can be met.

In some possible implementations, the first RSPU of the at least two RSPUs includes a plurality of sequentially coupled data processing units, the sequentially coupled plurality of data processing units including a first data processing unit and a second data processing unit that are sequentially coupled; the remaining RSPUs of the at least two RSPUs comprise a function extension unit;

an input interface of the function expansion unit is coupled to an output interface of the first data processing unit, and an output interface of the function expansion unit is coupled to an input interface of the second data processing unit;

the function extension unit is used for receiving signals from the first data processing unit of the first RSPU, performing corresponding processing on the received signals, and outputting the processed signals to the second data processing unit of the first RSPU.

In the manner of this embodiment, the RSPU including the function extension unit is an intermediate algorithm point of the RSPU connected to the microwave signal processing apparatus, and a cooperative cascade of at least two RSPUs is implemented. In practical application, at least two RSPUs can be connected in hardware by the method of the present embodiment, and the operating state of the function extension unit is controlled by software according to actual requirements, so as to meet the requirements of the signal processing algorithm on the extension of the intermediate algorithm.

In some possible designs, the first of the at least two RSPUs comprises a plurality of data processing units coupled in series, and remaining ones of the at least two RSPUs comprise a function extension unit;

the input interface of the function expansion unit is coupled to the output interface of one of the plurality of data processing units, and the input interface of the function expansion unit is coupled to the input interface of any one of the remaining data processing units of the plurality of data processing units.

In the mode of this embodiment, the RSPU including the function extension unit is a branch algorithm point of the RSPU connected to the microwave signal processing apparatus, and a cooperative cascade of at least two RSPUs is implemented. In practical application, at least two RSPUs may be connected to each other in hardware by using the method of the present embodiment, and the operating state of the function extension unit is controlled by software according to actual requirements, so as to meet the requirements of the signal processing algorithm on the extension of the branch algorithm.

It should be understood that in some cases, the implementation of the RSPU as an intermediate algorithm point and the RSPU as a branch algorithm point may exist simultaneously, enabling a coordinated concatenation of at least two RSPUs. In practical application, the RSPU can be simultaneously supported as an intermediate algorithm point and the RSPU as a branch algorithm point by hardware between at least two RSPUs, the working state of the RSPU as the intermediate algorithm point and the working state of the RSPU as the branch algorithm point are controlled by software according to actual requirements, the requirement of a signal processing algorithm for the expansion of the intermediate algorithm and the requirement of the signal processing algorithm point for the expansion of the branch algorithm are met, and the data processing efficiency of the radar signal processing device is improved.

The sequentially coupled plurality of data processing units comprises: the device comprises a distance dimension Fourier transform unit, a Doppler dimension Fourier transform unit, a CFAR unit, a DOA calculation unit and a data tracking unit;

the signal input part of the distance dimension Fourier transform unit is coupled with the output interface of the microwave signal processing device through the input interface of the first RSPU, the signal output part of the distance dimension Fourier transform unit is connected with the signal input part of the Doppler dimension Fourier transform unit, the signal output part of the Doppler dimension Fourier transform unit is connected with the signal input part of the CFAR unit, the signal output part of the CFAR unit is connected with the signal input part of the DOA calculation unit, the signal output part of the DOA calculation unit is connected with the signal output input part of the data tracking unit, and the signal output part of the data tracking unit is coupled with the output interface of the first RSPU.

In some possible designs, further comprising: a seventh RSPU, wherein an input interface of the seventh RSPU is coupled to an output interface of the first RSPU, and the seventh RSPU is configured to receive the signal output by the first RSPU, process the received signal accordingly, and output the processed signal through an output interface of the seventh RSPU.

The seventh RSPU is coupled to the output interface of the first RSPU in a serial cascade mode, and the seventh RSPU can be used for further processing data output by the first RSPU when the algorithm of the radar device is expanded, so that the radar device can meet the requirement of a signal processing algorithm.

In a second aspect, an embodiment of the present application further provides a radar system, including: a microwave signal processing apparatus and the radar signal processing apparatus according to any one of the first to third aspects;

the microwave signal processing device comprises one or more Monolithic Microwave Integrated Circuits (MMICs), wherein an input interface of each MMIC is coupled to an output interface of one or more antenna units, and an output interface of each MMIC is coupled to an input interface of one Radar Signal Processing Unit (RSPU) in the radar signal processing device; each MMIC is used for carrying out radio frequency and analog signal processing on signals input by one or more antenna units;

the radar signal processing device comprises at least two RSPUs which are interconnected in a cascade mode;

an input interface of a first RSPU in the at least two RSPUs is coupled with an output interface of the microwave signal processing device, and the input interface of the first RSPU is used for receiving a signal output by the microwave signal processing device; the at least two RSPUs are used for performing cascade processing on the signals output by the microwave signal processing device;

the other RSPUs in the at least two RSPUs are coupled with the first RSPU, and the output interface of the first RSPU is used for outputting the cascade-processed signals; or, the other RSPUs of the at least two RSPUs are sequentially coupled to the output interface of the first RSPU, and the output interface of the last RSPU is used for outputting the signal after the cascade processing.

In the radar system provided by this embodiment, the radar signal processing device performs cascade expansion on the RSPU according to the dimensionality of the signal processing unit or according to the dimensionality of the data processing unit included in the signal processing unit, so that the data processing capability of the radar signal processing device is improved, and the processing efficiency of the radar system can be improved; in addition, the RSPU included in the radar signal processing device can be flexibly expanded according to the requirements of intelligent driving of all levels, the increasing signal processing algorithm requirements of the vehicle-mounted radar and the like.

In some possible designs, the microwave signal processing device includes at least two sets of microwave signal processing circuits, each set of microwave signal processing circuits includes at least one MMIC, and each set of MMICs is correspondingly connected to one RSPU in the radar signal processing device.

In the radar system provided by this embodiment, at least two MMICs included in the microwave signal processing device are connected in a parallel cascade manner, and each MMIC processes data of different antenna units, so that the data processing capability of the microwave signal processing device is improved, and the processing efficiency of the radar system is further improved; and the MMIC included in the microwave signal processing device can be flexibly expanded according to the requirements of intelligent driving of each level, the increasing signal processing algorithm requirements of the vehicle-mounted radar and the like.

In a third aspect, an embodiment of the present application further provides a mobile platform, including: the radar signal processing apparatus, the microwave signal processing apparatus, and the automatic driving control system according to any one of the first aspect,

the microwave signal processing device comprises one or more MMICs, wherein an input interface of each MMIC is coupled with an output interface of one or more antenna units, and an output interface of each MMIC is coupled with an input interface of one radar signal processing unit RSPU in the radar signal processing device; each MMIC is used for carrying out radio frequency and analog signal processing on signals input by one or more antenna units;

the other RSPUs in the at least two RSPUs are coupled with the first RSPU, and the output interface of the first RSPU is used for outputting the signals after the cascade processing to the automatic driving control system; or other RSPUs in the at least two RSPUs are sequentially coupled to the output interface of the first RSPU, and the output interface of the last RSPU is used for outputting the cascade-processed signal to the automatic driving control system;

the automatic driving control system is used for acquiring a radar detection result according to the signal output by the radar signal processing device and controlling the vehicle to carry out intelligent driving according to the radar detection result.

In the mobile platform provided in this embodiment, the radar signal processing apparatus performs cascade expansion on the RSPU according to the dimension of the signal processing unit or according to the dimension of the data processing unit included in the signal processing unit, so as to improve the data processing capability of the radar signal processing apparatus and improve the processing efficiency of the radar system; in addition, the RSPU included in the radar signal processing device can be flexibly expanded according to the requirements of intelligent driving of all levels, the increasing signal processing algorithm requirements of the vehicle-mounted radar and the like.

In a fourth aspect, an embodiment of the present application further provides a radar signal processing method applied to a radar system, where the radar system includes a radar signal processing apparatus, and the radar signal processing apparatus includes: the radar signal processing unit comprises at least two Radar Signal Processing Units (RSPUs), wherein the at least two RSPUs are interconnected in a cascade mode; the method comprises the following steps:

receiving a signal output by the microwave signal processing device through an input interface of a first RSPU in the at least two RSPUs; the at least two RSPUs carry out cascade processing on the signals output by the microwave signal processing device;

outputting the concatenated signals through an output interface of the first RSPU, wherein other RSPUs of the at least two RSPUs are coupled to the first RSPU; or, the cascaded processed signal is output through an output interface of the last RSPU, wherein other RSPUs of the at least two RSPUs are sequentially coupled to the output interface of the first RSPU.

In this embodiment, the radar signal processing apparatus performs cascade expansion on the RSPU according to the dimensionality of the signal processing unit or according to the dimensionality of the data processing unit included in the signal processing unit, thereby improving the data processing capability of the radar signal processing apparatus and improving the processing efficiency of the radar system; in addition, the RSPU included in the radar signal processing device can be flexibly expanded according to the requirements of intelligent driving of all levels, the increasing signal processing algorithm requirements of the vehicle-mounted radar and the like.

In some possible designs, when the at least two RSPUs are interconnected in a parallel cascade manner, the at least two RSPUs are used for performing parallel cascade processing on a signal output by the microwave signal processing device; the input ends of at least two first RSPUs are respectively coupled with the output interface of the microwave signal processing device, and the input interfaces of the at least two first RSPUs are respectively used for receiving signals output by the microwave signal processing device; the signal output ends of the last data processing units of the at least two first RSPUs are coupled to the same output interface, and the output interface is used for outputting signals after parallel cascade processing;

and each of the at least two first RSPUs comprises a plurality of data processing units coupled in sequence, and the plurality of data processing units comprise a first data processing unit and a second data processing unit coupled in sequence;

in the at least two first RSPUs, an output interface of the first data processing unit in each of the first RSPUs is coupled with an input interface of the second data processing unit in the remaining first RSPUs of the at least two first RSPUs;

the at least two RSPUs perform parallel cascade processing on the signals output by the microwave signal processing device, and the parallel cascade processing comprises the following steps:

in the at least two first RSPUs, the second data processing unit of each first RSPU acquires data output by the first data processing units of other first RSPUs;

each first RSPU performs load balancing on data output by all the first data processing units according to the quantity of the at least two first RSPUs and the characteristics of the data output by the first data processing units, and determines to-be-processed data corresponding to second data processing units of the first RSPUs;

and the second data processing unit of each first RSPU processes the determined data to be processed.

In this embodiment, at least two RSPUs are connected in a parallel cascade manner, each RSPU may have the same or equivalent data processing capability, and the at least two RSPUs may share the computation amount approximately in a balanced manner according to the data processing capability, thereby achieving approximately processing the same amount of data by each RSPU. Specifically, when the parallel cascade connection mode is adopted for connection, the first data processing unit included in each first RSPU is coupled with the second data processing units of other first RSPUs, so that the second data processing unit of each first RSPU can acquire all data output by the microwave signal processing device, and the second data processing unit of each first RSPU can share the computation amount based on the data processing capacity of the second data processing unit, and further ensure the basic synchronization of the processing time delay on the basis of realizing the parallel processing relationship among the RSPUs.

In some possible designs, the first data processing unit is a distance dimensional fourier transform unit and the second data processing unit is a doppler dimensional fourier transform unit; the load balancing of the data output by all the first data processing units is performed by each first RSPU according to the number of the at least two first RSPUs and the characteristics of the data output by the first data processing units, and determining to-be-processed data corresponding to the second data processing unit of the first RSPU includes:

in the at least two first RSPUs, each first RSPU performs load balancing on data output by all the distance dimension Fourier transform units according to the number and the distance dimension of the at least two first RSPUs, and determines to-be-processed data corresponding to the Doppler dimension Fourier transform units of the first RSPUs.

In this embodiment, when parallel cascade connection is adopted, in at least two first RSPUs, each first RSPU may obtain data output by distance dimension fourier transform units included in all first RSPUs, that is, data after distance dimension fourier transform is performed on all data output by the microwave signal processing apparatus; and then, the Doppler dimension Fourier transform unit of each first RSPU can share data of all antenna units in a balanced manner based on the distance dimension, and the basic synchronization of the processing time delay is further ensured on the basis of realizing the parallel processing relationship among the RSPUs.

In some possible designs, the first data processing unit is a constant false alarm detection, CFAR, unit and the second data processing unit is a direction of arrival, DOA, calculation unit; the load balancing of the data output by all the first data processing units by each first RSPU according to the number of the at least two first RSPUs and the characteristics of the data output by the first data processing units, and determining the data to be processed corresponding to the second data processing units of the first RSPUs include:

in the at least two first RSPUs, each first RSPU performs load balancing on data output by all CFAR units according to the number of the at least two first RSPUs and the dimension of a target number, and determines to-be-processed data corresponding to a DOA detection unit of the first RSPU.

In this embodiment, when parallel cascade connection is adopted, in at least two first RSPUs, each first RSPU can obtain data processed and output by a CFAR unit included in all the first RSPUs, that is, data after all data output by a microwave signal processing device passes through a CFAR; and then, the DOA calculation unit of each first RSPU can share data of all antenna units in a balanced manner based on the dimensionality of the target number after CFAR, and the basic synchronization of the processing time delay is further ensured on the basis of realizing the parallel processing relationship among the RSPUs.

In some possible designs, the first data processing unit is a DOA calculation unit and the second data processing unit is a data trace unit; the load balancing of the data output by all the first data processing units by each first RSPU according to the number of the at least two first RSPUs and the characteristics of the data output by the first data processing units, and determining the data to be processed corresponding to the second data processing units of the first RSPUs include:

in the at least two first RSPUs, each first RSPU performs load balancing on data output by all DOA computing units according to the number of the at least two first RSPUs and the dimension of a target number, and determines to-be-processed data corresponding to a data tracking unit of the first RSPU.

In this embodiment, when parallel cascade connection is adopted, in at least two first RSPUs, each first RSPU can obtain data output by a DOA calculation unit included in the first RSPU, that is, data after all data output by the microwave signal processing apparatus passes through the DOA; and then, the data tracking unit of each first RSPU can share the data of all the antenna units in a balanced manner based on the dimensionality of the target number calculated by the DOA, and the basic synchronization of the processing time delay is further ensured on the basis of realizing the parallel processing relationship among the RSPUs.

In addition, in practical application, the at least two first RSPUs may simultaneously support a plurality of tandem nodes on a hardware structure, and control the state of one or more tandem nodes between the at least two first RSPUs through software according to actual requirements. Therefore, the flexibility of cascading at least two first RSPUs is realized, and the radar signal processing device can flexibly adapt to the requirements of different signal processing algorithms.

In some possible designs, the radar signal processing apparatus further includes: a third RSPU having an input interface coupled with output interfaces of the at least two first RSPUs;

the method further comprises the following steps:

the third RSPU receives signals output by the at least two first RSPUs;

and the third RSPU carries out corresponding processing on the signals output by the at least two first RSPUs and outputs the processed signals through an output interface of the third RSPU.

In some possible designs, the radar signal processing apparatus further includes: a fourth RSPU; the fourth RSPU is coupled between two data processing units sequentially coupled in any one of the first RSPUs; or the fourth RSPU is coupled between two data processing units sequentially coupled in the third RSPU; or the input interface of the fourth RSPU is coupled to the input interface of any data processing unit in any of the first RSPUs, and the output interface of the fourth RSPU is coupled to the output interface of any other data processing unit in the first RSPU; alternatively, the input interface of the fourth RSPU is coupled to the input interface of any one of the data processing units in the third RSPU, and the output interface of the fourth RSPU is coupled to the output interface of any other one of the data processing units in the third RSPU.

The fourth RSPU is coupled to any one of the at least two RSPUs or the third RSPU in a cooperative processing cascade mode, the fourth RSPU can be used for realizing an intermediate algorithm node or a branch algorithm node, and the fourth RSPU can be used for realizing algorithm expansion, so that the radar signal processing device can flexibly adapt to the requirements of different signal processing algorithms.

In some possible designs, when the at least two RSPUs are interconnected in a serial cascade manner, an input interface of the first RSPU of the at least two RSPUs is coupled to an output interface of the microwave signal processing apparatus, other RSPUs of the at least two RSPUs are sequentially coupled to the output interface of the first RSPU, and an output interface of the last RSPU is used for outputting a signal after serial cascade processing; the at least two RSPUs comprise completely different data processing units;

the at least two RSPUs carry out cascade processing on the signals output by the microwave signal processing device and comprise the following steps:

and the at least two RSPUs carry out serial cascade processing on the signals output by the microwave signal processing device.

In this embodiment, at least two RSPUs are connected in a serial cascade connection manner, and the RSPUs are in a serial relationship with each other, that is, after the RSPU of the previous stage processes data, the processed data is output to the RSPU of the next stage, and each RSPU serially processes data corresponding to all antenna units. For the small-specification radar device, the connection can be realized in a serial cascade mode, loose coupling is realized among all RSPUs, and the method is favorable for carrying out independent algorithm expansion on different data processing units included by different RSPUs.

In some possible designs, the radar signal processing apparatus further includes: a fifth RSPU;

the method further comprises the following steps:

the fifth RSPU receives signals from the RSPU coupled to the input interface of the fifth RSPU or the microwave signal processing device, and performs corresponding processing on the received signals;

and the fifth RSPU outputs the processed signal through an output interface of the fifth RSPU.

In some possible designs, the radar signal processing apparatus further includes: a sixth RSPU; the sixth RSPU is coupled between two sequentially coupled data processing units in any of the RSPUs; or, the sixth RSPU is coupled between two data processing units sequentially coupled in the fifth RSPU; or the input interface of the sixth RSPU is coupled to the input interface of any data processing unit in any RSPU, and the output interface of the sixth RSPU is coupled to the output interface of any other data processing unit in the RSPU; alternatively, the input interface of the sixth RSPU is coupled to the input interface of any one of the data processing units in the fifth RSPU, and the output interface of the sixth RSPU is coupled to the output interface of any other one of the data processing units in the fifth RSPU.

The sixth RSPU is coupled to any one of the at least two RSPUs in a cooperative processing cascade mode, or coupled to the fifth RSPU, the sixth RSPU can be used for realizing an intermediate algorithm node or a branch algorithm node, and the sixth RSPU can be used for realizing algorithm expansion, so that the radar signal processing device can flexibly adapt to requirements of different signal processing algorithms.

In some possible designs, when the at least two RSPUs are coupled in a cooperative processing cascade manner, an input interface of the first RSPU of the at least two RSPUs is coupled to an output interface of the microwave signal processing apparatus, and other RSPUs of the at least two RSPUs are coupled to the first RSPU, and the output interface of the first RSPU is configured to output a cooperative cascade processed signal;

the at least two RSPUs perform cascade processing on the signals output by the microwave signal processing device, and the cascade processing comprises the following steps:

and the at least two RSPUs are used for carrying out cooperative cascade processing on the signals output by the microwave signal processing device.

In some possible implementations, the first RSPU of the at least two RSPUs includes a plurality of sequentially coupled data processing units including a first data processing unit and a second data processing unit that are sequentially coupled; the remaining RSPUs of the at least two RSPUs comprise a function extension unit;

the input interface of the function expansion unit is coupled with the output interface of the first data processing unit, and the output interface of the function expansion unit is coupled with the input interface of the second data processing unit;

the at least two RSPUs carry out cascade processing on the signals output by the microwave signal processing device, and the cascade processing comprises the following steps:

the function expansion unit receives data output by the first data processing unit;

the function expansion unit correspondingly processes the data output by the first data unit and outputs the processed data to the second data processing unit;

and the second data processing unit correspondingly processes the data output by the function expansion unit.

In this embodiment, the RSPU including the function extension unit is an intermediate algorithm point of the RSPU connected to the microwave signal processing apparatus, and realizes the cooperative cascade of at least two RSPUs. In practical application, at least two RSPUs can be connected in hardware by the method of the present embodiment, and the operating state of the function extension unit is controlled by software according to actual requirements, so as to meet the requirements of the signal processing algorithm on the extension of the intermediate algorithm.

In some possible designs, if the at least two RSPUs are connected in a cooperative processing cascade; one of the at least two RSPUs comprises a plurality of data processing units coupled in sequence, and the remaining RSPUs of the at least two RSPUs comprise function extension units; the signal input end of the function expansion unit is connected with the signal output end of one of the data processing units, and the signal output end of the function expansion unit is connected with the signal input end of any one of the rest data processing units in the data processing units;

the function expansion unit receives the data output by the data processing units coupled in sequence;

and the function expansion unit correspondingly processes the data output by the data processing units coupled in sequence and outputs the processed data to the other data processing unit coupled in sequence.

In this embodiment, the RSPU including the function extension unit is a branch algorithm point of the RSPU connected to the microwave signal processing apparatus, and realizes the cooperative cascade of at least two RSPUs. In practical application, at least two RSPUs may be connected in hardware by using the method of this embodiment, and the working state of the function extension unit is controlled by software according to actual requirements, so as to meet the requirements of the signal processing algorithm for the extension of the branch algorithm.

In some possible designs, the sequentially coupled plurality of data processing units includes: the device comprises a distance dimension Fourier transform unit, a Doppler dimension Fourier transform unit, a CFAR unit, a DOA calculation unit and a data tracking unit;

In some possible designs, the radar signal processing apparatus further includes: a seventh RSPU, wherein an input interface of the seventh RSPU is coupled to an output interface of the first RSPU;

the method further comprises the following steps:

the seventh RSPU receives the signal output by the first RSPU and correspondingly processes the received signal;

and the seventh RSPU outputs the processed signal through an output interface of the seventh RSPU.

The seventh RSPU is coupled to the output interface of the first RSPU in a serial cascade mode, and when the algorithm of the radar device is expanded, the seventh RSPU can be used for further processing the data output by the first RSPU, so that the radar device can meet the requirement of a signal processing algorithm.

The embodiment of the application provides a radar signal processing device and method, a radar system and a mobile platform, wherein the radar signal processing device comprises at least two RSPUs, and the at least two RSPUs are interconnected in one or more cascade connection modes, so that cascade connection processing of signals output by a microwave signal processing device is achieved. According to the method and the device, the signal processing unit dimension or the data processing unit dimension included by the signal processing unit is used for carrying out cascade expansion on the RSPU, so that the data processing capacity of the radar signal processing device is improved, and the processing efficiency of a radar system can be improved; in addition, the RSPU included in the radar signal processing device can be flexibly expanded according to the requirements of intelligent driving of all levels, the increasing signal processing algorithm requirements of the vehicle-mounted radar and the like.

Drawings

Fig. 1 is a schematic view of an application scenario of a radar system according to an embodiment of the present application;

FIG. 2 is a schematic diagram of a prior art radar system;

fig. 3 is a schematic structural diagram of a radar signal processing apparatus according to an embodiment of the present disclosure;

fig. 4 is a schematic structural diagram of a radar signal processing apparatus according to another embodiment of the present application;

fig. 5 is a schematic structural diagram of a radar signal processing apparatus according to another embodiment of the present application;

fig. 6a is a schematic structural diagram of a radar signal processing apparatus according to another embodiment of the present application;

fig. 6b is a schematic structural diagram of a radar signal processing apparatus according to another embodiment of the present application;

fig. 7a is a schematic structural diagram of a radar signal processing apparatus according to another embodiment of the present application;

fig. 7b is a schematic structural diagram of a radar signal processing apparatus according to another embodiment of the present application;

fig. 7c is a schematic structural diagram of a radar signal processing apparatus according to another embodiment of the present application;

fig. 7d is a schematic structural diagram of a radar signal processing apparatus according to another embodiment of the present application;

fig. 8a is a schematic structural diagram of a radar signal processing apparatus according to another embodiment of the present application;

fig. 8b is a schematic structural diagram of a radar signal processing apparatus according to another embodiment of the present application;

fig. 9a is a schematic structural diagram of a radar signal processing apparatus according to another embodiment of the present application;

fig. 9b is a schematic structural diagram of a radar signal processing apparatus according to another embodiment of the present application;

fig. 9c is a schematic structural diagram of a radar signal processing apparatus according to another embodiment of the present application;

fig. 10 is a flowchart of a radar signal processing method according to an embodiment of the present application;

fig. 11 is a flowchart of a radar signal processing method according to another embodiment of the present application;

fig. 12a is a flowchart of a radar signal processing method according to another embodiment of the present application;

FIG. 12b is a schematic diagram illustrating a structure of a memory in a process of moving data between at least two RSPUs according to an embodiment of the present application;

fig. 13 is a flowchart of a radar signal processing method according to another embodiment of the present application;

fig. 14 is a flowchart of a radar signal processing method according to another embodiment of the present application;

fig. 15 is a flowchart of a radar signal processing method according to another embodiment of the present application;

fig. 16 is a schematic structural diagram of a radar system according to an embodiment of the present application;

fig. 17 is a schematic structural diagram of a radar system according to another embodiment of the present application;

fig. 18a is a schematic structural diagram of a radar system according to another embodiment of the present application;

fig. 18b is a schematic structural diagram of a radar system according to another embodiment of the present application;

fig. 18c is a schematic structural diagram of a radar system according to another embodiment of the present application;

fig. 18d is a schematic structural diagram of a radar system according to another embodiment of the present application;

fig. 19 is a schematic structural diagram of a radar system according to another embodiment of the present application;

fig. 20 is a schematic structural diagram of a mobile platform according to an embodiment of the present application.

Detailed Description

In the present application, "at least one" means one or more, "a plurality" means two or more. "and/or" describes the association relationship of the associated objects, meaning that there may be three relationships, e.g., a and/or B, which may mean: a exists alone, A and B exist simultaneously, and B exists alone, wherein A and B can be singular or plural. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship. "at least one of the following" or similar expressions refer to any combination of these items, including any combination of the singular or plural items. For example, at least one (one) of a, b, or c, may represent: a, b, c, a-b, a-c, b-c, or a-b-c, wherein a, b, c may be single or multiple.

With the rapid development of internet technology and artificial intelligence technology, the era of intelligent driving has come. In the smart driving, it is necessary to sense an external environment through various sensors and detect information of a vehicle itself. As shown in fig. 1, in an autonomous driving scenario, smart-driving vehicle 101 may detect surrounding vehicles, pedestrians, or other environmental targets via millimeter-wave radar devices, e.g., vehicle 101 shown in fig. 1 may detect the position, speed, etc. of vehicle 102 in a direction of travel via millimeter-wave radar devices. Specifically, the millimeter wave radar device includes: a radar system 103 and an antenna unit 104, wherein the antenna unit 104 is used for transmitting and receiving millimeter wave signals, and the radar system 103 is used for acquiring the speed and the position of the surrounding vehicle 102 according to the signals transmitted by the antenna unit 104.

It should be noted that, in the scenario shown in fig. 1, the installation position of the millimeter wave radar is merely an illustration, and the structure of the millimeter wave radar apparatus is not limited. For example, in practical applications, the antenna unit of the millimeter wave radar apparatus and the radar system may be integrated in the same module.

Of course, the millimeter wave radar may also be applied to other scenarios, for example, in an automatic parking scenario, the smart driving vehicle may detect the position of a surrounding obstacle through the millimeter wave radar, which is not illustrated here.

The millimeter wave radar has the advantages of all-time, all-weather, strong anti-interference capability and the like, and is an important sensor for intelligent driving. The existing millimeter wave radar mainly aims at an Advanced Driver Assistance System (ADAS) application of an L2 level, and generally has low specification indexes. Therefore, a high-resolution and high-precision 4D radar (also referred to as a 4D radar device or other names) for autonomous driving has appeared, which is a hot spot and an important technical direction of current research. The 4D radar has a higher antenna specification and a higher signal processing capability, and can image vehicles, pedestrians, road structures, and the like in the surrounding environment.

The 4D radar adopts a multiple-in-multiple-out (MIMO) technology, namely a plurality of antenna units are used at a transmitting end and a receiving end to form an antenna system with a plurality of channels, so that the detection accuracy of the 4D radar is improved; however, the specification of the functional circuit for processing the radar baseband data signal in the conventional radar signal processing system is relatively fixed, for example, the radar system in the prior art shown in fig. 2 (a) includes 1 Monolithic Microwave Integrated Circuit (MMIC) for radio frequency and analog signal processing and 1 Radar Signal Processing Unit (RSPU) for baseband data processing, and the radar system shown in fig. 2 (a) can be applied to a radar with a small specification; the radar system of the prior art shown in fig. 2 (b) includes 2 MMICs and 1 RSPU, and the radar system shown in fig. 2b can be applied to a medium-sized radar; the radar system of the related art shown in fig. 2 (c) includes 4 MMICs and 1 RSPU, and the radar system shown in fig. 2 (c) can be applied to a high-specification radar. However, the cascade extension of the radar system in the prior art mostly focuses on the MMIC for performing radio frequency and analog signal processing on the millimeter wave signal, and the specification of the RSPU chip for performing baseband data processing on the signal output by the MMIC is relatively fixed. For the 4D radar adopting the MIMO technology, the data processing capability of the RSPU chip in the conventional radar system cannot match the requirement of the 4D radar, thereby resulting in lower processing efficiency of the radar system.

Based on this, the present application provides a radar signal processing apparatus, including: and the at least two RSPUs are connected in one or more cascade connection modes to carry out cascade connection processing on the signals output by the microwave signal processing device.

The core concept of the application is that: the RSPU is subjected to cascade expansion according to the dimensionality of the signal processing unit or the dimensionality of a data processing unit included by the signal processing unit, so that the data processing capacity of the radar signal processing device is improved, and the processing efficiency of a radar system is further improved; and the RSPU included in the radar signal processing device can be flexibly expanded according to the requirements of intelligent driving of each level, the increasing signal processing algorithm requirements of the vehicle-mounted radar and the like.

Optionally, the cascade mode may include: one or more of a parallel cascade mode, a serial cascade mode, and a co-processing cascade mode.

In this application, cascading means coupling two or more devices together in some way.

Parallel cascading: meaning that two or more devices are coupled in a parallel fashion.

Serial concatenation: indicating that two or more devices are coupled in a serial fashion.

A co-processing cascade: the method represents a coupling mode which can realize the cooperative sharing of computing tasks by a plurality of devices.

In the following, the radar signal processing apparatus using different cascading methods will be described in detail through some specific embodiments.

Fig. 3 is a schematic structural diagram of a radar signal processing apparatus according to an embodiment of the present application. The RSPUs in the radar signal processing apparatus shown in this embodiment are interconnected in a parallel cascade manner, where the parallel cascade manner connection may be applied to the case of extending an antenna unit, for example.

As shown in fig. 3, the radar signal processing apparatus 200 according to the present embodiment includes: the microwave signal processing device comprises N RSPU chips 201, wherein N is an integer greater than or equal to 2, the N RSPU chips 201 are interconnected in a parallel cascade mode, and the N RSPU chips 201 are used for performing parallel cascade processing on signals output by a previous microwave signal processing device.

Specifically, when a parallel cascade mode is adopted, the signal input end of each RSPU chip 201 is coupled to the output interface of one or more MMICs in the previous microwave signal processing device, and the signal output end of each RSPU chip 201 is coupled to form a signal output end. That is, each RSPU chip 201 receives data corresponding to a corresponding antenna unit, and after the parallel cascade processing is completed, the output interface of one RSPU chip 201 of the N RSPUs collects and outputs the processing result.

That is, when parallel cascade is adopted, each RSPU chip is a first RSPU chip, and the signal output ends of all the first RSPU chips are coupled into one signal output end.

In this embodiment, the RSPU chips are interconnected in a parallel cascade manner, and each RSPU chip may have the same or equivalent data processing capability, and the RSPU chips may share the computation amount in a balanced manner according to the data processing capability, so that each RSPU chip approximately processes the same amount of data, and the basic synchronization of the processing delay is further ensured on the basis of the parallel processing relationship between the RSPU chips.

It should be noted that, in this embodiment, each RSPU chip is packaged as an independent chip by way of example, in practical applications, N RSPUs may also be packaged as a same chip, or a part of the N RSPU chips are packaged as a same chip, and the remaining RSPUs are packaged as independent chips by way of example, which is not limited in this application embodiment.

Fig. 4 is a schematic structural diagram of a radar signal processing apparatus according to another embodiment of the present application. Here, the parallel cascade mode is described in detail by taking an example that the radar signal processing apparatus includes 2 RSPUs, and the RSPUs are each packaged as an independent chip. It should be noted that in some cases, multiple RSPUs may be packaged within the same chip.

As shown in fig. 4, the radar signal processing apparatus includes: RSPU chip 1 and RSPU chip 2.

The RSPU chip 1 includes: the microwave signal processing device comprises an input interface 1, a distance dimension Fourier transform unit 1, a Doppler dimension Fourier transform unit 1, a CFRA unit 1, a DOA calculation unit 1, a data tracking unit 1 and an output interface, wherein a signal input end of the input interface 1 is coupled with a microwave signal processing device, a signal output end of the input interface 1 is coupled with a signal input end of the distance dimension Fourier transform unit 1, a signal output end of the distance dimension Fourier transform unit 1 is coupled with a signal input end of the Doppler dimension Fourier transform unit 1, a signal output end of the Doppler dimension Fourier transform unit 1 is coupled with a signal input end of the CFAR unit 1, a signal output end of the CFAR unit 1 is coupled with a signal input end of the DOA calculation unit 1, a signal output end of the DOA calculation unit 1 is coupled with a signal output end of the data tracking unit 1, and a signal output end of the data tracking unit 1 is coupled with a signal input end of the output interface 1.

The RSPU chip 2 includes: an input interface 2, a distance dimension fourier transform unit 2, a doppler dimension fourier transform unit 2, a CFAR unit 2, a DOA calculation unit 2, and a data tracking unit 2. The input of input interface 2 is coupled with microwave signal processing apparatus, the signal output part of input interface 2 is coupled with the signal input part of distance dimension Fourier transform unit 2, the signal output part of distance dimension Fourier transform unit 2 is coupled with the signal input part of Doppler dimension Fourier transform unit 2, the signal output part of Doppler dimension Fourier transform unit 2 is coupled with the signal input part of constant false alarm detection unit 2, the signal output part of CFAR unit 2 is coupled with the signal input part of DOA calculation unit 2, the signal output part of DOA calculation unit 2 is coupled with the signal output input part of data tracking unit 2, the signal output part of data tracking unit 2 is coupled with the signal input part of output interface 1.

In the radar signal processing apparatus shown in fig. 4, one or more cascade nodes may be included between the RSPU chip 1 and the RSPU chip 2, and load balancing may be implemented by the one or more cascade nodes.

If the RSPU chip 1 and the RSPU chip 2 may be coupled through a cascade node a, specifically, a signal output end of the distance dimension fourier transform unit 1 is coupled with a signal input end of the doppler dimension fourier transform unit 2, and a signal output end of the distance dimension fourier transform unit 2 is coupled with a signal input end of the doppler dimension fourier transform unit 1.

Specifically, when the RSPU chip 1 and the RSPU chip 2 are coupled by the cascade node a, the distance dimension fourier transform unit 1 of the RSPU chip 1 performs distance-based fourier transform processing on data output by the corresponding microwave signal processing device, and then transmits the processing result to the RSPU chip 2, and the distance dimension fourier transform unit 2 of the RSPU chip 2 performs distance-based fourier transform processing on data output by the corresponding microwave signal processing device, and then transmits the processing result to the RSPU chip 1; the RSPU chip 1 and the RSPU chip 2 can respectively obtain data of all antenna units, and the RSPU chip 1 and the RSPU chip 2 can share the data of all the antenna units in a balanced manner based on the distance dimension after the distance dimension Fourier transform.

(II) if the RSPU chip 1 and the RSPU chip 2 can be coupled through the cascade node B, namely, the signal output end of the CFAR unit 1 is coupled with the signal input end of the DOA calculation unit 2 of the RSPU chip 2, and the signal output end of the CFAR unit 2 is coupled with the signal input end of the DOA calculation unit 1.

Specifically, when the RSPU chip 1 and the RSPU chip 2 are coupled by the cascade node B, the CFAR unit 1 of the RSPU chip 1 performs CFAR calculation on corresponding data and transmits the calculation result to the RSPU chip 2, the CFAR unit 2 of the RSPU chip 2 performs CFAR calculation on corresponding data and transmits the calculation result to the RSPU chip 1; the RSPU chip 1 and the RSPU chip 2 can respectively obtain CFAR results corresponding to all antenna units, and the RSPU chip 1 and the RSPU chip 2 can share all data to be processed in a balanced manner based on the dimensionality of a target number processed by CFAR.

The RSPU chip 1 and the RSPU chip 2 are coupled through the cascade node B, and all data to be processed are shared in a balanced mode based on the dimensionality of a target number, so that the subsequent DOA calculation amount of the RSPU chip 1 and the subsequent DOA calculation amount of the RSPU chip 2 are basically the same, and the processing time delay of the RSPU chip 1 and the processing time delay of the RSPU chip 2 are basically synchronous.

And (III) if the RSPU chip 1 and the RSPU chip 2 can be coupled through a cascade node C, namely, the signal output end of the DOA computing unit 1 of the RSPU chip 1 is coupled with the signal input end of the data tracking unit 2 of the RSPU chip 2, and the signal output end of the DOA computing unit 2 of the RSPU chip 2 is coupled with the signal input end of the data tracking unit 1 of the RSPU chip 1.

Specifically, when the RSPU chip 1 and the RSPU chip 2 are coupled through the cascade node C, the DOA calculation unit 1 of the RSPU chip 1 performs DOA calculation on corresponding data, the calculation result is transmitted to the RSPU chip 2, the DOA calculation unit 2 of the RSPU chip 2 performs DOA calculation on corresponding data, and the calculation result is transmitted to the RSPU chip 1; the RSPU chip 1 and the RSPU chip 2 can respectively obtain all DOA calculation results, and the RSPU chip 1 and the RSPU chip 2 can share all data to be processed in a balanced mode based on the dimensionality of the target number calculated by the DOA.

The RSPU chip 1 and the RSPU chip 2 are coupled through the cascade node C, and all data to be processed are shared in a balanced mode based on the dimensionality of the target number calculated by the direction of arrival, so that the data tracking calculation amount of the RSPU chip 1 and the data tracking calculation amount of the RSPU chip 2 are basically the same, and the processing time delay of the RSPU chip 1 and the processing time delay of the RSPU chip 2 are basically synchronous.

Optionally, in practical application, the RSPU chip 1 and the RSPU chip 2 may simultaneously support the coupling of three cascade nodes a, B, and C on a hardware structure, and control, according to actual requirements, the RSPU chip 1 and the RSPU chip 2 to simultaneously support one or more cascade nodes a, B, and C through software. For example, the RSPU chip 1 and the RSPU chip 2 have three cascade nodes a, B, and C on hardware at the same time, and control the cascade node a and the cascade node B to be in a working state and the cascade node C to be in a disconnected state through software.

Fig. 5 is a schematic structural diagram of a radar signal processing apparatus according to another embodiment of the present application. The RSPUs in the radar signal processing apparatus shown in this embodiment are interconnected in a serial cascade manner, where the radar signal processing apparatus in the serial cascade manner is applicable to a radar apparatus with a small specification, that is, a radar apparatus with a small number of antenna units.

As shown in fig. 5, the radar signal processing apparatus provided in this embodiment includes: n RSPU chips, wherein N is an integer greater than or equal to 2, and the N RSPU chips are interconnected in a serial cascade mode.

Specifically, when a serial cascade mode is adopted, an input interface of one RSPU chip of the at least two RSPU chips is coupled with an output interface of the microwave signal processing device, that is, an input interface of the first RSPU chip is coupled with an output interface of the microwave signal processing device; the first RSPU chip can receive data of all the antenna units, and after performing corresponding processing on the received data of all the antenna units, transmit the processed data to the next RSPU chip.

And when the N RSPU chips are interconnected in a serial cascade mode, outputting a signal after serial cascade processing through an output interface of the last RSPU chip, wherein the last RSPU chip is the second RSPU chip.

In this embodiment, serial cascade connection is adopted, and the RSPU chips are in a serial relationship with each other, that is, after the RSPU chip of the previous stage processes data, the processed data is output to the RSPU chip of the next stage, and each RSPU chip processes data corresponding to all antenna units. For the radar device with small specification, the serial cascade connection mode is adopted for connection, loose coupling is realized among all RSPU chips, and independent expansion is favorably carried out on different data processing units included by different RSPU chips.

It should be noted that, in this embodiment, it is described by taking an example that each RSPU chip is packaged as an independent chip, in practical applications, N RSPUs may also be packaged as a same chip, or a part of the RSPUs in the N RSPU chips are packaged as a same chip, and the remaining RSPUs are packaged as independent chips, which is not limited in this embodiment.

Fig. 6a is a schematic structural diagram of a radar signal processing apparatus according to another embodiment of the present application. Fig. 6b is a schematic structural diagram of a radar signal processing apparatus according to another embodiment of the present application. The radar signal processing apparatus shown in fig. 6a and 6b includes 2 RSPUs for detailed description, where the 2 RSPUs are respectively packaged as independent chips, namely RSPU chip 1 and RSPU chip 2. When at least two RSPUs are interconnected in a serial cascade mode, the flow nodes of the serial cascade algorithm can be behind the CFAR or behind the DOA.

If the flow node of the serial concatenation algorithm is after CFAR, as shown in fig. 6a, the radar signal processing apparatus includes: RSPU chip 1 and RSPU chip 2.

Wherein, RSPU chip 1 includes: the device comprises an input interface, a distance dimension Fourier transform unit, a Doppler dimension Fourier transform unit and a CFAR unit; the RSPU chip 2 includes: DOA calculation unit, data tracking unit and output interface.

The input end of the input interface is coupled with the microwave signal processing device, the signal output end of the input interface is coupled with the signal input end of the distance dimensional Fourier transform unit, the signal output end of the distance dimensional Fourier transform unit is coupled with the signal input end of the Doppler dimensional Fourier transform unit, the signal output end of the Doppler dimensional Fourier transform unit is coupled with the signal input end of the constant false alarm detection unit, the signal output end of the constant false alarm detection unit is coupled with the signal input end of the wave arrival direction calculation unit, the signal output end of the wave arrival direction calculation unit is coupled with the signal output end of the data tracking unit, and the signal output end of the data tracking unit is coupled with the signal input end of the output interface.

The input interface of the RSPU chip 1 receives data of all antenna units from the microwave signal processing device, after distance dimension Fourier transform, doppler dimension Fourier transform and CFAR are sequentially carried out on the received data of all antennas, the processed data are transmitted to the RSPU chip 2, and DOA calculation and data tracking are sequentially carried out on the received data by the RSPU chip 2.

If the flow node of the serial concatenation algorithm is after DOA calculation, as shown in fig. 6b, the radar signal processing apparatus includes: RSPU chip 1 and RSPU chip 2.

The RSPU chip 1 includes: the device comprises an input interface, a distance dimension Fourier transform unit, a Doppler dimension Fourier transform unit, a CFAR unit and a DOA calculation unit; the RSPU chip 2 includes: a data tracking unit and an output interface. The connections between the data processing units included in the RSPU chip 1 and the RSPU chip 2 can be shown in fig. 6a, and are not described herein again.

It should be understood that in some cases, the radar signal processing apparatus may also include a greater number of RSPU chips, each RSPU chip including a completely different data processing unit, and the multiple RSPU chips can collectively implement a complete data processing flow.

Fig. 7a is a schematic structural diagram of a radar signal processing apparatus according to another embodiment of the present application. In the radar signal processing apparatus shown in this embodiment, at least two RSPUs are connected in a cooperative processing cascade manner, where the radar signal processing apparatus connected in the cooperative processing cascade manner may be applicable to a radar apparatus that needs to perform signal processing algorithm expansion.

As shown in fig. 7a, the radar signal processing apparatus provided in this embodiment includes: and the N RSPU chips are interconnected in a cooperative processing cascade mode, wherein N is an integer greater than or equal to 2. And the N RSPU chips are used for performing cooperative cascade processing on the signals output by the microwave signal processing device.

Specifically, when the cooperative processing cascade connection manner is adopted for interconnection, an input interface of a first RSPU chip of the N RSPU chips is coupled with an output interface of the microwave signal processing device, and the remaining RSPU chips of the N RSPU chips are coupled with the first RSPU chip. As shown in fig. 7a, the RSPU chip 1 is coupled to the microwave signal processing device, and the RSPU chip 2 to the RSPU chip N are coupled to the RSPU chip 1, respectively.

When the cooperative processing cascade mode interconnection is adopted, at least the following situations can be adopted:

the remaining RSPU chips of the first and at least two RSPU chips are intermediate algorithm points of the RSPU chip coupled with the microwave signal processing device (i.e., the first RSPU chip).

In this case, the input interface of the first RSPU chip is coupled with the output interface of the microwave signal processing apparatus, and the first RSPU chip coupled with the output interface of the microwave signal processing apparatus includes a plurality of data processing units coupled in sequence, where the plurality of data processing units coupled in sequence includes a first data processing unit and a second data processing unit coupled in sequence.

Except the first RSPU chip, the rest RSPU chips of the at least two RSPU chips comprise function extension units, wherein the signal input ends of the function extension units are coupled with the signal output ends of the first data processing units, and the signal output ends of the function extension units are coupled with the signal input ends of the second data processing units.

That is to say, the function extension unit acquires data from the first data processing unit coupled to the previous stage, and after performing corresponding processing on the data acquired from the first data processing unit, the function extension unit sends the processed data to the second data processing unit connected to the next stage, thereby realizing that the function extension unit serves as an intermediate algorithm point.

For example, N =2 is taken as an example for explanation, wherein fig. 7b shows a schematic structural diagram of the RSPU chip 2 as a branch algorithm point of the RSPU chip 1.

In the embodiment, the function extension unit for realizing the intermediate algorithm is added to the first data processing unit and the second data processing unit which are sequentially coupled, and the working state of the function extension unit can be controlled through software, so that the flexible extension of the radar signal processing device is realized, and a hardware basis is provided for the flexible extension of the signal processing algorithm.

In some cases, an RSPU chip may include a plurality of function extension units coupled in sequence, which may be connected in a serial manner, as shown in fig. 7 c.

In other cases, the number of RSPU chips including a function expansion unit may be one or more, and each RSPU chip includes at least one function expansion unit, and these RSPU chips as intermediate algorithm points are coupled to the first RSPU chip. As shown in fig. 7d, there are two RSPU chips including a function extension unit, and the two RSPU chips are respectively coupled to the RSPU chip 1.

It is to be understood that in some cases, the approaches shown in fig. 7c and 7d may coexist.

The remaining RSPU chips of the second, at least two RSPU chips are branch algorithm points of the RSPU chip coupled with the microwave signal processing device (i.e., the first RSPU chip).

In this case, the input interface of the first RSPU chip is coupled with the output interface of the microwave signal processing apparatus, and the first RSPU chip connected with the microwave signal processing apparatus includes a plurality of data processing units coupled in sequence; the remaining RSPU chips of the at least two RSPU chips include a function extension unit.

For each RSPU chip comprising the function extension unit, the signal input end of the function extension unit is connected with the signal output end of one data processing unit in the plurality of data processing units, and the signal output end of the function extension unit is connected with the signal input end of any one data processing unit in the rest data processing units in the plurality of data processing units.

Optionally, a signal output end of the function extension unit is connected to a signal input end of the output interface, the function extension unit obtains data from a coupled previous-stage data processing unit, correspondingly processes the obtained data, and outputs the processed data to the output interface, and the output interface can transmit the data output by the function extension unit to a sequentially coupled next-stage data processing unit, thereby implementing that the function extension unit serves as a branch algorithm point.

For example, N =2 is taken as an example for explanation, wherein fig. 8a shows a schematic structural diagram of the RSPU chip 2 as a branch algorithm point of the RSPU chip 1. Referring to fig. 7a and 8a, the input interface of the RSPU chip 1 is coupled to the output interface of the microwave signal processing apparatus, the RSPU chip 2 includes a function expansion unit, the signal input terminal of the function expansion unit is coupled to the signal output terminal of the 1 st data processing unit, and the signal output terminal of the function expansion unit is coupled to the output interface of the RSPU chip 1.

Optionally, the RSPU for implementing the branch algorithm point may include one function extension unit, or may include a plurality of function extension units coupled in sequence. If the RSPU for implementing the branch algorithm point includes a plurality of sequentially coupled function extension units, in some possible implementations, in the plurality of sequentially coupled function extension units, signal input terminals of other function extension units except the first function extension unit and the last function extension unit may be further coupled to a signal output terminal of any data processing unit in the first RSPU. In practical application, the working state of the function extension unit can be controlled through software, so that the flexibility of the branch algorithm is realized.

For example, as shown in fig. 8b, the signal input of the function expansion unit 2 is coupled to the signal output of a data processing unit in the first RSPU chip. In practical application, the software controls the working states of the function extension unit 1 and the function extension unit 2 to realize flexible algorithm extension, for example, if the function extension unit 1 needs to be in a disconnected state and the function extension unit 2 needs to be in a working state, the software can control the function extension unit 1 and the RSPU chip 1 to be in a disconnected state and the function extension unit 2 and the RSPU chip 1 to be in a connected state, the function extension unit 1 cannot acquire data from the RSPU chip 1, the function extension unit 2 can acquire corresponding data from a last-stage data processing unit coupled in sequence, and the function extension unit 2 correspondingly processes the acquired data and outputs the processed data to an output interface of the RSPU chip 1.

It should be noted that, when the RSPU chip including the function extension unit is used to implement the branch algorithm point, the connection between the RSPU chip including the function extension unit and the RSPU chip connected to the microwave signal processing apparatus may be set according to actual requirements, as long as the branch algorithm point can be implemented.

In the embodiment, the function extension unit for realizing the branch algorithm is additionally arranged between the two sequentially coupled data processing units, and the working state of the function extension unit can be controlled by software, so that the flexible extension of the radar signal processing device is realized, and a hardware basis is further provided for the flexible extension of the signal processing algorithm.

Optionally, the two aforementioned manners of cooperative processing cascade may exist at the same time, that is, the radar signal processing apparatus may include: an RSPU chip for implementing an intermediate algorithm and an RSPU chip for implementing a branch algorithm. For example, the manner described above for implementing the intermediate algorithm point shown in fig. 7b or fig. 7d and the manner described above for implementing the branch algorithm point shown in fig. 8a or fig. 8b may exist simultaneously.

The following describes the cooperative processing cascade method in detail by taking an example that the radar signal processing apparatus includes two RSPU chips, and the two RSPU chips are packaged as independent chips respectively. Wherein, the two RSPUs are RSPU chip 1 and RSPU chip 2 respectively.

Fig. 9a is a schematic structural diagram of a radar signal processing apparatus according to another embodiment of the present application. In this embodiment, the RSPU chip 1 and the RSPU chip 2 are interconnected in a cooperative processing cascade manner, and the RSPU chip 2 is an intermediate algorithm point of the RSPU chip 1.

As shown in fig. 9a, the RSPU chip 1 includes an input interface, a distance dimension fourier transform unit, a doppler dimension fourier transform unit, a CFAR unit, a DOA calculation unit, a data tracking unit, and an output interface, which are coupled in sequence. The RSPU chip 2 includes: and a function expansion unit.

The signal input end of the function expansion unit is coupled with the signal output end of the distance dimensional Fourier transform unit, and the signal output end of the function expansion unit is coupled with the signal input end of the Doppler dimensional Fourier transform unit. The working state of the RSPU chip 2, that is, the working state of the function expansion unit, may be controlled by software, for example, if algorithm expansion needs to be performed, and the RSPU chip 2 is taken as an intermediate algorithm point, the RSPU chip 2 may be controlled by software to be in a conducting state, accordingly, data may only be transmitted to the RSPU chip 2 through the distance dimension fourier transform unit, and transmitted to the doppler dimension fourier transform unit through the RSPU chip 2, and data transmission between the distance dimension fourier transform unit and the doppler dimension fourier transform unit cannot be directly performed. If algorithm expansion is not needed, the RSPU chip 2 can be controlled to be in a disconnected state through software, and accordingly data can be directly transmitted to the Doppler dimension Fourier transform unit through the distance dimension Fourier transform unit.

Through the mode, the RSPU chip 2 comprising the function extension unit is additionally arranged between the distance dimension Fourier transform unit and the Doppler dimension Fourier transform unit of the RSPU chip 1, and the working state of the function extension unit can be controlled through software, so that the flexible extension of the radar signal processing device is realized, and a hardware basis is further provided for the flexible extension of a signal processing algorithm.

Fig. 9b is a schematic structural diagram of a radar signal processing apparatus according to another embodiment of the present application. In this embodiment, the RSPU chip 1 and the RSPU chip 2 are interconnected in a cooperative processing cascade manner, and the RSPU chip 2 is a branch algorithm point of the RSPU chip 1.

As shown in fig. 9b, the RSPU chip 1 includes an input interface, a distance dimension fourier transform unit, a doppler dimension fourier transform unit, a CFAR unit, a DOA calculation unit, a data tracking unit, and an output interface, which are coupled in sequence. The RSPU chip 2 includes: and a function expansion unit.

The signal input end of the function expansion unit is coupled with the signal output end of the distance dimension Fourier transform unit, and the signal output end of the function expansion unit is coupled with the signal input end of the output interface of the RSPU chip 1. The working state of the RSPU chip 2, that is, the working state of the function expansion unit, can be controlled by software, for example, if algorithm expansion is needed, when the RSPU chip 2 is taken as a branch algorithm point, the RSPU chip 2 can be controlled by software to be in a conducting state, accordingly, a part of data can be transmitted to the RSPU chip 2 through the distance dimension fourier transform unit, and transmitted to the output interface of the RSPU chip 1 by the SPU chip 2, and another part of data can be transmitted to the output interface through the distance dimension fourier transform unit, the doppler dimension fourier transform unit, the CFAR unit, the DOA calculation unit, and the data tracking unit in sequence, and the output interface collects and outputs two paths of data to the next-level device. If algorithm expansion is not needed, the RSPU chip 2 can be controlled to be in a disconnected state through software, and accordingly all data can be transmitted to the output interface through the distance dimension Fourier transform unit, the Doppler dimension Fourier transform unit, the CFAR unit, the DOA calculation unit and the data tracking unit in sequence.

Through the mode, the RSPU chip 2 comprising the function extension unit is additionally arranged between the distance dimension Fourier transform unit of the RSPU chip 1 and the output interface, and the working state of the function extension unit can be controlled through software, so that the flexible extension of the radar signal processing device is realized, and a hardware basis is further provided for the flexible extension of a signal processing algorithm.

Fig. 9c is a schematic structural diagram of a radar signal processing apparatus according to another embodiment of the present application. In this embodiment, the RSPU chip 1, the RSPU chip 2, and the RSPU chip 3 are interconnected in a cooperative processing cascade manner, and the RSPU chip 2 is a middle algorithm point of the RSPU chip 1, and the RSPU chip 3 is a branch algorithm point of the RSPU chip 1.

The RSPU chip 1 comprises an input interface, a distance dimension Fourier transform unit, a Doppler dimension Fourier transform unit, a CFAR unit, a DOA calculation unit, a data tracking unit and an output interface which are coupled in sequence. The RSPU chip 2 includes: the function extension unit a, the RSPU chip 3 includes: and a function expanding unit b.

The signal input end of the function expansion unit a is coupled with the signal output end of the distance dimensional Fourier transform unit, and the signal output end of the function expansion unit a is coupled with the signal input end of the Doppler dimensional Fourier transform unit; the signal input end of the function expansion unit b is coupled with the signal output end of the distance dimension Fourier transform unit, and the signal output end of the function expansion unit is coupled with the signal input end of the output interface of the RSPU chip 1.

In practical applications, the working states of the RSPU chip 2 and the RSPU chip 3 may be controlled by software, for example, when the intermediate algorithm point needs to be expanded, the RSPU chip 2 may be controlled by software to be in the working state, and when the branch algorithm point needs to be expanded, the RSPU chip 3 may be controlled by software to be in the working state, and for the RSPU chip 2 and the RSPU chip 3, reference may be made to the descriptions in fig. 9a and 9b, and details are not repeated here.

In this embodiment, the RSPU chip 2 including the function extension unit is added between the distance dimension fourier transform unit and the doppler dimension fourier transform unit of the RSPU chip 1, the RSPU chip 3 including the function extension unit is added between the distance dimension fourier transform unit and the output interface of the RSPU chip 1, and the operating states of the RSPU chip 2 and the RSPU chip 3 can be controlled by software, so that flexible extension of the radar signal processing apparatus is realized, and a hardware basis is provided for flexible extension of the signal processing algorithm.

On the basis of the embodiments shown in fig. 3 to 9c, the parallel cascade, the serial cascade and the cooperative cascade may be combined.

For example, on the basis of the embodiments shown in fig. 3 and fig. 4, optionally, the radar processing apparatus may further include: and the input interface of the third RSPU chip is coupled with the output interface of the first RSPU chip, and the third RSPU chip is used for correspondingly processing the signal output by the first RSPU chip and outputting the processed signal to a next-stage device through the output interface of the third RSPU chip.

In the radar signal processing apparatus of this embodiment, the third RSPU chip is interconnected with the N RSPU chips in a serial cascade manner on the basis of parallel cascade of the N RSPU chips, so as to meet the requirements of a signal processing algorithm.

Optionally, on this basis, the method may further include: a fourth RSPU; the fourth RSPU chip is coupled between two data processing units which are sequentially coupled in any one first RSPU chip; or the fourth RSPU chip is coupled between two data processing units which are sequentially coupled in the third RSPU chip; or the input interface of the fourth RSPU chip is coupled to the input interface of any data processing unit in any first RSPU chip, and the output interface of the fourth RSPU chip is coupled to the output interface of any other data processing unit in the first RSPU chip; or the input interface of the fourth RSPU chip is coupled to the input interface of any data processing unit in the third RSPU chip, and the output interface of the fourth RSPU chip is coupled to the output interface of any other data processing unit in the third RSPU chip.

In the radar signal processing apparatus of this embodiment, the fourth RSPU chip may be further interconnected with the N RSPU chips in a cooperative processing cascade manner on the basis of parallel cascade of the N RSPU chips, or on the basis of parallel cascade of the N RSPU chips and serial cascade of the third RSPU chip, so as to meet the requirement of a signal processing algorithm.

For another example, based on the embodiments shown in fig. 5, fig. 6a, and fig. 6b, optionally, the radar processing apparatus may further include: a fifth RSPU chip; the input interface of the fifth RSPU chip is coupled to the output interface of any one of the at least two RSPU chips, or the input interface of the fifth RSPU chip is coupled to the output interface of one or more MMICs in the microwave signal processing device; the output interface of the fifth RSPU chip is coupled with the output interface of any residual RSPU chip in the at least two RSPU chips; the fifth RSPU chip is used for receiving signals from the RSPU chip or the microwave signal processing device which is coupled with the input interface of the fifth RSPU chip, correspondingly processing the received signals and outputting the processed signals through the output interface of the fifth RSPU chip.

The fifth RSPU chip is coupled between the output interface of the microwave signal processing device and the output interfaces of the at least two RSPU chips in a parallel cascade connection mode, the specification of the radar device is expanded, for example, an antenna unit is added, and the fifth RSPU chip can be used for processing data of the newly added antenna unit, so that the radar device can meet the requirement of an intelligent driving level.

Optionally, the radar signal processing apparatus may further include: the sixth RSPU chip is coupled between two data processing units which are sequentially coupled in any one RSPU chip; or the sixth RSPU chip is coupled between two data processing units which are sequentially coupled in the fifth RSPU chip; or an input interface of the sixth RSPU chip is coupled to an input interface of any data processing unit in any RSPU chip, and an output interface of the sixth RSPU chip is coupled to an output interface of any other data processing unit in the RSPU chip; or the input interface of the sixth RSPU chip is coupled to the input interface of any data processing unit in the fifth RSPU chip, and the output interface of the sixth RSPU chip is coupled to the output interface of any other data processing unit in the fifth RSPU chip.

The sixth RSPU chip is coupled to any one of the at least two RSPU chips in a cooperative processing cascade mode or coupled to the fifth RSPU chip, the sixth RSPU chip can be used for realizing an intermediate algorithm node or a branch algorithm node, and the sixth RSPU chip can be used for realizing algorithm expansion, so that the radar signal processing device can flexibly adapt to the requirements of different signal processing algorithms.

As another example, based on the embodiments shown in fig. 7a to 9c, optionally, the radar signal processing apparatus further includes: and the seventh RSPU chip is used for receiving the signal output by the first RSPU chip, correspondingly processing the received signal and outputting the processed signal through the output interface of the seventh RSPU chip.

The seventh RSPU chip is coupled to the output interface of the first RSPU chip in a serial cascade mode, and the seventh RSPU chip can be used for further processing data output by the first RSPU chip when the algorithm of the radar device is expanded, so that the radar device can meet the requirement of a signal processing algorithm.

The following describes in detail the interaction between the RSPU chips when the radar signal processing apparatus is connected in different cascade ways by using several specific embodiments.

Fig. 10 is a flowchart of a radar signal processing method according to an embodiment of the present disclosure. The method of this embodiment is applied to the radar signal processing apparatus provided in the embodiment of the present application, where the radar signal processing apparatus includes at least two RSPUs, and the at least two RSPUs are connected in a cascade manner. As shown in fig. 10, the method of the present embodiment includes:

s101, the at least two RSPUs receive signals output by the microwave signal processing device.

Specifically, at least two RSPUs receive signals output by one or more MMICs included in the microwave signal processing apparatus.

S102, the at least two RSPUs carry out cascade processing on the signals output by the microwave signal processing device.

Specifically, at least two RSPUs perform different cascade processing on the signal output by the microwave signal processing device according to different cascade modes. If the at least two RSPUs are interconnected in a parallel cascade mode, the at least two RSPUs carry out parallel cascade processing on the signals output by the microwave signal processing device; if the at least two RSPUs are interconnected in a serial cascade mode, the at least two RSPUs carry out serial cascade processing on the signals output by the microwave signal processing device; and if the at least two RSPUs are interconnected in a cooperative cascade mode, the at least two RSPUs perform cooperative cascade processing on the signals output by the microwave signal processing device.

In the embodiment, the RSPU is subjected to cascade expansion according to the dimensionality of the signal processing unit or the dimensionality of the data processing unit included by the signal processing unit, so that the data processing capacity of the radar signal processing device is improved, and the processing efficiency of a radar system is improved; and the RSPU included in the radar signal processing device can be flexibly expanded according to the requirements of intelligent driving of each level, the increasing signal processing algorithm requirements of the vehicle-mounted radar and the like.

Fig. 11 is a flowchart of a radar signal processing method according to another embodiment of the present application. The radar signal processing method provided by the embodiment can be applied to: the radar signal processing device comprises at least two RSPUs which are connected in a parallel cascade mode. As shown in fig. 11, the method of the present embodiment includes:

s201, at least two RSPUs receive signals output by the microwave signal processing device.

When the at least two RSPUs are connected in parallel cascade, the input of the at least two RSPUs are coupled to the output interfaces of one or more MMICs included in the microwave signal processing device, i.e. in this step, each RSPU receives different data output by different MMICs of the microwave signal processing device.

S202, each RSPU acquires data output by the first data processing units of other RSPUs.

Wherein each RSPU comprises a first data processing unit and a second data processing unit which are connected; in the at least two RSPUs, the first data processing unit in each RSPU is connected with the second data processing unit in the rest RSPUs in the at least two data processing chips.

The purpose of this step is: after the first data processing unit of each RSPU performs corresponding processing on the data, each RSPU can acquire data corresponding to all antenna units, and a basis is provided for evenly distributing the data to be processed to each subsequent second data processing unit.

It should be understood that, for each RSPU, if one or more sequentially coupled data processing units are further included between the microwave signal processing apparatus and the first data processing unit, the microwave signal processing apparatus outputs a signal to the one or more connected data processing units, the one or more sequentially coupled data processing units sequentially perform corresponding processing on the signal output by the microwave signal processing apparatus and transmit the processed data to the first data processing unit, and after the first data processing unit performs corresponding processing on the data, the processed data is transmitted to other RSPUs.

And S203, each RSPU performs load balancing on the data output by all the first data processing units according to the quantity of at least two RSPUs and the characteristics of the data output by the first data processing units, and determines to-be-processed data corresponding to the second data processing unit of each RSPU.

In this step, each RSPU can receive data corresponding to all antenna units, and evenly distribute the data to be processed based on the characteristics of the data output by the previous-stage data processing unit.

For example, as shown in fig. 4, if the RSPU chip 1 and the RSPU chip 2 are connected through the cascade node a, the RSPU chip 1 and the RSPU chip 2 equally distribute the data output by the fourier transform unit in all distance dimensions according to the number of the RSPU chips and the distance dimensions, so that the RSPU chip 1 and the RSPU chip 2 share the data of all antenna units in a balanced manner.

As shown in fig. 4, if the RSPU chip 1 and the RSPU chip 2 are connected through the cascade node B, the RSPU chip 1 and the RSPU chip 2 equally distribute the data output by all the constant false alarm detection units according to the number of the RSPU chips and the target number dimension, so that the RSPU chip 1 and the RSPU chip 2 process the same number of data of the target object, thereby achieving that the RSPU chip 1 and the RSPU chip 2 equally share the data to be processed.

As shown in fig. 4, if the RSPU chip 1 and the RSPU chip 2 are coupled through the cascade node C, the RSPU chip 1 and the RSPU chip 2 equally distribute the data output by all the direction-of-arrival computing units according to the number of the RSPU chips and the target number dimension, so that the RSPU chip 1 and the RSPU chip 2 process the same number of data of the target object, thereby realizing that the RSPU chip 1 and the RSPU chip 2 equally share the data to be processed.

It can be understood that if multiple cascade nodes in a, B, and C are simultaneously supported between the RSPU chip 1 and the RSPU chip 2, when data processing is performed, data processing manners of different cascade nodes may be combined.

And S204, the second data processing unit of each RSPU carries out corresponding processing on the determined data to be processed.

And S205, outputting the processed data to a data processing unit at the next stage by the second data processing unit of each RSPU, and performing corresponding data processing.

In this embodiment, when the radar signal processing apparatus is connected in a parallel cascade manner, each RSPU may have the same data processing capability, and at least two RSPUs may interact with each other based on a cascade node, so that each RSPU processes the same amount of data, thereby ensuring that each RSPU can synchronously output a processing result, and while implementing a parallel processing relationship between the RSPUs, implementing balanced sharing of an operand, and basically synchronizing processing delays.

Taking the example that the radar signal processing apparatus includes 2 RSPUs as an example, how data interaction is performed between the RSPUs is described in detail, where the 2 RSPUs are RSPU chip 1 and RSPU chip 2, respectively.

Fig. 12a is a flowchart of a radar signal processing method according to another embodiment of the present application. Referring to fig. 4 and as shown in fig. 12a, in the present embodiment, the RSPU chip 1 includes: the device comprises a digital signal processing DSP1, a memory 1, a distance dimension Fourier transform unit 1 and an inter-chip transfer interface 1, wherein the memory 1 comprises storage areas a1 and b1, the storage area a1 is used for storing data output by the distance dimension Fourier transform unit 1 of an RSPU chip 1, and the storage area b1 is used for storing data output by the distance dimension Fourier transform unit 2 of an RSPU chip 2;

the RSPU chip 2 includes: the device comprises a digital signal processing DSP2, a memory 2, a distance dimension Fourier transform unit 2 and an inter-chip transfer interface 2, wherein the memory 2 comprises storage areas a2 and b2, the storage area a2 is used for storing data output by the distance dimension Fourier transform unit 1 of the RSPU chip 1, and the storage area b2 is used for storing data output by the distance dimension Fourier transform unit 2 of the RSPU chip 2.

If the RSPU chip 1 and the RSPU chip 2 interact based on the cascade node a, as shown in fig. 12a, for the RSPU chip 1, the following steps may be included:

step (1), the distance dimension Fourier transform unit 1 outputs the processed data to a storage area a1 of a memory 1; at this time, the RSPU chip 1 stores data corresponding to the antenna unit corresponding to the RSPU chip 1.

And (2) after the distance dimension Fourier transform unit 1 outputs all the data corresponding to all the antenna units corresponding to the distance dimension Fourier transform unit to the storage area a1, informing the DSP1 of configuring the DMA1 so as to start to move the data corresponding to the antenna units corresponding to the RSPU chip 1 to the RSPU chip 2.

And (3) after the DSP1 receives the notification of the data moving, starting the inter-chip transfer interfaces INF1 and INF2.

And (4) moving the data by using the INF1 and the INF2.

And (5) after the data transfer is finished, the INF2 of the RSPU chip 2 sends a message of finishing the data transfer to the DSP2.

For the RSPU chip 2, the steps executed are shown as step (1 ') to step (5') in fig. 12a, and the process is similar to the process of the RSPU chip 1 performing data movement at the cascade node a, and reference may be made to the description of the RSPU chip 1, which is not repeated herein.

Here, taking 512 data of distance ranges corresponding to 16 antenna units as an example, how the RSPU chip 1 and the RSPU chip store data when the RSPU chip 1 and the RSPU chip 2 perform data interaction through the cascade node a is described in detail.

As shown in fig. 12b, wherein the RSPU chip 1 is configured to receive the data of all the distance ranges corresponding to 8 antenna units from the distance dimension fourier transform unit 1, that is, the memory 1 of the RSPU chip 1 stores the ranging bin 0-ranging bin511 data corresponding to the antenna units R0 to R7 respectively; the RSPU chip 2 is configured to receive data of all distance ranges corresponding to another 8 antenna units output by the distance dimension fourier transform unit 2, that is, the memory 2 of the RSPU chip 2 stores data of ranging bin 0-ranging bin511 corresponding to the antenna units R8 to R15, respectively. Wherein "rangbin" represents a distance range.

After the interaction between the RSPU chip 1 and the RSPU chip 2 is completed, the RSPU chip 1 obtains the data of ranging bin 0-ranging bin255 corresponding to the antenna units R0 to R15, respectively, and the RSPU chip 2 obtains the data of ranging bin 256-ranging bin511 corresponding to the antenna units R0 to R15, respectively.

That is to say, in the process that the RSPU chip 1 and the RSPU chip 2 interact with each other through the cascade node a, the RSPU chip 1 averagely divides the data of the antenna unit stored in the memory 1 into two parts according to the antenna or the distance dimension, and transmits one part of the data to the RSPU chip 2; the RSPU chip 2 equally divides the data of the antenna units stored in the memory 2 into two parts according to the antenna or the distance dimension, and transmits one part of the data to the RSPU chip 1, thereby realizing that each RSPU chip can acquire the data of all the antenna units, and each RSPU chip acquires the data of a half distance range corresponding to all the antenna units based on the distance dimension, avoiding transmitting all the data between the RSPU chip 1 and the RSPU chip 2, causing unnecessary resource waste, and thus improving the processing efficiency of the radar signal processing device.

Fig. 13 is a flowchart of a radar signal processing method according to another embodiment of the present application. With reference to fig. 4 and fig. 13, in the present embodiment, the RSPU chip 1 includes: the system comprises a DSP1, a memory 1, a CFAR unit 1, a DOA computing unit 1, a first direct memory access system DMA and an inter-chip transfer interface 1;

the RSPU chip 2 includes: DSP2, memory 2, CFAR unit 2, DOA calculation unit 2, second DMA and inter-chip transfer interface 2.

The RSPU chip 1 and the RSPU chip 2 interact based on the cascade node B, and as shown in fig. 13, for the RSPU chip 1, the following steps may be included:

and (1) the CFAR unit 1 outputs the target data to the memory 1.

The target data referred to herein is data obtained by CFAR processing performed by the CFAR unit 1 on data output by a data processing unit of a previous stage.

And (2) outputting the target number to the DSP1 by the CFAR unit 2 so that the DSP1 determines whether the data processing capacity of the RSPU chip 1 is exceeded or not.

It should be noted that, the execution sequence of step (1) and step (2) may not be sequential.

And (3) if the DSP1 determines that the data processing capacity of the RSPU chip 1 is exceeded, sending the target number and the target address which exceed the data processing capacity of the RSPU chip 1 to the DSP2 of the RSPU chip 2.

And (4) the DSP2 judges according to the target number and the target address which are sent by the DSP1 and exceed the data processing capacity of the RSPU chip 1, and determines whether the sharing is available.

And (5) if the DSP2 can be shared, the DSP2 issues a command to the DOA calculating unit 2 for calculation.

And (6) the DOA computing unit 2 schedules a local second DMA to read the shared target data from the RSPU chip 1.

Thereafter, the DOA calculation unit 2 may perform direction-of-arrival calculation on the shared target data.

For the RSPU chip 2, the steps executed by the RSPU chip 2 are shown as step (1 ') to step (6') in fig. 13, and the process is similar to the process of the RSPU chip 1 performing data transfer at the tandem node B, and reference may be made to the description of the RSPU chip 1, which is not repeated herein.

It should be noted that, in fig. 13, for the RSPU chip 2, the steps (3 ') to (4') are not shown, but it should be understood that the steps (3 ') and (4') are interactions between the DSP2 and the DSP1, which are similar to the steps (3) and (4).

It should be noted that, after the tandem node B is located in the CFAR process, the number of targets obtained by the CFAR process is related to actual detection of each frame, and therefore, the processing capabilities of the RSPU chip 1 and the RSPU chip 2 are dynamically allocated. For example, in one frame, the RSPU chip 2 may share the target number of the RSPU chip 1, and in another frame, the RSPU chip 1 may share the target number of the RSPU chip 2.

Fig. 14 is a flowchart of a radar signal processing method according to another embodiment of the present application. With reference to fig. 4 and fig. 14, in the present embodiment, the RSPU chip 1 includes: DSP1, memory 1, DOA computational element 1, data tracking element 1, first DMA and chip transfer interface 1. The memory 1 includes a storage area a3 for storing data output by the direction-of-arrival calculation unit 1, and a storage area b3 for storing the history tracking list 1.

The RSPU chip 2 includes: DSP2, memory 2, DOA calculation unit 2, data tracking unit 2, second DMA and inter-chip transfer interface 2. The memory 2 includes an area a4 for storing data output by the DOA calculation unit 2, and an area b4 for storing the history tracking list 2.

The RSPU chip 1 and the RSPU chip 2 interact based on the cascade node C, and as shown in fig. 14, for the RSPU chip 1, the following steps may be included:

step (1), the DOA calculating unit 1 outputs the target data to the memory 1.

The target data referred to here is data obtained by the DOA calculation unit 1 performing DOA calculation processing on data output by a data processing unit of a previous stage.

And (2) outputting the target number to the DSP1 by the DOA computing unit 1 so that the DSP1 determines whether the data processing capacity of the RSPU chip 1 is exceeded or not.

And (4) the DSP2 judges according to the target number and the target address which are sent by the DSP1 and exceed the data processing capacity of the RSPU chip 1, and determines whether the targets can be shared.

And (5) if the DSP2 can be shared, the DSP2 issues a command to the data tracking unit 2 for calculation.

And (6) the data tracking unit 2 schedules a local second DMA to read the shared target data from the RSPU chip 1.

And (7) the data tracking unit 2 schedules a second DMA to read the history tracking list 1 from the RSPU chip 1.

Since the history tracking list 1 is required as a reference for data tracking, the second DMA data tracking unit 2 schedules the second DMA to read the history tracking list 1 from the memory 1 of the RSPU chip 1.

Thereafter, the data tracing unit 2 may perform data tracing processing on the shared target data.

For the RSPU chip 2, the steps executed are similar to the process of the RSPU chip 1 performing data transfer at the cascade node C in fig. 14, and refer to the description of the RSPU chip 1, which is not repeated herein.

Note that, when the tandem node C performs data tracking after DOA calculation, it is related to the history tracking list in addition to the actual measurement angle of the frame, and therefore, in order to balance the data tracking capability, it is necessary to read the history tracking list in addition to the shared target data.

It should be understood that, if the RSPU chip 1 and the RSPU chip 2 can simultaneously support the connection of three cascade nodes a, B, and C on a hardware structure, and control, according to actual requirements, the connection of multiple cascade nodes a, B, and C between the RSPU chip 1 and the RSPU chip 2 through software to be in a working state. The above-described manners in fig. 11 to 14 may be used in combination for the processing flow of data.

Fig. 15 is a flowchart of a radar signal processing method according to another embodiment of the present application. In this embodiment, the radar signal processing device includes an RSPU chip 1 and an RSPU chip 2, and the RSPU chip 1 and the RSPU chip 2 are interconnected in a cooperative processing cascade manner. With reference to fig. 9a, the RSPU chip 2 includes a function expansion unit having a signal input terminal connected to a signal output terminal of the distance dimension fourier transform unit of the RSPU chip 1, and a signal output terminal connected to a signal input terminal of the doppler dimension fourier transform unit of the RSPU chip 1. In this case, the RSPU chip 2 serves as an intermediate algorithm point of the RSPU chip 1.

As shown in fig. 9a and fig. 15, the RSPU chip 1 includes: the device comprises a distance dimension Fourier transform unit, a memory 1, an inter-chip transfer interface INF1, a DSP1 and a Doppler dimension Fourier transform unit; the RSPU chip 2 includes: DSP2, memory 2, function expansion unit, and inter-chip transfer interface INF2.

On the basis of fig. 15, the process of processing data by the RSPU chip 1 and the RSPU chip 2 may include the following steps:

and (1) the distance dimension Fourier transform unit sends the target data to the memory 1.

And (2) the RSPU chip 1 sends the target data to the memory 2 of the RSPU chip 2 through the INF1 and the INF2.

And (3) calling processor resources by the DSP2 of the RSPU chip 2 to complete a function extension algorithm. For example, the DSP2 invokes the FFT accelerator and the DSP itself computing resources to complete the function extension algorithm.

And (4) the RSPU chip 2 sends the processed data to the memory 1 of the RSPU chip 1 through the INF2 and the INF 1.

And (5) calling processor resources by a Doppler dimension Fourier transform unit of the RSPU chip 1 to perform Doppler dimension Fourier transform processing.

By the method, the RSPU chip 2 is used as an intermediate algorithm point of the RSPU chip 1, and whether the RSPU chip 1 and the RSPU chip 2 are conducted or not can be controlled through software, so that the working state of the function extension unit is controlled, and the flexibility of the radar signal processing device is improved.

The data processing flow of the radar signal processing device may refer to the description of the embodiment of the radar signal processing device when serial cascade, cooperative processing cascade, and mixed cascade of multiple cascade modes.

Fig. 16 is a schematic structural diagram of a radar system according to an embodiment of the present application. As shown in fig. 16, a radar system 1600 of the present embodiment includes: a microwave signal processing apparatus 1601 and a radar signal processing apparatus 1602.

Wherein, the output interface of the microwave signal processing device 1601 is coupled with the input interface of the radar signal processing device 1602, and the microwave signal processing device 1601 is configured to perform radio frequency and analog signal processing on the microwave signal transmitted between the antenna unit and the radar signal processing device 1602; the radar signal processing device 1602 includes at least two RSPUs, the at least two RSPUs are interconnected in a cascade manner, and the radar signal processing device 1602 is configured to perform cascade processing on a signal output by the microwave signal processing device 1601.

Alternatively, the radar signal processing apparatus 1602 may adopt the radar signal processing apparatus shown in any of the above embodiments.

On the basis of the embodiment shown in fig. 16, in a possible implementation manner, the microwave signal processing apparatus 1601 includes at least two MMICs, wherein an output interface of each MMIC is coupled with an input interface of one RSPU in the radar signal processing apparatus 1602.

Fig. 17 is a schematic structural diagram of a radar system according to another embodiment of the present application. As shown in fig. 17, in the radar system 1700 of the present embodiment, based on the embodiment shown in fig. 16, the microwave signal processing apparatus 1601 includes: the at least two sets of MMICs, i.e., the microwave signal processing means 1601, comprise at least two sets of MMICs, wherein each set of MMICs comprises at least one MMIC, and an output interface of each set of MMICs is coupled with an input interface of one RSPU in the radar signal processing means 1602.

At least two sets of MMICs may also be interconnected in a cascade manner, for example, at least two sets of MMICs are interconnected in a parallel cascade manner. Of course, the specific implementation manner of the microwave signal processing apparatus in the embodiment of the present application is not limited.

In a specific embodiment, referring to fig. 18a, the microwave signal processing apparatus of the radar system includes: and 2 groups of MMICs, wherein each group of MMICs comprises 2 MMICs, the radar signal processing device of the radar system comprises 2 RSPU chips, and the 2 RSPU chips are connected in a parallel cascade mode.

Specifically, the output interface of the 1 st group of MMICs is coupled with the input interface of the RSPU chip 1, and the output interface of the 2 nd group of MMICs is coupled with the input interface of the RSPU chip 2. The specific implementation manner of the interconnection of the RSPU chip 1 and the RSPU chip 2 in the parallel cascade manner may refer to the description in the above embodiments, and is not described herein again.

In another specific embodiment, referring to fig. 18b, the microwave signal processing apparatus of the radar system includes: 4 MMICs; the radar signal processing device of the radar system comprises 2 RSPU chips, and the 2 RSPU chips are interconnected in a serial cascade mode.

Specifically, the output interfaces of the 4 pieces of MMICs are all coupled with the input interface of the RSPU chip 1, and the output interface of the RSPU chip 1 is coupled with the input interface of the RSPU chip 2. The specific implementation manner of the interconnection between the RSPU chip 1 and the RSPU chip 2 in the serial cascade connection manner may refer to the description in the foregoing embodiments, and is not described herein again.

In another specific embodiment, referring to fig. 18c, the microwave signal processing apparatus of the radar system includes: 4 MMICs; the radar signal processing device of the radar system comprises 2 RSPU chips, and the 2 RSPU chips are interconnected in a cooperative processing cascade mode.

Specifically, the output interface of the 4 MMIC chips is coupled with the input interface of the RSPU chip 1, the RSPU chip 2 is coupled with the RSPU chip 1, and the RSPU chip 2 can be the intermediate algorithm point of the RSPU chip 1 or the branch algorithm point of the RSPU chip 2. The specific implementation manner of the interconnection between the RSPU chip 1 and the RSPU chip 2 in the cooperative processing cascade manner may refer to the description in the above embodiments, and is not described herein again.

In another specific embodiment, referring to fig. 18d, the microwave signal processing apparatus of the radar system includes: 2 groups of MMICs, wherein each group of MMICs comprises 4 MMIC chips; the radar signal processing device of the radar system comprises 4 RSPU chips, and the 4 RSPU chips are comprehensively interconnected in a parallel cascade mode, a serial cascade mode and a cooperative processing cascade mode.

Specifically, the output interface of the 1 st group of MMICs is coupled with the input interface of the RSPU chip 1, the output interface chip of the 2 nd group of MMICs is coupled with the input interface of the RSPU chip 2, and the RSPU chip 1 and the RSPU chip 2 are interconnected in a parallel cascade manner; the RSPU chip 1 and the RSPU chip 3 are interconnected in a serial cascade mode, and the RSPU chip 2 and the RSPU chip 4 are interconnected in a serial cascade mode; and the RSPU chip 3 and the RSPU chip 4 are interconnected in a cooperative processing cascade mode.

In the radar systems provided in the foregoing embodiments, at least two RSPUs included in the radar signal processing apparatus are interconnected in one or more of parallel cascade, serial cascade, and cooperative cascade according to the dimension of the signal processing unit or the dimension of the data processing unit included in the signal processing unit, so that the data processing capability of the radar signal processing apparatus is improved, and the processing efficiency of the radar system is further improved; and the RSPU included in the radar signal processing device can be flexibly expanded according to the requirements of intelligent driving of each level, the increasing signal processing algorithm requirements of the vehicle-mounted radar and the like.

Fig. 19 is a schematic structural diagram of a radar system according to another embodiment of the present application. As shown in fig. 19, the radar system 1900 according to the embodiment further includes, in addition to the embodiment shown in fig. 16: antenna elements 1603.

Wherein the antenna unit 1603 is coupled to the microwave signal processing device 1601, the antenna unit 1603 is used for transmitting and receiving signals.

In one possible implementation, radar system 1900 includes multiple antenna unit sets, each including at least one antenna unit 1603, each coupled to one MMIC in a microwave signal processing device.

Fig. 20 is a schematic structural diagram of a mobile platform according to an embodiment of the present application. As shown in fig. 20, the mobile platform 2000 of the present embodiment includes: a radar signal processing device 2001, a microwave signal processing device 2002, and an automatic driving control system 2003.

Wherein the microwave signal processing means 2002 comprises one or more MMICs, an input interface of each MMIC being coupled to an output interface of one or more antenna units, an output interface of each MMIC being coupled to an input interface of one RSPU in the radar signal processing means 2001; each MMIC is used for carrying out radio frequency and analog signal processing on signals input by one or more antenna units;

the radar signal processing device 2001 comprises at least two RSPUs which are interconnected in a cascade manner;

specifically, an input interface of a first RSPU of the at least two RSPUs is coupled to an output interface of the microwave signal processing apparatus, and the input interface of the first RSPU is configured to receive a signal output by the microwave signal processing apparatus; the at least two RSPUs are used for carrying out cascade processing on the signals output by the microwave signal processing device; the other RSPUs in the at least two RSPUs are coupled to the first RSPU, and the output interface of the first RSPU is used for outputting the cascade-processed signals to the automatic driving control system; or other RSPUs in the at least two RSPUs are sequentially coupled to the output interface of the first RSPU, and the output interface of the last RSPU is used for outputting the signal after the cascade processing to the automatic driving control system;

the automatic driving control system 2003 is configured to obtain a radar detection result according to the signal output by the radar signal processing device 2001, and control the vehicle to perform intelligent driving according to the radar detection result.

For example, the automatic driving control system 2003 may sense the surrounding environment information based on the signal output from the radar signal processing device 2001 and detect that an obstacle exists ahead, and the automatic driving control system 2003 may control the states of a body controller, an engine control unit, and the like of the vehicle to execute an avoidance maneuver, for example: deceleration, emergency braking, etc.

The mobile platform can also be applied to various types of unmanned aerial vehicles, such as shooting unmanned aerial vehicles, agricultural unmanned aerial vehicles and the like. And is not limited to autonomous vehicles.

It should be noted that, in the above embodiments, the RSPU and the RSPU chip are used to indicate the same device, but the RSPU may be packaged as a separate chip, or may be integrated with other functional circuits, such as MMIC, or a plurality of RSPUs may be integrated together and packaged as the same chip. The MMIC and the MMIC chip are used to indicate the same device, and similarly, the MMIC may be packaged as a separate chip, or may be integrated with other functional circuits, such as the RSPU, or multiple MMICs may be integrated and packaged together as the same chip.

The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

A radar signal processing apparatus for use in a radar system, comprising:

the system comprises at least two Radar Signal Processing Units (RSPUs), wherein the at least two RSPUs are interconnected in a cascade mode;

wherein, adopt cascade mode interconnection between at least two RSPUs, include:

an input interface of a first RSPU in the at least two RSPUs is coupled with an output interface of a microwave signal processing device, and the input interface of the first RSPU is used for receiving a signal output by the microwave signal processing device; the at least two RSPUs are used for performing cascade processing on the signals output by the microwave signal processing device;

the other RSPUs in the at least two RSPUs are coupled with the first RSPU, and the output interface of the first RSPU is used for outputting the cascade-processed signals; or, the other RSPUs of the at least two RSPUs are sequentially coupled to the output interface of the first RSPU, and the output interface of the last RSPU is used for outputting the signal after the cascade processing.
The device of claim 1, wherein when the at least two RSPUs are interconnected in a parallel cascade manner, the at least two RSPUs are configured to perform parallel cascade processing on the signal output by the microwave signal processing device;

the input ends of at least two first RSPUs are respectively coupled with the output interface of the microwave signal processing device, and the input interfaces of the at least two first RSPUs are respectively used for receiving signals output by the microwave signal processing device;

in the at least two first RSPUs, a signal output end of a last data processing unit of each first RSPU is coupled to a same output interface, and the output interface is used for outputting a signal after parallel cascade processing.
The apparatus of claim 2, wherein the input interface of each of the at least two first RSPUs is coupled to the output interface of the monolithic microwave integrated circuit MMIC of one or more of the microwave signal processing apparatuses.
The apparatus of claim 2 or 3, wherein each of the at least two first RSPUs comprises a plurality of sequentially coupled data processing units, the plurality of data processing units comprising a first data processing unit and a second data processing unit that are sequentially coupled;

in the at least two first RSPUs, an output interface of the first data processing unit in each of the first RSPUs is coupled with an input interface of the second data processing unit of the remaining first RSPUs in the at least two first RSPU ways;

the input interface of the second data processing unit in each of the first RSPUs is configured to receive signals output by the first data processing units of the remaining first RSPUs of the at least two first RSPUs.
The apparatus of claim 4, wherein the first data processing unit is a distance dimension Fourier transform unit and the second data processing unit is a Doppler dimension Fourier transform unit.
The apparatus of claim 4, wherein the first data processing unit is a constant false alarm detection (CFAR) unit and the second data processing unit is a direction of arrival (DOA) calculation unit.
The apparatus of claim 4, wherein the first data processing unit is a DOA calculation unit and the second data processing unit is a data trace unit.
The apparatus of any of claims 2 to 7, further comprising: and the input interface of the third RSPU is coupled with the output interfaces of the at least two first RSPUs, and the third RSPU is used for correspondingly processing the signals output by the at least two first RSPUs and outputting the processed signals through the output interface of the third RSPU.
The apparatus of any of claims 2 to 8, further comprising: a fourth RSPU;

the fourth RSPU is coupled between two data processing units sequentially coupled in any one of the first RSPUs; or,

the fourth RSPU is coupled between two sequentially coupled data processing units in the third RSPU; or,

an input interface of the fourth RSPU is coupled with an input interface of any data processing unit in any first RSPU, and an output interface of the fourth RSPU is coupled with an output interface of any other data processing unit in the first RSPU; or,

an input interface of the fourth RSPU is coupled to an input interface of any of the data processing units in the third RSPU, and an output interface of the fourth RSPU is coupled to an output interface of any of the other data processing units in the third RSPU.
The device of claim 1, wherein when the at least two RSPUs are interconnected in a serial cascade manner, the at least two RSPUs are configured to perform serial cascade processing on the signal output by the microwave signal processing device;

the input interface of the first RSPU in the at least two RSPUs is coupled with the output interface of the microwave signal processing device, other RSPUs in the at least two RSPUs are sequentially coupled with the output interface of the first RSPU, and the output interface of the last RSPU is used for outputting signals after serial cascade processing;

the at least two RSPUs comprise completely different data processing units.
The apparatus of claim 10, wherein the at least two RSPUs each comprise: one or more of a distance dimensional Fourier transform unit, a Doppler dimensional Fourier transform unit, a CFAR unit, a DOA computation unit, a data tracking unit, and the at least two RSPUs are completely different.
The apparatus of claim 10 or 11, further comprising: a fifth RSPU;

wherein an input interface of the fifth RSPU is coupled to an output interface of any one of the at least two RSPUs, or an input interface of the fifth RSPU is coupled to an output interface of one or more MMICs in the microwave signal processing device; an output interface of the fifth RSPU is coupled to an output interface of any remaining RSPU of the at least two RSPUs;

the fifth RSPU is configured to receive a signal from an RSPU coupled to an input interface of the fifth RSPU or the microwave signal processing apparatus, perform corresponding processing on the received signal, and output the processed signal through an output interface of the fifth RSPU.
The apparatus of any one of claims 10 to 12, further comprising: the sixth RSPU is one of the RSPUs,

the sixth RSPU is coupled between two sequentially coupled data processing units in any of the RSPUs; or,

the sixth RSPU is coupled between two data processing units sequentially coupled in the fifth RSPU; or,

the input interface of the sixth RSPU is coupled with the input interface of any data processing unit in any RSPU, and the output interface of the sixth RSPU is coupled with the output interface of any other data processing unit in the RSPU; or,

an input interface of the sixth RSPU is coupled to an input interface of any of the data processing units in the fifth RSPU, and an output interface of the sixth RSPU is coupled to an output interface of any of the other data processing units in the fifth RSPU.
The device according to claim 1, wherein when the at least two RSPUs are coupled in a cooperative processing cascade manner, the at least two RSPUs are configured to perform cooperative cascade processing on the signal output by the microwave signal processing device;

wherein an input interface of the first RSPU of the at least two RSPUs is coupled to an output interface of the microwave signal processing apparatus, other RSPUs of the at least two RSPUs are coupled to the first RSPU, and an output interface of the first RSPU is configured to output a cooperatively cascaded processed signal.
The apparatus of claim 14, wherein the first RSPU of the at least two RSPUs comprises a plurality of sequentially coupled data processing units, the sequentially coupled plurality of data processing units comprising a first data processing unit and a second data processing unit that are sequentially coupled; the remaining RSPUs of the at least two RSPUs include a function extension unit;

the input interface of the function expansion unit is coupled with the output interface of the first data processing unit, and the output interface of the function expansion unit is coupled with the input interface of the second data processing unit;

the function extension unit is used for receiving signals from the first data processing unit of the first RSPU, correspondingly processing the received signals and outputting the processed signals to the second data processing unit of the first RSPU.
The apparatus of claim 14, wherein the first of the at least two RSPUs comprises a plurality of data processing units coupled in sequence, and wherein remaining RSPUs of the at least two RSPUs comprise function extension units;

the input interface of the function extension unit is coupled to the output interface of one of the plurality of data processing units, and the input interface of the function extension unit is coupled to the input interface of any one of the remaining data processing units of the plurality of data processing units.
The apparatus according to claim 15 or 16, wherein the sequentially coupled plurality of data processing units comprises: the device comprises a distance dimension Fourier transform unit, a Doppler dimension Fourier transform unit, a CFAR unit, a DOA calculation unit and a data tracking unit;

the signal input part of the distance dimension Fourier transform unit is coupled with the output interface of the microwave signal processing device through the input interface of the first RSPU, the signal output part of the distance dimension Fourier transform unit is connected with the signal input part of the Doppler dimension Fourier transform unit, the signal output part of the Doppler dimension Fourier transform unit is connected with the signal input part of the CFAR unit, the signal output part of the CFAR unit is connected with the signal input part of the DOA calculation unit, the signal output part of the DOA calculation unit is connected with the signal output input part of the data tracking unit, and the signal output part of the data tracking unit is coupled with the output interface of the first RSPU.
The apparatus of any one of claims 14 to 17, further comprising: a seventh RSPU, wherein an input interface of the seventh RSPU is coupled to an output interface of the first RSPU, and the seventh RSPU is configured to receive the signal output by the first RSPU, process the received signal accordingly, and output the processed signal through an output interface of the seventh RSPU.
A radar system, comprising: microwave signal processing apparatus and radar signal processing apparatus according to any one of claims 1 to 18;

wherein the microwave signal processing device comprises one or more Monolithic Microwave Integrated Circuits (MMICs), an input interface of each MMIC is coupled to an output interface of one or more antenna units, and an output interface of each MMIC is coupled to an input interface of one Radar Signal Processing Unit (RSPU) in the radar signal processing device; each MMIC is used for carrying out radio frequency and analog signal processing on signals input by one or more antenna units;

the radar signal processing device comprises at least two RSPUs which are interconnected in a cascade mode;

wherein, adopt cascade mode interconnection between at least two RSPUs, include:

an input interface of a first RSPU in the at least two RSPUs is coupled with an output interface of the microwave signal processing device, and the input interface of the first RSPU is used for receiving a signal output by the microwave signal processing device; the at least two RSPUs are used for carrying out cascade processing on the signals output by the microwave signal processing device;

the other RSPUs in the at least two RSPUs are coupled with the first RSPU, and the output interface of the first RSPU is used for outputting the cascade-processed signals; or, the other RSPUs in the at least two RSPUs are sequentially coupled to the output interface of the first RSPU, and the output interface of the last RSPU is used for outputting the cascade-processed signal.
The radar system of claim 19, wherein the microwave signal processing device comprises at least two sets of microwave signal processing circuits, each set of microwave signal processing circuits comprises at least one MMIC, and each set of MMICs is connected to one RSPU of the radar signal processing device.
A mobile platform, comprising: the radar signal processing apparatus, the microwave signal processing apparatus, and the automatic driving control system according to any one of claims 1 to 18,

wherein the microwave signal processing device comprises one or more MMICs, an input interface of each MMIC is coupled to an output interface of one or more antenna units, and an output interface of each MMIC is coupled to an input interface of one Radar Signal Processing Unit (RSPU) in the radar signal processing device; each MMIC is used for carrying out radio frequency and analog signal processing on signals input by one or more antenna units;

the radar signal processing device comprises at least two RSPUs which are interconnected in a cascade mode;

wherein, adopt cascade mode interconnection between at least two RSPUs, include:

an input interface of a first RSPU in the at least two RSPUs is coupled with an output interface of the microwave signal processing device, and the input interface of the first RSPU is used for receiving a signal output by the microwave signal processing device; the at least two RSPUs are used for performing cascade processing on the signals output by the microwave signal processing device;

the other RSPUs in the at least two RSPUs are coupled with the first RSPU, and the output interface of the first RSPU is used for outputting the signals after the cascade processing to the automatic driving control system; or other RSPUs in the at least two RSPUs are sequentially coupled to the output interface of the first RSPU, and the output interface of the last RSPU is used for outputting the signal after the cascade processing to the automatic driving control system;

the automatic driving control system is used for acquiring a radar detection result according to the signal output by the radar signal processing device and controlling the vehicle to carry out intelligent driving according to the radar detection result.
A radar signal processing method applied to a radar system, wherein the radar system comprises a radar signal processing device, and the radar signal processing device comprises: the radar signal processing unit comprises at least two Radar Signal Processing Units (RSPUs), wherein the at least two RSPUs are interconnected in a cascade mode; the method comprises the following steps:

receiving a signal output by the microwave signal processing device through an input interface of a first RSPU in the at least two RSPUs; the at least two RSPUs carry out cascade processing on the signals output by the microwave signal processing device;

outputting the cascade processed signal through an output interface of the first RSPU, wherein other RSPUs of the at least two RSPUs are coupled to the first RSPU; or, the cascaded processed signal is output through an output interface of the last RSPU, wherein other RSPUs of the at least two RSPUs are sequentially coupled to the output interface of the first RSPU.
The method according to claim 22, wherein when the at least two RSPUs are interconnected in a parallel cascade manner, the at least two RSPUs are used for performing parallel cascade processing on the signal output by the microwave signal processing apparatus; the input ends of at least two first RSPUs are respectively coupled with the output interface of the microwave signal processing device, and the input interfaces of the at least two first RSPUs are respectively used for receiving signals output by the microwave signal processing device; the signal output ends of the last data processing units of the at least two first RSPUs are coupled to the same output interface, and the output interface is used for outputting signals after parallel cascade processing;

and each of the at least two first RSPUs comprises a plurality of data processing units coupled in sequence, and the plurality of data processing units comprise a first data processing unit and a second data processing unit coupled in sequence;

the output interface of the first data processing unit in each of the at least two first RSPUs is coupled with the input interface of the second data processing unit in the remaining first RSPUs of the at least two first RSPUs;

the at least two RSPUs perform parallel cascade processing on the signals output by the microwave signal processing device, and the parallel cascade processing comprises the following steps:

in the at least two first RSPUs, the second data processing unit of each first RSPU acquires data output by the first data processing units of other first RSPUs;

each first RSPU performs load balancing on data output by all the first data processing units according to the quantity of the at least two first RSPUs and the characteristics of the data output by the first data processing units, and determines to-be-processed data corresponding to second data processing units of the first RSPUs;

and the second data processing unit of each first RSPU processes the determined data to be processed.
The method of claim 23, wherein the first data processing unit is a distance dimensional fourier transform unit and the second data processing unit is a doppler dimensional fourier transform unit; the load balancing of the data output by all the first data processing units by each first RSPU according to the number of the at least two first RSPUs and the characteristics of the data output by the first data processing units, and determining the data to be processed corresponding to the second data processing units of the first RSPUs include:

in the at least two first RSPUs, each first RSPU performs load balancing on data output by all distance dimension Fourier transform units according to the number and the distance dimension of the at least two first RSPUs, and determines to-be-processed data corresponding to the Doppler dimension Fourier transform units of the first RSPUs.
The method of claim 23, wherein the first data processing unit is a constant false alarm detection (CFAR) unit and the second data processing unit is a direction of arrival (DOA) calculation unit; the load balancing of the data output by all the first data processing units by each first RSPU according to the number of the at least two first RSPUs and the characteristics of the data output by the first data processing units, and determining the data to be processed corresponding to the second data processing units of the first RSPUs include:

in the at least two first RSPUs, each first RSPU performs load balancing on data output by all CFAR units according to the number of the at least two first RSPUs and the dimension of a target number, and determines to-be-processed data corresponding to a DOA detection unit of the first RSPU.
The method of claim 23, wherein the first data processing unit is a DOA computation unit and the second data processing unit is a data trace unit; the load balancing of the data output by all the first data processing units is performed by each first RSPU according to the number of the at least two first RSPUs and the characteristics of the data output by the first data processing units, and determining to-be-processed data corresponding to the second data processing unit of the first RSPU includes:

in the at least two first RSPUs, each first RSPU performs load balancing on data output by all DOA computing units according to the number of the at least two first RSPUs and the dimension of a target number, and determines to-be-processed data corresponding to a data tracking unit of the first RSPU.