CN115802761A - Integrated chip structure and forming method thereof - Google Patents

Integrated chip structure and forming method thereof Download PDF

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Publication number
CN115802761A
CN115802761A CN202210683828.6A CN202210683828A CN115802761A CN 115802761 A CN115802761 A CN 115802761A CN 202210683828 A CN202210683828 A CN 202210683828A CN 115802761 A CN115802761 A CN 115802761A
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bit line
memory devices
interconnect
coupled
additional
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Chinese (zh)
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尹煜峰
戴铭昆
黄建桦
林仲德
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/161—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1653—Address circuits or decoders
    • G11C11/1655—Bit-line or column circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/18—Bit line organisation; Bit line lay-out
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
    • H10B61/20—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors
    • H10B61/22—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors of the field-effect transistor [FET] type
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/80—Constructional details

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  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)

Abstract

The present disclosure relates to integrated chip structures and methods of forming the same. An integrated chip structure includes a memory array having a plurality of memory devices arranged in a plurality of rows and a plurality of columns. The word lines are coupled to a first group of the plurality of memory devices disposed within a first row of the plurality of rows. The bit lines are coupled to a second group of the plurality of memory devices disposed within a first column of the plurality of columns. The local interconnect extends parallel to the bit line and is coupled to the bit line and two or more of the second group of the plurality of memory devices. The local interconnect is coupled to the bit line through a plurality of interconnect vias located between the local interconnect and the bit line.

Description

Integrated chip structure and forming method thereof
Technical Field
Embodiments of the present invention relate to the field of semiconductor technology, and more particularly, to integrated chip structures and methods of forming the same.
Background
Many modern electronic devices contain electronic memory configured to store data. The electronic memory may be volatile memory or non-volatile memory. Volatile memory stores data when powered on, while non-volatile memory is capable of storing data when powered off. Magnetoresistive Random Access Memory (MRAM) is a promising candidate for the next generation of non-volatile memory technologies.
Disclosure of Invention
According to an aspect of an embodiment of the present invention, there is provided an integrated chip structure including: a memory array comprising a plurality of memory devices arranged in a plurality of rows and a plurality of columns; a word line coupled to a first group of the plurality of memory devices disposed within a first row of the plurality of rows; a bit line coupled to a second group of the plurality of memory devices disposed within a first column of the plurality of columns; and a local interconnect extending parallel to the bit line and coupled to the bit line and to two or more memory devices of the second group of the plurality of memory devices, wherein the local interconnect is coupled to the bit line through a plurality of interconnect vias located between the local interconnect and the bit line.
According to another aspect of an embodiment of the present invention, there is provided an integrated chip structure, including: a memory array comprising a plurality of memory devices arranged in a cross-sectional view within a dielectric structure over a substrate; bit lines disposed over the plurality of memory devices; a local interconnect extending parallel to a bit line and coupled to the plurality of memory devices, the bit line extending laterally past opposite ends of the local interconnect; and wherein the local interconnect is coupled to the bit line through a plurality of interconnect vias disposed between a top of the local interconnect and a bottom of the bit line.
According to yet another aspect of embodiments of the present invention, there is provided a method of forming an integrated chip structure, including: forming a plurality of memory devices over a substrate; forming a first upper interlayer dielectric layer over the plurality of memory devices; patterning the first upper interlayer dielectric layer to form local interconnect openings extending laterally past opposing edges of the plurality of memory devices; forming a local interconnect within the local interconnect opening; forming a plurality of interconnect vias in a second upper interlevel dielectric layer located above the first upper interlevel dielectric layer; and forming a bit line over the plurality of interconnect vias, wherein the plurality of interconnect vias connect the local interconnect to the bit line.
Drawings
Various aspects of the invention are best understood from the following detailed description when read with the accompanying drawing figures. It should be emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale and are used for illustration purposes only. In fact, the dimensions of the various elements may be arbitrarily increased or decreased for clarity of discussion.
1A-1B illustrate some embodiments of an integrated chip structure including a memory array having local interconnects configured to reduce resistance of bit lines.
FIG. 2 illustrates a cross-sectional view of some embodiments of an integrated chip structure including a memory array having local interconnects configured to reduce resistance of bit lines.
FIG. 3 illustrates a cross-sectional view of some additional embodiments of an integrated chip structure including a memory array having local interconnects configured to reduce resistance of bit lines.
FIG. 4 illustrates a schematic diagram of some additional embodiments of an integrated chip structure including a memory array having local interconnects configured to reduce resistance of bit lines.
FIG. 5 illustrates a cross-sectional view of some additional embodiments of an integrated chip structure including a memory array having local interconnects configured to reduce resistance of bit lines.
Fig. 6A-6C illustrate integrated chip structures including some additional embodiments of memory arrays having local interconnects configured to reduce resistance of bit lines.
Figure 7 illustrates a cross-sectional view of some additional embodiments of an integrated chip structure including a memory array having local interconnects configured to reduce resistance of bit lines.
FIG. 8 illustrates a cross-sectional view of some additional embodiments of an integrated chip structure including a memory array having local interconnects configured to reduce resistance of bit lines.
Fig. 9A-9B illustrate integrated chip structures including some additional embodiments of memory arrays having local interconnects configured to reduce resistance of bit lines.
10-29 illustrate cross-sectional views showing some embodiments of methods of forming memory arrays and integrated chip structures including local interconnects configured to reduce resistance of bit lines.
FIG. 30 illustrates a flow diagram of some embodiments of a method of forming an integrated chip structure including a memory array having local interconnects configured to reduce resistance of bit lines.
Detailed Description
The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Moreover, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Furthermore, for ease of description, spaced relationship terms such as "below 8230; below", "below 8230; lower", "below", "at 8230; upper", "upper", and the like may be used herein to describe the relationship of one element or component to another element or component as shown in the figures. The term spaced relationship is intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spacing relationship descriptors used herein interpreted accordingly as such.
A Magnetoresistive Random Access Memory (MRAM) cell includes a Magnetic Tunnel Junction (MTJ) disposed between conductive electrodes. The MTJ includes a pinned layer separated from a free layer by a tunnel barrier layer. The magnetic orientation of the pinned layer is static (i.e., fixed), while the magnetic orientation of the free layer can be switched between a parallel configuration and an anti-parallel configuration with respect to the pinned layer. The parallel configuration provides a low resistance state that stores data digitally as a first bit value (e.g., a logic "1"). The anti-parallel configuration provides a high resistance state that digitally stores the data as a second bit value (e.g., a logic "0").
The MRAM devices may be arranged on an integrated chip structure that is located in an array that includes rows and columns. The MRAM devices within a row are operatively coupled to word lines, which are further coupled to word line decoders. The MRAM devices within a column are operably coupled to bit lines that are further coupled to a bit line decoder. During operation, a word line decoder and a bit line decoder are configured to selectively apply signals to the word line and the bit line. By selectively applying signals to the word lines and bit lines, data may be written to and/or read from different MRAM devices within the array.
As the functionality of integrated chips increases, so does the demand for more memory, resulting in increased amounts of available memory for integrated chip designers and manufacturers. To achieve this goal, the size of the memory array may be increased, thereby increasing the length of the word lines and/or bit lines within the array. In addition, the size of the memory array components, and thus the size (e.g., width and/or height) of the word lines and bit lines, may also be reduced. However, increasing the length of the word lines and bit lines and/or decreasing the size of the word lines and bit lines results in an increase in the resistance of the word lines and bit lines (because R = ρ × L/a, where R is the resistance, ρ is the resistivity, L is the length, and a is the cross-sectional area). Increasing the resistance of the word lines and/or bit lines decreases the performance of the memory array. For example, increasing the resistance of the bit lines may increase the variation in the read signals received from and/or drive signals provided to different portions of the array. The increased variation may reduce the memory window of the memory array (e.g., the difference between the signals output from the MRAM devices in the low resistance state and the high resistance state) and ultimately lead to errors in reading and/or writing data.
The present disclosure relates to an integrated chip structure including a memory array having local interconnects configured to reduce resistance of bit lines within the memory array. In some embodiments, an integrated chip structure may include a memory array having a plurality of memory devices. The plurality of memory devices are arranged in a plurality of rows and a plurality of columns. A word line is operatively coupled to a first plurality of memory devices disposed within a first row of the plurality of rows. The bit lines are operatively coupled to a second plurality of memory devices disposed within a first column of the plurality of columns. The local interconnect extends parallel to the bit line and is coupled between the bit line and two or more of the second plurality of memory devices. Since the local interconnect is coupled with and extends parallel to the bit line, the local interconnect can reduce the resistance of the first bit line. By reducing the resistance of the bit lines, the local interconnects can improve the performance of the integrated chip structure.
FIG. 1A illustrates a schematic diagram 100 of some embodiments of an integrated chip structure including a memory array having local interconnects configured to reduce resistance of bit lines.
As shown in the schematic diagram 100, the integrated chip structure includes a memory array 102, the memory array 102 including a plurality of memory cells 103 arranged in rows and/or columns. The plurality of memory cells 103 includes a memory device 104 and an access device 106, the access device 106 configured to control access to the memory device 104. A first plurality of memory devices 104 within a row each have an access device 106 operatively coupled to a word line 108. A second plurality of memory devices 104 within a column is operatively coupled to a bit line 110. In some embodiments, a second plurality of memory devices 104 within a column may have an access device 106 further coupled to a source line 112. The word lines 108 and bit lines 110 are coupled to control circuitry 114, the control circuitry 114 being configured to selectively apply signals to the word lines 108 and/or the bit lines 110 to access (e.g., write data to and/or read data from) one or more of the plurality of memory devices 104.
The local interconnects 116 extend parallel to the bit lines 110. The local interconnect 116 is coupled between the bit line 110 of the memory array 102 and two or more of the second plurality of memory devices 104 within a column. Since the local interconnect 116 is coupled to the bit line 110 and extends parallel to the bit line 110, the local interconnect 116 is able to provide an alternative path for signals applied to the bit line 110 by the control circuitry 114. The local interconnect 116 can reduce the resistance of the bit line 110 by providing an alternative path for signals applied to the bit line 110. By reducing the resistance of the bit lines 110, the local interconnects 116 can improve the performance (e.g., memory window) of the memory array 102.
FIG. 1B illustrates a cross-sectional view 120 of some embodiments of an integrated chip structure corresponding to the portion 118 of the schematic 100 illustrated in FIG. 1A.
As shown in cross-sectional view 120, the integrated chip structure includes an embedded memory region 124 and a peripheral region 136 (e.g., a logic region including one or more transistor devices configured to perform a logic function). The memory array 102 is disposed within an embedded memory region 124. Memory array 102 includes a plurality of memory devices 104 disposed within a dielectric structure 126 over a substrate 122. The plurality of memory devices 104 respectively include a data storage structure 104b disposed between a bottom electrode 104a and a top electrode 104c. In some embodiments, dielectric structures 126 include a lower inter-layer dielectric (ILD) structure 126L and an upper ILD structure 126U above lower ILD structure 126L.
In some embodiments, a plurality of access devices 106 are disposed within the embedded memory region 124. In some embodiments, the plurality of access devices 106 are coupled to the plurality of memory devices 104 through a plurality of lower interconnects 128 within the lower ILD structure 126L. In some additional embodiments, one or more transistor devices 138 are disposed within the peripheral region 136. The one or more transistor devices 138 may be part of the control circuitry 114, the control circuitry 114 configured to selectively apply signals to the one or more memory devices 104.
The local interconnect 116 is disposed within the upper ILD structure 126U and extends parallel to the bit line 110. The local interconnect 116 is coupled to the plurality of memory devices 104. The local interconnect 116 is further coupled to the overlying bit line 110 by a plurality of interconnect vias 130 located directly between the local interconnect 116 and the bit line 110. In some embodiments, the local interconnect 116 has a first length 132 (e.g., measured along the longest dimension of the local interconnect 116), and the bit line 110 has a second length 134 (e.g., measured along the longest dimension of the bit line 110) that is greater than the first length 132. In some embodiments, the bit line 110 extends past one end of the local interconnect 116. In some additional embodiments, the bit lines 110 extend past opposite ends of the local interconnects 116.
Bit lines 110 extend from within embedded memory region 124 to within peripheral region 136. The bit lines 110 are coupled to the control circuitry 114 through one or more peripheral interconnects 140. In some embodiments, one or more peripheral interconnects 140 may include interconnect vias and/or interconnect routing. In some alternative embodiments (not shown), the bit line 110 may be coupled to a voltage source disposed within a dielectric structure 126 above the bit line 110. In some embodiments, the bit lines 110 extend into the peripheral region 136 of the substrate 122 and the local interconnects 116 are confined within the embedded memory region 124 of the substrate 122. Confining the local interconnects 116 within the embedded memory region 124 provides space within the peripheral region 136 for other interconnect routing.
During operation, the control circuitry 114 is configured to perform an access operation (e.g., a read operation or a write operation, etc.) on one of the plurality of memory devices 104 by selectively applying a signal 142 (e.g., a read current, a drive current, etc.) to the bit line 110. Generally, the resistance of the bit line 110 will be proportional to the second length 134 of the bit line 110 divided by the cross-sectional area of the bit line 110 (since R = ρ × L/a). However, because the local interconnects 116 are coupled to the bit lines 110 through the plurality of interconnect vias 130, the signals 132 have multiple parallel paths between the control circuitry 114 and the plurality of memory devices 104. The multiple parallel paths provide a larger cumulative cross-sectional area for signal 142 to travel through, thereby reducing the resistance of bit line 110. By reducing the resistance of the bit line 110, the performance of the integrated chip structure (e.g., memory window) may be improved.
Fig. 2 illustrates a cross-sectional view of some additional embodiments of an integrated chip structure 200 including a memory array having local interconnects configured to reduce resistance of bit lines.
The integrated chip structure 200 includes an embedded memory region 124 and a peripheral region 136. The memory array 102 is disposed within the embedded memory region 124. Memory array 102 includes a plurality of memory devices 104 disposed within a dielectric structure 126 over a substrate 122. The plurality of memory devices 104 each include a data storage structure 104b disposed between a bottom electrode 104a and a top electrode 104c. In some embodiments, the bottom electrode 104a and the top electrode 104c may comprise a metal, such as tantalum, titanium, tantalum nitride, titanium nitride, platinum, nickel, hafnium, zirconium, ruthenium, iridium, and the like.
In some embodiments, dielectric structure 126 includes a lower ILD structure 126L and an upper ILD structure 126U. The lower ILD structure laterally surrounds the plurality of lower interconnects 128. In some embodiments, the plurality of lower interconnects 128 may include conductive contacts, interconnect wires, and/or interconnect vias including one or more of copper, aluminum, tungsten, ruthenium, and the like. Upper ILD structure 126U laterally surrounds the plurality of memory devices 104. In some embodiments, lower ILD structure 126L and/or upper ILD structure 126U may comprise one or more of silicon dioxide, carbon doped silicon oxide (SiCOH), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), borosilicate glass (BSG), fluorosilicate glass (FSG), undoped Silicate Glass (USG), and the like.
In some embodiments, the plurality of access devices 106 are disposed within the embedded memory region 124 and coupled to the plurality of memory devices 104 through a plurality of lower interconnects 128. In some embodiments, the plurality of access devices 106 may each include a MOSFET device having a gate structure 106c, the gate structure 106c being laterally disposed between the source region 106a and the drain region 106 b. In some embodiments, the gate structure 106c may include a gate electrode separated from the substrate 122 by a gate dielectric. In some embodiments, the source region 106a is coupled to a source line 112 and the gate structure 106c is coupled to a word line 108. In various embodiments, the MOSFET devices may include planar FETs, finfets, full Gate All Around (GAA) devices, and the like. In other embodiments, the access device 106 may include a HEMT (high electron mobility transistor), BJT (bipolar junction transistor), JFET (junction gate field effect transistor), or the like.
In some embodiments, lower ILD structure 126L is separated from upper ILD structure 126U by lower insulating structure 202. Bottom electrode vias 204 extend through the lower insulating structure 202 to couple the plurality of memory devices 104 to the plurality of lower interconnects 128. In some embodiments, the lower insulating structure 202 may include one or more dielectric layers stacked on top of each other. In various embodiments, the one or more dielectric layers may comprise one or more of silicon-rich oxide, silicon carbide, silicon dioxide, silicon nitride, and the like.
The local interconnects 116 are disposed within the upper ILD structure 126U and are coupled to the plurality of memory devices 104. The local interconnect 116 is further coupled to an overlying bit line 110 by a plurality of interconnect vias 130. The local interconnects 116 extend parallel to the bit lines 110 and are coupled between the bit lines 110 and the plurality of memory devices 104. In some embodiments, the local interconnects 116 extend laterally continuously through the plurality of memory devices 104 and the plurality of interconnect vias 130. In some embodiments, the bit line 110 includes a bottom surface that continuously extends laterally across both the plurality of interconnect vias 130 and the local interconnect 116. In some embodiments, the plurality of interconnect vias 130 are arranged in an array that extends laterally across two or more of the plurality of memory devices 104 such that the plurality of interconnect vias 130 extend laterally across the two or more memory devices 104. In some embodiments (not shown), the memory array 102 includes one or more additional memory devices located laterally outward of the local interconnects 116 and directly below the bit lines 110. In such embodiments, the memory array 102 extends laterally beyond one or more outer edges of the local interconnects 116.
In some embodiments, the plurality of interconnect vias 130 have bottom surfaces that physically contact the local interconnects 116 and top surfaces that physically contact the bit lines 110. In some such embodiments, the local interconnects 116 and bit lines 110 may be disposed on adjacent interconnect wiring levels of a back end of line (BEOL) stack. For example, local interconnects 116 may be disposed on a sixth interconnect routing layer (e.g., an interconnect routing layer that is a sixth interconnect routing layer above substrate 122), while bit lines 110 may be disposed on a seventh interconnect routing layer (e.g., an interconnect routing layer that is a seventh interconnect routing layer above substrate 122).
Fig. 3 illustrates a cross-sectional view of some additional embodiments of an integrated chip structure 300 including a memory array having local interconnects configured to reduce resistance of bit lines.
The integrated chip structure 300 includes an embedded memory region 124 and a peripheral region 136. The memory array 102 is disposed within the embedded memory region 124. Memory array 102 includes a plurality of memory devices 104 disposed within a dielectric structure 126 over a substrate 122. The local interconnects 116 are disposed within a dielectric structure 126 that is directly over the plurality of memory devices 104. The local interconnect 116 is coupled to the plurality of memory devices 104. The local interconnect 116 is further coupled to the overlying bit line 110 by a plurality of interconnect vias 130, a plurality of interconnect islands 304, and a plurality of additional upper interconnect vias 306.
The plurality of interconnect vias 130 have bottom surfaces that physically contact the local interconnects 116 and top surfaces that physically contact the plurality of interconnect islands 304. A plurality of additional upper interconnect vias 306 have bottom surfaces that physically contact the plurality of interconnect islands 304 and top surfaces that physically contact the bit lines 110. The plurality of interconnect islands 304 have a bottom surface that extends laterally past one or more outer edges of the plurality of interconnect vias 130 and a top surface that extends laterally past one or more outer edges of the plurality of additional upper interconnect vias 306. In some embodiments, the plurality of interconnect islands 304 have outer edges that are located directly above the top surface of the local interconnect 116 and are separated from each other by one or more non-zero distances 308 above the top surface of the interconnect 116.
By providing a plurality of interconnect islands 304 between the local interconnect 116 and the bit line 110, the distance between the local interconnect 116 and the bit line 110 is increased, thereby reducing capacitance on the bit line 110 and improving performance of the integrated chip structure 300. Further, the plurality of interconnect islands 304 allows the bit lines 110 to be formed on a relatively large interconnect wiring level (e.g., including a greater height and/or width than the bit lines 110 shown in fig. 2). Forming the bit lines 110 on a relatively large interconnect wiring level will cause the bit lines 110 to have a relatively low resistance, which will further improve the performance of the integrated chip structure 300.
Fig. 4 illustrates a schematic diagram 400 of some additional embodiments of an integrated chip structure including a memory array having local interconnects configured to reduce resistance of bit lines.
As shown in schematic diagram 400, an integrated chip structure includes a memory array 102, the memory array 102 including a plurality of memory cells 103 arranged in rows and/or columns. The plurality of memory cells 103 includes a plurality of memory devices 104 and a plurality of access devices 106, the plurality of access devices 106 configured to control access to the plurality of memory devices 104. A first plurality of memory devices 104 within a row each have an access device 106 operatively coupled to one of a plurality of word lines 108a-108 n. A second plurality of memory devices 104 within a column is operatively coupled to one of the plurality of bit lines 110a-110 n. In some embodiments, the plurality of memory devices 104 within a column includes an access device 106 further coupled to one of a plurality of source lines 112a-112 n.
The plurality of local interconnects 116a-116n extend parallel to the plurality of bit lines 110a-110 n. The plurality of local interconnects 116a-116n are coupled between one of the plurality of bit lines 110a-110n of the memory array 102 and two or more of the plurality of memory devices 104 within a column. The plurality of word lines 108a-108n, the plurality of bit lines 110a-110n, and/or the plurality of source lines 112a-112n are further coupled to a control circuit 114. In some embodiments, the control circuitry 114 includes a word line decoder 402 coupled to the plurality of word lines 108a-108n, a bit line decoder 404 coupled to the plurality of bit lines 110a-110n, and/or a source line decoder 406 coupled to the plurality of source lines 112a-112 n. In some embodiments, the control circuitry 114 also includes a control unit 410 coupled to the word line decoder 402, the bit line decoder 404, and/or the source line decoder 406.
During operation, the control circuit 114 is configured to provide address information S to the word line decoder 402, the bit line decoder 404, and/or the source line decoder 406 ADR . Based on address information S ADR The word line decoder 402 is configured to selectively apply a bias voltage to one of the plurality of word lines 108a-108 n. Meanwhile, the bit line decoder 404 is configured to selectively apply a bias voltage to one of the plurality of bit lines 110a-110n and/or the source line decoder 406 is configured to selectively apply a bias voltage to one of the plurality of source lines 112a-112 n. The control circuit 114 may be operable to write different data states to the plurality of memory cells 103 and/or read data states from the plurality of memory cells 103 by applying bias voltages to selected ones of the plurality of word lines 108a-108n, the plurality of bit lines 110a-110n, and/or the plurality of source lines 112a-112 n.
In some embodiments, the control circuit 114 also includes a sense amplifier 408 coupled to the plurality of bit lines 110a-110 n. During a read operation, the plurality of bit lines 110a-110n are configured to provide a read signal (e.g., a read current and/or voltage) to the sense amplifier 408. The sense amplifier 408 is configured to compare the read signal to a reference signal to determine a data state within the accessed memory device. Because the plurality of local interconnects 116a-116n are coupled in parallel to the plurality of bit lines 110a-110n, the plurality of bit lines 110a-110n will have a lower resistance that mitigates read signal degradation.
Fig. 5 illustrates a cross-sectional view of some additional embodiments of an integrated chip structure 500 including a memory array having local interconnects configured to reduce resistance of bit lines.
The integrated chip structure 500 includes an embedded memory region 124 and a peripheral region 136. The memory array 102 is disposed within an embedded memory region 124. Memory array 102 includes a plurality of memory devices 104 disposed within a dielectric structure 126 over a substrate 122. In some embodiments, dielectric structure 126 includes a lower ILD structure 126L, lower ILD structure 126L being separated from upper ILD structure 126U by a lower insulating structure 202. Lower ILD structure 126L surrounds a pluralityThe lower interconnect 128. In some embodiments, a plurality of memory devices 104 may be disposed over the lower insulating structure 202 and surrounded by the upper ILD structure 126U. In some embodiments, upper ILD structure 126U may comprise a plurality of upper ILD layers 126U stacked on top of each other 1 -126U 3 。
In some embodiments, the lower insulating structure 202 includes a first lower insulating layer 501 disposed within the embedded memory region 124 and the peripheral region 136. The lower insulating structure 202 may further include a second lower insulating layer 502 disposed over the first lower insulating layer 501 and a third lower insulating layer 504 disposed over the second lower insulating layer 502. In some embodiments, a second lower insulating layer 502 and a third lower insulating layer 504 are defined within the embedded memory region 124.
Bottom electrode vias 204 extend through the lower insulating structure 202 between the plurality of lower interconnects 128 and the plurality of memory devices 104. In some embodiments, the bottom electrode via 204 may include a diffusion barrier layer 514 and a conductive core 512 surrounded by the diffusion barrier layer 514. In some embodiments, diffusion barrier layer 514 may comprise one or more of titanium, titanium nitride, tantalum nitride, and the like. In some embodiments, the conductive core 512 may include one or more of aluminum, copper, tungsten, titanium nitride, tantalum nitride, and the like.
In some embodiments, each of the plurality of memory devices 104 includes a data storage structure 104b disposed between a bottom electrode 104a and a top electrode 104c. In some embodiments, the data storage structure 104b may include a Magnetic Tunnel Junction (MTJ). In such embodiments, the data storage structure 104b may include a pinned layer 516 separated from a free layer 520 by a dielectric tunnel barrier 518. The pinned layer 516 has a fixed magnetization, while the magnetization of the free layer 520 may be changed (by the Tunneling Magnetoresistance (TMR) effect) to be parallel (i.e., the "P" state) or antiparallel (i.e., the "AP" state) with respect to the magnetization of the pinned layer 516 during operation. The relationship between the magnetizations of the pinned layer 516 and the free layer 520 defines the resistance state of the MTJ and, thus, enables the MTJ to store a data state.
Sidewall spacers 505 may be disposed along sidewalls of the lower insulating structure 202 and the plurality of memory devices 104And (4) placing. In some embodiments, sidewall spacer 505 may comprise a first layer of sidewall spacers 506 and a second layer of sidewall spacers 508 over first layer of sidewall spacers 506. In some embodiments, the top electrode 104c protrudes outward from the top of the sidewall spacer layer 505. In some embodiments, first sidewall spacer layer 506 and/or second sidewall spacer layer 508 can comprise an oxide (e.g., silicon-rich oxide), a nitride (e.g., silicon nitride), a carbide (e.g., silicon carbide), and the like. A dielectric seal structure 510 is disposed on the sidewall spacers 505 and the first upper ILD layer 126U 1 Disposed on dielectric seal structure 510 and around dielectric seal structure 510.
An upper level etch stop dielectric layer 524 is disposed on the first upper ILD layer 126U l And (4) upward. In various embodiments, the upper-level etch stop dielectric layer 524 comprises silicon nitride, silicon carbide, silicon carbonitride, aluminum nitride, metal oxides (such as aluminum oxide, titanium oxide, tantalum oxide, etc.), and the like. In some embodiments, the upper level etch stop dielectric layer 524 physically contacts the first upper ILD layer 126U 1 Of the substrate. In various embodiments, the upper level etch stop dielectric layer 524 may have a thickness 525, the thickness 525 being in a range between about 4 nanometers (nm) and about 20nm, in a range between about 10nm and about 15nm, about 12.5nm, or other similar values.
A first dielectric matrix layer 526 is disposed over the upper level etch stop dielectric layer 524 and a second dielectric matrix layer 528 is disposed over the first dielectric matrix layer 526. In some embodiments, the first dielectric matrix layer 526 may comprise, for example, silicon nitride, silicon carbide, silicon carbonitride, aluminum nitride, metal oxides (such as aluminum oxide, titanium oxide, tantalum oxide, etc.), and the like. In some embodiments, the second dielectric matrix layer 528 may comprise, for example, tetraethylorthosilicate (TEOS), USG, BPSG, FSG, PSG, BSG, and the like. In some embodiments, the cumulative thickness of the first dielectric matrix layer 526 and the second dielectric matrix layer 528 may be in a range between about 15nm and about 60nm, a range between about 20nm and about 40nm, or other similar values. In some embodiments, the first dielectric host layer 526 may have a thickness 527, the thickness 527 ranging between about 4nm and about 8nm, about 6nm, or other similar values. In some embodiments, the second dielectric matrix layer 528 may have a thickness 529, the thickness 529 being in a range between about 10nm and about 20nm, about 16nm, or other similar values.
The common electrode 522 is disposed within the upper level etch stop dielectric layer 524 and at least one dielectric matrix layer 526-528. The common electrode 522 extends continuously over the plurality of memory devices 104. In some embodiments, the common electrode 522 extends continuously past the outermost edges of the plurality of memory devices 104. In some embodiments, the common electrode 522 is in direct physical contact with the top electrodes 104c of the plurality of memory devices 104.
A cap-level etch stop dielectric layer 530 is disposed over the at least one dielectric matrix layer 526-528 and the common electrode 522. In some embodiments, the cap-level etch stop dielectric layer 530 comprises silicon nitride, silicon carbide, silicon carbonitride, aluminum nitride, metal oxides (e.g., aluminum oxide, titanium oxide, tantalum oxide, etc.), and the like. In some embodiments, the cap-level etch stop dielectric layer 530 may physically contact a top surface of at least one of the dielectric matrix layers 526-528. In some embodiments, the cap-level etch stop dielectric layer 530 may have a thickness 531, the thickness 531 being in a range between about 4nm and about 20nm, in a range between about 10nm and about 15nm, about 12.5nm, or other similar values.
An upper level dielectric layer 532 is disposed on the cap level etch stop dielectric layer 530. The upper level dielectric layer 532 may include TEOS, USG, BPSG, FSG, PSG, BSG, etc. In some embodiments, the thickness 533 of the upper-level dielectric layer 532 may be in a range between about 5nm and about 20nm, a range between about 8nm and about 12nm, about 10nm, or other similar values. A plurality of local interconnect vias 534 are disposed within the overlying level etch stop dielectric 530 and the upper level dielectric 532. A plurality of local interconnect vias 534 contact the top of the common electrode 522.
Second upper ILD layer 126U 2 Disposed on the upper level dielectric layer 532. The local interconnect 116 is disposed on the second upper ILD layer 126U 2 And (4) inside. A plurality of interconnect vias 130 are disposed on the local interconnects 116 and are interconnected by a third upper ILD layer 126U 3 And (4) surrounding. A plurality of interconnect vias 130 couple the local interconnect 116 to the thirdUpper ILD layer 126U 3 The inner bit line 110. In various embodiments, the second upper ILD layer 126U 2 And/or third upper ILD layer 126U 3 May include USG, BPSG, FSG, PSG, BSG, etc. In various embodiments, the local interconnect 116, the plurality of interconnect vias 130, and/or the bit line 110 may comprise aluminum, copper, tungsten, or the like.
In some embodiments, the peripheral interconnect vias 536 are disposed within the peripheral region 136 of the substrate 122. The peripheral interconnect vias 536 are disposed within the dielectric structure 126 outside of the memory array 102. A peripheral interconnect via 536 extends vertically through the common electrode 522 and at least a portion of the plurality of local interconnect vias 534.
Fig. 6A illustrates a cross-sectional view of some additional embodiments of an integrated chip structure 600 including a memory array having local interconnects configured to reduce resistance of bit lines.
The integrated chip structure 600 includes an embedded memory region 124 and a peripheral region 136. The memory array 102 is disposed within the embedded memory region 124. The memory array 102 includes a first upper ILD layer 126U of a dielectric structure 126 disposed over a substrate 122 1 A plurality of memory devices 104. The local interconnect 116 is disposed on the second upper ILD layer 126U 2 And is coupled to the plurality of memory devices 104 by a common electrode 522 and a plurality of local interconnect vias 534. The local interconnects 116 extend continuously laterally across the plurality of memory devices 104.
The local interconnect 116 is coupled to an overlying bit line 110 by a plurality of interconnect vias 130, a plurality of interconnect islands 304, and a plurality of additional upper interconnect vias 306. The plurality of interconnect vias 130 physically contact the local interconnect 116 and the plurality of interconnect islands 304. A plurality of additional upper interconnect vias 306 physically contact the plurality of interconnect islands 304 and the bit line 110. In some embodiments, a plurality of interconnect vias 130 and a plurality of interconnect islands 304 are disposed on the third upper ILD layer 126U 3 And a plurality of additional upper interconnect vias 306 and bit lines 110 are disposed on the fourth upper ILD layer 126U 4 And (4) inside.
In some embodiments, the plurality of interconnect vias 130 may have a first height 125, the first height 125 being in a range between about 25nm and about 100nm, a range between about 50nm and about 90nm, or other similar values. In some embodiments, the plurality of interconnected islands 304 may have a second height 305, the second height 305 being in a range between about 25nm and about 100nm, a range between about 50nm and about 90nm, or other similar values. In some embodiments, the plurality of additional upper interconnect vias 306 may have a third height 307, the third height 307 being in a range between about 40nm and about 130nm, a range between about 50nm and about 120nm, or other similar values. In some embodiments, the bit line 110 may have a fourth height 111, the fourth height 111 being in a range between about 40nm and about 130nm, a range between about 50nm and about 120nm, or other similar values.
Fig. 6B illustratesbase:Sub>A top view 602 of some additional embodiments of the integrated chip structure 600 taken along section linebase:Sub>A-base:Sub>A' of fig. 6A.
As shown in the top view 602, the plurality of interconnect vias 130 are disposed within the boundaries of the plurality of interconnect islands 304. In some embodiments, the plurality of interconnect vias 130 may be recessed from the boundaries along the first direction 604 and/or along the second direction 606 perpendicular to the first direction 604. In some embodiments, the plurality of interconnected islands 304 may be square. In other embodiments, the plurality of interconnected islands 304 may be rectangular or other similar shapes.
In some embodiments, the plurality of interconnected islands 304 may be separated from each other by a first distance 608 along the first direction 604 and a second distance 610 along the second direction 606. In some embodiments, first distance 608 and/or second distance 610 may be in a range between about 10nm and about 100nm, between about 20nm and about 80nm, or other similar values. In some embodiments, the plurality of interconnected islands 304 may have a width 614, the width 614 being in a range between about 10nm and about 70nm, a range between about 20nm and about 50nm, or other similar values.
In some embodiments, the plurality of interconnect vias 130 may have a circular shape. In other embodiments, the plurality of interconnect vias 130 may have a square shape, a rectangular shape, or other similar shapes. In some embodiments, the plurality of interconnect vias 130 may have a width 612, the width 612 being in a range between about 10nm and about 100nm, a range between about 20nm and about 80nm, or other similar values.
FIG. 6C illustrates a top view 616 of some additional embodiments of the integrated chip structure 600 taken along section line B-B' of FIG. 6A.
As shown in the top view 616, the bit line 110 extends continuously along the second direction 606 through a plurality of additional upper interconnect vias 306 along the first direction 604. In some embodiments, the bit line 110 may have a width 620, the width 620 being in a range between about 10nm and about 200nm, a range between about 20nm and about 160nm, or other similar values. In some embodiments, the bit lines 110 may be separated from the additional bit lines 624 by a third distance 622 along the second direction 606. In some embodiments, third distance 622 may be in a range between about 10nm to about 200nm, in a range between about 20nm to about 160nm, or other similar values.
In some embodiments, the plurality of additional upper interconnect vias 306 may have a circular shape. In other embodiments, the plurality of additional upper interconnect vias 306 may have a square shape, a rectangular shape, or other similar shapes. In some embodiments, the plurality of additional upper interconnect vias 306 may have a width 618, the width 618 being in a range between about 10nm and about 100nm, a range between about 20nm and about 80nm, or other similar values.
Fig. 7 illustrates a cross-sectional view of some additional embodiments of an integrated chip structure 700 including a memory array having local interconnects configured to reduce resistance of bit lines.
The integrated chip structure 700 includes an embedded memory region 124 and a peripheral region 136. A memory array 102 comprising a plurality of memory devices 104 is disposed within a dielectric structure 126 within an embedded memory region 124. The local interconnect 116 is disposed within the dielectric structure 126 and is coupled to the plurality of memory devices 104. The local interconnects 116 are vertically arranged between the plurality of memory devices 104 and the bit lines 110. The local interconnects 116 include a bottom surface that continuously extends laterally across the plurality of memory devices 104.
The local interconnect 116 is coupled to the overlying bit line 110 by a plurality of interconnect vias 130. The plurality of interconnect vias 130 have bottom surfaces that physically contact the local interconnects 116 and top surfaces that physically contact the bit lines 110. In some embodiments, the local interconnects 116 extend continuously from within the embedded memory region 124 into the peripheral region 136. In some such embodiments, the plurality of interconnect vias 130 may also extend from within the embedded memory region 124 to a non-zero distance 702 within the peripheral region 136. By extending a non-zero distance 702 within the embedded memory region 124, the local interconnect 116 can further reduce the resistance of the bit line 110.
Fig. 8 illustrates a cross-sectional view of some additional embodiments of an integrated chip structure 800 including a memory array having local interconnects configured to reduce resistance of bit lines.
The integrated chip structure 800 includes an embedded memory region 124 and a peripheral region 136. The memory array 102 is disposed within an embedded memory region 124. Memory array 102 includes a plurality of memory devices 104 disposed within a dielectric structure 126 over a substrate 122. The local interconnects 116 are disposed within the dielectric structure 126 and are coupled to the plurality of memory devices 104. The local interconnect 116 is vertically disposed between the substrate 122 and the bit line 110.
The local interconnect 116 is coupled to the overlying bit line 110 by a plurality of interconnect vias 130, an additional interconnect wiring 802, and a plurality of additional upper interconnect vias 306. Additional interconnect routing 802 is coupled to both the local interconnect 116 and the bit line 110 and extends parallel to both the local interconnect 116 and the bit line 110. The plurality of interconnect vias 130 have bottom surfaces that physically contact the local interconnects 116. The additional interconnect wiring 802 has a bottom surface that physically contacts a top surface of the plurality of interconnect vias 130 and a top surface that physically contacts the plurality of additional upper interconnect vias 306. A plurality of additional upper interconnect vias 306 couple the additional interconnect wiring 802 to the bit lines 110.
Figure 9A illustrates a schematic diagram 900 of some embodiments of an integrated chip structure including a memory array having local interconnects configured to reduce resistance of bit lines.
As shown in schematic diagram 900, an integrated chip structure includes a memory array 102, the memory array 102 including a plurality of memory cells 103 arranged in rows and/or columns. The plurality of memory cells 103 includes a plurality of memory devices 104 and a plurality of access devices 106, the plurality of access devices 106 configured to control access to the plurality of memory devices 104. A first plurality of memory devices 104 within a row each have an access device 106 operatively coupled to one of a plurality of word lines 108a-108 n. A second plurality of memory devices 104 within a column is operatively coupled to one of the plurality of bit lines 110a-110 n. A third plurality of memory devices 104 within a column is operatively coupled to one of a plurality of additional bit lines 902a-902 n. In some embodiments, the plurality of memory devices 104 within a column are further coupled to one of a plurality of source lines 112a-112 n.
The plurality of local interconnects 116a-116n are coupled to the plurality of bit lines 110a-110n and the second plurality of memory devices 104 within a column of the memory array 102, respectively. The plurality of local interconnects 116a-116n extend parallel to the plurality of bit lines 110a-110 n. An additional plurality of local interconnects 904a-904n is also coupled to the plurality of additional bit lines 902a-902n, respectively, and a third plurality of memory devices 104 within a column of the memory array 102.
The plurality of word lines 108a-108n, the plurality of bit lines 110a-110n, and the plurality of additional bit lines 902a-902n are coupled to the control circuit 114. In some embodiments, the control circuit 114 includes a word line decoder 402 coupled to the plurality of word lines 108a-108n, a bit line decoder 404 coupled to the plurality of bit lines 110a-110n, and an additional bit line decoder 906 coupled to a plurality of additional bit lines 902a-902 n. In some such embodiments, the bit line decoder 404 is configured to provide signals to the plurality of bit lines 110a-110n during an access operation, and the additional bit line decoder 906 is configured to provide additional signals to the plurality of additional bit lines 902a-902n during an additional access operation. In some alternative embodiments (not shown), the control circuit 114 may include a bit line decoder 404 coupled to both the plurality of bit lines 110a-110n and the plurality of additional bit lines 902a-902 n. In some such embodiments, the bit line decoder 404 is configured to provide signals to both the plurality of bit lines 110a-110n and the plurality of additional bit lines 902a-902n during an access operation.
By having multiple memory devices 104 within a column of the memory array 102 coupled to both the bit line 110a and the additional bit line 902a, the distance spanned by the bit line 110a and the additional bit line 902a can be reduced, thereby reducing the resistance of the bit line 110a and the additional bit line 902 a. Further, by having the bit line 110a and the additional bit line 902a coupled to the local interconnect 116a and the additional local interconnect 904a, respectively, the resistance of the bit line 110a and the additional bit line 902a may be further reduced.
FIG. 9B illustrates a cross-sectional view of some additional embodiments of an integrated chip structure 910 corresponding to portion 908 of the diagram 900 shown in FIG. 9A.
The integrated chip structure 910 includes an embedded memory region 124 and a peripheral region 136. The memory array 102 is disposed within the embedded memory region 124. Memory array 102 includes a plurality of memory devices 104 disposed within a dielectric structure 126 over a substrate 122.
The local interconnects 116 are disposed within the dielectric structure 126 and coupled to the second plurality of memory devices 104. The local interconnects 116 are vertically arranged between the second plurality of memory devices 104 and the bit lines 110. The local interconnects 116 include bottom surfaces that continuously extend laterally across the second plurality of memory devices 104. Additional local interconnects 904 are disposed within the dielectric structure 126 and coupled to the third plurality of memory devices 104. The additional local interconnects 904 are vertically arranged between the third plurality of memory devices 104 and the additional bit lines 902. The additional local interconnects 904 include bottom surfaces that continuously extend laterally across the third plurality of memory devices 104.
In some embodiments, the additional local interconnects 904 are coupled to the additional common electrode 916 by a plurality of additional local interconnect vias 918. In some embodiments, the additional common electrode 916 physically contacts the third plurality of memory devices 104. The additional local interconnect 904 is further coupled to the additional bit line 902 by a plurality of additional interconnect vias 920, a plurality of additional interconnect islands 922 over the plurality of additional interconnect vias 920, and a second plurality of additional upper interconnect vias 924 over the plurality of additional interconnect islands 922.
The local interconnects 116 include ends that are laterally separated from the ends of the additional local interconnects 904 by a first non-zero distance 912, the first non-zero distance 912 being located between the second plurality of memory devices 104 and the third plurality of memory devices 104. The bit line 110 also includes an end portion laterally separated from an end portion of the additional bit line 902 by a second non-zero distance 914. In some embodiments, the first non-zero distance 912 may be approximately equal to the second non-zero distance 914. In other embodiments, the first non-zero distance 912 and the second non-zero distance 914 may be different. The separation between the local interconnects and the bit lines reduces the length of the local interconnects and the bit lines, thereby reducing the resistance of the bit lines, further improving the performance of the integrated chip structure 910.
Fig. 10-29 illustrate cross-sectional views 1000-2900 showing some embodiments of methods of forming integrated chip structures including memory arrays having local interconnects configured to reduce resistance of bit lines. Although fig. 10-29 are described with respect to a method, it should be understood that the structures disclosed in fig. 10-29 are not limited to such a method, but may exist independently as a structure independent of the method.
As shown in cross-sectional view 1000 of fig. 10, a substrate 122 is provided. In various embodiments, the substrate 122 may be any type of semiconductor body (e.g., silicon, siGe, SOI, etc.), such as a semiconductor wafer and/or one or more dies on a wafer, as well as any other type of semiconductor and/or epitaxial layers associated therewith. In some embodiments, the substrate 122 may include one or more dielectric layers, one or more interlayer dielectric (ILD) layers, and/or one or more interconnect layers disposed over the semiconductor body. In some embodiments, the substrate 122 may include an embedded memory region 124 and a peripheral region 136.
In some embodiments, access device 106 is formed on substrate 122 and within embedded memory region 124. In some embodiments, transistor device 138 is formed on substrate 122 and within peripheral region 136. In some embodiments, the access device 106 may include a gate structure 106c formed over the substrate 122. In such embodiments, the gate structure 106c may be formed by depositing a gate dielectric over the substrate 122 and depositing a gate electrode over the gate dielectric. The gate electrode and gate dielectric are then patterned to form a gate structure 106c. The source region 106a and the drain region 106b may be formed in the substrate 122 on opposite sides of the gate structure 106c by an implantation process. In some embodiments, the access device 106 may be formed within an active area defined by one or more isolation structures (e.g., shallow Trench Isolation (STI) structures) disposed within the substrate 122.
As shown in cross-sectional view 1100 of fig. 11, a plurality of lower interconnects 128 are formed within a lower ILD structure 126L formed on substrate 122. In some embodiments, the plurality of lower interconnects 128 may be formed using a damascene process (e.g., a single damascene process or a dual damascene process). The damascene process is performed by forming an ILD layer over the substrate 122, etching the ILD layer to form vias and/or trenches, and filling the vias and/or trenches with a conductive material. In some embodiments, the ILD layer may comprise USG, BPSG, FSG, PSG, BSG, etc., formed by deposition techniques (e.g., PVD, CVD, PE-CVD, ALD, etc.). The conductive material may include tungsten, copper, aluminum, copper, etc., formed using a deposition process and/or a plating process (e.g., electroplating, electroless plating, etc.).
An intermediate lower insulating structure 1102 is formed over one or more lower interconnects 128 and/or lower ILD structures 126L. In some embodiments, the intermediate underlying insulating structure 1102 comprises one or more of a silicon-rich oxide, silicon carbide, silicon nitride, and the like. In some embodiments, the intermediate lower insulating structure 1102 may be formed by one or more deposition processes (e.g., a Physical Vapor Deposition (PVD) process, a Chemical Vapor Deposition (CVD) process, a plasma-enhanced CVD (PE-CVD) process, etc.).
As shown in cross-sectional view 1200 of fig. 12, bottom electrode via 204 is formed within intermediate lower insulating structure 1102. In some embodiments, the bottom electrode via 204 may be formed by selectively etching the intermediate lower insulating layer forming structure 1102 to form an opening 1202 extending through the intermediate lower insulating structure 1102 to expose an upper surface of the one or more lower interconnects 128. In some embodiments, the openings 1202 may then be filled with a conductive material to form the bottom electrode vias 204 that extend through the intermediate lower insulating structure 1102. In some embodiments, the bottom electrode via 204 may include a diffusion barrier layer 514 and a conductive core 512 formed over the diffusion barrier layer 514. In some embodiments, the diffusion barrier layer 514 may include one or more of a metal, a metal nitride, and/or the like. In some embodiments, the conductive core 512 may include tungsten, tantalum nitride, titanium nitride, ruthenium, platinum, iridium, and the like. In some embodiments, the diffusion barrier layer 514 and the conductive core 512 may be formed by a deposition process (e.g., a PVD process, a CVD process, a PE-CVD process, etc.). In some embodiments, a planarization process 1204 (e.g., a Chemical Mechanical Planarization (CMP) process) is performed to remove excess diffusion barrier 514 and conductive core 512 from over the intermediate underlying insulating structure 1102.
As shown in cross-sectional view 1300 of fig. 13, bottom electrode structure 1302 is formed over intermediate lower insulating structure 1102, and memory device stack 1303 is formed over bottom electrode structure 1302. In some embodiments, the bottom electrode structure 1302 can include a metal such as tantalum, titanium, tantalum nitride, titanium nitride, platinum, nickel, hafnium, zirconium, ruthenium, iridium, and the like. In some embodiments, memory device stack 1303 may include a pinning layer 1304 formed over bottom electrode structure 1302, a dielectric barrier tunnel layer 1306 formed over pinning layer 1304, and a free layer 1308 formed over dielectric barrier tunnel layer 1306. In other embodiments (not shown), the free layer 1308 may be formed over the bottom electrode structure 1302, the dielectric barrier tunnel layer 1306 is formed over the free layer 1308, and the pinned layer 1304 may be formed over the dielectric barrier tunnel layer 1306.
As shown in cross-sectional view 1400 of fig. 14, top electrode structure 1402 is formed over memory device stack 1303. In some embodiments, the top electrode structure 1402 may include a metal such as tantalum, titanium, tantalum nitride, titanium nitride, platinum, nickel, hafnium, zirconium, ruthenium, iridium, and the like. In some embodiments, the top electrode structure 1402 may be formed by one or more deposition processes (e.g., PVD processes, CVD processes, PE-CVD processes, etc.).
As shown in cross-sectional view 1500 of fig. 15, the top electrode structure (e.g., 1402 of fig. 14) is selectively patterned to define the top electrode 104c. In some embodiments, the top electrode structure may be selectively patterned by exposing the top electrode structure to an etchant 1502 according to a mask layer 1504 (e.g., silicon nitride, silicon carbide, etc.).
As shown in cross-sectional view 1600 of fig. 16, the memory device stack (e.g., 1303 of fig. 15) and the bottom electrode structure (e.g., 1302 of fig. 15) are selectively patterned to define a memory device 104 having a data storage structure 104b disposed between a bottom electrode 104a and a top electrode 104c. In some embodiments, the memory device stack can be selectively etched according to the mask layer (1504 of fig. 15) and/or the top electrode 104c to define the data storage structure 104b and the bottom electrode 104a.
In some embodiments, the intermediate lower insulating structure (1102 of fig. 15) may also be etched to define the lower insulating structure 202. The lower insulating structure 202 includes a first lower insulating layer 501, a second lower insulating layer 502 over the first lower insulating layer 501, and a third lower insulating layer 504 over the second lower insulating layer 502. In some embodiments, a second lower insulating layer 502 and a third lower insulating layer 504 may be defined within the embedded memory region 124.
As shown in cross-sectional view 1700 of fig. 17, a first sidewall spacer layer 506 is formed along the sidewalls of the memory device 104. In some embodiments, the first sidewall spacer layer 506 may comprise a first dielectric material, such as silicon nitride, silicon oxide, and the like. In some embodiments, the first dielectric material may be deposited using a deposition process (e.g., a PVD process, a CVD process, a PE-CVD process, etc.). An etching process (e.g., an anisotropic etching process) may then be performed to remove the horizontal portions of the first dielectric material. The first dielectric material may be formed to a thickness in a range between about 2nm and about 20nm, a range between about 4nm and about 10nm, or other similar values.
As shown in cross-section 1800 of fig. 18, an intermediate second sidewall spacer layer 1802 is located on the first sidewall spacer layer 506 and the top electrode 104c. In some embodiments, the intermediate second sidewall spacer layer 1802 may include a second dielectric material, such as a dielectric metal oxide, such as aluminum oxide, hafnium oxide, lanthanum oxide, or yttrium oxide. In some embodiments, the second dielectric material may be deposited using a deposition process (e.g., a PVD process, a CVD process, a PE-CVD process, etc.). The second dielectric material may be formed to a thickness in a range between about 2nm and about 20nm, a range between about 4nm and about 10nm, or other similar values. In one embodiment, the second dielectric material may be deposited directly on the sidewalls of the top electrode 104c.
As shown in cross-sectional view 1900 of fig. 19, dielectric seal structure 510 is formed over intermediate second sidewall spacer layer 1802. In some embodiments, the dielectric seal structure 510 may comprise silicon oxide, silicon nitride, or a dielectric metal oxide. In some embodiments, dielectric seal structure 510 may be formed by depositing a dielectric seal material (e.g., by a conformal deposition process such as an atomic layer deposition process or a chemical vapor deposition process) and then etching (e.g., anisotropically etching) the dielectric seal material to remove the dielectric seal material from peripheral region 136. In one embodiment, the top surface of the dielectric sealing structure 510 may be located on top of the top electrode 104c.
As shown in cross-sectional view 2000 of FIG. 20, first upper ILD layer 126U 1 Formed over dielectric seal structure 510. In some embodiments, first upper ILD layer 126U 1 May include USG, BPSG, FSG, PSG, BSG, etc. In some embodiments, first upper ILD layer 126U 1 May be formed by a deposition process (e.g., PVD, CVE, PE-CVD, ALD, etc.).
As shown in the cross-sectional view 2100 of fig. 21, one or more peripheral interconnects 140 are formed within the peripheral region 136. In some embodiments, the one or more peripheral interconnects 140 may be formed by a damascene process and/or a dual damascene process. In some such embodiments, the first upper ILD layer 126U is etched 1 To form holes and/or trenches that are subsequently filled with a conductive material (e.g., tungsten, copper, and/or aluminum). A planarization process 2102 (e.g., a CMP process) is then performed to planarize the first ILD layer 126U from the first upper ILD layer 1 Excess conductive material is removed above.
As shown in cross-sectional view 2200 of FIG. 22, a first dielectric stack 2201 is formed on the first upper ILD layer 126U 1 And (3) upward. In some embodiments, the first dielectric stack 2201 may include a first ILD layer 12 formed on the first upper ILD layer6U 1 An upper intermediate upper level etch stop dielectric layer 2202, an intermediate first dielectric matrix layer 2204 formed above the intermediate upper level etch stop dielectric layer 2202, and an intermediate second dielectric matrix layer 2206 formed above the intermediate first dielectric matrix layer 2204. In some embodiments, the intermediate upper level etch stop dielectric layer 2202 may comprise silicon nitride, silicon carbide, silicon carbonitride, aluminum nitride, metal oxides (such as aluminum oxide, titanium oxide, tantalum oxide, etc.), and the like formed by one or more deposition processes (e.g., PVD processes, CVD processes, PE-CVD processes, etc.). In some embodiments, the intermediate first dielectric matrix layer 2204 may comprise silicon nitride, silicon carbide, silicon carbonitride, aluminum nitride, metal oxides (e.g., aluminum oxide, titanium oxide, tantalum oxide, etc.), and the like, formed by one or more deposition processes (e.g., PVD processes, CVD processes, PE-CVD processes, etc.). In some embodiments, the intermediate second dielectric matrix layer 2206 can include TEOS, USG, BPSG, FSG, PSG, BSG, etc., formed by one or more deposition processes (e.g., PVD process, CVD process, PE-CVD process, etc.).
As shown in cross-sectional view 2300 of fig. 23, the intermediate upper level etch stop dielectric layer (2202 of fig. 22), the intermediate first dielectric matrix layer (2204 of fig. 22), and the intermediate second dielectric matrix layer (2206 of fig. 22) are selectively patterned to form an upper level etch stop dielectric layer 524, a first dielectric matrix layer 526, and a second dielectric matrix layer 528. The upper-level etch-stop dielectric layer 524, the first dielectric matrix layer 526, and the second dielectric matrix layer 528 respectively have sidewalls defining a common electrode opening 2302 that exposes an upper surface of the top electrode 104c within the plurality of memory devices 104.
As shown in the sectional view 2400 of fig. 24, the common electrode 522 is formed in the common electrode opening 2302.
In some embodiments, the common electrode 522 can be formed by depositing a conductive material (e.g., tungsten, copper, and/or aluminum) within the common electrode opening 2302. A planarization process 2102 (e.g., a chemical CMP process) is then performed to remove excess conductive material from over second dielectric matrix layer 528.
As shown in the cross-sectional view 2500 of fig. 25, an overlying level etch stop dielectric layer 530 is formed over the common electrode 522, and an upper level dielectric layer 532 is formed over the overlying level etch stop dielectric layer 530.
In some embodiments, the cap-level etch stop dielectric layer 530 may comprise silicon nitride, silicon carbide, silicon carbonitride, aluminum nitride, metal oxides (such as aluminum oxide, titanium oxide, tantalum oxide, etc.) formed by one or more deposition processes (e.g., PVD processes, CVD processes, PE-CVD processes, etc.). In some embodiments, the upper level dielectric layer 532 may include TEOS, USG, BPSG, FSG, PSG, BSG, etc., formed by one or more deposition processes (e.g., PVD processes, CVD processes, PE-CVD processes, etc.). In some embodiments, the capping-level etch stop dielectric layer 530 and the upper-level dielectric layer 532 may be formed to extend continuously from above the common electrode 522 into the peripheral region 136.
As shown in cross-sectional view 2600 of FIG. 26, a second upper ILD layer 126U 2 Formed over the upper level dielectric layer 532. In some embodiments, the second upper ILD layer 126U 2 May include TEOS, USG, BPSG, FSG, PSG, BSG, etc., formed by one or more deposition processes (e.g., PVD process, CVD process, PE-CVD process, etc.).
Selectively patterning the cap level etch stop dielectric 530, the upper level dielectric 532, and the second upper ILD layer 126U 2 To form a plurality of interconnect via openings 2602 and local interconnect openings 2604 exposing the upper surface of the common electrode 522. A plurality of local interconnect vias 2602 are defined by sidewalls of the overlying level etch stop dielectric 530 and the upper level dielectric 532, and local interconnect openings 2604 are defined by the second upper ILD layer 126U 2 Is defined by the side walls of (a). The local interconnect openings 2604 extend laterally through the plurality of interconnect via openings 2602 and through opposing edges of the plurality of memory devices 104.
As shown in cross-sectional view 2700 of fig. 27, a plurality of local interconnect vias 534 are formed within the plurality of local interconnect via openings 2602 and local interconnects 116 are formed within the local interconnect openings 2604. In an embodiment, the conductive material may be deposited by depositing within the plurality of local interconnect via openings 2602 and local interconnect openings 2604 (e.g., by vacuum deposition)Such as tungsten, copper, and/or aluminum) to form a plurality of local interconnect vias 534 and/or local interconnects 116. A planarization process 2702 (e.g., a CMP process) is then performed to remove the second ILD layer 126U from the second upper ILD layer 2 Excess conductive material is removed over.
The third upper ILD layer 126U is shown in cross-sectional view 2800 in FIG. 28 3 Formed on the second upper ILD layer 126U 2 And (4) upward. In some embodiments, third upper ILD layer 126U 3 May include TEOS, USG, BPSG, FSG, PSG, BSG, etc., formed by one or more deposition processes (e.g., PVD processes, CVD processes, PE-CVD processes, etc.). Selectively patterning the third upper ILD layer 126U 3 To form a plurality of interconnect via openings 2802 and bit line openings 2804 that expose the upper surface of the local interconnects 116. A plurality of interconnect via openings 2802 and bit line openings 2804 are formed from the third upper ILD layer 126U 3 Is defined by the side walls of (a).
As shown in cross-sectional view 2900 of fig. 29, a plurality of interconnect vias 130 are formed within a plurality of interconnect via openings 2802 and bit lines 110 are formed within bit line openings 2804. In some embodiments, the plurality of interconnect vias 130 and/or the bit lines 110 may be formed by depositing a conductive material (e.g., tungsten, copper, and/or aluminum) within the plurality of interconnect via openings 2802 and bit line openings 2804. A planarization process 2902 (e.g., CMP process) is then performed to planarize the third ILD layer 126U from the third upper ILD layer 3 Excess conductive material is removed over.
Figure 30 illustrates a flow diagram of some embodiments of a method 3000 of forming an integrated chip structure including a memory array having local interconnects configured to reduce resistance of bit lines.
While method 3000 is illustrated and described herein as a series of acts or events, it will be appreciated that the illustrated ordering of such acts or events are not to be interpreted in a limiting sense. For example, some acts may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described herein. Moreover, not all illustrated acts may be required to implement one or more aspects or embodiments described herein. Further, one or more of the acts described herein may be performed in one or more separate acts and/or phases.
At act 3002, a plurality of memory devices are formed within a memory array disposed above a substrate. Fig. 13-21 illustrate cross-sectional views 1300-2100 corresponding to some embodiments of action 3002.
At act 3004, a common electrode is formed on the plurality of memory devices. 22-24 illustrate cross-sectional views 2200-2400 of some embodiments corresponding to act 3004.
At act 3006, a plurality of local interconnect vias are formed on the common electrode. FIGS. 25-27 illustrate cross-sectional views 2500-2700 of some embodiments, corresponding to act 3006.
At act 3008, a local interconnect is formed over the plurality of local interconnect vias. FIGS. 25-27 illustrate cross-sectional views 2500-2700 of some embodiments corresponding to act 3008.
At act 3010, a plurality of interconnect vias are formed over the local interconnect. 28-29 illustrate cross-sectional views 2800-2900 of some embodiments corresponding to act 3010.
At act 3012, bit lines extending laterally past opposing ends of the local interconnects are formed over and in electrical contact with the plurality of interconnect vias. 28-29 illustrate cross-sectional views 2800-2900 of some embodiments corresponding to act 3012.
Accordingly, in some embodiments, the present disclosure is directed to an integrated chip structure including a memory array having local interconnects configured to reduce resistance of bit lines within the memory array.
In some embodiments, the present disclosure relates to integrated chip structures. The integrated chip structure includes: a memory array comprising a plurality of memory devices arranged in a plurality of rows and a plurality of columns; a word line coupled to a first group of the plurality of memory devices disposed within a first row of the plurality of rows; a bit line coupled to a second group of the plurality of memory devices disposed within a first column of the plurality of columns; a local interconnect extending parallel to the bit line and coupled to the bit line and to two or more memory devices of the second group of the plurality of memory devices, wherein the local interconnect is coupled to the bit line through a plurality of interconnect vias located between the local interconnect and the bit line. In some embodiments, the local interconnect is vertically between two or more memory devices in the second group of the plurality of memory devices and the bit line. In some embodiments, the local interconnect extends laterally continuously past the outermost edges of the two or more memory devices in the second group of the plurality of memory devices. In some embodiments, the local interconnect extends continuously laterally across the plurality of interconnect vias. In some embodiments, bit lines extend laterally past opposite ends of the local interconnects. In some embodiments, the integrated chip architecture further includes a bit line decoder coupled to the bit lines and configured to selectively apply signals to the bit lines during an access operation. In some embodiments, the integrated chip structure further comprises: an additional bit line coupled to a third group of the plurality of memory devices disposed within a first column of the plurality of columns, wherein an end of the bit line is separated from an end of the additional bit line by a non-zero distance; and an additional local interconnect extending parallel to the additional bit line, wherein the additional local interconnect is coupled between the additional bit line and two or more memory devices in a third group of the plurality of memory devices. In some embodiments, the integrated chip structure further comprises: a bit line decoder coupled to the bit line, wherein the bit line decoder is configured to selectively apply a signal to the bit line during an access operation; and an additional bit line decoder coupled to the additional bit line, wherein the additional bit line decoder is configured to selectively apply an additional signal to the additional bit line during an additional access operation. In some embodiments, the integrated chip structure further comprises a common electrode disposed between the local interconnect and two or more memory devices of the second group of the plurality of memory devices, wherein the local interconnect is coupled to the common electrode through the plurality of local interconnect vias.
In other embodiments, the present disclosure relates to integrated chip structures. The integrated chip structure includes: a memory array comprising a plurality of memory devices arranged within a dielectric structure over a substrate in a cross-sectional view; bit lines disposed over the plurality of memory devices; a local interconnect extending parallel to a bit line and coupled to the plurality of memory devices, the bit line extending laterally past opposite ends of the local interconnect; the local interconnect is coupled to the bit line through a plurality of interconnect vias disposed between a top of the local interconnect and a bottom of the bit line. In some embodiments, the plurality of interconnect vias extend laterally through two or more of the plurality of memory devices. In some embodiments, the integrated chip structure further comprises a common electrode disposed between the local interconnect and the plurality of memory devices and extending continuously past an outermost edge of the plurality of memory devices, wherein the local interconnect is coupled to the common electrode by a plurality of local interconnect vias. In some embodiments, the local interconnects extend laterally past opposite ends of the common electrode. In some embodiments, the integrated chip structure further comprises: an upper interlayer dielectric structure laterally surrounding the bit line; and a peripheral interconnect via extending vertically through the upper interlayer dielectric structure outside the memory array, wherein the peripheral interconnect via extends vertically through the common electrode and the plurality of local interconnect vias. In some embodiments, the plurality of memory devices each include a Magnetic Tunnel Junction (MTJ) disposed between a bottom electrode and a top electrode. In some embodiments, the integrated chip structure further comprises: a plurality of interconnection islands contacting upper surfaces of the plurality of interconnection vias; and a plurality of additional upper interconnect vias contacting upper surfaces of the plurality of interconnect islands and lower surfaces of the bit lines. In some embodiments, the memory array includes one or more additional memory devices disposed laterally outward of the local interconnect in the cross-sectional view. In some embodiments, the integrated chip structure further includes a transistor device disposed within a peripheral region of the substrate, the peripheral region surrounding an embedded memory region of the substrate including the plurality of memory devices, wherein the bit line extends into the peripheral region of the substrate, and the local interconnect is defined within the embedded memory region of the substrate.
In yet another embodiment, the present disclosure is directed to a method for forming an integrated chip structure. The method comprises the following steps: forming a plurality of memory devices over a substrate; forming a first upper interlayer dielectric layer over the plurality of memory devices; patterning the first upper interlayer dielectric layer to form local interconnect openings extending laterally past opposing edges of the plurality of memory devices; forming a local interconnect within the local interconnect opening; forming a plurality of interconnect vias in a second upper interlevel dielectric layer located above the first upper interlevel dielectric layer; bit lines are formed over a plurality of interconnect vias, wherein the plurality of interconnect vias connect the local interconnects to the bit lines. In some embodiments, the method further comprises: forming a first dielectric stack over a plurality of memory devices; patterning the first dielectric stack to form a common electrode opening exposing tops of the plurality of memory devices; a common electrode is formed in the common electrode opening.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims (10)

1. An integrated chip structure, comprising:
a memory array comprising a plurality of memory devices arranged in a plurality of rows and a plurality of columns;
a word line coupled to a first group of the plurality of memory devices disposed within a first row of the plurality of rows;
a bit line coupled to a second group of the plurality of memory devices disposed within a first column of the plurality of columns; and
a local interconnect extending parallel to the bit line and coupled to the bit line and two or more memory devices of the second group of the plurality of memory devices, wherein the local interconnect is coupled to the bit line through a plurality of interconnect vias located between the local interconnect and the bit line.
2. The integrated chip structure of claim 1, wherein the local interconnect is vertically located between two or more memory devices in the second group of the plurality of memory devices and the bit line.
3. The integrated chip structure of claim 1, wherein the local interconnect extends laterally continuously past outermost edges of two or more memory devices of the second group of the plurality of memory devices.
4. The integrated chip structure of claim 1, wherein the local interconnect extends laterally continuously through the plurality of interconnect vias.
5. The integrated chip structure of claim 1, wherein the bit lines extend laterally past opposite ends of the local interconnects.
6. The integrated chip structure of claim 1, further comprising:
a bit line decoder coupled to the bit line and configured to selectively apply a signal to the bit line during an access operation.
7. The integrated chip structure of claim 1, further comprising:
an additional bit line coupled to a third group of the plurality of memory devices disposed within the first column of the plurality of columns, wherein an end of the bit line is separated from an end of the additional bit line by a non-zero distance; and
an additional local interconnect extending parallel to the additional bit line, wherein the additional local interconnect is coupled between the additional bit line and two or more memory devices of the third group of the plurality of memory devices.
8. The integrated chip structure of claim 7, further comprising:
a bit line decoder coupled to the bit line, wherein the bit line decoder is configured to selectively apply a signal to the bit line during an access operation; and
an additional bit line decoder coupled to the additional bit line, wherein the additional bit line decoder is configured to selectively apply an additional signal to the additional bit line during an additional access operation.
9. An integrated chip structure, comprising:
a memory array comprising a plurality of memory devices arranged within a dielectric structure over a substrate in a cross-sectional view;
bit lines disposed over the plurality of memory devices;
a local interconnect extending parallel to the bit lines and coupled to the plurality of memory devices, the bit lines extending laterally past opposite ends of the local interconnect; and
wherein the local interconnect is coupled to the bit line through a plurality of interconnect vias disposed between a top of the local interconnect and a bottom of the bit line.
10. A method of forming an integrated chip structure, comprising:
forming a plurality of memory devices over a substrate;
forming a first upper interlayer dielectric layer over the plurality of memory devices;
patterning the first upper interlayer dielectric layer to form local interconnect openings extending laterally past opposing edges of the plurality of memory devices;
forming a local interconnect within the local interconnect opening;
forming a plurality of interconnect vias within a second upper interlevel dielectric layer located above the first upper interlevel dielectric layer; and
forming a bit line over the plurality of interconnect vias, wherein the plurality of interconnect vias connect the local interconnect to the bit line.
CN202210683828.6A 2021-11-16 2022-06-16 Integrated chip structure and forming method thereof Pending CN115802761A (en)

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US17/690,728 US20230157032A1 (en) 2021-11-16 2022-03-09 Bit-line resistance reduction
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