CN115801710B - CPU interface expansion method, device, equipment and storage medium - Google Patents
CPU interface expansion method, device, equipment and storage medium Download PDFInfo
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Abstract
The application discloses a method, a device, equipment and a storage medium for expanding a CPU interface, wherein the method comprises the following steps: expanding the CPU interface of the network equipment through a plurality of cascaded exchange chips to obtain an expanded exchange chip interface and an expansion interface led out by each exchange chip; setting the expanded exchange chip interface as a DSA mode and setting the expanded interface as a common mode; configuring the expanded exchange chip interface; based on DSA mode and interface configuration, message forwarding is carried out between the extended exchange chip interfaces by using DSA labels. According to the method and the device, a series of operations such as vlan division, encapsulation and stripping are completed without changing a hardware driving code, meanwhile, the DSA label is used, forwarding of messages among the exchange chips can be completed very conveniently and rapidly, and a complicated mode of encapsulating multiple layers of labels under the multistage exchange chips is avoided.
Description
Technical Field
The present disclosure relates to the field of interface expansion technologies, and in particular, to a method, an apparatus, a device, and a storage medium for expanding a CPU interface.
Background
With the wide application of switch devices, multi-stage switch device interconnection is more and more popular, and a message is forwarded among a plurality of switches in cascade, and needs to be guided by forwarding labels.
At present, the expansion of the CPU interface inside the device usually adopts a traditional vlan (virtual local area network) label division mode.
However, in the conventional vlan tag packaging method, when the multi-level switch chip is expanded, the multi-level vlan tag needs to be sealed, and a hardware driving code needs to be changed to complete a series of complicated operations such as vlan division, packaging, stripping and the like, so that great inconvenience is brought to the CPU processing.
Disclosure of Invention
The main purpose of the application is to provide an expansion method, a device, equipment and a storage medium of a CPU interface, which aims at completing forwarding and processing of messages among exchange chips very conveniently and rapidly without changing hardware driving codes, and avoids the complicated mode of packaging multi-layer labels under multi-stage exchange chips.
In order to achieve the above object, the present application provides an extension method of a CPU interface, which is applied to a network device, and the method includes the following steps:
expanding the CPU interface of the network equipment through a plurality of cascaded exchange chips to obtain an expanded exchange chip interface and an expansion interface led out by each exchange chip;
setting the expanded exchange chip interface to be in a DSA mode, and setting the expanded interface to be in a common mode;
configuring the expanded exchange chip interface;
and based on the DSA mode and the interface configuration condition, forwarding the message between the extended exchange chip interfaces by using a DSA label.
Optionally, the extended exchange chip interface includes an upper interface of the exchange chip connected with the CPU interface, and a cascade interface connected with each other between the exchange chips; the step of configuring the extended switch chip interface includes:
setting a corresponding relation table Dev Map of the cascade port and the connected exchange chip;
and dividing vlan groups to which each interface belongs, wherein the cascade port and the upper connection port belong to all vlan groups.
Optionally, the step of setting the extended switch chip interface to DSA mode includes:
isolating the exchange chip corresponding to the extended exchange chip interface through a DSA label to divide an independent message channel;
and sealing different DSA labels on messages entering from different exchange chip interfaces.
Optionally, the step of using DSA tags to forward the message between the extended switch chip interfaces based on the DSA mode and the interface configuration condition includes:
after a message enters the exchange chip from a common physical interface, marking a DSA label on the message when passing through a first cascade port or an upper port, and marking source equipment information, source port information, destination equipment information and destination port information of an input interface of the message;
and when the message is forwarded, searching the corresponding relation table Dev Map according to the destination equipment information stored in the DSA label to obtain a cascade output port.
Optionally, the step of using DSA tags to forward the message between the extended switch chip interfaces based on the DSA mode and the interface configuration condition further includes:
if the directly forwarded cascade port is not found, broadcasting to the next exchange chip in the vlan group to continue the search until the directly forwarded cascade port is found.
Optionally, the step of using DSA tags to forward the message between the extended switch chip interfaces based on the DSA mode and the interface configuration condition further includes:
when the message is detected to be sent out from the expansion interface, judging that the interface type is in a non-DSA mode, and stripping the DSA label on the message and then sending the message.
Optionally, the step of using DSA tags to forward the message between the extended switch chip interfaces based on the DSA mode and the interface configuration condition further includes:
and uniformly sending the messages sent by the exchange chip interface into a CPU interface for processing in a parity distribution or hash mode.
The embodiment of the application also provides an expansion device of the CPU interface, which comprises:
the expansion module is used for expanding the CPU interface of the network equipment through a plurality of cascaded exchange chips to obtain an expanded exchange chip interface and an expansion interface led out by each exchange chip;
the setting module is used for setting the expanded exchange chip interface to be in a DSA mode and setting the expanded interface to be in a common mode;
the configuration module is used for configuring the expanded exchange chip interface;
and the message forwarding module is used for forwarding the message between the extended exchange chip interfaces by using a DSA label based on the DSA mode and the interface configuration condition.
The embodiment of the application also provides a network device, which comprises: the network equipment comprises a memory, a processor and an expansion program of the CPU interface, wherein the expansion program of the CPU interface is stored in the memory and can run on the processor, and the expansion method of the CPU interface is realized when the expansion program of the CPU interface is executed by the processor.
The embodiment of the application also provides a computer readable storage medium, wherein the computer readable storage medium is stored with a computer readable program, and the computer readable program realizes the expansion method of the CPU interface when being executed by a processor.
The CPU interface of the network equipment is expanded through a plurality of cascaded exchange chips, so that an expanded exchange chip interface and an expansion interface led out by each exchange chip are obtained, wherein the expanded exchange chip interface comprises an upper connecting port of the exchange chip connected with the CPU interface and a cascade interface connected with each exchange chip; setting the expanded exchange chip interface to be in a DSA mode, and setting the expanded interface to be in a common mode; configuring the expanded exchange chip interface; and based on the DSA mode and the interface configuration condition, forwarding the message between the extended exchange chip interfaces by using a DSA label. The application applies the DSA technology to the expansion of the multistage exchange chip under the CPU interface of the single firewall equipment, namely, the DSA technology is used between the expanded exchange chip interfaces to realize the interface expansion. By means of the scheme, the traditional vlan tag division mode is not adopted for the expansion of the CPU interface in the device, and DSA tags are adopted for guiding forwarding. The cascade port and the upper port are set to be in a DSA mode, and the extension port is set to be in a common mode, so that the DSA label can be ensured to exist in the network equipment only. Compared with the traditional vlan tag packaging mode, the vlan tag packaging method has the advantages that a series of operations such as vlan division, packaging and stripping are completed without changing a hardware driving code, meanwhile, the DSA tag is used, the complicated mode of packaging multiple layers of tags under a multi-level exchange chip is avoided, and only one layer of DSA tag is used.
Compared with the prior art, the scheme has the following advantages:
1. when in multi-stage expansion, a plurality of layers of vlan tag labels are not required to be sealed, only one layer of DSA label is required, and great convenience is brought to CPU processing.
2. The DSA mode can be realized by configuring the register of the exchange chip, and operations such as vlan tag division, sealing and stripping are not required to be added by hardware driving.
3. On the exchange chip supporting the DSA technology, the method can very conveniently complete the forwarding of the message among the exchange chips.
Drawings
FIG. 1 is a schematic diagram of a functional module of a terminal device to which an expansion device of a CPU interface of the present application belongs;
FIG. 2 is a diagram of a large multi-stage switching network architecture according to an embodiment of the present application;
FIG. 3 is a schematic diagram of a multi-level expansion architecture of a CPU interface according to an embodiment of the present application;
fig. 4 is a flowchart of an exemplary embodiment of a method for expanding a CPU interface of the present application.
The realization, functional characteristics and advantages of the present application will be further described with reference to the embodiments, referring to the attached drawings.
Detailed Description
It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the present application.
The main solutions of the embodiments of the present application are: expanding CPU interfaces of network equipment through a plurality of cascaded exchange chips to obtain expanded exchange chip interfaces and expansion interfaces led out by each exchange chip, wherein the expanded exchange chip interfaces comprise upper interfaces of the exchange chips connected with the CPU interfaces and cascade interfaces connected with each other; setting the expanded exchange chip interface to be in a DSA mode, and setting the expanded interface to be in a common mode; configuring the expanded exchange chip interface; and based on the DSA mode and the interface configuration condition, forwarding the message between the extended exchange chip interfaces by using a DSA label. The application applies the DSA technology to the expansion of the multistage exchange chip under the CPU interface of the single firewall equipment, namely, the DSA technology is used between the expanded exchange chip interfaces to realize the interface expansion. By means of the scheme, the traditional vlan tag division mode is not adopted for the expansion of the CPU interface in the device, and DSA tags are adopted for guiding forwarding. The cascade port and the upper port are set to be in a DSA mode, and the extension port is set to be in a common mode, so that the DSA label can be ensured to exist in the network equipment only. Compared with the traditional vlan tag packaging mode, the vlan tag packaging method has the advantages that a series of operations such as vlan division, packaging, stripping and the like do not need to be completed by changing a hardware driving code, meanwhile, the DSA tag is used, the complicated mode of packaging multiple layers of tags under a multi-stage switching chip is avoided, and forwarding and processing of messages among the switching chips can be completed very conveniently and rapidly only by using one layer of DSA tag.
Technical terms related to embodiments of the present application:
DSA, distributed Switch Architecture, a distributed switch architecture, is a Linux kernel subsystem for network switches. It is an upstream substitute for the swconfig framework of OpenWrt, and many new routers use DSA drivers instead of swconfig drivers.
In DSA, each switch port is a separate Linux interface. This means that the ip/ifconfig command will display interfaces etc. lan1, lan2, wan etc.
DSA switch ports can be used as stand-alone interfaces (common solutions for WANs) or bridging can be done using Linux bridging interfaces. In the latter case, the switch is still able to route traffic at the hardware level and therefore does not affect performance.
VLAN, virtual Local Area Network, virtual local area network. A VLAN is a group of logical devices and users that are not limited by physical location, and may be organized according to functions, departments, etc., to communicate with each other as if they were in the same network segment. The virtual local area network has the advantages that the management overhead of the movement, addition and modification of the network equipment is reduced, the broadcasting activity can be controlled, and the security of the network can be improved.
Specifically, referring to fig. 1, fig. 1 is a schematic functional block diagram of a terminal device to which an extension device of a CPU interface of the present application belongs. The expansion device of the CPU interface is a device capable of carrying out data processing, and can be loaded on terminal equipment in a form of hardware or software, wherein the terminal equipment can be mobile terminals such as mobile phones and tablets, and can also be fixed terminals such as vehicle-mounted equipment and PCs.
In this embodiment, the terminal device to which the expansion device of the CPU interface belongs at least includes an output module 110, a processor 120, a memory 130, and a communication module 140.
The memory 130 stores therein an operating system and an extension program of the CPU interface; the output module 110 may be a display screen or the like. The communication module 140 may include a WIFI module, a mobile communication module, a bluetooth module, and the like, and communicates with an external device or a server through the communication module 140.
Wherein the extension program of the CPU interface in the memory 130, when executed by the processor, implements the steps of:
expanding the CPU interface of the network equipment through a plurality of cascaded exchange chips to obtain an expanded exchange chip interface and an expansion interface led out by each exchange chip;
setting the expanded exchange chip interface to be in a DSA mode, and setting the expanded interface to be in a common mode;
configuring the expanded exchange chip interface;
and based on the DSA mode and the interface configuration condition, forwarding the message between the extended exchange chip interfaces by using a DSA label.
Further, the extension program of the CPU interface in the memory 130 when executed by the processor further implements the steps of:
setting a corresponding relation table Dev Map of the cascade port and the connected exchange chip;
and dividing vlan groups to which each interface belongs, wherein the cascade port and the upper connection port belong to all vlan groups.
Further, the extension program of the CPU interface in the memory 130 when executed by the processor further implements the steps of:
isolating the exchange chip corresponding to the extended exchange chip interface through a DSA label to divide an independent message channel;
and sealing different DSA labels on messages entering from different exchange chip interfaces.
Further, the extension program of the CPU interface in the memory 130 when executed by the processor further implements the steps of:
after a message enters the exchange chip from a common physical interface, marking a DSA label on the message when passing through a first cascade port or an upper port, and marking source equipment information, source port information, destination equipment information and destination port information of an input interface of the message;
and when the message is forwarded, searching the corresponding relation table Dev Map according to the destination equipment information stored in the DSA label to obtain a cascade output port.
Further, the extension program of the CPU interface in the memory 130 when executed by the processor further implements the steps of:
if the directly forwarded cascade port is not found, broadcasting to the next exchange chip in the vlan group to continue the search until the directly forwarded cascade port is found.
Further, the extension program of the CPU interface in the memory 130 when executed by the processor further implements the steps of:
when the message is detected to be sent out from the expansion interface, judging that the interface type is in a non-DSA mode, and stripping the DSA label on the message and then sending the message.
Further, the extension program of the CPU interface in the memory 130 when executed by the processor further implements the steps of:
and uniformly sending the messages sent by the exchange chip interface into a CPU interface for processing in a parity distribution or hash mode.
According to the scheme, the CPU interface of the network equipment is expanded through the plurality of cascaded exchange chips to obtain an expanded exchange chip interface and an expansion interface led out by each exchange chip, wherein the expanded exchange chip interface comprises an upper connecting port of the exchange chip connected with the CPU interface and a cascade interface connected with each other between each exchange chip; setting the expanded exchange chip interface to be in a DSA mode, and setting the expanded interface to be in a common mode; configuring the expanded exchange chip interface; and based on the DSA mode and the interface configuration condition, forwarding the message between the extended exchange chip interfaces by using a DSA label. The application applies the DSA technology to the expansion of the multistage exchange chip under the CPU interface of the single firewall equipment, namely, the DSA technology is used between the expanded exchange chip interfaces to realize the interface expansion. By means of the scheme, the traditional vlan tag division mode is not adopted for the expansion of the CPU interface in the device, and DSA tags are adopted for guiding forwarding. The cascade port and the upper port are set to be in a DSA mode, and the extension port is set to be in a common mode, so that the DSA label can be ensured to exist in the network equipment only. Compared with the traditional vlan tag packaging mode, the vlan tag packaging method has the advantages that a series of operations such as vlan division, packaging and stripping are completed without changing a hardware driving code, meanwhile, the DSA tag is used, the complicated mode of packaging multiple layers of tags under a multi-level exchange chip is avoided, and only one layer of DSA tag is used.
Based on the above terminal device architecture, but not limited to the above architecture, the method embodiments of the present application are presented.
In the embodiment of the application, the conventional vlan tag division mode is generally adopted for the expansion of the CPU interface in the equipment at present. However, in the conventional vlan tag packaging method, when the multi-level switch chip is expanded, the multi-level vlan tag needs to be sealed, and a hardware driving code needs to be changed to complete a series of complicated operations such as vlan division, packaging, stripping and the like, so that great inconvenience is brought to the CPU processing.
The solution is provided, the forwarding and processing of the message between the exchange chips can be very convenient and fast without changing the hardware driving code, and the complicated mode of packaging the multi-layer label under the multi-stage exchange chip is avoided.
Specifically, for the situation in the prior art, the Marvell DSA (distributed switching architecture) technology can be well applied to forwarding of multi-stage switching equipment, and forwarding and processing of messages among the switching equipment are accelerated.
As shown in fig. 2, the DSA technology forms a large-scale switching network by cascading a plurality of switching devices, and interfaces of adjacent devices are all configured as DSA mode cascading ports. When in DSA mode, a message is tagged with a DSA tag (similar to a VLAN tag) by the switch chip. The content in the DSA tag is dependent on the various configurations of the device and is thereafter forwarded with the DSA tag all the way to all possible ingress tandem devices. When a message is forwarded from the tandem interface to the network interface, the DSA tag is stripped off automatically.
The main information in DSA tags is: vlan-ID, souce ID (for marking the source of the message), trgDev (destination device), trgPort (destination port), srcDev (source device), srcPort (source port), etc. When each switching device forwards the message, the destination device and the destination interface can be found only according to the DSA label information of the message and forwarded to any point in the switching network, so that the forwarding of the message is accelerated to the greatest extent.
On the exchange chip supporting the DSA technology, the method can very conveniently complete the forwarding of the message among the exchange chips. Compared with the traditional vlan tag packaging mode, the vlan tag packaging method has the advantages that a series of operations such as vlan division, packaging and stripping are completed without changing a hardware driving code, meanwhile, the DSA tag is used, the complicated mode of packaging multiple layers of tags under a multi-level exchange chip is avoided, and only one layer of DSA tag is used.
The embodiment of the application provides a scheme based on a DSA technology, which is applied to multi-stage exchange chip expansion under a CPU interface of a single firewall device, namely, the DSA technology is used between the expanded exchange chip interfaces to realize interface expansion.
Specifically, referring to fig. 3, fig. 3 is a schematic diagram of a multi-level expansion architecture of a CPU interface according to an embodiment of the present application.
As shown in fig. 3, a basic hardware architecture of a network device through a switch chip expansion interface, where the network device according to the embodiment of the present application is a firewall device, where:
the interface of the forwarding chip CPU is connected with the exchange chip, more interfaces are divided by the exchange chip for use, and the multi-stage exchange chip can be used for expansion.
As shown in fig. 3, the network device includes: the CPU interface is used for expanding the CPU interface, and comprises a plurality of cascaded exchange chips, an upper connecting port, a cascading port and an expansion interface.
Taking the three-stage exchange chip shown in fig. 3 as an example, the cascade exchange chip includes: a first-level exchange chip, a second-level exchange chip and a third-level exchange chip.
The interface of the first-level exchange chip connecting with the CPU interface is an upper interface A, cascade interfaces B, B ', C, C' connected with each other between the exchange chips, for example, the cascade interfaces are sent from the second-level exchange chip to the third-level exchange chip, and the cascade outlet is C; otherwise, C'.
The expansion interface led out by each exchange chip and facing the outside is D, E, F, G.
Each exchange chip is isolated by a label to divide individual message channels: and sealing different labels on messages entering from different interfaces so as not to interfere with each other. And uniformly sending the messages sent by the exchange chip interface into the CPU interface for processing in a parity distribution or hash mode.
Referring to fig. 4, fig. 4 is a flowchart of a first exemplary embodiment of an extension method of a CPU interface of the present application. The expansion method of the CPU interface is applied to network equipment, and comprises the following steps:
step S101, expanding a CPU interface of network equipment through a plurality of cascaded exchange chips to obtain an expanded exchange chip interface and an expansion interface led out by each exchange chip;
the extended exchange chip interface comprises an upper interface of an exchange chip connected with the CPU interface and a cascade interface connected with each other among the exchange chips.
The scheme of the embodiment can be similar to cascading networking of switch equipment for multi-stage exchange chip expansion of CPU interfaces.
Taking the network device hardware architecture of the interface extended by the exchange chip as shown in fig. 3 as an example, the interface of the CPU is connected with the exchange chip, and more interfaces are divided by the exchange chip for use, so that the multi-stage exchange chip can be used for extension.
As shown in fig. 3, the cascade switching chip extended to the CPU interface includes: a first-level exchange chip, a second-level exchange chip and a third-level exchange chip.
The interface of the first-level exchange chip connecting with the CPU interface is an upper interface A, cascade interfaces B, B ', C, C' connected with each other between the exchange chips, for example, the cascade interfaces are sent from the second-level exchange chip to the third-level exchange chip, and the cascade outlet is C; otherwise, C'. The expansion interface led out by each exchange chip and facing the outside is D, E, F, G.
Step S102, setting the expanded exchange chip interface to be in a DSA mode and setting the expanded interface to be in a common mode;
the scheme of the embodiment is based on the DSA technology, and the DSA technology is applied to the expansion of the multistage exchange chip under the CPU interface of the single firewall equipment, namely, the DSA technology is used between the expanded exchange chip interfaces to realize the interface expansion. For this interface extension mode, the present embodiment proposes a scheme for forwarding using DSA tags.
Specifically, taking the network device hardware architecture through the exchange chip expansion interface as shown in fig. 3 as an example, a primary exchange chip on-chip interface a connected with the CPU interface is set to be in DSA mode; the cascade interfaces B, B ', C, C' interconnected between the switching chips are set to the DSA mode, i.e., the cascade interface B, B 'interconnected between the primary and secondary switching chips, and the cascade interface C, C' interconnected between the secondary and tertiary switching chips are set to the DSA mode.
Further, the expansion interface D, E, F, G facing the outside, which is led out from each of the switch chips, is set to the normal mode.
Therefore, the cascade port and the upper port are set to be in a DSA mode, and the expansion interface is set to be in a common mode, so that the DSA label is ensured to exist in the equipment only.
Step S103, configuring the expanded exchange chip interface;
specifically, as an implementation manner, the configuration of the extended switch chip interface may adopt the following scheme:
setting a cascade connection port and a connected exchange chip corresponding relation table Dev Map, for example, transmitting the Dev Map from a second-level exchange chip to a third-level exchange chip, wherein the cascade connection port is C; otherwise, C'.
The partition interfaces belong to vlan groups, and the cascade ports and the upper connection ports belong to all vlan groups.
Step S104, based on the DSA mode and the interface configuration condition, the DSA label is used for forwarding the message between the extended exchange chip interfaces.
In this embodiment, the extension of the CPU interface inside the device does not adopt the conventional vlan tag division manner any more, but adopts DSA tags to guide forwarding.
Specifically, the exchange chip corresponding to the extended exchange chip interface is isolated through a DSA label, and an independent message channel is divided; and sealing different DSA labels on messages entering from different exchange chip interfaces.
After a message enters the exchange chip from a common physical interface, when the message passes through a first cascade port or an upper port, a DSA label is marked on the message, and the number (source equipment information) of the exchange chip where the input interface of the message is located, the position (source port information) of the exchange chip where the interface is located, and the information of the destination equipment and the destination port are marked.
And when the message is forwarded, searching the corresponding relation table Dev Map according to the destination equipment information stored in the DSA label to obtain a cascade output port.
If the directly forwarded cascade port is not found, broadcasting to the next exchange chip in the vlan group to continue the search until the directly forwarded cascade port is found.
Further, when the message is detected to be sent out from the expansion interface, judging that the interface type is in a non-DSA mode, and sending the message after stripping a DSA label on the message.
Further, the messages sent by the switching chip interface are evenly sent to the CPU interface for processing in a parity distribution or hash mode.
Based on the above scheme, in this embodiment, the DSA technology forms a large-scale switching network from a plurality of switching devices through cascading, and interfaces of adjacent devices are all configured as DSA mode cascading ports. DSA mode when transmitting a message, the message is tagged with a DSA tag (similar to a VLAN tag) by the switch chip. The content in the DSA tag is dependent on the various configurations of the device and is thereafter forwarded with the DSA tag all the way to all possible ingress tandem devices. When a message is forwarded from the tandem interface to the network interface, the DSA tag is stripped off automatically.
The main information in DSA tags is: vlan-ID, souce ID (for marking the source of the message), trgDev (destination device), trgPort (destination port), srcDev (source device), srcPort (source port), etc. When each switching device forwards the message, the destination device and the destination interface can be found only according to the DSA label information of the message and forwarded to any point in the switching network, so that the forwarding of the message is accelerated to the greatest extent.
On the exchange chip supporting the DSA technology, the method of the embodiment can complete the forwarding of the message among the exchange chips very conveniently. Compared with the traditional vlan tag packaging mode, the vlan tag packaging method has the advantages that a series of operations such as vlan division, packaging and stripping are completed without changing a hardware driving code, meanwhile, the DSA tag is used, the complicated mode of packaging multiple layers of tags under a multi-level exchange chip is avoided, and only one layer of DSA tag is used.
According to the scheme, the CPU interface of the network equipment is expanded through the plurality of cascaded exchange chips to obtain an expanded exchange chip interface and an expansion interface led out by each exchange chip, wherein the expanded exchange chip interface comprises an upper connecting port of the exchange chip connected with the CPU interface and a cascade interface connected with each other between each exchange chip; setting the expanded exchange chip interface to be in a DSA mode, and setting the expanded interface to be in a common mode; configuring the expanded exchange chip interface; and based on the DSA mode and the interface configuration condition, forwarding the message between the extended exchange chip interfaces by using a DSA label. The application applies the DSA technology to the expansion of the multistage exchange chip under the CPU interface of the single firewall equipment, namely, the DSA technology is used between the expanded exchange chip interfaces to realize the interface expansion. By means of the scheme, the traditional vlan tag division mode is not adopted for the expansion of the CPU interface in the device, and DSA tags are adopted for guiding forwarding. The cascade port and the upper port are set to be in a DSA mode, and the extension port is set to be in a common mode, so that the DSA label can be ensured to exist in the network equipment only. Compared with the traditional vlan tag packaging mode, the vlan tag packaging method has the advantages that a series of operations such as vlan division, packaging and stripping are completed without changing a hardware driving code, meanwhile, the DSA tag is used, the complicated mode of packaging multiple layers of tags under a multi-level exchange chip is avoided, and only one layer of DSA tag is used.
In addition, the embodiment of the application also provides an expansion device of the CPU interface, which comprises:
the expansion module is used for expanding the CPU interface of the network equipment through a plurality of cascaded exchange chips to obtain an expanded exchange chip interface and an expansion interface led out by each exchange chip;
the setting module is used for setting the expanded exchange chip interface to be in a DSA mode and setting the expanded interface to be in a common mode;
the configuration module is used for configuring the expanded exchange chip interface;
and the message forwarding module is used for forwarding the message between the extended exchange chip interfaces by using a DSA label based on the DSA mode and the interface configuration condition.
The specific principle of the expansion of the CPU interface is realized in this embodiment, please refer to the above embodiments, and the description is omitted herein.
In addition, the embodiment of the application also provides a network device, which comprises: the network equipment comprises a memory, a processor and an expansion program of the CPU interface, wherein the expansion program of the CPU interface is stored in the memory and can run on the processor, and the expansion method of the CPU interface is realized when the expansion program of the CPU interface is executed by the processor.
Because the expansion program of the CPU interface is executed by the processor, all the technical solutions of all the foregoing embodiments are adopted, and therefore, at least all the beneficial effects brought by all the technical solutions of all the foregoing embodiments are not described in detail herein.
In addition, the embodiment of the application also provides a computer readable storage medium, and a computer readable program is stored on the computer readable storage medium, and when the computer readable program is executed by a processor, the method for expanding the CPU interface is realized.
Because the expansion program of the CPU interface is executed by the processor, all the technical solutions of all the foregoing embodiments are adopted, and therefore, at least all the beneficial effects brought by all the technical solutions of all the foregoing embodiments are not described in detail herein.
The CPU interface of the network equipment is expanded through a plurality of cascaded exchange chips, so that an expanded exchange chip interface and an expansion interface led out by each exchange chip are obtained, wherein the expanded exchange chip interface comprises an upper connecting port of the exchange chip connected with the CPU interface and a cascade interface connected with each exchange chip; setting the expanded exchange chip interface to be in a DSA mode, and setting the expanded interface to be in a common mode; configuring the expanded exchange chip interface; and based on the DSA mode and the interface configuration condition, forwarding the message between the extended exchange chip interfaces by using a DSA label. The application applies the DSA technology to the expansion of the multistage exchange chip under the CPU interface of the single firewall equipment, namely, the DSA technology is used between the expanded exchange chip interfaces to realize the interface expansion. By means of the scheme, the traditional vlan tag division mode is not adopted for the expansion of the CPU interface in the device, and DSA tags are adopted for guiding forwarding. The cascade port and the upper port are set to be in a DSA mode, and the extension port is set to be in a common mode, so that the DSA label can be ensured to exist in the network equipment only. Compared with the traditional vlan tag packaging mode, the vlan tag packaging method has the advantages that a series of operations such as vlan division, packaging and stripping are completed without changing a hardware driving code, meanwhile, the DSA tag is used, the complicated mode of packaging multiple layers of tags under a multi-level exchange chip is avoided, and only one layer of DSA tag is used.
Compared with the prior art, the scheme has the following advantages:
1. when in multi-stage expansion, a plurality of layers of vlan tag labels are not required to be sealed, only one layer of DSA label is required, and great convenience is brought to CPU processing.
2. The DSA mode can be realized by configuring the register of the exchange chip, and operations such as vlan tag division, sealing and stripping are not required to be added by hardware driving.
3. On the exchange chip supporting the DSA technology, the method can very conveniently complete the forwarding of the message among the exchange chips.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or system that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or system. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or system that comprises the element.
The foregoing embodiment numbers of the present application are merely for describing, and do not represent advantages or disadvantages of the embodiments.
From the above description of the embodiments, it will be clear to those skilled in the art that the above-described embodiment method may be implemented by means of software plus a necessary general hardware platform, but of course may also be implemented by means of hardware, but in many cases the former is a preferred embodiment. Based on such understanding, the technical solution of the present application may be embodied essentially or in a part contributing to the prior art in the form of a software product stored in a storage medium (e.g. ROM/RAM, magnetic disk, optical disk) as above, including several instructions for causing a terminal device (which may be a mobile phone, a computer, a server, a controlled terminal, or a network device, etc.) to perform the method of each embodiment of the present application.
The foregoing description is only of the preferred embodiments of the present application, and is not intended to limit the scope of the claims, and all equivalent structures or equivalent processes using the descriptions and drawings of the present application, or direct or indirect application in other related technical fields are included in the scope of the claims of the present application.
Claims (9)
1. An extension method of a CPU interface, applied to a network device, the method comprising the steps of:
expanding the CPU interface of the network equipment through a plurality of cascaded exchange chips to obtain an expanded exchange chip interface and an expansion interface led out by each exchange chip;
setting the extended switching chip interface to a distributed switch architecture DSA mode, and setting the extended interface to a common mode;
configuring the expanded exchange chip interface;
based on the DSA mode and interface configuration condition, using DSA label to forward message between the extended exchange chip interfaces;
the extended exchange chip interface comprises an upper connecting port of the exchange chip connected with the CPU interface and a cascade port connected with each other between the exchange chips; the step of configuring the extended switch chip interface includes:
setting a corresponding relation table Dev Map of the cascade port and the connected exchange chip;
dividing vlan groups of the virtual local area network to which each interface belongs, wherein the cascade port and the upper port belong to all vlan groups.
2. The method of claim 1, wherein the step of setting the extended switch chip interface to DSA mode comprises:
isolating the exchange chip corresponding to the extended exchange chip interface through a DSA label to divide an independent message channel;
and sealing different DSA labels on messages entering from different exchange chip interfaces.
3. The method of claim 2, wherein the step of using DSA tags to forward messages between the extended switch chip interfaces based on the DSA mode and interface configuration conditions comprises:
after a message enters the exchange chip from a common physical interface, marking a DSA label on the message when passing through a first cascade port or an upper port, and marking source equipment information, source port information, destination equipment information and destination port information of an input interface of the message;
and when the message is forwarded, searching the corresponding relation table Dev Map according to the destination equipment information stored in the DSA label to obtain a cascade output port.
4. The method of claim 3, wherein the step of using DSA tags to forward messages between the extended switch chip interfaces based on the DSA mode and interface configuration conditions further comprises:
if the directly forwarded cascade port is not found, broadcasting to the next exchange chip in the vlan group to continue the search until the directly forwarded cascade port is found.
5. The method of claim 3, wherein the step of using DSA tags to forward messages between the extended switch chip interfaces based on the DSA mode and interface configuration conditions further comprises:
when the message is detected to be sent out from the expansion interface, judging that the interface type is in a non-DSA mode, and stripping the DSA label on the message and then sending the message.
6. The method of claim 3, wherein the step of using DSA tags to forward messages between the extended switch chip interfaces based on the DSA mode and interface configuration conditions further comprises:
and uniformly sending the messages sent by the extended exchange chip interface into a CPU interface for processing in a parity distribution or hash mode.
7. An expansion device for a CPU interface, the device comprising:
the expansion module is used for expanding the CPU interface of the network equipment through a plurality of cascaded exchange chips to obtain an expanded exchange chip interface and an expansion interface led out by each exchange chip;
the setting module is used for setting the expanded exchange chip interface to be in a DSA mode and setting the expanded interface to be in a common mode;
the configuration module is used for configuring the expanded exchange chip interface;
the message forwarding module is used for forwarding the message between the extended exchange chip interfaces by using a DSA label based on the DSA mode and the interface configuration condition;
the extended exchange chip interface comprises an upper connecting port of the exchange chip connected with the CPU interface and a cascade port connected with each other between the exchange chips; the configuration module is also used for setting a corresponding relation table Dev Map of the cascade port and the connected exchange chip; dividing vlan groups of the virtual local area network to which each interface belongs, wherein the cascade port and the upper port belong to all vlan groups.
8. A network device, the network device comprising: the network device comprises a memory, a processor and an expansion program of the CPU interface, wherein the expansion program of the CPU interface is stored in the memory and can run on the processor, and the expansion method of the CPU interface is realized when the expansion program of the CPU interface is executed by the processor.
9. A computer readable storage medium, characterized in that the computer readable storage medium has stored thereon a computer readable program, which when executed by a processor, implements a method of expanding a CPU interface according to any of claims 1-6.
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104158768A (en) * | 2014-07-01 | 2014-11-19 | 汉柏科技有限公司 | Method and system for extending network interfaces, and method for receiving and sending message |
| CN107645391A (en) * | 2016-07-21 | 2018-01-30 | 中兴通讯股份有限公司 | A kind of port configuration method and device of Interface Expanding equipment |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8379644B1 (en) * | 2006-06-30 | 2013-02-19 | Marvell International Ltd. | System and method of processing management frames |
| CN101610217B (en) * | 2009-06-05 | 2011-08-24 | 中兴通讯股份有限公司 | Method for implementing message transmission between extensible processor and switch chip and system thereof |
| CN109565477B (en) * | 2016-05-18 | 2021-06-22 | 马维尔以色列(M.I.S.L.)有限公司 | Traffic management in a network switching system having remote physical ports |
| CN110383777B (en) * | 2017-03-28 | 2022-04-08 | 马维尔亚洲私人有限公司 | Flexible processor for port expander device |
| CN110620725A (en) * | 2018-06-20 | 2019-12-27 | 北京东土科技股份有限公司 | Method for expanding out-of-band interface of switching equipment and switching equipment |
| US10785120B2 (en) * | 2018-06-27 | 2020-09-22 | Dell Products L.P. | Systems and methods for extending link layer discovery over virtual Ethernet bridges |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104158768A (en) * | 2014-07-01 | 2014-11-19 | 汉柏科技有限公司 | Method and system for extending network interfaces, and method for receiving and sending message |
| CN107645391A (en) * | 2016-07-21 | 2018-01-30 | 中兴通讯股份有限公司 | A kind of port configuration method and device of Interface Expanding equipment |
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