CN115799315A - IGBT device and manufacturing method thereof - Google Patents
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- CN115799315A CN115799315A CN202211491920.9A CN202211491920A CN115799315A CN 115799315 A CN115799315 A CN 115799315A CN 202211491920 A CN202211491920 A CN 202211491920A CN 115799315 A CN115799315 A CN 115799315A
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Abstract
The application discloses IGBT device and manufacturing method thereof, the device includes: the grid dielectric layer is formed among the surface of the substrate, the first grid, the second grid and the substrate; a first doped region is formed from the front surface of the substrate to a first depth, a first heavily doped region is formed from the front surface of the substrate to a second depth, a second doped region is formed from the back surface of the substrate to a third depth, a second heavily doped region is formed from the back surface of the substrate to a fourth depth, the second depth is smaller than the first depth, and the fourth depth is smaller than the third depth; a cylindrical doped region is formed between the first grid and the second grid, the bottom of the cylindrical doped region is lower than the bottoms of the first grid and the second grid, and the top of the cylindrical doped region is lower than the tops of the first grid and the second grid. According to the IGBT device, the columnar doped region is formed in the table-board region below the first grid and the second grid of the IGBT device, so that an electric field of the drift region is converted into nearly uniform distribution along the vertical direction, and the electrical performance of the device is improved.
Description
Technical Field
The application relates to the technical field of semiconductor integrated circuit manufacturing, in particular to an IGBT device and a manufacturing method thereof.
Background
An Insulated Gate Bipolar Transistor (IGBT) device is one of important switching elements for energy control and conversion of a power electronic system, and the performance of the IGBT device directly affects the conversion efficiency, volume and weight of the power electronic system.
Generally, an IGBT device applied to a power electronic system is based on a double-Diffused Metal Oxide Semiconductor (DMOS) having a vertical device structure (e.g., a vertical N (negative) -P (positive) -N double-gate transistor).
However, the drift region electric field distribution of the DMOS-based IGBT device exhibits a single-peak curve in the vertical direction, and its substrate is thick and its resistivity is large. In view of this, it is desirable to provide an IGBT device with a uniform drift region electric field distribution and a small resistivity.
Disclosure of Invention
The application provides an IGBT device and a manufacturing method thereof, which can solve the problem that the IGBT device based on DMOS provided in the related technology has poor electrical performance.
On one hand, the embodiment of the application provides a manufacturing method of an IGBT device, which is characterized by comprising the following steps:
providing a substrate, wherein a first groove and a second groove are formed in the substrate, gate dielectric layers are formed on the surfaces of the substrate, the first groove and the second groove, a polycrystalline silicon layer is formed on the gate dielectric layers in the first groove and the second groove, the polycrystalline silicon layer in the first groove forms a first gate of the IGBT device, and the polycrystalline silicon layer in the second groove forms a second gate of the IGBT device;
performing ion implantation, and forming a first doped region from the front surface of the substrate to a first depth, wherein the front surface of the substrate is the surface of the substrate towards which the openings of the first trench and the second trench point;
performing ion implantation, and forming a first heavily doped region from the front surface of the substrate to a second depth, wherein the second depth is smaller than the first depth;
forming a cylindrical doped region in the substrate between the first gate and the second gate, wherein the bottom of the cylindrical doped region is lower than the bottom of the first gate and the bottom of the second gate, and the top of the cylindrical doped region is lower than the top of the first gate and the top of the second gate;
forming a first metal layer on the front surface of the substrate, wherein the first metal layer is used for leading out a first heavily doped region and a first doped region;
performing ion implantation, and forming a second doped region from the back surface of the substrate to a third depth, wherein the back surface of the substrate is a surface of the substrate facing along the bottoms of the first trench and the second trench;
carrying out ion implantation, and forming a second heavily doped region from the back of the substrate to a fourth depth, wherein the fourth depth is smaller than the third depth;
and forming a second metal layer on the back of the substrate.
In some embodiments, the ratio of the height to the width of the columnar doped region is greater than 2.
In some embodiments, the first trench and the second trench are equal in depth and width.
In some embodiments, the ratio of the depth to the width of the first trench and the second trench is greater than 3.
In some embodiments, after forming the first metal layer on the front side of the substrate and before forming the second doped region from the back side of the substrate to the third depth, the method further includes:
and thinning the back of the substrate.
In some embodiments, the forming a first metal layer on the front side of the substrate includes:
forming buffer layers on the gate dielectric layer, the first gate and the second gate;
forming a third trench between the first gate and the second gate, wherein the bottom of the third trench is lower than the bottom of the first heavily doped region and higher than the bottom of the first doped region;
and forming a first metal layer on the buffer layer, wherein the third groove is filled with the first metal layer.
On the other hand, the embodiment of the present application provides an IGBT device, including:
the IGBT device comprises a substrate, wherein a first groove and a second groove are formed in the substrate, gate dielectric layers are formed on the surfaces of the substrate, the first groove and the second groove, polycrystalline silicon layers are formed on the gate dielectric layers in the first groove and the second groove, the polycrystalline silicon layers in the first groove form a first grid of the IGBT device, and the polycrystalline silicon layers in the second groove form a second grid of the IGBT device;
a first doped region is formed from the front surface of the substrate to a first depth, a first heavily doped region is formed from the front surface of the substrate to a second depth, a second doped region is formed from the back surface of the substrate to a third depth, a second heavily doped region is formed from the back surface of the substrate to a fourth depth, the front surface of the substrate is the surface of the substrate towards which the openings of the first trench and the second trench point, the back surface of the substrate is the surface of the substrate towards which the bottoms of the first trench and the second trench point, the second depth is smaller than the first depth, and the fourth depth is smaller than the third depth;
a cylindrical doped region is formed in the substrate between the first gate and the second gate, the bottom of the cylindrical doped region is lower than the bottom of the first gate and the bottom of the second gate, and the top of the cylindrical doped region is lower than the top of the first gate and the top of the second gate.
In some embodiments, a buffer layer is formed on the gate dielectric layer, the first gate and the second gate;
a third groove is formed between the first grid and the second grid, and the bottom of the third groove is lower than the bottom of the first heavily doped region and higher than the bottom of the first doped region;
and a first metal layer is formed on the buffer layer and fills the third groove.
In some embodiments, the ratio of the height to the width of the columnar doped region is greater than 2.
In some embodiments, the first trench and the second trench are equal in depth and width.
In some embodiments, a ratio of a depth to a width of the first trench and the second trench is greater than 3.
The technical scheme at least comprises the following advantages:
according to the IGBT device, the columnar doped region is formed in the table-board region below the first grid and the second grid of the IGBT device, so that an electric field of the drift region is converted into nearly uniform distribution along the vertical direction, the breakdown voltage of the device is improved, and the electrical performance of the device is further improved.
Drawings
In order to more clearly illustrate the detailed description of the present application or the technical solutions in the prior art, the drawings needed to be used in the detailed description of the present application or the prior art description will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a flowchart of a method for fabricating an IGBT device according to an exemplary embodiment of the present application;
fig. 2 to 9 are schematic diagrams illustrating formation of an IGBT device according to an exemplary embodiment of the present application.
Detailed Description
The technical solutions in the present application will be described clearly and completely with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on orientations or positional relationships shown in the drawings, and are only for convenience of description and simplification of description, but do not indicate or imply that the device or element referred to must have a particular orientation, be constructed in a particular orientation, and operate, and thus should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; the connection can be mechanical connection or electrical connection; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.
In addition, the technical features mentioned in the different embodiments of the present application described below may be combined with each other as long as they do not conflict with each other.
Referring to fig. 1, which shows a flowchart of a method for manufacturing an IGBT device according to an exemplary embodiment of the present application, as shown in fig. 1, the method includes:
step S1, a substrate is provided, a first groove and a second groove are formed in the substrate, gate dielectric layers are formed on the surfaces of the substrate, the first groove and the second groove, polycrystalline silicon layers are formed on the gate dielectric layers in the first groove and the second groove, the polycrystalline silicon layers in the first groove form a first grid electrode of an IGBT device, and the polycrystalline silicon layers in the second groove form a second grid electrode of the IGBT device.
Referring to fig. 2, a cross-sectional view before forming the first doped region is shown. Illustratively, as shown in fig. 2, a first trench 301 and a second trench 302 are formed in the substrate 210, a gate dielectric layer 220 is formed on the surface of the substrate 210, the first trench 301 and the second trench 302, a polysilicon layer is formed on the gate dielectric layer 220 in the first trench 301 and the second trench 302, the polysilicon layer in the first trench 301 forms a first gate 231 of the IGBT device, and the polysilicon layer in the second trench 302 forms a second gate 232 of the IGBT device. Wherein the thickness of the substrate 210 is h1; the first trench 301 and the second trench 302 have the same size (depth and width), and the ratio of the depth to the width (of the first trench 301 or the second trench 302) is greater than 3.
And S2, carrying out ion implantation to form a first doped region from the front surface of the substrate to a first depth.
And S3, performing ion implantation, and forming a first heavily doped region from the front surface of the substrate to a second depth, wherein the second depth is smaller than the first depth.
Referring to fig. 3, a schematic cross-sectional view after forming the first doped region and the first heavily doped region is shown. Illustratively, as shown in fig. 3, in the embodiment of the present application, the front surface of the substrate 210 is the surface of the substrate 210 to which the openings of the first trench 301 and the second trench 302 are directed, and correspondingly, the back surface of the substrate 210 is the surface of the substrate 210 to which the bottoms of the first trench 301 and the second trench 302 are directed, after ion implantation, the first doped region 201 is formed on the front surface of the substrate 210 to a first depth, the first heavily doped region 202 is formed on the front surface of the substrate 210 to a second depth, and the second depth is smaller than the first depth (i.e., the first heavily doped region 202 is formed in the first doped region 201). The first doped region 201 may serve as a well (well) region of the IGBT device.
And S4, forming a cylindrical doped region in the substrate between the first grid and the second grid, wherein the bottom of the cylindrical doped region is lower than the bottoms of the first grid and the second grid, and the top of the cylindrical doped region is lower than the tops of the first grid and the second grid.
Referring to fig. 4, a cross-sectional view after forming a column-shaped doped region is shown. Illustratively, the photoresist may be removed by covering the photoresist by a photolithography process, opening the area above the pillar-shaped doped region 203, performing ion implantation, forming the pillar-shaped doped region 203 in the substrate 210 between the first gate 231 and the second gate 232. Wherein, the ratio of the height to the width of the column-shaped doped region 203 is greater than 2.
And S5, forming a first metal layer on the front surface of the substrate, wherein the first metal layer is used for leading out a first heavily doped region and a first doped region.
Illustratively, step S3 includes, but is not limited to: forming buffer layers on the gate dielectric layer, the first gate and the second gate; forming a third trench between the first gate and the second gate; and forming a first metal layer on the buffer layer, wherein the third groove is filled with the first metal layer.
Referring to fig. 5, a schematic cross-sectional view after forming a buffer layer is shown; referring to fig. 6, a schematic cross-sectional view after forming a third trench is shown; referring to fig. 7, a schematic cross-sectional view after forming a first metal layer is shown.
Illustratively, as shown in fig. 5 to 7, an oxide layer (e.g., silicon dioxide (SiO) may be deposited on the gate dielectric layer 220, the first gate 231, and the second gate 232 by a Chemical Vapor Deposition (CVD) process 2 ) Layer) or a nitride layer (e.g., a silicon nitride (SiN) layer) forms the buffer layer 240; a photoresist can be covered on the buffer layer 240 through a photolithography process, the region above the third trench 303 is exposed, etching is performed, the third trench 303 is formed between the first gate 231 and the second gate 232, and the photoresist is removed; a first metal layer 251 is formed on the buffer layer 240.
Wherein the bottom of the third trench 303 is higher than the bottom of the first doped region 201, and the bottom of the third trench 303 is lower than the bottom of the first heavily doped region 202; if the first metal layer 251 includes copper (Cu), the first metal layer 251 may be formed by electroplating a copper layer, if the first metal layer 251 includes tungsten (W), the first metal layer 251 may be formed by depositing a tungsten layer through a CVD process, and if the first metal layer 251 includes aluminum (Al), the first metal layer 251 may be formed by depositing an aluminum layer through a Physical Vapor Deposition (PVD) process.
In some embodiments, before step S6, the method further includes: and thinning the back surface of the substrate. Referring to fig. 8, a schematic cross-sectional view of the substrate after thinning process is shown. Illustratively, as shown in fig. 8, after thinning, the thickness of the substrate 210 is reduced from h1 to h2, where h2 < h1.
And S6, carrying out ion implantation, and forming a second doped region from the back surface of the substrate to a third depth.
And S7, performing ion implantation, and forming a second heavily doped region from the back of the substrate to a fourth depth, wherein the fourth depth is smaller than the third depth.
And step S8, forming a second metal layer on the back surface of the substrate.
Referring to fig. 9, a cross-sectional view after forming the second doped region, the second heavily doped region and the second metal layer is shown. Illustratively, as shown in fig. 9, the substrate 210 is formed with a second doped region 204 and a second heavily doped region 205 at the bottom thereof, and the substrate 210 is formed with a second metal layer 252 at the back thereof, wherein the depth of the second heavily doped region 205 is smaller than the depth of the second doped region 204. The second doped region 204 may serve as a Field Stop (FS) region of the IGBT device.
The second metal layer 252 may be formed by electroplating a copper layer if the second metal layer 252 includes copper, the second metal layer 252 may be formed by depositing a tungsten layer by a CVD process if the second metal layer 252 includes tungsten, and the second metal layer 252 may be formed by depositing an aluminum layer by a PVD process if the second metal layer 252 includes aluminum.
In the embodiment of the present application, the impurity concentrations of the first heavily doped region 202 and the second heavily doped region 205 are greater than the impurity concentrations of the first doped region 201, the columnar doped region 203, and the second doped region 205; the first doping region 201, the column-shaped doping region 203 and the second heavily doping region 205 are doped with impurities of a first type, and the first heavily doping region 202 and the second doping region 204 are doped with impurities of a second type.
In the embodiment of the present application, if the first type impurity is an N (negative) type impurity, the second type impurity is a P (positive) type impurity; if the first type impurity is a P-type impurity, the second type impurity is an N-type impurity.
In summary, in the embodiment of the present application, the column-shaped doped region is formed in the mesa region below the first gate and the second gate of the IGBT device, so that the electric field of the drift region is converted into a nearly uniform distribution along the vertical direction, the breakdown voltage of the device is improved, and the electrical performance of the device is further improved. Furthermore, the thickness and the resistivity of the substrate are reduced by thinning the back surface of the substrate.
Referring to fig. 9, which shows a schematic cross-sectional view of an IGBT device provided in an exemplary embodiment of the present application, the device may be manufactured by the above-mentioned embodiment, as shown in fig. 9, the device includes:
the back side of the substrate 210 is thinned after the front side is manufactured, wherein a first trench and a second trench are formed in the substrate 210, a gate dielectric layer 220 is formed on the surfaces of the substrate 210, the first trench and the second trench, a polysilicon layer is formed on the gate dielectric layer 220 in the first trench and the second trench, the polysilicon layer in the first trench 301 forms a first gate 231 of the IGBT device, the polysilicon layer in the second trench 302 forms a second gate 232 of the IGBT device. In some embodiments, the first trench and the second trench are the same size (depth and width), and the ratio of the depth to the width (of the first trench or the second trench) is greater than 3.
A first doped region 201 (which may be a well region of an IGBT device) is formed on the front surface of the substrate 210 to a first depth, a first heavily doped region 202 (which may be a field stop region of the IGBT device) is formed on the front surface of the substrate 210 to a second depth (which is smaller than the first depth), a second doped region 204 (which may be a field stop region of the IGBT device) is formed on the back surface of the substrate 210 to a third depth, a second heavily doped region 205 (which may be a field stop region of the IGBT device) is formed on the back surface of the substrate 210 to a fourth depth (which is smaller than the third depth), and a second metal layer 252 is formed on the back surface of the substrate 210.
A column-shaped doped region 203 is formed in the substrate between the first gate 231 and the second gate 232, the bottom of the column-shaped doped region 203 is lower than the bottom of the first gate 231 and the second gate 232, the top of the column-shaped doped region 203 is lower than the top of the first gate 231 and the second gate 232, and the bottom of the column-shaped doped region 203 is lower than the bottom of the first doped region 201. In some embodiments, the ratio of the height to the width of the columnar doped region 203 is greater than 2.
A buffer layer 240 is formed on the gate dielectric layer 220, the first gate 231 and the second gate 232; a third trench is formed between the first gate 231 and the second gate 232, and the bottom of the third trench is lower than the bottom of the first heavily doped region 202 and higher than the bottom of the first doped region 201; a first metal layer 251 is formed on the buffer layer 240, and the third trench is filled with the first metal layer 251. The first and second metal layers 251 and 252 may include copper, tungsten, or aluminum; the buffer layer 240 may be an oxide layer or a nitride layer.
The impurity concentrations of the first heavily doped region 202, the second heavily doped region 205, the third heavily doped region 206, and the fourth heavily doped region 207 are greater than the impurity concentrations of the first doped region 201, the columnar doped region 203, and the second doped region 205; the first, column-shaped, and second heavily doped regions 201, 203, 205 are doped with impurities of a first type, and the first, second, third, and fourth heavily doped regions 202, 204, 206, and 207 are doped with impurities of a second type.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of this invention are intended to be covered by the scope of the invention as expressed herein.
Claims (11)
1. A manufacturing method of an IGBT device is characterized by comprising the following steps:
providing a substrate, wherein a first groove and a second groove are formed in the substrate, gate dielectric layers are formed on the surfaces of the substrate, the first groove and the second groove, polycrystalline silicon layers are formed on the gate dielectric layers in the first groove and the second groove, the polycrystalline silicon layer in the first groove forms a first gate of the IGBT device, and the polycrystalline silicon layer in the second groove forms a second gate of the IGBT device;
performing ion implantation, and forming a first doped region from the front surface of the substrate to a first depth, wherein the front surface of the substrate is the surface of the substrate towards which the openings of the first trench and the second trench point;
performing ion implantation, and forming a first heavily doped region from the front surface of the substrate to a second depth, wherein the second depth is smaller than the first depth;
forming a cylindrical doped region in the substrate between the first gate and the second gate, wherein the bottom of the cylindrical doped region is lower than the bottom of the first gate and the bottom of the second gate, and the top of the cylindrical doped region is lower than the top of the first gate and the top of the second gate;
forming a first metal layer on the front surface of the substrate, wherein the first metal layer is used for leading out a first heavily doped region and a first doped region;
performing ion implantation, and forming a second doped region from the back surface of the substrate to a third depth, wherein the back surface of the substrate is the surface of the substrate, to which the bottoms of the first trench and the second trench point;
performing ion implantation, and forming a second heavily doped region from the back surface of the substrate to a fourth depth, wherein the fourth depth is smaller than the third depth;
and forming a second metal layer on the back surface of the substrate.
2. The method of claim 1, wherein the ratio of the height to the width of the columnar doped region is greater than 2.
3. The method of claim 2, wherein the first trench and the second trench are equal in depth and width.
4. The method of claim 3, wherein a ratio of a depth to a width of the first trench and the second trench is greater than 3.
5. The method according to any one of claims 1 to 4, wherein after forming the first metal layer on the front surface of the substrate and before forming the second doped region on the back surface of the substrate to a third depth, the method further comprises:
and thinning the back surface of the substrate.
6. The method of claim 5, wherein forming a first metal layer on the front side of the substrate comprises:
forming buffer layers on the gate dielectric layer, the first gate and the second gate;
forming a third trench between the first gate and the second gate, wherein the bottom of the third trench is lower than the bottom of the first heavily doped region and higher than the bottom of the first doped region;
and forming a first metal layer on the buffer layer, wherein the third groove is filled with the first metal layer.
7. An IGBT device, characterized by comprising:
the IGBT device comprises a substrate, wherein a first groove and a second groove are formed in the substrate, gate dielectric layers are formed on the surfaces of the substrate, the first groove and the second groove, polycrystalline silicon layers are formed on the gate dielectric layers in the first groove and the second groove, the polycrystalline silicon layers in the first groove form a first grid of the IGBT device, and the polycrystalline silicon layers in the second groove form a second grid of the IGBT device;
a first doped region is formed from the front surface of the substrate to a first depth, a first heavily doped region is formed from the front surface of the substrate to a second depth, a second doped region is formed from the back surface of the substrate to a third depth, a second heavily doped region is formed from the back surface of the substrate to a fourth depth, the front surface of the substrate is the surface of the substrate towards which the openings of the first trench and the second trench point, the back surface of the substrate is the surface of the substrate towards which the bottoms of the first trench and the second trench point, the second depth is smaller than the first depth, and the fourth depth is smaller than the third depth;
a cylindrical doped region is formed in the substrate between the first gate and the second gate, the bottom of the cylindrical doped region is lower than the bottom of the first gate and the bottom of the second gate, and the top of the cylindrical doped region is lower than the top of the first gate and the top of the second gate.
8. The device of claim 7, wherein buffer layers are formed on the gate dielectric layer, the first gate electrode and the second gate electrode;
a third groove is formed between the first grid and the second grid, and the bottom of the third groove is lower than the bottom of the first heavily doped region and higher than the bottom of the first doped region;
and a first metal layer is formed on the buffer layer and fills the third groove.
9. The device of claim 8, wherein the ratio of the height to the width of the columnar doped region is greater than 2.
10. The device of claim 9 wherein the first trench and the second trench are equal in depth and width.
11. The device of claim 10 wherein the ratio of the depth to the width of the first trench and the second trench is greater than 3.
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| CN202211491920.9A CN115799315A (en) | 2022-11-25 | 2022-11-25 | IGBT device and manufacturing method thereof |
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