CN115799297A - Vertical channel transistor - Google Patents

Vertical channel transistor Download PDF

Info

Publication number
CN115799297A
CN115799297A CN202210498032.3A CN202210498032A CN115799297A CN 115799297 A CN115799297 A CN 115799297A CN 202210498032 A CN202210498032 A CN 202210498032A CN 115799297 A CN115799297 A CN 115799297A
Authority
CN
China
Prior art keywords
source
drain electrode
layer
channel pattern
pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202210498032.3A
Other languages
Chinese (zh)
Inventor
卞卿溵
金尚元
金昌炫
申建旭
李昌锡
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of CN115799297A publication Critical patent/CN115799297A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1606—Graphene
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys
    • H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41741—Source or drain electrodes for field effect devices for vertical or pseudo-vertical devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H01L29/42392—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor fully surrounding the channel, e.g. gate-all-around
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Thin Film Transistor (AREA)

Abstract

A vertical channel transistor comprising: a first source/drain electrode; a second source/drain electrode spaced apart from the first source/drain electrode in the first direction; a first channel pattern between the first source/drain electrode and the second source/drain electrode; a first gate electrode on a side surface of the first channel pattern; a first gate insulating layer between the first channel pattern and the first gate electrode; and a first graphene insertion layer between the first source/drain electrode and the first channel pattern.

Description

Vertical channel transistor
Technical Field
The present disclosure relates to vertical channel transistors.
Background
As the integration degree of semiconductor devices increases, in order to reduce the area occupied by each unit device in a top view, a device having a vertical channel structure in which a source and a drain are vertically arranged, such as a Vertical Channel Array Transistor (VCAT) (hereinafter referred to as a vertical channel transistor), has been proposed. A relatively large number of devices can be integrated in the same area by vertical channel transistors compared to horizontal channel transistors. Since vertical channel transistors have different forms than previous devices, the fabrication process using existing materials can become very complex and may require a high level of fabrication techniques.
Disclosure of Invention
Vertical channel transistors are provided that include graphene in the junctions between conductors and semiconductors, between conductors and insulators, and between semiconductors and insulators.
However, example embodiments are not limited thereto.
Additional aspects will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the presented embodiments of the disclosure.
According to an embodiment, a vertical channel transistor may include: a first source/drain electrode; a second source/drain electrode spaced apart from the first source/drain electrode in the first direction; a first channel pattern between the first source/drain electrode and the second source/drain electrode; a first gate electrode on a side surface of the first channel pattern; a first gate insulating layer between the first channel pattern and the first gate electrode; and a first graphene insertion layer between the first source/drain electrode and the first channel pattern.
In some embodiments, a portion of a surface of the first source/drain electrode may face a surface of the first gate insulating layer in the first direction, and the first graphene insertion layer may extend between the first gate insulating layer and the first source/drain electrode in the second direction. The second direction may cross the first direction.
In some embodiments, the vertical channel transistor may further include a first additional source/drain electrode between the first graphene insertion layer and the first channel pattern. The first source/drain electrode and the first additional source/drain electrode may include different materials from each other.
In some embodiments, a portion of a surface of the first additional source/drain electrode may face a surface of the first gate insulating layer in the first direction, and the first additional source/drain electrode may directly contact the first gate insulating layer.
In some embodiments, the vertical channel transistor may further include a second graphene insertion layer between the second source/drain electrode and the first channel pattern.
In some embodiments, at least one of the first graphene insertion layer and the second graphene insertion layer may have a thickness of about 0.34 nanometers (nm) to about 3nm.
In some embodiments, at least one of the first graphene insertion layer and the second graphene insertion layer may include crystals having a size of from about 0.5nm to about 100 nm.
In some embodiments, a proportion of carbon atoms having an sp2 bonding structure to all carbon atoms in at least one of the first and second graphene insertion layers may be 50% to 99%.
In some embodiments, at least one of the first graphene insertion layer and the second graphene insertion layer may have a density of from about 1.6g/cc to about 2.1 g/cc.
In some embodiments, the second graphene insertion layer may surround the second source/drain electrode.
In some embodiments, the first gate insulating layer may surround a side surface of the first channel pattern, and the first gate electrode may extend along the first gate insulating layer and surround the first channel pattern.
In some embodiments, the vertical channel transistor may further include: a second gate electrode facing the first gate electrode with the first channel pattern interposed therebetween; and a second gate insulating layer between the second gate electrode and the first channel pattern.
In some embodiments, the vertical channel transistor may further include a passivation layer on the first source/drain electrode. The passivation layer may cover the second source/drain electrode. A portion of the first graphene insertion layer may be between the passivation layer and the first source/drain electrode.
In some embodiments, the vertical channel transistor may further include a second graphene insertion layer between the second source/drain electrode and the first channel pattern. A portion of the second graphene insertion layer may be between the passivation layer and the second source/drain electrode.
In some embodiments, the vertical channel transistor may further include: a second channel pattern facing the first channel pattern with the first gate electrode interposed therebetween; and a second gate insulating layer between the first gate electrode and the second channel pattern. The first channel pattern and the second channel pattern may be in a region where the first source/drain electrode and the second source/drain electrode face each other in the first direction.
In some embodiments, the vertical channel transistor may further include: a second graphene insertion layer between the second source/drain electrode and the first channel pattern; a first insulating pattern between the first gate electrode and the first graphene insertion layer; a second insulating pattern between the first gate electrode and the second graphene insertion layer; and a third channel pattern between the second graphene insertion layer and the second insulation pattern. The first channel pattern, the second channel pattern, and the third channel pattern may constitute a single structure.
According to an embodiment, a vertical channel transistor may include: a first source/drain electrode; a channel pattern on the first source/drain electrode; a second source/drain electrode on the channel pattern; a first graphene insertion layer between the first source/drain electrode and the channel pattern; a gate electrode over the first source/drain electrode; and a gate insulating layer on sidewalls of the channel pattern between the gate electrode and the channel pattern. The second source/drain electrode may be spaced apart from the first source/drain electrode in the first direction. The gate electrode may be spaced apart from the first source/drain electrode in the first direction.
In some embodiments, the channel pattern may be between the first source/drain electrode and the second source/drain electrode.
In some embodiments, the second graphene insertion layer may be on the second source/drain electrode. A surface of the second graphene insertion layer may face a surface of the first source/drain electrode.
In some embodiments, the gate electrode may be between the first source/drain electrode and a portion of the channel pattern.
Drawings
The above and other aspects, features and advantages of certain embodiments of the present disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:
FIG. 1 is a cross-sectional view of a vertical channel transistor according to an example embodiment;
FIG. 2 is a cross-sectional view of a vertical channel transistor according to an example embodiment;
FIG. 3 is a cross-sectional view of a vertical channel transistor according to an example embodiment;
FIG. 4 is a cross-sectional view of a vertical channel transistor according to an example embodiment;
fig. 5A and 5B are plan views of portions of vertical channel transistors according to some example embodiments.
Fig. 6 and 7 are block diagrams of electronic systems according to some example embodiments; and
FIG. 8 is a diagram of an electronic circuit according to an example embodiment.
Detailed Description
Reference will now be made in detail to embodiments, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the like elements throughout. In this regard, the present embodiments may have different forms and should not be construed as limited to the descriptions set forth herein. Therefore, only the embodiments are described below to explain aspects by referring to the figures. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. When following a column of elements, expressions such as at least one of "\8230;" 8230 "; modify the entire column of elements rather than modifying individual elements in the list.
When the term "about" or "substantially" is used in this specification in connection with a numerical value, it is intended that the relevant numerical value include manufacturing or operating tolerances (e.g., ± 10%) around the numerical value recited. Further, when the words "substantially" and "substantially" are used in connection with a geometric shape, it is intended that the accuracy of the geometric shape not be required, but that the latitude of the shape be within the scope of the present disclosure. Further, whether a value or shape is modified to be "about" or "substantially," it is to be understood that such values and shapes are to be interpreted as including manufacturing or operating tolerances (e.g., ± 10%) around the value or shape recited.
Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the drawings, like reference numerals denote like elements, and the size and thickness of each element may be exaggerated for clarity of illustration. In addition, the embodiments described below are merely examples, and various modifications may be made by these embodiments.
Hereinafter, things described as "on 8230above 8230, or" on 82308230, on 8230, may include not only things directly on top of contact but also things on top of contact in a non-contact manner.
The use of the singular forms "a", "an" and "the" encompass plural referents unless the context clearly dictates otherwise. Moreover, unless explicitly described to the contrary, the word "comprise" and variations such as "comprises" or "comprising 8230 \8230;" 8230; "are to be understood as implying the inclusion of stated elements, but not the exclusion of any other elements.
In addition, terms such as "\8230; unit" used in the specification refer to a unit that handles at least one function or operation.
Hereinafter, it should be understood that "at least one of a, b and c" includes "only a", "only b", "only c", "a and b", "a and c", "b and c" or "a, b and c".
Fig. 1 is a cross-sectional view of a vertical channel transistor according to an example embodiment.
Referring to fig. 1, a vertical channel transistor 11 may be provided. The vertical channel transistor 11 may include a substrate 100, a first source/drain electrode 210, a second source/drain electrode 220, a channel pattern 300, a first gate electrode 410, a second gate electrode 420, a first gate insulating layer 510, a second gate insulating layer 520, a passivation layer 600, a first graphene insertion layer 710, and a second graphene insertion layer 720. The substrate 100 may include an insulating material and/or a semiconductor material. For example, the substrate 100 may be an intrinsic semiconductor substrate, a glass substrate, a sapphire substrate, or a substrate including silicon oxide.
The first source/drain electrode 210 may be provided on the substrate 100. In an embodiment of the present disclosure, the first source/drain electrode 210 may be a source electrode of a transistor device. The first source/drain electrode 210 may include a metal or a metal alloy. For example, the first source/drain electrode 210 may include copper (Cu), ruthenium (Ru), aluminum (Al), cobalt (Co), tungsten (W), molybdenum (Mo), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), chromium (Cr), or an alloy thereof.
The second source/drain electrode 220 may be provided on the first source/drain electrode 210. The second source/drain electrode 220 may be spaced apart from the first source/drain electrode 210 in the first direction DR 1. For example, the first direction DR1 may be perpendicular to the top surface of the substrate 100. When the first source/drain electrode 210 is a source electrode of a transistor device, the second source/drain electrode 220 can be a drain electrode of the transistor device. The second source/drain electrode 220 may include a metal or metal alloy. For example, the second source/drain electrode 220 may include Cu, ru, al, co, W, mo, ti, ta, ni, pt, cr, or alloys thereof.
The channel pattern 300 may be provided between the first source/drain electrode 210 and the second source/drain electrode 220. The channel pattern 300 may include a semiconductor material. For example, the channel pattern 300 may include silicon (Si), germanium (Ge), or silicon germanium (SiGe). The channel pattern 300 may extend in the first direction DR 1. The shape of the channel pattern 300 may be determined as desired. According to an embodiment of the present disclosure, the channel pattern 300 may have a pillar shape extending in the first direction DR 1. For example, the channel pattern 300 may have a cylindrical shape. According to an embodiment of the present disclosure, the channel pattern 300 may have a fin shape extending in a third direction DR3 crossing the first and second directions DR1 and DR 2.
The first gate electrode 410 and the second gate electrode 420 may be provided at one side and the other side of the channel pattern 300, respectively. In an embodiment of the present disclosure, the first gate electrode 410 and the second gate electrode 420 may be gate electrodes of a transistor. According to an embodiment of the present disclosure, the first gate electrode 410 and the second gate electrode 420 may be connected to each other. For example, fig. 5A illustrates a plan view of an example of a portion of vertical channel transistor 11 in fig. 1, according to some example embodiments. As depicted in fig. 1 and 5A, the channel pattern 300 may have a pillar shape, and the first gate electrode 410 and the second gate electrode 420 may be different portions of one gate electrode surrounding the channel pattern 300.
According to an embodiment of the present disclosure, the first gate electrode 410 and the second gate electrode 420 may be spaced apart from each other. For example, fig. 5B illustrates a plan view of an example of a portion of the vertical channel transistor 11 in fig. 1, according to some example embodiments. As depicted in fig. 1 and 5B, the channel pattern 300 may have a fin shape, and the first and second gate electrodes 410 and 420 may be disposed at both sides of the channel pattern 300 to be spaced apart from each other. The first gate electrode 410 and the second gate electrode 420 may include a conductive material. For example, the first gate electrode 410 and the second gate electrode 420 may include gold (Au). When the vertical channel transistor 11 is driven, the same voltage may be applied to the first gate electrode 410 and the second gate electrode 420.
A first gate insulating layer 510 may be provided between the channel pattern 300 and the first gate electrode 410. The first gate insulating layer 510 may include an insulating material. For example, the first gate insulating layer 510 may include silicon oxide (e.g., siO) 2 ) Silicon nitride (e.g., siN), silicon oxynitride (e.g., siON), or high-k materials (e.g., al) 2 O 3 、HfO 2 、ZrO 2 )。
A second gate insulating layer 520 may be provided between the channel pattern 300 and the second gate electrode 420. The second gate insulating layer 520 may include an insulating material. For example, the second gate insulating layer 520 may include silicon oxide (e.g., siO) 2 ) Silicon nitride (e.g., siN), silicon oxynitride (e.g., siON), or high-k material (e.g., al) 2 O 3 、HfO 2 、ZrO 2 )。
According to an embodiment of the present disclosure, the first gate insulating layer 510 and the second gate insulating layer 520 may be connected to each other. For example, as depicted in fig. 1 and 5A, the first gate insulating layer 510 and the second gate insulating layer 520 may be different portions of one insulating layer surrounding the side surface of the channel pattern 300. Alternatively, according to an embodiment of the present disclosure, as depicted in fig. 1 and 5B, the first gate insulating layer 510 and the second gate insulating layer 520 may be spaced apart from each other.
The passivation layer 600 may be provided on the substrate 100. The passivation layer 600 may protect components provided on the substrate 100. For example, the passivation layer 600 may cover the first gate electrode 410, the second gate electrode 420, the first source/drain electrode 210, and the second source/drain electrode 220. The passivation layer 600 may include an insulating material. For example, the passivation layer 600 may include silicon oxide (e.g., siO) 2 ) Silicon nitride (e.g., siN), or silicon oxynitride (e.g., siON).
The first graphene insertion layer 710 may be provided between the first source/drain electrode 210 and the channel pattern 300. The first graphene insertion layer 710 may have a single layer structure or a multi-layer structure in which a plurality of layers are stacked. The first graphene insertion layer 710 may include nanocrystalline graphene. The nanocrystalline graphene may be graphene including crystals having a size smaller than that of crystals of intrinsic graphene, which is common crystalline graphene. Nanocrystalline graphene may include crystals having nanoscale dimensions (e.g., from about 0.5nm to about 100 nm). In the nanocrystalline graphene, the proportion of carbon atoms having an sp2 bonding structure with respect to all carbon atoms may be, for example, from about 50% to about 100%, for example, from about 50% to about 99%. The nanocrystalline graphene may include, for example, from about 1at% (atomic percent) to about 20at% hydrogen. The density of the nanocrystalline graphene may be, for example, from about 1.6g/cc (grams/cubic centimeter) to about 2.1g/cc, and the sheet resistance of the nanocrystalline graphene may be, for example, greater than about 1000Ohm/sq. The thickness of the first graphene insertion layer 710 may be from about 0.34nm to about 3nm.
The first graphene insertion layer 710 may be an ohmic contact layer configured to provide an ohmic contact between the channel pattern 300 and the first source/drain electrode 210. The first graphene insertion layer 710 may be a diffusion barrier that limits and/or prevents a dopant of the channel pattern 300 from diffusing into the first source/drain electrode 210. For example, the first graphene insertion layer 710 may limit and/or prevent diffusion of phosphorus (P) atoms and oxygen (O) atoms of the channel pattern 300.
The first graphene insertion layer 710 may extend to a region between the first source/drain electrode 210 and the passivation layer 600. The first graphene insertion layer 710 may pass through at least one of a region between the first gate insulating layer 510 and the first source/drain electrode 210 and a region between the second gate insulating layer 520 and the first source/drain electrode 210. According to an embodiment of the present disclosure, the first graphene insertion layer 710 may directly contact at least one of the first gate insulating layer 510 and the second gate insulating layer 520. The first graphene insertion layer 710 may extend along the top surface of the first source/drain electrode 210. The first source/drain electrode 210 and the passivation layer 600 may be spaced apart from each other by the first graphene insertion layer 710. The first graphene insertion layer 710 may limit and/or prevent diffusion (e.g., electromigration) of the material of the first source/drain electrode 210 into the passivation layer 600 between the first source/drain electrode 210 and the passivation layer 600. The first graphene insertion layer 710 may reduce the resistance of the first source/drain electrode 210 and improve process stability. The first graphene insertion layer 710 may be a cap layer covering the first source/drain electrode 210.
The second graphene insertion layer 720 may be provided between the second source/drain electrode 220 and the channel pattern 300. The second graphene insertion layer 720 may include nanocrystalline graphene. The second graphene insertion layer 720 may have a single-layer structure or a multi-layer structure in which a plurality of layers are stacked. The thickness of the second graphene insertion layer 720 may be from about 0.34nm to about 3nm. The second graphene insertion layer 720 may be an ohmic contact layer configured to provide an ohmic contact between the channel pattern 300 and the second source/drain electrode 220. The second graphene insertion layer 720 may be a diffusion barrier that limits and/or prevents the dopant of the channel pattern 300 from diffusing into the second source/drain electrode 220. For example, the second graphene insertion layer 720 may limit and/or prevent diffusion of P atoms and O atoms of the channel pattern 300.
The second graphene insertion layer 720 may extend to a region between the second source/drain electrode 220 and the passivation layer 600. According to an embodiment of the present disclosure, the second graphene insertion layer 720 may pass through at least one of a region between the first gate insulating layer 510 and the second source/drain electrode 220 and a region between the second gate insulating layer 520 and the second source/drain electrode 220. For example, the second graphene insertion layer 720 may directly contact at least one of the first gate insulating layer 510 and the second gate insulating layer 520. The second graphene insertion layer 720 may extend along surfaces (e.g., a bottom surface, a top surface, and two side surfaces opposite to each other) of the second source/drain electrode 220. The second graphene insertion layer 720 may surround the second source/drain electrode 220. The second source/drain electrode 220 and the passivation layer 600 may be spaced apart from each other by a second graphene insertion layer 720. The second graphene insertion layer 720 may limit and/or prevent diffusion (e.g., electromigration) of the material of the second source/drain electrode 220 into the passivation layer 600 between the second source/drain electrode 220 and the passivation layer 600. The second graphene insertion layer 720 may reduce the resistance of the second source/drain electrode 220 and improve process stability. The second graphene insertion layer 720 may be a cap layer covering the second source/drain electrode 220.
The present disclosure may provide a vertical channel transistor 11 in which an ohmic contact layer and a diffusion barrier layer between the channel pattern 300 and the source/ drain electrodes 210 and 220 and a cap layer covering the source/ drain electrodes 210 and 220 are graphene layers. In other words, the present disclosure may provide a vertical channel transistor 11 in which graphene is used for a junction between a conductor and a semiconductor, a junction between a conductor and an insulator, and a junction between a semiconductor and an insulator. When the ohmic contact layer, the diffusion barrier layer, and the cap layer include different materials, a plurality of deposition and patterning processes are required. According to the present disclosure, since the ohmic contact layer, the diffusion barrier layer, and the capping layer include graphene (e.g., nanocrystalline graphene), the entire manufacturing process may be simplified.
When the ohmic contact layer, the diffusion barrier layer, and the capping layer include different materials, degradation may occur due to mixing between components of the layers during deposition. Further, in the case of the double layer, unintended capacitance between layers may occur, and thus electrical noise, a transmission speed delay, and the like may occur. In other words, when the ohmic contact layer, the diffusion barrier layer, and the cap layer include different materials, crosstalk may occur between the ohmic contact layer, the diffusion barrier layer, and the cap layer.
In the present disclosure, since the ohmic contact layer, the diffusion barrier layer, and the capping layer include graphene (e.g., nanocrystalline graphene), cross-talk between the layers may be limited and/or prevented.
Fig. 2 is a cross-sectional view of a vertical channel transistor according to an example embodiment. For simplicity of description, a description substantially the same as the description given above with reference to fig. 1 may not be given.
Referring to fig. 2, a vertical channel transistor 12 may be provided. The vertical channel transistor 12 may include a substrate 100, a first source/drain electrode 210, a second source/drain electrode 220, a channel pattern 300, a first gate electrode 410, a second gate electrode 420, a first gate insulating layer 510, a second gate insulating layer 520, a passivation layer 600, a first graphene insertion layer 710, a second graphene insertion layer 720, a first additional source/drain electrode 810, and a second additional source/drain electrode 820.
The substrate 100, the first source/drain electrode 210, the second source/drain electrode 220, the channel pattern 300, the first gate electrode 410, the second gate electrode 420, the first gate insulating layer 510, the second gate insulating layer 520, the passivation layer 600, the first graphene insertion layer 710, and the second graphene insertion layer 720 may be substantially the same as those described above with reference to fig. 1.
A first additional source/drain electrode 810 may be provided between the first graphene insertion layer 710 and the channel pattern 300. The first additional source/drain electrode 810 may extend into a region between the first source/drain electrode 210 and the passivation layer 600. The first additional source/drain electrode 810 may pass through at least one of an area between the first gate insulating layer 510 and the first source/drain electrode 210 and an area between the second gate insulating layer 520 and the first source/drain electrode 210. According to an embodiment of the present disclosure, the first additional source/drain electrode 810 may directly contact at least one of the first and second gate insulating layers 510 and 520. The first additional source/drain electrode 810 may face the channel pattern 300, the first gate insulating layer 510, the second gate insulating layer 520, and the passivation layer 600 in the first direction DR 1. The first additional source/drain electrode 810 may include a material different from a material constituting the first source/drain electrode 210. For example, the first additional source/drain electrode 810 may include a doped semiconductor material (e.g., doped Si).
A second additional source/drain electrode 820 may be provided between the second graphene insertion layer 720 and the channel pattern 300. For example, the top and bottom surfaces of the second additional source/drain electrode 820 may directly contact the second graphene insertion layer 720 and the channel pattern 300, respectively. The side surface of the second additional source/drain electrode 820 may directly contact the passivation layer 600. Although fig. 2 illustrates that the second additional source/drain electrode 820 is not provided on the first and second gate insulating layers 510 and 520, the present disclosure is not limited thereto. According to another embodiment, the second additional source/drain electrode 820 may extend to a region on the first and second gate insulating layers 510 and 520. The second additional source/drain electrode 820 may include a material different from a material constituting the second source/drain electrode 220. For example, the second additional source/drain electrode 820 may include a doped semiconductor material (e.g., doped Si).
The present disclosure may provide a vertical channel transistor 12 in which graphene is used for the junction between the conductor and the semiconductor, the junction between the conductor and the insulator, and the junction between the semiconductor and the insulator.
Like the vertical channel transistor 11 described above with reference to fig. 1, 5A, and 5B, in some embodiments, the first gate electrode 410 and the second gate electrode 420 of the vertical channel transistor 12 may be connected to each other and provide one gate electrode (see fig. 5A), and the first gate insulating layer 510 and the second gate insulating layer 520 of the vertical channel transistor 12 may be connected to each other and provide one gate insulating layer (see fig. 5A). Alternatively, the first gate electrode 410 and the second gate electrode 420 of the vertical channel transistor 12 may be spaced apart from each other by the channel pattern 300 (see fig. 5B), and the first gate insulating layer 510 and the second gate insulating layer 520 of the vertical channel transistor 12 may be spaced apart from each other by the channel pattern 300 (see fig. 5B).
Fig. 3 is a cross-sectional view of a vertical channel transistor according to an example embodiment. For simplicity of description, a description substantially the same as the description given above with reference to fig. 1 may not be given.
Referring to fig. 3, a vertical channel transistor 13 may be provided. The vertical channel transistor 13 may include a substrate 100, a first source/drain electrode 210, a second source/drain electrode 220, a channel pattern 300, a first gate electrode 410, a second gate electrode 420, a first gate insulating layer 510, a second gate insulating layer 520, a passivation layer 600, a first graphene insertion layer 710, and a second graphene insertion layer 720.
The substrate 100, the first source/drain electrode 210, the second source/drain electrode 220, the channel pattern 300, the first gate electrode 410, the second gate electrode 420, the first gate insulating layer 510, the second gate insulating layer 520, and the first graphene insertion layer 710 may be substantially the same as those described above with reference to fig. 1.
The passivation layer 600 may include a first sub-passivation layer 610 and a second sub-passivation layer 620. The first sub-passivation layer 610 may be provided on a side surface of the channel pattern 300. The first sub-passivation layer 610 may cover the first gate electrode 410, the second gate electrode 420, the first gate insulating layer 510, and the second gate insulating layer 520. According to an embodiment of the present disclosure, the top surface of the first sub-passivation layer 610 and the top surface of the channel pattern 300 may be disposed at the same height from the top surface of the substrate 100.
The second sub-passivation layer 620 may be provided on the first sub-passivation layer 610. The second sub-passivation layer 620 may cover the second source/drain electrode 220. The first and second sub-passivation layers 610 and 620 may include an insulating material. For example, the first and second sub-passivation layers 610 and 620 may include silicon oxide (e.g., siO) 2 ) Silicon nitride (e.g., siN), and silicon oxynitride (e.g., siON). According to an embodiment of the present disclosure, the first sub-passivation layer 610 and the second sub-passivation layer 620 may include the same material.
The second graphene insertion layer 720 may extend to a region between the first sub-passivation layer 610 and the second sub-passivation layer 620. The first and second sub-passivation layers 610 and 620 may be spaced apart from each other by the second graphene insertion layer 720.
The present disclosure may provide a vertical channel transistor 13 in which graphene is used for a junction between a conductor and a semiconductor, a junction between a conductor and an insulator, and a junction between a semiconductor and an insulator.
Like the vertical channel transistor 11 described above with reference to fig. 1, 5A, and 5B, in some embodiments, the first gate electrode 410 and the second gate electrode 420 of the vertical channel transistor 13 may be connected to each other and provide one gate electrode (see fig. 5A), and the first gate insulating layer 510 and the second gate insulating layer 520 of the vertical channel transistor 13 may be connected to each other and provide one gate insulating layer (see fig. 5A). Alternatively, the first gate electrode 410 and the second gate electrode 420 of the vertical channel transistor 13 may be spaced apart from each other by the channel pattern 300 (see fig. 5B), and the first gate insulating layer 510 and the second gate insulating layer 520 of the vertical channel transistor 13 may be spaced apart from each other by the channel pattern 300 (see fig. 5B).
Fig. 4 is a cross-sectional view of a vertical channel transistor according to an example embodiment. For simplicity of description, a description substantially the same as the description given above with reference to fig. 1 may not be given.
Referring to fig. 4, a vertical channel transistor 14 may be provided. The vertical channel transistor 14 may include a substrate 100, a first source/drain electrode 210, a second source/drain electrode 220, a channel pattern 310, a gate electrode 400, a first gate insulating layer 510, a second gate insulating layer 520, a passivation layer 600, a first graphene insertion layer 710, a second graphene insertion layer 720, a first insulating pattern 910, and a second insulating pattern 920.
The substrate 100, the first source/drain electrode 210, the second source/drain electrode 220, the first gate insulating layer 510, the second gate insulating layer 520, the passivation layer 600, the first graphene insertion layer 710, and the second graphene insertion layer 720 may be substantially the same as those described above with reference to fig. 1.
The gate electrode 400 may be provided between the first gate insulating layer 510 and the second gate insulating layer 520. According to an embodiment of the present disclosure, a side surface of the gate electrode 400 may contact the first gate insulating layer 510, and the other side surface of the gate electrode 400 may contact the second gate insulating layer 520. In an embodiment of the present disclosure, the gate electrode 400 may be a gate electrode of a transistor device. The gate electrode 400 may include a conductive material. For example, the gate electrode 400 may include Au.
The first insulation pattern 910 may be provided between the gate electrode 400 and the first graphene insertion layer 710. The first insulation pattern 910 may electrically insulate the first graphene insertion layer 710 from the gate electrode 400. The first insulation pattern 910 may include an electrically insulating material. For example, the first insulation pattern 910 may include silicon oxide (e.g., siO) 2 ) Silicon nitride (e.g., siN), or silicon oxynitride (e.g., siON). According to an embodiment of the present disclosure, a side surface of the first insulation pattern 910 may contact the first gate insulation layer 510, and the other side surface of the first insulation pattern 910 may contact the second gate insulation layer 520.
The second insulating pattern 920 may be provided between the gate electrode 400 and the second graphene insertion layer 720. The second insulation pattern 920 may electrically insulate the second graphene insertion layer 720 from the gate electrode 400. The second insulation pattern 920 may include an electrically insulating material. For example, the second insulation pattern 920 may include silicon oxide (e.g., siO) 2 ) Silicon nitride (e.g., siN), or silicon oxynitride (e.g., siON). According to an embodiment of the present disclosure, a side surface of the second insulation pattern 920 may contact the first gate insulation layer 510, and the other side surface of the second insulation pattern 920 may contact the second gate insulation layer 520. According to an embodiment of the present disclosure, the top surface of the second insulation pattern 920 may be disposed at the same height from the top surface of the substrate 100 as the top surface of the first gate insulation layer 510 and the top surface of the second gate insulation layer 520.
The channel pattern 310 may extend along a surface of the first graphene insertion layer 710, a surface of the first gate insulating layer 510, a surface of the second insulating pattern 920, and a surface of the second gate insulating layer 520. The channel pattern 310 on the surface of the first graphene insertion layer 710, the surface of the first gate insulating layer 510, and the surface of the second gate insulating layer 520 may be located between the passivation layer 600 and the first graphene insertion layer 710, the first gate insulating layer 510, and the second gate insulating layer 520. On the second insulation pattern 920, the channel pattern 310 may be positioned between the second insulation pattern 920 and the second graphene insertion layer 720. The channels may be formed in the region opposite to the gate electrode 400 with respect to the first gate insulating layer 510 and the region opposite to the gate electrode 400 with respect to the second gate insulating layer 520, respectively. The channel pattern 310 may include a semiconductor material. For example, the channel pattern 310 may include Si, ge, or SiGe.
The present disclosure may provide a vertical channel transistor 14 in which graphene is used for the junction between the conductor and the semiconductor, the junction between the conductor and the insulator, and the junction between the semiconductor and the insulator.
However, the effect of the present disclosure is not limited thereto.
Fig. 6 and 7 are block diagrams of electronic systems according to some example embodiments.
Referring to fig. 6, in an example embodiment, electronic system 1000 may form a wireless communication device or a device capable of transmitting and/or receiving information in a wireless environment. Electronic system 1000 may include a controller 1010, an input/output (I/O) device 1020, a memory 1030, and a wireless interface 1040 connected to each other by a bus 1050.
The controller 1010 may include at least one selected from the group consisting of a microprocessor, a digital signal processor, and a processing device similar thereto. User commands may be input through I/O device 1020 for controller 1010, and I/O device 1020 may include at least one selected from the group consisting of a keypad, a keyboard, and a display. Memory 1030 may be used to store instructions that are executed by controller 1010. For example, memory 1030 may be used to store user data. Electronic system 1000 may send/receive data over a wireless communication network using wireless interface 1040. The wireless interface 1040 may include an antenna and/or a wireless transceiver. In some embodiments, electronic system 1000 may be used for communication interface protocols (e.g., second or third generation communication systems such as Code Division Multiple Access (CDMA), global system for mobile communication (GSM), north American Digital Cellular (NADC), extended time division multiple access (E-TDMA), and/or Wideband Code Division Multiple Access (WCDMA)), fourth generation communication systems such as 4G LTE, fifth generation communication systems, and so forth). The electronic system 1000 may include at least one of the vertical channel transistors 11 to 14 according to the various embodiments described above. For example, the memory 1030 and/or the controller 1010 may include at least one of the vertical channel transistors 11 to 14 described with reference to fig. 1 to 5B.
Referring to fig. 7, in an example embodiment, an electronic system 1100 may include a memory 1110 and a memory controller 1120. The memory controller 1120 may control the memory 1110 to read data from the memory 1110 and/or write data to the memory 1110 in response to a request from the host 1130. At least one of the memory 1110 and the memory controller 1120 may include at least one of the vertical channel transistors 11 to 14 described with reference to fig. 1 to 5B according to various embodiments.
FIG. 8 is a diagram of an electronic circuit according to an example embodiment.
The electronic circuit 1200 may include a CMOS transistor 1210.CMOS transistor 1210 may include a p-channel transistor 1220 and an n-channel transistor 1230 connected between a power supply terminal Vdd and a ground terminal. The CMOS transistor 1210 may include at least one of the vertical channel transistors 11, 12, 13, and 14 according to the various embodiments described above.
One or more of the above disclosed elements may include or be implemented as: processing circuitry, such as hardware including logic circuitry; a hardware/software combination, such as a processor running software; or a combination thereof. For example, the processing circuitry may more particularly include, but is not limited to, a Central Processing Unit (CPU), an Arithmetic Logic Unit (ALU), a digital signal processor, a microcomputer, a Field Programmable Gate Array (FPGA), a system on a chip (SoC), a programmable logic unit, a microprocessor, an Application Specific Integrated Circuit (ASIC), and so forth.
It should be understood that the embodiments described herein should be considered in a descriptive sense only and not for purposes of limitation. Descriptions of features or aspects within each embodiment should generally be considered as available for other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the inventive concept as defined by the following claims.
This application is based on and claims priority from korean patent application No. 10-2021-0121173, filed on korean intellectual property office on 10/9/2021, the disclosure of which is incorporated herein by reference in its entirety.

Claims (20)

1. A vertical channel transistor, comprising:
a first source/drain electrode;
a second source/drain electrode spaced apart from the first source/drain electrode in a first direction;
a first channel pattern between the first source/drain electrode and the second source/drain electrode;
a first gate electrode on a side surface of the first channel pattern;
a first gate insulating layer between the first channel pattern and the first gate electrode; and
a first graphene insertion layer between the first source/drain electrode and the first channel pattern.
2. The vertical channel transistor of claim 1,
wherein a part of a surface of the first source/drain electrode faces a surface of the first gate insulating layer in the first direction,
the first graphene insertion layer extends in the second direction between the first gate insulating layer and the first source/drain electrode, and
the second direction intersects the first direction.
3. The vertical channel transistor of claim 1, further comprising:
a first additional source/drain electrode between the first graphene insertion layer and the first channel pattern,
wherein the first source/drain electrode and the first additional source/drain electrode comprise different materials from each other.
4. The vertical channel transistor of claim 3,
wherein a part of a surface of the first additional source/drain electrode faces a surface of the first gate insulating layer in the first direction, and
the first additional source/drain electrode directly contacts the first gate insulating layer.
5. The vertical channel transistor of claim 1, further comprising:
a second graphene insertion layer between the second source/drain electrode and the first channel pattern.
6. The vertical channel transistor of claim 5,
wherein at least one of the first graphene insertion layer and the second graphene insertion layer has a thickness of 0.34nm to 3nm.
7. The vertical channel transistor of claim 5,
wherein at least one of the first graphene insertion layer and the second graphene insertion layer comprises crystals having a size from 0.5nm to 100 nm.
8. The vertical channel transistor of claim 5,
wherein a proportion of carbon atoms having an sp2 bonding structure to all carbon atoms in at least one of the first graphene insertion layer and the second graphene insertion layer is 50% to 99%.
9. The vertical channel transistor of claim 5,
wherein at least one of the first graphene insertion layer and the second graphene insertion layer has a density of 1.6g/cc to 2.1 g/cc.
10. The vertical channel transistor of claim 5,
wherein the second graphene insertion layer surrounds the second source/drain electrode.
11. The vertical channel transistor of claim 1,
wherein the first gate insulating layer surrounds a side surface of the first channel pattern, an
The first gate electrode extends along the first gate insulating layer and surrounds the first channel pattern.
12. The vertical channel transistor of claim 1, further comprising:
a second gate electrode facing the first gate electrode with the first channel pattern interposed therebetween; and
a second gate insulating layer between the second gate electrode and the first channel pattern.
13. The vertical channel transistor of claim 1, further comprising:
a passivation layer on the first source/drain electrode, the passivation layer covering the second source/drain electrode,
wherein a portion of the first graphene insertion layer is between the passivation layer and the first source/drain electrode.
14. The vertical channel transistor of claim 13, further comprising:
a second graphene insertion layer between the second source/drain electrode and the first channel pattern,
wherein a portion of the second graphene insertion layer is between the passivation layer and the second source/drain electrode.
15. The vertical channel transistor of claim 1, further comprising:
a second channel pattern provided opposite to the first channel pattern with the first gate electrode interposed therebetween; and
a second gate insulating layer between the first gate electrode and the second channel pattern,
wherein the first channel pattern and the second channel pattern are in a region where the first source/drain electrode and the second source/drain electrode face each other in the first direction.
16. The vertical channel transistor of claim 15, further comprising:
a second graphene insertion layer between the second source/drain electrode and the first channel pattern;
a first insulating pattern between the first gate electrode and the first graphene insertion layer;
a second insulating pattern between the first gate electrode and the second graphene insertion layer; and
a third channel pattern between the second graphene insertion layer and the second insulation pattern,
wherein the first channel pattern, the second channel pattern, and the third channel pattern constitute a single structure.
17. A vertical channel transistor, comprising:
a first source/drain electrode;
a channel pattern on the first source/drain electrode;
a second source/drain electrode on the channel pattern, the second source/drain electrode being spaced apart from the first source/drain electrode in a first direction;
a first graphene insertion layer between the first source/drain electrode and the channel pattern;
a gate electrode over and spaced apart from the first source/drain electrode in the first direction; and
and a gate insulating layer between the gate electrode and the channel pattern on sidewalls of the channel pattern.
18. The vertical channel transistor of claim 17, wherein
The channel pattern is between the first source/drain electrode and the second source/drain electrode.
19. The vertical channel transistor of claim 17, further comprising:
a second graphene insertion layer on the second source/drain electrode, wherein
A surface of the second graphene insertion layer faces a surface of the first source/drain electrode.
20. The vertical channel transistor of claim 17, wherein the gate electrode is between the first source/drain electrode and a portion of the channel pattern.
CN202210498032.3A 2021-09-10 2022-05-09 Vertical channel transistor Pending CN115799297A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020210121173A KR20230037988A (en) 2021-09-10 2021-09-10 Vertical channel transistor
KR10-2021-0121173 2021-09-10

Publications (1)

Publication Number Publication Date
CN115799297A true CN115799297A (en) 2023-03-14

Family

ID=82850078

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202210498032.3A Pending CN115799297A (en) 2021-09-10 2022-05-09 Vertical channel transistor

Country Status (4)

Country Link
US (1) US20230081960A1 (en)
EP (1) EP4148803A1 (en)
KR (1) KR20230037988A (en)
CN (1) CN115799297A (en)

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20130006999A (en) * 2011-06-28 2013-01-18 삼성디스플레이 주식회사 Thin film transistor and method of manufacturing the same
US11211487B2 (en) * 2019-08-15 2021-12-28 Micron Technology, Inc. Transistors, memory structures and memory arrays containing two-dimensional materials between a source/drain region and a channel region

Also Published As

Publication number Publication date
KR20230037988A (en) 2023-03-17
EP4148803A1 (en) 2023-03-15
US20230081960A1 (en) 2023-03-16

Similar Documents

Publication Publication Date Title
US10727348B2 (en) Semiconductor device with adjacent source/drain regions connected by a semiconductor bridge, and method for fabricating the same
US8643087B2 (en) Reduced leakage memory cells
US10868246B2 (en) Conductive bridge random access memory (CBRAM) devices with low thermal conductivity electrolyte sublayer
US8637927B2 (en) Semiconductor devices and methods of forming the same
EP3644367B1 (en) 3d memory array with memory cells having a 3d selector and a storage component
US11145660B2 (en) Dual-port SRAM cell structure
US10043813B2 (en) Method of manufacturing semiconductor device
CN111199973A (en) Semiconductor device with a plurality of transistors
US20220384311A1 (en) Semiconductor device and method for fabricating the same
US20240170427A1 (en) Memory devices and related electronic systems
US20230081960A1 (en) Vertical channel transistor
US20230035916A1 (en) Semiconductor device and method for fabricating the same
KR20230036887A (en) Semiconductor element, electronic system including the semiconductor element, and method for fabricating the semiconductor element
CN114678356A (en) Semiconductor device with a plurality of transistors
CN113130476A (en) Semiconductor device structure with multiple gate terminals and method of forming the same
US20240162350A1 (en) Semiconductor device and method of manufacturing the same
US11955561B2 (en) Carrier modification devices for avoiding channel length reduction and methods for fabricating the same
US20240090206A1 (en) Microelectronic devices, and related memory devices, electronic systems, and methods
US20230146530A1 (en) Integrated circuit device
US20220415775A1 (en) Semiconductor package
US20230070355A1 (en) Layer structure including metal layer and carbon layer, method of manufacturing the layer structure, electronic device including the layer structure, and electronic apparatus including the electronic device
CN117855248A (en) Semiconductor device with a semiconductor layer having a plurality of semiconductor layers
KR20210008882A (en) Semiconductor memory device
CN115910926A (en) Semiconductor device with a plurality of transistors
CN116093107A (en) Semiconductor device with a semiconductor device having a plurality of semiconductor chips

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication