CN115799103A - Defect detection method - Google Patents
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- CN115799103A CN115799103A CN202310046257.XA CN202310046257A CN115799103A CN 115799103 A CN115799103 A CN 115799103A CN 202310046257 A CN202310046257 A CN 202310046257A CN 115799103 A CN115799103 A CN 115799103A
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Abstract
The invention provides a defect detection method, which comprises the following steps: providing a wafer to be detected with an insulating dielectric layer and a patterned metal layer; performing first defect scanning on the surface of the patterned metal layer to obtain a first scanning image, and determining defect position information of the surface of the patterned metal layer according to the first scanning image; and performing second defect scanning on the exposed part of the insulating medium layer of the patterned metal layer to obtain a second scanning image, and determining the defect position information of the bottom of the patterned metal layer according to the second scanning image. According to the defect detection method, before or after the conventional first defect scanning is carried out on the surface of the patterned metal layer, the second defect scanning is carried out on the bottom of the patterned metal layer, and the second defect scanning can be used for carrying out automatic on-line detection on the bottom internal contact defect of the patterned metal layer, so that the problem that the bottom internal contact defect is difficult to detect in the conventional detection method is solved, the detection efficiency is improved, and the wafer yield is ensured.
Description
Technical Field
The field relates to the technical field of semiconductor integrated circuits, in particular to a defect detection method.
Background
A top metal aluminum process is used to form top aluminum interconnects, which are typically formed by etching an aluminum metal layer. During the process of etching the aluminum metal layer, a recessed structural defect is easily generated at the bottom of the aluminum interconnection line due to lateral etching (also called as under cut). Fig. 1 is a Transmission Electron Microscope (TEM) diagram of a bottom internal tangent defect generated in a top metal aluminum process, and fig. 1 shows that when an aluminum metal layer deposited on a bottom structure layer 01 is etched to form an aluminum metal wire 02, a bottom internal tangent defect 03 with critical dimensions of 300nm to 400nm is formed at the bottom of the aluminum metal wire due to a lateral etching effect. The larger the etch bias, the larger the bottom-side-cut defect 03 critical dimension when the aluminum layer is thicker. The bottom internal tangent defect of the key size of 300nm to 400nm shown in fig. 1 affects the stability of the aluminum interconnection line, and finally, the aluminum interconnection line is peeled off, so that the device fails. In the prior art, means for detecting bottom internal defects include slice Analysis performed in Failure Analysis (Failure Analysis) stage and local electron microscopy (e.g., focused ion beam microanalysis, FIB). However, these inspection methods require manual intervention, are time consuming, cannot perform on-line inspection on multiple lots and multiple wafers, and have a large impact on the wafer device area, which may result in yield loss of the wafers.
Optical or electron beam defect inspection methods in the industry can automatically detect defects on the wafer surface on-line (inline). The defect detection process comprises the following steps: firstly, scanning the surface of a wafer to be detected by a defect scanning (defect scan) machine to obtain defect position information; and then transmitting the defect position information to a defect review (defect review) machine, shooting the structure of the position of the defect by the defect review machine according to the defect position information to obtain a defect image (image), and processing and analyzing the defect image to determine the truth, the type and the influence of the defect as a judgment basis for performing subsequent yield analysis. The working principle of the scanner is to scan the surface of the wafer to be detected by optical detection, compare the acquired digital scanning image signals with adjacent chips (die to die), compare the comparison result with a preset threshold value, and leave the defect position exceeding the threshold value. The defect detection method can overcome the defects of the slicing analysis method, the electron microscope analysis method and the like, and has the advantages of automatic online detection, high efficiency, no influence on the yield of the wafer to be detected and the like. However, in the conventional defect detection method, when the defect of the top aluminum interconnection line is detected, the defect scan is generally performed only on the upper surface of the aluminum interconnection line to detect the defect information of the upper surface of the aluminum interconnection line. The detection method can not obtain the information of the bottom of the aluminum interconnection line, so that the internally tangent defect of the bottom of the aluminum interconnection line can not be detected. Therefore, improvement on the existing defect detection method is urgently needed to solve the problem that the existing defect detection method cannot detect the internal contact defect at the bottom of the aluminum interconnection line.
Disclosure of Invention
In order to solve the problem that the existing defect detection method cannot detect the bottom internal cutting defect of the aluminum interconnection line, the invention provides a defect detection method, which comprises the following steps:
providing a wafer to be detected, wherein the wafer to be detected comprises an insulating medium layer and a patterned metal layer formed on the insulating medium layer, and the patterned metal layer exposes part of the insulating medium layer;
performing first defect scanning on the surface of the patterned metal layer to obtain a first scanning image, and determining defect position information of the surface of the patterned metal layer according to the first scanning image;
and performing secondary defect scanning on the exposed part of the insulating medium layer of the patterned metal layer to obtain a second scanning image, and determining defect position information of the bottom of the patterned metal layer according to the second scanning image.
Preferably, the bottom defects of the patterned metal layer comprise bottom undercut defects.
Preferably, the patterned metal layer includes a plurality of metal lines arranged at intervals.
Preferably, the patterned metal layer includes a patterned Al layer, and the patterned Al layer is formed by an Al etching process.
Preferably, the wafer to be detected comprises a silicon wafer; and/or the insulating medium layer comprises SiO 2 And (3) a layer.
Preferably, the first defect scan and the second defect scan comprise bright field scans.
Preferably, the wafer to be detected comprises a plurality of chip units, and the structures of the plurality of chip units are the same.
Preferably, the first scan image includes a first image block of a plurality of chip units, and the method of determining the defect location information of the surface of the patterned metal layer according to the first scan image includes: setting a first defect threshold corresponding to the surface of the patterned metal layer; performing superposition cancellation on first image blocks of adjacent chip units to obtain comparison image blocks, and determining defect signal values of corresponding chip units according to the key size or area of the comparison image blocks; and when the defect signal value of the chip unit is larger than the first defect threshold value, judging the position corresponding to the comparison image block as a defect position, and recording the information of the defect position.
Preferably, the second scan image includes a second image block of the plurality of chip units, and the method of determining the defect location information of the bottom of the patterned metal layer according to the second scan image includes: setting a second defect threshold corresponding to the bottom of the patterned metal layer; performing superposition cancellation on second image blocks of adjacent chip units to obtain comparison image blocks, and determining defect signal values of the corresponding chip units according to the key size or area of the comparison image blocks; and when the defect signal value of the chip unit is larger than the first defect threshold value, judging the position corresponding to the comparison image block as a defect position, and recording the information of the defect position.
Preferably, the defect position information includes position coordinate information of the defect in the wafer to be detected and position coordinate information of the defect in the single chip unit.
Compared with the prior art, the defect detection method provided by the invention has the following advantages:
according to the defect detection method provided by the invention, before or after the conventional first defect scanning is carried out on the surface of the patterned metal layer, the second defect scanning is additionally carried out on the bottom of the patterned metal layer, the first defect scanning can effectively detect the surface defects of the patterned metal layer, and the second defect scanning can detect the bottom defects of the patterned metal layer, so that the problem that the bottom inscribe defects of the patterned metal layer are difficult to detect in the existing detection method is solved; the detection method provided by the invention can realize automatic online detection of the bottom internal contact defect, and can improve the detection efficiency and ensure the yield of wafers compared with the existing method for detecting the bottom internal contact defect through section analysis and electron microscope analysis.
Drawings
FIG. 1 is a transmission electron microscope image of a bottom inscribed defect generated in a top layer aluminum metal process;
FIG. 2 is a flowchart illustrating steps of a defect detection method according to an embodiment of the invention;
fig. 3 is a schematic structural diagram of a wafer to be tested according to an embodiment;
FIG. 4 is a schematic diagram illustrating a first defect scan in the defect detection method according to an embodiment;
FIG. 5 is a first scanned image obtained by a first defect scan in the defect detection method according to an embodiment;
FIG. 6 is a diagram illustrating a second defect scan in the defect detection method according to an embodiment;
fig. 7 is a second scanned image obtained by a second defect scan in the defect detection method according to an embodiment;
fig. 8 is a schematic diagram illustrating a comparative image block obtained in a defect detection method according to an embodiment;
wherein the reference numerals are as follows:
in FIG. 1, 01-bottom structural layer; 02-aluminum metal wire; 03-bottom inscribed defects;
in fig. 3 to 8, 1-wafer to be detected; 11-insulating dielectric layer; 12-patterning a metal layer; 121-a first metal line; 122-a second metal line; 13-bottom inscribed defects; 20-reflected light; 3-bright field scanning machine; 31-a condenser; 32-a mirror; 33-an optical detector; 1211-a block of surface images of the first metal line; 1221 — a surface image block of a second metal line; 1212-bottom image block of first metal line; 1222-bottom image block of second metal line; 120-contrast image block.
Detailed Description
To make the objects, advantages and features of the present invention more apparent, a defect detecting method provided by the present invention is further described in detail below with reference to the accompanying drawings. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Referring to fig. 2, a defect detection method provided by the present invention includes the following steps:
step S1: providing a wafer to be detected, wherein the wafer to be detected comprises an insulating medium layer and a patterned metal layer formed on the insulating medium layer, and part of the insulating medium layer is exposed out of the patterned metal layer;
step S2: performing first defect scanning on the surface of the patterned metal layer to obtain a first scanning image, and determining defect position information of the surface of the patterned metal layer according to the first scanning image;
and step S3: and performing second defect scanning on the exposed part of the insulating medium layer of the patterned metal layer to obtain a second scanning image, and determining defect position information of the bottom of the patterned metal layer according to the second scanning image.
Referring to fig. 3, step S1 is executed to provide a wafer 1 to be detected, where the wafer 1 to be detected includes an insulating dielectric layer 11 and a patterned metal layer 12 formed on the insulating dielectric layer 11, and the patterned metal layer exposes a portion of the insulating dielectric layer 11.
In this embodiment, the wafer 1 to be detected preferably includes a silicon wafer, but is not limited thereto, and may be other semiconductor wafers; the insulating medium layer 11 comprises SiO 2 The layer is not limited thereto, but may be other suitable dielectric layers.
In the present embodiment, the patterned metal layer 12 is preferably a patterned Al layer, and the patterned Al layer may be formed by an Al etching process. The patterned metal layer 12 includes a plurality of metal lines arranged at intervals, in this embodiment, the metal lines may include a first metal line 121 and a second metal line 122, the critical dimensions of the first metal line 121 and the second metal line 122 are the same, and the only difference is that the second metal line 122 has an undercut defect 13 formed at the bottom, and the first metal line 121 does not have an undercut defect formed at the bottom. It is understood that the patterned metal layer 12 may include a plurality of first metal lines 121 and a plurality of second metal lines 122, and for clarity and simplicity of the drawing, only one first metal line 121 and one second metal line 122 are schematically illustrated in fig. 3.
In this embodiment, the wafer 1 to be detected includes a plurality of chip units (not shown in fig. 3), the plurality of chip units have the same structure (do not include a defect structure), each chip unit at least includes one first metal line 121 or one second metal line 122, and further includes a part of the insulating dielectric layer 11. For convenience of explanation, the first metal line 121 and the second metal line 122 shown in fig. 3 respectively belong to two adjacent chip units and correspond to the same position in the two adjacent chip units.
Referring to fig. 4 and 5, step S2 is performed to perform a first defect scan on the surface of the patterned metal layer 12 to obtain a first scan image, and determine defect position information of the surface of the patterned metal layer 12 according to the first scan image.
The first defect scan is used to capture the defect locations on the surface of the patterned metal layer 12. Fig. 4 is a schematic diagram of a first defect scan, which is preferably a bright field scan, and the bright field scan can be performed in a bright field scanner. The bright field scanner stage 3 at least includes a light source (not shown in fig. 4), a condenser 31, a reflector 32, and an optical detector 33. During the first defect scanning, the light source is focused on the surface of the patterned metal layer 12, and the reflected light 20 is generated from the surface, and the reflected light 20 is converged by the condenser lens 31, then turned by the reflector 32, and finally collected by the optical detector 33 to form the first scanned image.
The method for determining the position information of the surface defect of the patterned metal layer 12 according to the first scanned image may refer to the prior art, for example, a conventional method for comparing adjacent chips may be adopted to determine the defect position information, and specifically may include the following steps:
setting a first defect threshold corresponding to the surface of the patterned metal layer 12; performing superposition cancellation on first image blocks of adjacent chip units to obtain comparison image blocks, and determining defect signal values of corresponding chip units according to the key size or area of the comparison image blocks; and when the defect signal value of the chip unit is larger than the first defect threshold, judging the position corresponding to the comparison image block as a defect position, and recording the information of the defect position. The first image block of each chip unit and the first image block of the adjacent chip unit can be subjected to superposition cancellation and judgment in sequence, and finally, the defect position information of the surface of the patterned metal layer on the whole wafer 1 to be detected can be obtained according to the defect position information of the chip units. The defect position information comprises position coordinate information of the defect in the wafer to be detected and position coordinate information of the defect in a single chip unit.
Referring to fig. 5, fig. 5 is a schematic diagram illustrating a first scanned image according to the present embodiment. In this embodiment, the wafer to be detected includes a plurality of chip units, the first scan image includes a first image block of the plurality of chip units, and the first image block at least includes the image block 1211 or the image block 1221. The image blocks 1211 and 1221 are surface image blocks of the first metal line 121 and the second metal line 122, respectively. In the present embodiment, the image block 1211 and the image block 1221 belong to two adjacent chip units, respectively.
In this embodiment, the surfaces of the first metal line 121 and the second metal line 122 have no defect, the image block 1211 and the image block 1221 are completely the same, and the contrast image block formed by the superposition and cancellation of the image block 1211 and the image block 1221 does not display a defect signal. In other embodiments, the surface of the first metal line 121 or the second metal line 122 has a defect, the image block 1211 and the image block 1221 are not identical, and the contrast image block formed by the superposition and cancellation of the image block 1211 and the image block 1221 displays a defect signal. A defect signal value may be determined according to the critical dimension or area of the contrast image block, and when the defect signal value exceeds the first defect threshold, the surface position of the first metal line 121 or the second metal line 122 may be determined as a defect position.
Referring to fig. 6 and 7, step S3 is performed to perform a second defect scanning on the exposed portion of the insulating medium layer 11 of the patterned metal layer 12 to obtain a second scanning image, and determine defect position information of the bottom of the patterned metal layer according to the second scanning image.
The second defect scan is used to capture the defect locations at the bottom of the patterned metal layer 12. Fig. 6 is a schematic diagram of the second defect scanning, which is preferably a bright field scanning, and the bright field scanning can be performed in the bright field scanner 3. The bright field scanner stage 3 at least includes a light source (not shown in fig. 6), a condenser 31, a reflector 32, and an optical detector 33. During the second defect scanning, the light source is focused on the surface of the insulating medium layer 11 where the patterned metal layer 12 remains, so as to obtain a bottom image of the patterned metal layer 12. And generating reflected light 20 from the surface of the insulating medium layer 11, wherein the reflected light 20 is converged by the condenser lens 31, then is turned by the reflector 32, and is finally collected by the optical detector 33 to form the second scanning image.
As well as determining the location information of the surface defects of the patterned metal layer 12 from the first scan image, the method of determining the location information of the bottom defects of the patterned metal layer 12 from the second scan image may comprise the steps of:
setting a second defect threshold corresponding to the bottom of the patterned metal layer; performing superposition cancellation on second image blocks of adjacent chip units to obtain comparison image blocks, and determining defect signal values of corresponding chip units according to the key size or area of the comparison image blocks; and when the defect signal value of the chip unit is greater than the second defect threshold, judging the position corresponding to the contrast image block as a defect position, and recording the information of the defect position. The second image block of each chip unit and the second image block of the adjacent chip unit can be subjected to superposition cancellation and judgment in sequence, and finally the defect position information of the bottom of the patterned metal layer on the whole wafer 1 to be detected can be obtained according to the defect position information of the chip units. The defect position information comprises position coordinate information of the defect in the wafer to be detected and position coordinate information of the defect in a single chip unit.
In this embodiment, the second scan image is as shown in fig. 7, in this embodiment, the wafer to be detected includes a plurality of chip units, the second scan image includes a second image block of the plurality of chip units, the second image block includes at least an image block 1212 or an image block 1222, where the image block 1212 and the image block 1222 are bottom image blocks of the first metal line 121 and the second metal line 122, respectively, and in this embodiment, the image block 1212 and the image block 1222 belong to two adjacent chip units, respectively.
In this embodiment, the second metal line 122 has an undercut defect 13, and the first metal line 121 does not have an undercut defect, and correspondingly, the width of the bottom tile 1222 of the second metal line 122 is smaller than the width of the bottom tile 1212 of the first metal line 121. Thus, contrast image block 120 resulting from the superposition cancellation of image block 1212 and image block 1222 will appear as stripes as shown in FIG. 8. A defect signal value may be determined according to the critical dimension or area of the contrast image block, and when the defect signal value exceeds the second defect threshold, the position of the second metal line 122 may be determined as a defect position. Further, the critical dimension of the contrast image block 120 corresponds to the critical dimension of the bottom inscribed defect 13, so that the second defect scanning can obtain not only the corresponding defect position information, but also the critical dimension information of the bottom inscribed defect 13 through the contrast image block 120, and the workload of the subsequent rechecking step can be reduced.
During the second defect scanning, the light source is focused on the surface of the insulating medium layer 11, and since the surface of the insulating medium layer 11 has a small reflectivity to light and the intensity of the reflected light 20 is smaller than the intensity of the reflected light 20 during the first defect scanning, the intensity of the light source during the second defect scanning is preferably greater than the intensity of the light source during the first defect scanning, so as to improve the quality of the second scanned image formed by the second defect scanning.
It should be noted that the order of the step S2 and the step S3 may be exchanged, for example, in another embodiment, the step S3 may be performed first, and then the step S2 may be performed.
In summary, the defect detection method provided by the present invention adds a second defect scan to the bottom of the patterned metal layer before or after performing a conventional first defect scan to the surface of the patterned metal layer, where the first defect scan can effectively detect the surface defects of the patterned metal layer, and the second defect scan can detect the bottom defects of the patterned metal layer, thereby solving the problem that the bottom cut defects of the patterned metal layer are difficult to detect in the existing detection method; the detection method provided by the invention can realize automatic on-line detection of the bottom internal contact defect, and can improve the detection efficiency and ensure the yield of the wafer compared with the existing method for detecting the bottom internal contact defect through slice analysis and electron microscope analysis.
In addition, it is to be understood that while the present invention has been described in conjunction with the preferred embodiments thereof, it is not intended to limit the invention to the same. It will be apparent to those skilled in the art from this disclosure that many changes and modifications can be made, or equivalents modified, in the embodiments of the invention without departing from the scope of the invention. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are within the scope of the technical solution of the present invention, unless the technical essence of the present invention is not departed from the content of the technical solution of the present invention. It is to be further understood that the present invention is not limited to the particular methodology, compounds, materials, manufacturing techniques, uses, and applications described herein, as such may, of course, vary. It is also to be understood that the terminology used herein is for the purpose of describing particular embodiments only, and is not intended to limit the scope of the present invention. It must be noted that, as used herein and in the appended claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. Thus, for example, reference to "a step" means a reference to one or more steps and may include sub-steps. All conjunctions used should be understood in the broadest sense. Thus, the word "or" should be understood to have the definition of a logical "or" rather than the definition of a logical "exclusive or" unless the context clearly dictates otherwise. Structures described herein are to be understood as also referring to functional equivalents of such structures. Language that can be construed as approximate should be understood as such unless the context clearly dictates otherwise.
Claims (10)
1. A method of defect detection, comprising the steps of:
providing a wafer to be detected, wherein the wafer to be detected comprises an insulating medium layer and a patterned metal layer formed on the insulating medium layer, and part of the insulating medium layer is exposed out of the patterned metal layer;
performing first defect scanning on the surface of the patterned metal layer to obtain a first scanning image, and determining defect position information of the surface of the patterned metal layer according to the first scanning image;
and performing second defect scanning on the exposed part of the insulating medium layer of the patterned metal layer to obtain a second scanning image, and determining defect position information of the bottom of the patterned metal layer according to the second scanning image.
2. The defect detection method of claim 1, wherein the bottom defects of the patterned metal layer comprise bottom inscribed defects.
3. The defect detection method of claim 1, wherein the patterned metal layer comprises a plurality of metal lines arranged at intervals.
4. The defect detection method of claim 1, wherein the patterned metal layer comprises a patterned Al layer formed by an Al etching process.
5. The defect detection method of claim 1, wherein the wafer to be detected comprises a silicon wafer; and/or the insulating medium layer comprises SiO 2 A layer.
6. The defect detection method of claim 1 wherein said first defect scan and said second defect scan comprise bright field scans.
7. The defect detection method of claim 1, wherein the wafer to be detected comprises a plurality of chip units, and the plurality of chip units have the same structure.
8. The defect detection method of claim 7, wherein the first scan image comprises a first image block of the plurality of chip units, and the method of determining defect location information of the surface of the patterned metal layer from the first scan image comprises:
setting a first defect threshold corresponding to the surface of the patterned metal layer;
carrying out superposition cancellation on first image blocks of adjacent chip units to obtain contrast image blocks, and determining defect signal values of corresponding chip units according to the key size or area of the contrast image blocks;
and when the defect signal value of the chip unit is larger than the first defect threshold, judging the position corresponding to the comparison image block as a defect position, and recording the information of the defect position.
9. The defect detection method of claim 7, wherein the second scan image comprises a second image patch of the plurality of chip units, and wherein determining the defect location information of the bottom portion of the patterned metal layer from the second scan image comprises:
setting a second defect threshold corresponding to the bottom of the patterned metal layer;
performing superposition cancellation on second image blocks of adjacent chip units to obtain comparison image blocks, and determining defect signal values of corresponding chip units according to the key size or area of the comparison image blocks;
and when the defect signal value of the chip unit is larger than the second defect threshold, judging the position corresponding to the comparison image block as a defect position, and recording the information of the defect position.
10. The defect detection method of claim 7, wherein the defect location information comprises location coordinate information of the defect in the wafer to be detected and location coordinate information of the defect in a single chip unit.
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