CN115798560A - Test method and test device for semiconductor structure - Google Patents
Test method and test device for semiconductor structure Download PDFInfo
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- CN115798560A CN115798560A CN202111055312.9A CN202111055312A CN115798560A CN 115798560 A CN115798560 A CN 115798560A CN 202111055312 A CN202111055312 A CN 202111055312A CN 115798560 A CN115798560 A CN 115798560A
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Abstract
The application relates to a test method and a test device of a semiconductor structure. The method for testing the semiconductor structure comprises the following steps: providing a storage array, wherein the storage array comprises a plurality of storage units, a plurality of word lines and a plurality of bit lines which are arranged in an array manner, and the plurality of bit lines are electrically connected with a plurality of sense amplifiers; executing the following first circulation step for multiple times until all the storage units in the storage array are full of 0; the first cycle step includes: selecting a word line as a first target word line, and starting the first target word line; starting a sensing amplifier after delaying a first preset time from the start of a first target word line; and after the first target word line is started and the second preset time is delayed, the first target word line and the sense amplifier are closed, and the next word line adjacent to the first target word line is used as the first target word line of the next first circulation step. The method and the device improve the accuracy and the detection efficiency of the short-circuit defect detection between the word line and the bit line.
Description
Technical Field
The present disclosure relates to the field of integrated circuit technologies, and in particular, to a method and an apparatus for testing a semiconductor structure.
Background
Dynamic Random Access Memory (DRAM) is a semiconductor device commonly used in electronic devices such as computers, and is composed of a plurality of Memory cells, each of which typically includes a transistor and a capacitor. The transistor has a gate electrically connected to a word line, a source electrically connected to a bit line, and a drain electrically connected to the capacitor, and a word line voltage on the word line can control the transistor to be turned on and off, so that data information stored in the capacitor can be read or written through the bit line.
A semiconductor structure such as a dynamic random access memory includes a word line and a bit line. Most of the Word lines currently adopt a Buried Word Line (BWL), and the bit lines are electrically connected to the sources of the transistors through bit Line plugs. Due to process variations, a short circuit between the embedded word Line and the Bit Line Contact plug (BLC) may be caused, which may generate a defect (Cross fail). The short circuit between the embedded word line and the bit line contact plug can cause the failure of the bit line, and seriously affect the electrical performance of the semiconductor structure. However, there is currently no effective method for detecting a short defect between the buried word line and the bit line contact plug, thereby limiting the improvement of the semiconductor structure.
Therefore, how to effectively detect the short circuit defect between the word line and the bit line and improve the electrical performance of the semiconductor structure is a technical problem to be solved.
Disclosure of Invention
Some embodiments of the present application provide a method and an apparatus for testing a semiconductor structure, which are used to solve the problem that a short defect between a word line and a bit line cannot be effectively detected, so as to improve the electrical performance of the semiconductor structure.
According to some embodiments, the present application provides a method of testing a semiconductor structure, comprising the steps of:
providing a storage array, wherein the storage array comprises a plurality of storage units arranged in an array, a plurality of word lines arranged in parallel along a first direction, and a plurality of bit lines arranged in parallel along a second direction, the plurality of bit lines are electrically connected with a plurality of sense amplifiers, and the first direction is intersected with the second direction;
executing the following first circulation step for multiple times until all the memory cells in the memory array are full of 0;
the first loop step includes:
selecting a word line as a first target word line, and starting the first target word line;
starting the induction amplifier after delaying a first preset time from the start of the first target word line;
and after the first target word line is started and the second preset time is delayed, the first target word line and the sense amplifier are closed, and the next word line adjacent to the first target word line is used as the first target word line of the next first circulation step.
In some embodiments, before the step of executing the loop, the method further comprises the steps of:
writing all the memory cells in the memory array with 0;
the memory array is refreshed.
In some embodiments, before executing the loop step, the step of writing all of the memory cells in the memory array with 0 includes:
executing the following second loop steps for multiple times until all the memory cells in the memory array are full of 0, wherein the second loop steps comprise:
selecting a word line as a second target word line, and starting the second target word line;
sequentially writing 0 to all the memory cells connected with the second target word line;
and closing the second target word line, and taking the next word line adjacent to the second target word line as the second target word line of the next second circulation step.
In some embodiments, the first cycling step comprises:
selecting a bit line as a target bit line, and starting the target bit line;
sequentially executing a first sub-cycle step on a plurality of word lines;
closing the target bit line, and taking the next bit line adjacent to the target bit line as the target bit line of the next first circulation step;
the first sub-loop step includes:
selecting a word line as a first target word line, starting the first target word line, and writing 0 into the memory cells electrically connected with the first target word line and the target bit line;
starting the induction amplifier electrically connected with the target bit line after delaying for a first preset time from the start of the first target word line;
and after the first target word line is started and the second preset time is delayed, the first target word line and the sense amplifier electrically connected with the target bit line are closed, and the next word line adjacent to the first target word line is used as the first target word line of the next first circulation step.
In some embodiments, the first cycling step comprises:
selecting one word line as a first target word line, and executing a second subcycle step on the first target word line;
after the second sub-cycle step is executed on the first target word line, taking the next word line adjacent to the first target word line as the first target word line of the next first cycle step;
the second sub-loop step includes:
turning on the first target word line;
starting a plurality of bit lines, and writing 0 into a plurality of memory cells connected with the first target word line and the bit lines;
starting the sense amplifier electrically connected with the bit lines after delaying for a first preset time from the start of the first target word line;
and after the first target word line is started and a second preset time is delayed, the first target word line and the sense amplifiers electrically connected with the bit lines are closed.
In some embodiments, the first cycling step comprises:
selecting a word line as a first target word line, and starting the first target word line;
starting all the bit lines, and writing 0 into all the memory cells connected with the first target word line;
starting the sense amplifiers electrically connected with all the bit lines after delaying a first preset time from the start of the first target word line;
and after the first target word line is started and the second preset time is delayed, the first target word line and the sense amplifiers electrically connected with all the bit lines are closed, and the next word line adjacent to the first target word line is used as the first target word line of the next first circulation step.
In some embodiments, the first predetermined time is 10ns to 400ns.
In some embodiments, the second predetermined time is 100ns to 1000ns.
In some embodiments, the number of the storage arrays is plural; after all the memory cells in one of the memory arrays are written with 0, the method further comprises the following steps:
refreshing the memory array written with 0;
and executing the first circulation step on the next storage array until all the storage units in the next storage array are full of 0.
In some embodiments, after all the memory cells in the memory array are written with 0, the method further comprises the following steps:
reading all the memory cells in the memory array;
and judging whether the read values of all the storage units are 0, if not, confirming that the word line at the storage unit with the read value not being 0 is electrically connected with the bit line.
In some embodiments, the specific step of reading all of the memory cells in the memory array comprises:
executing a third loop step a plurality of times until all the memory cells in the memory array are read, the third loop step comprising:
selecting a word line as a third target word line, and reading all memory cells connected with the third target word line;
and after all the memory cells connected with the third target word line are read, taking the next word line adjacent to the third target word line as a third target word line of a next third circulation step.
According to other embodiments, the present application also provides a test apparatus for a semiconductor structure, comprising:
the writing module is used for executing the following first circulation steps for multiple times until all the storage units in the storage array are fully written with 0; the memory array comprises a plurality of memory units arranged in an array, a plurality of word lines arranged in parallel along a first direction, and a plurality of bit lines arranged in parallel along a second direction, wherein the plurality of bit lines are electrically connected with a plurality of sense amplifiers, and the first direction is intersected with the second direction; the first cycle step includes: selecting a word line as a first target word line, and starting the first target word line; starting the induction amplifier after delaying a first preset time from the start of the first target word line; and after the first target word line is started and the second preset time is delayed, the first target word line and the sense amplifier are closed, and the next word line adjacent to the first target word line is used as the first target word line of the next first circulation step.
In some embodiments, the apparatus for testing a semiconductor structure further comprises:
and the refreshing module is used for refreshing the memory array which is written with 0.
In some embodiments, further comprising:
a reading module, configured to read all the memory cells in the memory array;
and the judging module is used for judging whether the read values of all the storage units are 0 or not, and if not, determining that the storage array has the defect of short circuit of the bit lines and the word lines.
In some embodiments, the first predetermined time is 10ns to 400ns.
In some embodiments, the second predetermined time is 100ns to 1000ns.
In some embodiments of the present disclosure, a test method and a test apparatus for a semiconductor structure are provided, where all memory cells of a memory array are filled with 0, and a short circuit between a word line and a bit line is simulated by using a voltage difference generated between a high potential when the word line is turned on and a low potential of the bit line. According to some embodiments of the present application, the sense amplifier is turned on after the target word line is started and delayed for a first preset time, and the target word line is turned off after the target word line is started and delayed for a second preset time, so that the time from the start of the target word line to the start of the sense amplifier and the time when the target word line is in an active state are extended, and thus, once a short circuit between the word line and the bit line occurs, the sense amplifier can sufficiently detect the defect, and the accuracy and the detection efficiency of the detection of the short circuit defect between the word line and the bit line are improved.
Drawings
FIG. 1 is a flow chart of a method for testing a semiconductor structure in accordance with an embodiment of the present application;
FIG. 2 is a schematic diagram of a memory array according to an embodiment of the present application;
FIG. 3 is a schematic diagram of a first method for testing a semiconductor structure in accordance with an embodiment of the present application;
FIG. 4 is a schematic diagram of a second method for testing a semiconductor structure in accordance with an embodiment of the present application;
FIG. 5 is a schematic diagram of a method for testing a third semiconductor structure in accordance with an embodiment of the present application;
fig. 6 is a block diagram of a semiconductor structure testing apparatus according to an embodiment of the present invention.
Detailed Description
The following describes in detail embodiments of a method and an apparatus for testing a semiconductor structure provided in the present application with reference to the accompanying drawings.
Fig. 1 is a flowchart of a method for testing a semiconductor structure in an embodiment of the present application, fig. 2 is a schematic structural diagram of a memory array in the embodiment of the present application, and fig. 3 is a schematic structural diagram of a first semiconductor structure in the embodiment of the present application. As shown in fig. 1, fig. 2 and fig. 3, the method for testing a semiconductor structure includes the following steps:
step S11, providing a memory array, where the memory array includes a plurality of memory cells 20 arranged in an array, a plurality of word lines WL arranged in parallel along a first direction, and a plurality of bit lines BL arranged in parallel along a second direction, where the plurality of bit lines BL are electrically connected to a plurality of sense amplifiers, and the first direction intersects with the second direction.
Specifically, the first direction and the second direction may intersect obliquely or perpendicularly. The semiconductor structure may be, but is not limited to, a DRAM, and accordingly, the memory array may be a memory array in a DRAM. The memory array is positioned on a substrate, a plurality of active regions arranged in an array are arranged in the substrate, and each active region comprises a bit line contact region and a capacitor contact region. The word lines WL may be buried word lines located within the substrate. The bit line BL is electrically connected to the bit line contact region in the substrate through a bit line contact plug. When a process deviation occurs, the bit line contact plug may be brought into contact with the word line, thereby causing a short-circuit connection between the bit line BL and the word line WL. Taking the schematic structural diagram of the memory array shown in fig. 2 as an example, each of the word lines WL extends along the X-axis direction, and a plurality of the word lines WL are arranged in parallel along the Y-axis direction. Each bit line BL extends along the Y-axis direction, and the plurality of bit lines BL are arranged in parallel along the X-axis direction. In the structure shown in fig. 2, a position where each of the word lines WL crosses each of the bit lines BL forms one of the memory cells 20. The plurality of strips in the present embodiment means two or more strips.
The plurality of sense amplifiers are electrically connected to the plurality of bit lines BL in a one-to-one correspondence, each of the memory cell units 20 is electrically connected to one of the bit lines BL, and one of the bit lines BL is electrically connected to the plurality of memory cells arranged in parallel along the Y axis direction. Therefore, one of the sense amplifiers is electrically connected to a plurality of the memory cells 20, and one of the memory cells 20 is electrically connected to only one of the sense amplifiers. When the bit line BL is electrically connected with the word line WL, the sense amplifier electrically connected with the bit line BL in short circuit can detect leakage current generated by short circuit of the bit line BL and the word line WL, and therefore the detection of short circuit defects of the bit line BL and the word line WL is achieved. The specific electrical connection mode between the sense amplifier and the bit line BL can be selected by a person skilled in the art according to actual needs, as long as the leakage current generated when the bit line BL is short-circuited with the word line WL can be detected.
Step S12, executing the following first loop step for multiple times until all the memory cells 20 in the memory array are full of 0;
the first cycle step includes:
selecting a word line as a first target word line, and starting the first target word line;
starting the induction amplifier after delaying a first preset time from the start of the first target word line;
and after the first target word line is started and the second preset time is delayed, closing the first target word line and the sense amplifier, and taking the next word line adjacent to the first target word line as the first target word line of the next first circulation step.
Specifically, in the process of detecting a defect in the memory array, all the memory cells 20 in the memory array are filled with 0, and a phenomenon of a short circuit between a word line and a bit line is simulated by using a voltage difference generated between a high potential when the word line is turned on and a low potential of the bit line. By sequentially turning on each word line WL and sequentially writing 0 into the memory cell 20 electrically connected to the turned-on word line, it can be determined whether the word line WL and the bit line BL connected to the memory cell 20 having completed the write operation are short-circuited (i.e., short-circuited) by detecting a leakage current condition detected by the sense amplifier electrically connected to the memory cell 20 corresponding to the memory cell 20 having completed the write operation. For example, when the leakage current detected by the sense amplifier is greater than a threshold value, it is determined that the bit line BL electrically connected to the sense amplifier is shorted with the turned-on word line WL. The specific value of the threshold value can be set by those skilled in the art according to actual needs, for example, according to the specific structure of the storage unit 20.
In the specific embodiment, the sensing amplifier is started after the target word line is started and delays for a first preset time, and the target word line is closed after the target word line is started and delays for a second preset time, so that the time from starting the target word line to starting the sensing amplifier and the time of the target word line in an activated state are prolonged, the sensing amplifier can fully detect the defect once the short circuit between the word line and the bit line occurs, and the accuracy and the detection efficiency of the detection of the short circuit defect between the word line and the bit line are improved.
In some embodiments, the first predetermined time is 10ns to 400ns. For example, the first preset time is 10ns, 50ns, 100ns, 200ns, or 400ns.
In some embodiments, the second predetermined time is 100ns to 1000ns. For example, the second preset time is 100ns, 300ns, 500ns, 700ns, or 1000ns.
In some embodiments, before the step of executing the loop, the method further comprises the steps of:
writing all the memory cells 20 in the memory array with 0, as shown in (a) of fig. 3;
the memory array is refreshed as shown in (b) of fig. 3.
In some embodiments, before executing the loop step, the step of writing all of the memory cells 20 in the memory array with 0 includes:
executing the following second loop steps for a plurality of times until all the memory cells 20 in the memory array are full of 0, where the second loop steps include:
selecting a word line WL as a second target word line, and starting the second target word line;
sequentially writing 0's into all the memory cells 20 connected to the second target word line;
and closing the second target word line, and taking the next word line WL adjacent to the second target word line as the second target word line of the next second circulation step.
For example, the second loop step is performed a first time: selecting the word line WL located in the first row of the memory array as the second target word line; then, turning on the second target word line and all the bit lines BL, so that all the memory cells 20 electrically connected to the second target word line are fully written with 0; then, the second target word line is turned off. Executing the second loop step a second time: selecting the word line WL located in a second row of the memory array as the second target word line; then, turning on the second target word line and all the bit lines BL, so that all the memory cells 20 electrically connected to the second target word line are fully written with 0; then, the second target word line is turned off. Executing the second circulation step for the third time: selecting the word line WL located in a third row of the memory array as the second target word line; then, turning on the second target word line and all the bit lines BL, so that all the memory cells 20 electrically connected to the second target word line are fully written with 0; then, the second target word line is turned off. By analogy, by executing the second loop step multiple times, all the word lines WL in the memory array complete the on and off operations, so as to write a 0 in the memory array.
In the present embodiment, before entering the test mode and performing the first cycle step for multiple times, the second cycle step is performed for multiple times, and 0 is written in the memory array, so as to avoid the influence of other defects in the memory array, and ensure that the leakage current detected by the sense amplifier is caused by the short circuit between the word line WL and the bit line BL, thereby further improving the accuracy and reliability of the test result.
In other embodiments, the first cycling step comprises:
selecting a bit line as a target bit line, and starting the target bit line;
sequentially executing a first sub-cycle step on a plurality of word lines;
closing the target bit line, and taking the next bit line adjacent to the target bit line as the target bit line of the next first circulation step;
the first sub-loop step includes:
selecting a word line WL as a first target word line, starting the first target word line, and writing 0 into the memory cells electrically connected with the first target word line and the target bit line;
starting the induction amplifier electrically connected with the target bit line after delaying for a first preset time from the start of the first target word line;
and after the first target word line is started and the second preset time is delayed, the first target word line and the sense amplifier electrically connected with the target bit line are closed, and the next word line WL adjacent to the first target word line is used as the first target word line of the next first circulation step.
For example, after entering the test mode, the first loop step is performed for the first time: and selecting the bit line BL positioned in the first column of the memory array as a target bit line, and starting the target bit line. Then, a first sub-loop step is executed for the first time: selecting the word line WL positioned in a first row of the memory array as a first target word line, starting the first target word line, and writing 0 into one memory cell electrically connected with the first target word line and the target bit line; starting the induction amplifier electrically connected with the target bit line after delaying for a first preset time from the start of the first target word line; and after the first target word line is started and the second preset time is delayed, the first target word line and the induction amplifier electrically connected with the target bit line are closed. Then, the first sub-loop step is executed for the second time: selecting the word line WL positioned in a second row of the memory array as a first target word line, starting the first target word line, and writing 0 into one memory cell electrically connected with the first target word line and the target bit line; starting the sensing amplifier electrically connected with the target bit line after delaying a first preset time from the start of the first target word line; and after the first target word line is started and the second preset time is delayed, the first target word line and the induction amplifier electrically connected with the target bit line are closed. And so on, until all the word lines WL complete the first sub-cycle step, so that all the memory cells 20 electrically connected to the target bit line complete the operation of writing 0, as shown in (c) of fig. 3.
After the target bit line is closed, executing the first loop step for the second time: and selecting the bit line BL positioned in the second column of the memory array as a target bit line, and starting the target bit line. Then, the first sub-cycle step is executed a plurality of times, so that all the memory cells 20 electrically connected to the target bit line complete the operation of writing 0. The specific operation of executing the first sub-loop step for multiple times is the same as the operation of executing the first sub-loop step for multiple times in the first loop step for the first time.
And so on, after the first cycle step is executed for multiple times, all the bit lines BL in the memory array are made to complete the first cycle step in sequence, and the memory array is full of 0.
In other embodiments, the first cycling step comprises:
selecting one word line WL as a first target word line, and executing a second subcycle step on the first target word line;
after the second sub-cycle step is executed on the first target word line, taking the next word line WL adjacent to the first target word line as the first target word line of the next first cycle step;
the second sub-loop step includes:
turning on the first target word line;
starting a plurality of bit lines, and writing 0 into a plurality of memory cells connected with the first target word line and the bit lines;
starting the sense amplifier electrically connected with the bit lines after delaying for a first preset time from the start of the first target word line;
and after the first target word line is started and a second preset time is delayed, the first target word line and the sense amplifiers electrically connected with the bit lines are closed.
FIG. 4 is a schematic diagram of a second method for testing a semiconductor structure in accordance with an embodiment of the present invention. The operations (a) and (b) in fig. 4 are the same as the operations (a) and (b) in fig. 3 except that the first circulation step ((c) in fig. 4) is different from the first circulation step ((c) in fig. 3. In the embodiment shown in fig. 4, after entering the test mode, the first loop step is performed for the first time: the word line WL located in the first row of the memory array is selected as the first target word line. Then, the second sub-loop step is executed for the first time on the first target word line: turning on the first target word line for a first time; starting a preset number of bit lines BL, and writing 0 into a preset number of memory cells 20 connected to the first target word line and the plurality of bit lines; starting the sense amplifier electrically connected with the bit lines BL after delaying a first preset time from the start of the first target word line; and after the first target word line is started and a second preset time is delayed, the first target word line and the sense amplifiers electrically connected with the bit lines BL are closed. Then, performing the second sub-loop step for the first target word line for a second time: turning on the first target word line a second time; starting a next preset number of bit lines BL adjacent to the bit lines BL started in the step of executing the second sub-cycle for the first time in the memory array, and writing 0 to a next preset number of memory cells 20 connected to the first target word line and the next preset number of bit lines; starting the sense amplifiers electrically connected with the bit lines BL of the next preset number after the first target word line is started and delaying for a first preset time; and after the first target word line is started and the second preset time is delayed, the first target word line and the induction amplifiers electrically connected with the bit lines BL of the next preset number are closed. And so on until all the memory cells 20 connected to the first target word line are full of 0.
Executing the first loop step a second time: the word line WL located in a second row of the memory array is selected as the first target word line. Then, the second sub-cycle step is executed a plurality of times, so that all the memory cells 20 electrically connected to the target word line complete the operation of writing 0. And the specific operation of executing the second sub-cycle step for multiple times is the same as the operation of executing the second sub-cycle step for multiple times in the first cycle step for the first time.
In other embodiments, the first cycling step comprises:
selecting a word line WL as a first target word line, and starting the first target word line;
starting all the bit lines, and writing 0 into all the memory cells connected with the first target word line;
starting the sense amplifiers electrically connected with all the bit lines after delaying a first preset time from the start of the first target word line;
and after the first target word line is started and the second preset time is delayed, the first target word line and the sense amplifiers electrically connected with all the bit lines are closed, and the next word line adjacent to the first target word line is used as the first target word line of the next first circulation step.
FIG. 5 is a schematic diagram of a method for testing a third semiconductor structure in accordance with embodiments of the present application. The operations (a) and (b) in fig. 5 are the same as the operations (a) and (b) in fig. 3 except that the first circulation step ((c) in fig. 5) is different from the first circulation step ((c) in fig. 3. In the embodiment shown in fig. 5, after entering the test mode, the first loop step is performed for the first time: selecting the word line WL positioned in a first row of the memory array as a first target word line, and starting the first target word line; turning on all the bit lines BL, and writing 0 into all the memory cells 20 connected to the first target word line; starting the sense amplifiers electrically connected with all the bit lines BL after delaying a first preset time from the start of the first target word line; and after the first target word line is started and a second preset time is delayed, the first target word line and the sense amplifiers electrically connected with all the bit lines BL are closed.
Executing the first loop step for a second time: selecting the word line WL positioned in a second row of the memory array as a first target word line, and starting the first target word line; turning on all the bit lines BL, and writing 0 into all the memory cells 20 connected to the first target word line; starting the sense amplifiers electrically connected with all the bit lines BL after delaying a first preset time from the start of the first target word line; and after the first target word line is started and the second preset time is delayed, the first target word line and the sense amplifiers electrically connected with all the bit lines BL are closed. By analogy, by performing the first loop step multiple times, all the word lines WL in the memory array complete the on and off operations, so as to write a 0 in the memory array.
In some embodiments, the number of the storage arrays is plural; after all the memory cells in one of the memory arrays are written with 0, the method further comprises the following steps:
refreshing the memory array which is written with 0;
and executing the first circulation step on the next storage array until all the storage units in the next storage array are full of 0.
As shown in fig. 3, 4 and 5, the number of the memory arrays is plural, and the plural memory arrays are arranged in parallel along the Z-axis direction. After all the memory cells in one of the memory arrays are written with 0, the test mode is exited (i.e., (d) operation in fig. 3, (d) operation in fig. 4, and (d) operation in fig. 4), and the memory arrays written with 0 are refreshed (i.e., (e) operation in fig. 3, (e) operation in fig. 4, and (e) operation in fig. 4). Thereafter, the test mode is performed again, and the first loop step (operation (c) in fig. 3, operation (c) in fig. 4, and operation (c) in fig. 4) is performed on the next memory array until all the memory cells in the next memory array are full of 0. After the next memory array is written with 0, the test mode is exited, and a refresh operation is performed on the memory array written with 0 in the test mode. And the like until a plurality of storage arrays complete the operation of writing full 0 through the first circulation step for a plurality of times.
In some embodiments, after all the memory cells 20 in the memory array are written with 0, the method further includes the following steps:
reading all of the memory cells 20 in the memory array (operation (f) in fig. 3, operation (f) in fig. 4, and operation (f) in fig. 4);
judging whether the read values of all the memory cells 20 are 0, if not, confirming that the word lines WL and the bit lines BL at the memory cells 20 with the read values not being 0 are electrically connected.
In some embodiments, the specific step of reading all of the memory cells 20 in the memory array includes:
executing a third loop step for a plurality of times until all the memory cells 20 in the memory array are read, the third loop step comprising:
selecting one word line WL as a third target word line, and reading all memory cells 20 connected to the third target word line;
after all the memory cells 20 connected to the third target word line are read, the next word line WL adjacent to the third target word line is used as the third target word line in the next third cycle step.
For example, after all the memory arrays have completed the operation session of writing full 0 by executing the first loop step multiple times, the third loop step is executed for the first time: the word line WL in the first row of one of the memory arrays is selected as a third target word line, and all memory cells 20 connected to the target word line are read. Thereafter, performing the third loop step a second time: the word line WL in the second row of one of the memory arrays is selected as a third target word line, and all the memory cells 20 connected to the target word line are read. And so on, reading row by row until all the memory cells 20 in all the memory arrays are read.
Since the value written into the memory cell 20 is 0 in the write operation, if the word line WL is short-circuited with the bit line BL, a leakage current generated by the short-circuited word line WL and bit line BL is transmitted to a capacitor electrically connected to the bit line BL. In a read operation, a leakage current in the capacitor is transmitted to the memory cell 20 electrically connected to both the word line WL and the bit line BL in which the short circuit occurs, so that a read value of the memory cell 20 becomes 1. Therefore, by determining whether the read values of all the memory cells 20 are 0, it can be determined whether the word line WL and the bit line BL at the memory cell 20 are shorted.
According to other embodiments, the present detailed description also provides a test apparatus for a semiconductor structure. Fig. 6 is a block diagram of a semiconductor structure testing apparatus according to an embodiment of the present invention. The semiconductor structure testing apparatus provided in this embodiment mode can test a semiconductor structure by using the method shown in fig. 1 to 5. As shown in fig. 1 to 6, the testing apparatus for a semiconductor structure includes:
a write module 61, configured to perform the following first loop step for multiple times until all the memory cells in the memory array are full of 0; the memory array comprises a plurality of memory units arranged in an array, a plurality of word lines arranged in parallel along a first direction, and a plurality of bit lines arranged in parallel along a second direction, wherein the plurality of bit lines are electrically connected with a plurality of sense amplifiers, and the first direction is intersected with the second direction; the first loop step includes: selecting a word line as a first target word line, and starting the first target word line; starting the induction amplifier after delaying a first preset time from the start of the first target word line; and after the first target word line is started and the second preset time is delayed, closing the first target word line and the sense amplifier, and taking the next word line adjacent to the first target word line as the first target word line of the next first circulation step.
In some embodiments, the apparatus for testing a semiconductor structure further comprises:
a refresh module 62 for refreshing the memory array written with 0.
In some embodiments, further comprising:
a reading module 63, configured to read all the memory cells in the memory array;
and a determining module 64, configured to determine whether the read values of all the memory cells are 0, and if not, determine that the memory array has a short-circuit defect between the bit line and the word line.
The testing apparatus for a semiconductor structure may further include a control module 60, the control module 60 is connected to the writing module 61, the refreshing module 62, the reading module 63, and the determining module 64, and the control module 60 may be an upper computer, and is configured to receive an operation instruction from a user and control the writing module 61, the refreshing module 62, the reading module 63, and the determining module 64 to perform corresponding operations.
In the test method and the test apparatus for a semiconductor structure according to the present embodiment, all the memory cells of the memory array are filled with 0, and the phenomenon of short circuit between the word line and the bit line is simulated by using the voltage difference generated between the high potential when the word line is turned on and the low potential of the bit line. According to some embodiments of the application, the sense amplifier is turned on after the target word line is started and delays for a first preset time, and the target word line is turned off after the target word line is started and delays for a second preset time, so that the time from the turning on of the target word line to the turning on of the sense amplifier and the time of the target word line in an activated state are prolonged, once a short circuit between the word line and the bit line occurs, the sense amplifier can fully detect the short circuit defect, and the accuracy and the detection efficiency of the detection of the short circuit defect between the word line and the bit line are improved.
The foregoing is only a preferred embodiment of the present application and it should be noted that, for a person skilled in the art, several modifications and refinements can be made without departing from the principle of the present application, and these modifications and refinements should also be regarded as the protection scope of the present application.
Claims (16)
1. A method for testing a semiconductor structure, comprising the steps of:
providing a storage array, wherein the storage array comprises a plurality of storage units arranged in an array, a plurality of word lines arranged in parallel along a first direction, and a plurality of bit lines arranged in parallel along a second direction, the plurality of bit lines are electrically connected with a plurality of sense amplifiers, and the first direction is intersected with the second direction;
executing the following first circulation step for multiple times until all the memory cells in the memory array are full of 0;
the first loop step includes:
selecting a word line as a first target word line, and starting the first target word line;
starting the induction amplifier after delaying a first preset time from the start of the first target word line; and after the first target word line is started and the second preset time is delayed, the first target word line and the sense amplifier are closed, and the next word line adjacent to the first target word line is used as the first target word line of the next first circulation step.
2. The method of testing a semiconductor structure of claim 1, further comprising, before the step of performing a loop, the steps of:
writing all the memory cells in the memory array with 0;
the memory array is refreshed.
3. The method of claim 2, wherein prior to performing the cycling step, the step of writing all of the memory cells in the memory array with 0 comprises: executing the following second loop step for multiple times until all the memory cells in the memory array are full of 0, wherein the second loop step comprises:
selecting a word line as a second target word line, and starting the second target word line;
sequentially writing 0 to all the memory cells connected with the second target word line;
and closing the second target word line, and taking the next word line adjacent to the second target word line as the second target word line of the next second circulation step.
4. The method of testing a semiconductor structure of claim 1, wherein said first cycling step comprises:
selecting a bit line as a target bit line, and starting the target bit line;
sequentially executing a first sub-cycle step on a plurality of word lines;
closing the target bit line, and taking the next bit line adjacent to the target bit line as the target bit line of the next first circulation step;
the first sub-loop step includes:
selecting a word line as a first target word line, starting the first target word line, and writing 0 into the memory cells electrically connected with the first target word line and the target bit line;
starting the induction amplifier electrically connected with the target bit line after delaying for a first preset time from the start of the first target word line;
and after the first target word line is started and the second preset time is delayed, the first target word line and the sense amplifier electrically connected with the target bit line are closed, and the next word line adjacent to the first target word line is used as the first target word line of the next first circulation step.
5. The method of testing a semiconductor structure of claim 1, wherein said first cycling step comprises:
selecting a word line as a first target word line, and executing a second sub-cycle step on the first target word line;
after the second sub-cycle step is executed on the first target word line, taking the next word line adjacent to the first target word line as the first target word line of the next first cycle step;
the second sub-loop step includes:
turning on the first target word line;
starting a plurality of bit lines, and writing 0 into a plurality of memory cells connected with the first target word line and the bit lines;
starting the sense amplifier electrically connected with the bit lines after delaying for a first preset time from the start of the first target word line;
and after the first target word line is started and the second preset time is delayed, the first target word line and the induction amplifiers electrically connected with the bit lines are closed.
6. The method of testing a semiconductor structure of claim 1, wherein the first cycling step comprises:
selecting a word line as a first target word line, and starting the first target word line;
starting all the bit lines, and writing 0 into all the memory cells connected with the first target word line;
starting the sense amplifiers electrically connected with all the bit lines after delaying a first preset time from the start of the first target word line;
and after the first target word line is started and the second preset time is delayed, the first target word line and the sense amplifiers electrically connected with all the bit lines are closed, and the next word line adjacent to the first target word line is used as the first target word line of the next first circulation step.
7. The method for testing a semiconductor structure according to claim 1, wherein the first predetermined time is 10ns to 400ns.
8. The method as claimed in claim 1, wherein the second predetermined time is 100 ns-1000 ns.
9. The method of testing a semiconductor structure of claim 1, wherein the number of said memory arrays is plural; after all the memory cells in one of the memory arrays are written with 0, the method further comprises the following steps:
refreshing the memory array which is written with 0;
and executing the first circulation step on the next storage array until all the storage units in the next storage array are full of 0.
10. The method for testing a semiconductor structure according to claim 1, further comprising the steps of, after all of said memory cells in said memory array are fully written with 0:
reading all the memory cells in the memory array;
and judging whether the read values of all the storage units are 0, if not, confirming that the word line at the storage unit with the read value not being 0 is electrically connected with the bit line.
11. The method for testing a semiconductor structure as recited in claim 10, wherein the step of reading all of said memory cells in said memory array comprises:
executing a third loop step a plurality of times until all the memory cells in the memory array are read, the third loop step comprising:
selecting a word line as a third target word line, and reading all memory cells connected with the third target word line;
and after all the memory cells connected with the third target word line are read, taking the next word line adjacent to the third target word line as a third target word line of a next third circulation step.
12. An apparatus for testing a semiconductor structure, comprising:
the write-in module is used for executing the following first cycle step for multiple times until all the storage units in the storage array are full of 0; the memory array comprises a plurality of memory units arranged in an array, a plurality of word lines arranged in parallel along a first direction, and a plurality of bit lines arranged in parallel along a second direction, wherein the plurality of bit lines are electrically connected with a plurality of sense amplifiers, and the first direction is intersected with the second direction; the first cycle step includes: selecting a word line as a first target word line, and starting the first target word line; starting the sensing amplifier after delaying a first preset time from the start of the first target word line; and after the first target word line is started and the second preset time is delayed, closing the first target word line and the sense amplifier, and taking the next word line adjacent to the first target word line as the first target word line of the next first circulation step.
13. The apparatus for testing a semiconductor structure as defined in claim 12, further comprising:
and the refreshing module is used for refreshing the memory array which is written with 0.
14. The apparatus for testing a semiconductor structure of claim 12, further comprising:
a reading module, configured to read all the memory cells in the memory array;
and the judging module is used for judging whether the read values of all the storage units are 0 or not, and if not, confirming that the word line at the storage unit with the read value not being 0 is electrically connected with the bit line.
15. The apparatus for testing a semiconductor structure as defined in claim 12, wherein the first predetermined time is in a range of 10 ns-400 ns.
16. The apparatus for testing the semiconductor structure as claimed in claim 12, wherein the second predetermined time is 100ns to 1000ns.
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