CN115796089B - Coverage rate driven verification method, coverage rate driven verification device, coverage rate driven verification medium and electronic equipment - Google Patents
Coverage rate driven verification method, coverage rate driven verification device, coverage rate driven verification medium and electronic equipment Download PDFInfo
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Abstract
The application provides a coverage rate driven verification method, a coverage rate driven verification device, a coverage rate driven medium and electronic equipment. The coverage rate driven verification method comprises the following steps: acquiring a first coverage rate corresponding to a first random excitation according to the first random excitation, issuing the first random excitation to enable a chip to be tested to be verified under the first random excitation if the first coverage rate exceeds a coverage rate corresponding to a previous excitation, acquiring a second random excitation and issuing the second random excitation to enable the chip to be tested to be verified under the second random excitation if the first coverage rate does not exceed the coverage rate corresponding to the previous excitation; acquiring output data of the chip to be tested and output data of a reference model of the chip to be tested; and comparing the output data of the chip to be tested with the output data of the reference model to obtain a verification result. The coverage rate driven verification method can reduce the time consumption of the whole verification process.
Description
Technical Field
The application belongs to the field of chip verification, relates to a chip function coverage rate verification method, and particularly relates to a coverage rate driven verification method, a coverage rate driven verification device, a medium and electronic equipment.
Background
As semiconductor processes develop, a plurality of functions are often integrated in one chip. In the functional design of chips, some design errors and design defects often occur. In the functional verification of the chip, the coverage rate of the chip test is an important index of the chip test quality, and the improvement of the coverage rate of the chip test through different excitation is an indispensable process for the chip verification.
In the prior art, when verifying a chip, the coverage rate of the chip test is improved by requiring multiple rounds of random tests, and the random excitation of the test is not improved due to the fact that the random excitation and the previous excitation of the test may be repeated, if the simulation verification is still performed under the random excitation, the whole verification process is definitely caused to have useless time consumption. Thus, the current verification method has the problem that repeated tests are wasteful and time-consuming.
Disclosure of Invention
The application aims to provide a coverage rate driven verification method, a coverage rate driven verification device, a coverage rate driven verification medium and electronic equipment, which are used for solving the problem that repeated tests in the existing verification method cause waste of time.
In a first aspect, the present application provides a coverage rate driven verification method, applied to a verification system, where the coverage rate driven verification method includes: acquiring a first coverage rate corresponding to a first random excitation according to the first random excitation, if the first coverage rate exceeds a coverage rate corresponding to a previous excitation, issuing the first random excitation to enable a chip to be tested to be verified under the first random excitation, if the first coverage rate does not exceed the coverage rate corresponding to the previous excitation, acquiring a second random excitation and issuing the second random excitation to enable the chip to be tested to be verified under the second random excitation, wherein the second coverage rate corresponding to the second random excitation exceeds the coverage rate corresponding to the previous excitation; acquiring output data of the chip to be tested and output data of a reference model of the chip to be tested; and comparing the output data of the chip to be tested with the output data of the reference model to obtain a verification result. The random excitation with the coverage rate necessarily larger than the coverage rate corresponding to the previous excitation is obtained, so that the coverage rate of the chip test is necessarily improved by the random excitation of the round of test, the repeated test of the whole verification process is avoided, and the time consumption of the whole verification process is further reduced.
In an embodiment of the present application, the verification system includes a functional coverage component, a rate mode of each port of the chip to be tested includes 10M, 100M and 1000M, an operation mode of each port of the chip to be tested includes full duplex and half duplex, a coverage point of the functional coverage component includes the port of the chip to be tested, the rate mode and the operation mode, and a coverage group of the coverage component includes cross coverage between the coverage points.
In an embodiment of the present application, the verification system includes an incentive generating component, and the implementation method for obtaining the first coverage rate corresponding to the first random incentive according to the first random incentive includes: generating, by the stimulus generation component, the first random stimulus; and processing the first random stimulus by the functional coverage rate component to obtain the first coverage rate.
In an embodiment of the present application, the coverage rate driven verification method further includes: if the coverage rate corresponding to the previous excitation exceeds the preset coverage rate, not issuing random excitation, wherein the random excitation comprises the first random excitation and the second random excitation, and generating a stop mark, and the stop mark is used for ending the verification process of the chip to be tested.
In one embodiment of the present application, the verification system includes a driving component and an entry monitoring component, and the implementation method for issuing the first random stimulus includes: transmitting the first random stimulus to the chip to be tested and the inlet monitoring assembly through the driving assembly; acquiring inlet information of the first random excitation through the inlet monitoring component; and sending the inlet information to the reference model through the inlet monitoring component.
In an embodiment of the present application, the verification system includes an exit monitoring component, and the implementation method for obtaining the output data of the chip to be tested and the output data of the reference model of the chip to be tested includes: if the issued excitation is the first random excitation, acquiring output data of the chip to be tested under the first random excitation and output data of the reference model in real time through the outlet monitoring assembly; and if the issued excitation is the second random excitation, acquiring output data of the chip to be tested under the second random excitation and output data of the reference model in real time through the outlet monitoring component. The output data of the chip to be tested and the output data of the reference model are obtained in real time through the outlet monitoring component, so that the verification efficiency of the whole verification process can be effectively improved.
In an embodiment of the present application, the verification system further includes a verification component, and the implementation method for comparing the output data of the chip to be tested with the output data of the reference model includes: and carrying out real-time comparison processing on the output data of the chip to be tested and the output data of the reference model through the verification component so as to acquire the verification result in real time.
In a second aspect, the present application provides a coverage driven verification apparatus for use in a verification system, the coverage driven verification apparatus comprising: the coverage rate acquisition module is used for acquiring a first coverage rate corresponding to the first random excitation according to the first random excitation, issuing the first random excitation to enable the chip to be tested to be verified under the first random excitation if the first coverage rate exceeds the coverage rate corresponding to the previous excitation, acquiring a second random excitation and issuing the second random excitation to enable the chip to be tested to be verified under the second random excitation if the first coverage rate does not exceed the coverage rate corresponding to the previous excitation, wherein the second coverage rate corresponding to the second random excitation exceeds the coverage rate corresponding to the previous excitation; the output data acquisition module is used for acquiring output data of the chip to be detected and output data of a reference model of the chip to be detected; and the verification result acquisition module is used for comparing the output data of the chip to be tested with the output data of the reference model to acquire a verification result.
In a third aspect, the present application provides a computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements a coverage driven verification method according to any one of the first aspects of the present application.
In a fourth aspect, the present application provides an electronic device, including: a memory storing a computer program; and the processor is in communication connection with the memory and executes the coverage rate driven verification method according to any one of the first aspect of the application when the computer program is called.
As described above, the coverage rate driven verification method, verification device, medium and electronic device according to the present application have the following
The beneficial effects are that:
Firstly, the coverage rate driven verification method of the application can ensure that the random excitation of the round of test can necessarily improve the coverage rate of the chip test by acquiring the random excitation of which the coverage rate is necessarily larger than the coverage rate corresponding to the previous excitation, thereby avoiding the repeated test of the whole verification process and further reducing the time consumption of the whole verification process.
Secondly, according to the coverage rate driven verification method, the output data of the chip to be tested and the output data of the reference model are obtained in real time through the outlet monitoring component, so that the verification efficiency of the whole verification process can be effectively improved.
Drawings
Fig. 1 is a schematic structural diagram of a verification system according to an embodiment of the application.
FIG. 2 is a flow chart of a coverage driven verification method according to an embodiment of the application.
Fig. 3 is a flowchart of an implementation method for obtaining a first coverage rate corresponding to a first random stimulus according to the first random stimulus in an embodiment of the present application.
FIG. 4 is a flow chart showing a method for implementing the first random stimulus issued by the embodiment of the application.
Fig. 5 is a flowchart of an implementation method for obtaining output data of the chip to be tested and output data of the reference model according to an embodiment of the present application.
Fig. 6 is a schematic structural diagram of a coverage-driven verification device according to an embodiment of the application.
Fig. 7 is a schematic structural diagram of an electronic device according to an embodiment of the application.
Description of element reference numerals
100. Verification system
110. Excitation generating assembly
120. Functional coverage component
130. Driving assembly
140. Inlet monitoring assembly
150. Outlet monitoring assembly
160. Verification assembly
600. Coverage rate driven verification device
610. Coverage rate acquisition module
620. Output data acquisition module
630. Verification result acquisition module
700. Electronic equipment
710. Memory device
720. Processor and method for controlling the same
S11-S13 step
S21-S22 step
S31-S33 step
S41-S42 step
Detailed Description
Other advantages and effects of the present application will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present application with reference to specific examples. The application may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present application. It should be noted that the following embodiments and features in the embodiments may be combined with each other without conflict.
It should be noted that the illustrations provided in the following embodiments merely illustrate the basic concept of the present application by way of illustration, and only the components related to the present application are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complicated.
The following describes the technical solution in the embodiment of the present application in detail with reference to the drawings in the embodiment of the present application.
As shown in fig. 1, an embodiment of the present application provides a verification system 100, where the verification system 100 specifically includes: the system comprises an excitation generation component 110, a function coverage component 120, a driving component 130, an entrance monitoring component 140, an exit monitoring component 150 and a verification component 160, wherein the excitation generation component 110 is used for generating random excitation, the random excitation comprises first random excitation and second random excitation, the function coverage component 120 is used for acquiring first coverage rate corresponding to the first random excitation or second coverage rate corresponding to the second random excitation, the driving component 130 is used for sending the first random excitation or the second random excitation to a chip to be tested and the entrance monitoring component 140, the entrance monitoring component 140 is used for acquiring entrance information of the first random excitation or the second random excitation, the exit monitoring component 150 is used for acquiring output data of the chip to be tested under the first random excitation or the second random excitation and output data of the reference model in real time, and the verification component 160 is used for carrying out real-time comparison processing on the output data of the chip to be tested and the output data of the reference model to acquire verification results in real time. The reference model is used for simulating the functions of the chip to be tested.
Alternatively, the verification system 100 may be deployed on a computer device having stored thereon a set of computer instructions for implementing the functions associated with the incentive generating component 110, the function coverage component 120, the driving component 130, the ingress monitoring component 140, the egress monitoring component 150, and the verification component 160.
Optionally, the function coverage component 120 has a corresponding function method, for example, the function method that the function coverage component 120 has may be get_coverage (), and the function method is used to obtain the coverage of the random stimulus in the function coverage component 120, and the method may be called to obtain the coverage corresponding to the random stimulus.
Alternatively, the incentive generating component 110, the function coverage component 120, the driving component 130, the ingress monitoring component 140, the egress monitoring component 150, and the verification component 160 may each be in the form of a set of computer instructions by which the functions of the components in the verification system 100 are implemented.
Optionally, in the verification system 100, the excitation generating component 110 generates a first random excitation, and obtains a first coverage rate corresponding to the first random excitation through a functional method in the functional coverage rate component 120, if the first coverage rate exceeds a coverage rate corresponding to a previous excitation, the first random excitation is issued to the driving component 130, the driving component 130 issues the first random excitation to the entrance monitoring component 140 and the chip to be tested, the entrance monitoring component 140 sends entrance information of the first random excitation to the reference model, the exit monitoring component 150 obtains output data of the chip to be tested and output data of the reference model under the first random excitation in real time, and the verification component 160 processes the output data of the chip to be tested and the output data of the reference model under the first random excitation in real time to obtain a verification result in real time. If the first coverage rate does not exceed the coverage rate corresponding to the previous excitation, a second random excitation is generated and issued to the driving component 130, and the process of issuing the second random excitation by the driving component 130 and the related process of acquiring the output data under the second random excitation are similar to those of the first random excitation, which is not described herein again. The second coverage corresponding to the second random stimulus exceeds the coverage corresponding to the previous stimulus.
As shown in fig. 2, the present embodiment provides a coverage rate driven verification method, which is applied to a verification system, and the coverage rate driven verification method may be implemented by a processor of a computer device, and the coverage rate driven verification method includes:
S11, acquiring a first coverage rate corresponding to first random excitation according to first random excitation, if the first coverage rate exceeds a coverage rate corresponding to previous excitation, issuing the first random excitation to enable a chip to be tested to be verified under the first random excitation, if the first coverage rate does not exceed the coverage rate corresponding to the previous excitation, acquiring a second random excitation and issuing the second random excitation to enable the chip to be tested to be verified under the second random excitation, wherein the second coverage rate corresponding to the second random excitation exceeds the coverage rate corresponding to the previous excitation.
Alternatively, the verification of the chip may require multiple rounds of testing, either the first random stimulus or the second random stimulus may be considered as the stimulus required for the test of the round, and the previous stimulus may be the stimulus required for the test prior to the round. The first coverage rate corresponding to the first random excitation is the functional coverage rate of the chip to be tested under the first random excitation, the coverage rate corresponding to the previous excitation is the functional coverage rate of the chip to be tested under the previous excitation, and the second coverage rate corresponding to the second random excitation is the functional coverage rate of the chip to be tested under the second random excitation. For example, when the coverage rate corresponding to the previous stimulus is seventy percent, if the first coverage rate is eighty percent, the first random stimulus is directly issued, and if the first coverage rate is sixty percent, the second random stimulus is acquired, and the second coverage rate exceeds seventy percent.
Optionally, if the first random stimulus is just the first round of test of chip verification, then the coverage rate corresponding to the previous stimulus is a default value of 0.
Optionally, the verification system includes a functional coverage component, a rate mode of each port of the chip to be tested includes 10M, 100M and 1000M, an operation mode of each port of the chip to be tested includes full duplex and half duplex, a coverage point of the functional coverage component includes the port of the chip to be tested, the rate mode and the operation mode, a coverage group of the functional coverage component includes cross coverage between the coverage points, and the chip to be tested may be a switching chip.
Optionally, the coverage rate component may be a user-defined class, where the class may include a method for obtaining coverage rate corresponding to the current stimulus and a number of variables or expressions related to the coverage points, for example, the coverage point y of the coverage rate component includes {1,2,3,4,5}, and when the data included in the current stimulus is {1,2}, the coverage rate corresponding to the current stimulus is only forty percent, and the coverage group of the coverage rate component may be a set of a number of coverage points. The cross coverage between the coverage points may be, for example, that the port a has 3 rate modes, which may be represented as { a,1}, { a,2}, { a,3}, and the port B also has 3 rate modes, which may be represented as { B,1}, { B,2}, { B, 3}, and after the coverage points of the port a and the port B cross coverage, nine combinations may be obtained, which are not represented one by one any more, and the coverage group of the functional coverage component includes these nine combinations.
Optionally, the coverage rate driven verification method further includes: if the coverage rate corresponding to the previous excitation exceeds the preset coverage rate, not issuing random excitation, wherein the random excitation comprises the first random excitation and the second random excitation, and generating a stop mark, and the stop mark is used for ending the verification process of the chip to be tested. For example, if the preset coverage rate is ninety percent, and the coverage rate corresponding to the previous stimulus is ninety-five percent, the verification process of the chip to be tested may be ended here, which indicates that the previous stimulus has met the verification requirement.
Optionally, the implementation method for obtaining the second random excitation includes: and continuously generating new random excitation until the coverage rate corresponding to the finally generated random excitation exceeds the coverage rate corresponding to the previous excitation, and obtaining the finally generated random excitation as the second random excitation.
S12, obtaining output data of the chip to be tested and output data of a reference model of the chip to be tested.
Optionally, the implementation method for obtaining the output data of the chip to be tested and the output data of the reference model of the chip to be tested includes: and if the issued excitation is the first random excitation, acquiring output data of the chip to be tested under the first random excitation and output data of the reference model, and if the issued excitation is the second random excitation, acquiring output data of the chip to be tested under the second random excitation and output data of the reference model.
Optionally, for example, when the rate mode of the chip port to be tested is functionally verified, the output data of the chip to be tested is data related to the rate of the chip port to be tested.
S13, comparing the output data of the chip to be tested with the output data of the reference model to obtain a verification result.
Optionally, the verification result includes verification passing and verification failure, and the implementation method for comparing the output data of the chip to be tested with the output data of the reference model includes: and acquiring the absolute value of the difference between the output data of the chip to be tested and the output data of the reference model, wherein if the absolute value of the difference is smaller than a preset threshold, the verification result is verification passing, and if the absolute value of the difference is larger than the preset threshold, the verification result is verification failure. For example, when the absolute value of the difference is 20 and the preset threshold is 30, the verification result is verification passing, and when the absolute value of the difference is 40 and the preset threshold is 30, the verification result is verification failure. And if the verification result is verification failure, ending the verification process of the chip to be tested, and correcting possible defects of the chip to be tested.
As can be seen from the above description, the coverage driving verification method according to the present embodiment includes: acquiring a first coverage rate corresponding to a first random excitation according to the first random excitation, if the first coverage rate exceeds a coverage rate corresponding to a previous excitation, issuing the first random excitation to enable a chip to be tested to be verified under the first random excitation, if the first coverage rate does not exceed the coverage rate corresponding to the previous excitation, acquiring a second random excitation and issuing the second random excitation to enable the chip to be tested to be verified under the second random excitation, wherein the second coverage rate corresponding to the second random excitation exceeds the coverage rate corresponding to the previous excitation; acquiring output data of the chip to be tested and output data of a reference model of the chip to be tested; and comparing the output data of the chip to be tested with the output data of the reference model to obtain a verification result. The random excitation with the coverage rate necessarily larger than the coverage rate corresponding to the previous excitation is obtained, so that the coverage rate of the chip test is necessarily improved by the random excitation of the round of test, the repeated test of the whole verification process is avoided, and the time consumption of the whole verification process is further reduced.
As shown in fig. 3, the verification system includes a stimulus generating component, and the implementation method for obtaining the first coverage rate corresponding to the first random stimulus according to the first random stimulus includes:
S21, generating the first random stimulus through the stimulus generating component.
Alternatively, the stimulus generation component can be a user-defined class that can be used to generate the random stimulus required for the authentication process.
S22, processing the first random stimulus through the functional coverage rate component to obtain the first coverage rate.
Optionally, the functional coverage rate component has a plurality of functional methods, including a functional method for obtaining an excitation coverage rate, and the first coverage rate can be obtained by calling the functional method of the functional coverage rate component.
Optionally, the second random excitation may also be generated by the excitation generating component, and a method for obtaining the second coverage rate corresponding to the second random excitation is similar to a method for obtaining the first coverage rate, which is not described herein.
As shown in fig. 4, the verification system includes a driving component and an entry monitoring component, and the implementation method for issuing the first random stimulus includes:
S31, the first random excitation is sent to the chip to be tested and the entrance monitoring assembly through the driving assembly.
Optionally, the implementation method for sending the first random stimulus to the chip to be tested and the entrance monitoring component through the driving component includes: the driving component obtains the first random stimulus from the stimulus generation component; the driving component sends the first random excitation to the chip to be tested and the entrance monitoring component, the driving component can successfully send the first random excitation to the chip to be tested according to a certain interface protocol, and the related content of the interface protocol is not described in detail in this embodiment.
S32, acquiring inlet information of the first random excitation through the inlet monitoring component.
Optionally, since the format requirements of the reference model and the chip to be tested on the input data are different, the entry information of the first random stimulus may be data with different format but same content as the first random stimulus. The entry monitoring component may have a related method for converting a data format, and the design of the entry monitoring component will not be described in detail in this embodiment.
S33, sending the entrance information to the reference model through the entrance monitoring component.
Optionally, the implementation method for issuing the second random excitation is consistent with the implementation method for issuing the first random excitation, which is not described in detail herein.
As can be seen from the above description, the implementation method for issuing the first random excitation in this embodiment includes: transmitting the first random stimulus to the chip to be tested and the inlet monitoring assembly through the driving assembly; acquiring inlet information of the first random excitation through the inlet monitoring component; and sending the inlet information to the reference model through the inlet monitoring component. The driving component and the entrance monitoring component can be used for transmitting the data content of the first random excitation to the chip to be tested and the reference model.
As shown in fig. 5, the verification system includes an exit monitoring component, and the implementation method for obtaining the output data of the chip to be tested and the output data of the reference model includes:
S41, if the issued excitation is the first random excitation, acquiring output data of the chip to be tested and output data of the reference model under the first random excitation in real time through the outlet monitoring component.
S42, if the issued excitation is the second random excitation, acquiring output data of the chip to be tested and output data of the reference model under the second random excitation in real time through the outlet monitoring component.
Optionally, the outlet monitoring component may include a first outlet monitoring component and a second outlet monitoring component, where the first outlet monitoring component is configured to obtain output data of the chip to be tested in real time, the second outlet monitoring component is configured to obtain output data of the reference model in real time, and the first outlet monitoring component and the second outlet monitoring component may be integrated in the outlet monitoring component.
Optionally, the implementation method for acquiring, in real time, the output data of the chip to be tested and the output data of the reference model under the first random excitation by the exit monitoring component includes: acquiring output data of the chip to be tested under the first random excitation in real time through the first outlet monitoring component; and acquiring output data of the reference model under the first random excitation in real time through the second outlet monitoring component.
Optionally, the implementation method for acquiring, in real time, the output data of the chip to be tested and the output data of the reference model under the second random excitation by the exit monitoring component includes: acquiring output data of the chip to be tested under the second random excitation in real time through the first outlet monitoring component; and acquiring output data of the reference model under the second random excitation in real time through the second outlet monitoring component.
As can be seen from the above description, the implementation method for obtaining the output data of the chip to be tested and the output data of the reference model according to the present embodiment includes: if the issued excitation is the first random excitation, acquiring output data of the chip to be tested under the first random excitation and output data of the reference model in real time through the outlet monitoring assembly; and if the issued excitation is the second random excitation, acquiring output data of the chip to be tested under the second random excitation and output data of the reference model in real time through the outlet monitoring component. The output data of the chip to be tested and the output data of the reference model are obtained in real time through the outlet monitoring component, so that the verification efficiency of the whole verification process can be effectively improved.
The protection scope of the control method according to the embodiment of the present application is not limited to the execution sequence of the steps listed in the embodiment, and all the schemes implemented by adding or removing steps and replacing steps according to the prior art made by the principles of the present application are included in the protection scope of the present application.
As shown in fig. 6, an embodiment of the present application provides a coverage-driven authentication apparatus 600, the coverage-driven authentication apparatus 600 including:
the coverage rate obtaining module 610 is configured to obtain a first coverage rate corresponding to a first random excitation according to a first random excitation, if the first coverage rate exceeds a coverage rate corresponding to a previous excitation, issue the first random excitation to enable a chip to be tested to verify under the first random excitation, and if the first coverage rate does not exceed the coverage rate corresponding to the previous excitation, obtain a second random excitation and issue the second random excitation to enable the chip to be tested to verify under the second random excitation, where the second coverage rate corresponding to the second random excitation exceeds the coverage rate corresponding to the previous excitation.
And the output data acquisition module 620 is configured to acquire output data of the chip to be tested and output data of a reference model of the chip to be tested.
And the verification result obtaining module 630 is used for comparing the output data of the chip to be tested with the output data of the reference model to obtain a verification result.
As can be seen from the above description, the coverage rate driven verification device in this embodiment can make the random stimulus of the present round of test necessarily improve the coverage rate of the chip test by obtaining the random stimulus whose coverage rate is necessarily greater than the coverage rate corresponding to the previous stimulus, thereby avoiding the repeated test in the whole verification process and reducing the time consumption of the whole verification process.
In the several embodiments provided in the present application, it should be understood that the disclosed apparatus or method may be implemented in other manners. For example, the apparatus embodiments described above are merely illustrative, e.g., the division of modules/units is merely a logical function division, and there may be additional divisions when actually implemented, e.g., multiple modules or units may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or modules or units, which may be in electrical, mechanical or other forms.
The modules/units illustrated as separate components may or may not be physically separate, and components shown as modules/units may or may not be physical modules, i.e., may be located in one place, or may be distributed over a plurality of network elements. Some or all of the modules/units may be selected according to actual needs to achieve the objectives of the embodiments of the present application. For example, functional modules/units in various embodiments of the application may be integrated into one processing module, or each module/unit may exist alone physically, or two or more modules/units may be integrated into one module/unit.
Those of ordinary skill would further appreciate that the elements and algorithm steps of the examples described in connection with the embodiments disclosed herein may be embodied in electronic hardware, in computer software, or in a combination of the two, and that the elements and steps of the examples have been generally described in terms of function in the foregoing description to clearly illustrate the interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
As shown in fig. 5, the present embodiment provides an electronic device 700, which includes a memory 710 storing a computer program; and a processor 720, communicatively coupled to the memory 710, for executing the coverage driven verification method of FIG. 2 when the computer program is invoked.
The embodiment of the application also provides a computer readable storage medium. Those of ordinary skill in the art will appreciate that all or part of the steps in a method implementing the above embodiments may be implemented by a program to instruct a processor, where the program may be stored in a computer readable storage medium, where the storage medium is a non-transitory (non-transitory) medium, such as a random access memory, a read only memory, a flash memory, a hard disk, a solid state disk, a magnetic tape (MAGNETIC TAPE), a floppy disk (floppy disk), a compact disk (optical disk), and any combination thereof. The storage media may be any available media that can be accessed by a computer or a data storage device such as a server, data center, or the like that contains an integration of one or more available media. The usable medium may be a magnetic medium (e.g., a floppy disk, a hard disk, a magnetic tape), an optical medium (e.g., a digital video disc (digital video disc, DVD)), or a semiconductor medium (e.g., a Solid State Drive (SSD)), or the like.
Embodiments of the present application may also provide a computer program product comprising one or more computer instructions. When the computer instructions are loaded and executed on a computing device, the processes or functions in accordance with embodiments of the present application are fully or partially developed. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from one website, computer, or data center to another website, computer, or data center by a wired (e.g., coaxial cable, fiber optic, digital Subscriber Line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.).
The computer program product is executed by a computer, which performs the method according to the preceding method embodiment. The computer program product may be a software installation package, which may be downloaded and executed on a computer in case the aforementioned method is required.
The descriptions of the processes or structures corresponding to the drawings have emphasis, and the descriptions of other processes or structures may be referred to for the parts of a certain process or structure that are not described in detail.
The above embodiments are merely illustrative of the principles of the present application and its effectiveness, and are not intended to limit the application. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the application. Accordingly, it is intended that all equivalent modifications and variations of the application be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.
Claims (5)
1. A coverage driven verification method, characterized by being applied to a verification system, the coverage driven verification method comprising:
Acquiring a first coverage rate corresponding to a first random excitation according to the first random excitation, if the first coverage rate exceeds a coverage rate corresponding to a previous excitation, issuing the first random excitation to enable a chip to be tested to be verified under the first random excitation, if the first coverage rate does not exceed the coverage rate corresponding to the previous excitation, acquiring a second random excitation and issuing the second random excitation to enable the chip to be tested to be verified under the second random excitation, wherein the second coverage rate corresponding to the second random excitation exceeds the coverage rate corresponding to the previous excitation, and the implementation method for acquiring the second random excitation comprises the following steps: continuously generating new random excitation until the coverage rate corresponding to the finally generated random excitation exceeds the coverage rate corresponding to the previous excitation, wherein the finally generated random excitation is the second random excitation;
Acquiring output data of the chip to be tested and output data of a reference model of the chip to be tested;
comparing the output data of the chip to be tested with the output data of the reference model to obtain a verification result;
the verification system comprises a functional coverage rate component, the rate mode of each port of the chip to be tested comprises 10M, 100M and 1000M, the working mode of each port of the chip to be tested comprises full duplex and half duplex, the coverage points of the functional coverage rate component comprise the ports of the chip to be tested, the rate mode and the working mode, the coverage group of the coverage rate component comprises the cross coverage among the coverage points, the verification system comprises an excitation generation component, and the implementation method for acquiring the first coverage rate corresponding to the first random excitation according to the first random excitation comprises the following steps: generating, by the stimulus generation component, the first random stimulus; processing the first random excitation through the functional coverage rate component to obtain the first coverage rate, wherein the functional coverage rate component has a functional method of get_coverage (), and the functional method is used for obtaining the coverage rate of the random excitation in the functional coverage rate component;
the coverage rate driven verification method further comprises the following steps: if the coverage rate corresponding to the previous excitation exceeds a preset coverage rate, not issuing random excitation, wherein the random excitation comprises the first random excitation and the second random excitation, and generating a stop mark, and the stop mark is used for ending the verification process of the chip to be tested;
The verification system comprises a driving component and an entrance monitoring component, and the implementation method for issuing the first random excitation comprises the following steps: transmitting the first random stimulus to the chip to be tested and the inlet monitoring assembly through the driving assembly; acquiring inlet information of the first random excitation through the inlet monitoring component; transmitting, by the portal monitoring component, the portal information to the reference model;
The verification system comprises an outlet monitoring component, and the implementation method for obtaining the output data of the chip to be tested and the output data of the reference model of the chip to be tested comprises the following steps: if the issued excitation is the first random excitation, acquiring output data of the chip to be tested under the first random excitation and output data of the reference model in real time through the outlet monitoring assembly; if the issued excitation is the second random excitation, acquiring output data of the chip to be tested and output data of the reference model under the second random excitation in real time through the outlet monitoring assembly, wherein the outlet monitoring assembly comprises a first outlet monitoring assembly and a second outlet monitoring assembly, the first outlet monitoring assembly is used for acquiring the output data of the chip to be tested in real time, the second outlet monitoring assembly is used for acquiring the output data of the reference model in real time, and the first outlet monitoring assembly and the second outlet monitoring assembly can be integrated in the outlet monitoring assembly;
The implementation method for acquiring the output data of the chip to be tested and the output data of the reference model under the first random excitation in real time through the outlet monitoring component comprises the following steps: acquiring output data of the chip to be tested under the first random excitation in real time through the first outlet monitoring component; and acquiring output data of the reference model under the first random excitation in real time through the second outlet monitoring component.
2. The coverage rate driven verification method according to claim 1, wherein the verification system further comprises a verification component, and the implementation method for comparing the output data of the chip to be tested with the output data of the reference model comprises: and carrying out real-time comparison processing on the output data of the chip to be tested and the output data of the reference model through the verification component so as to acquire the verification result in real time.
3. A coverage driven verification device for use in a verification system, the coverage driven verification device comprising:
The coverage rate obtaining module is configured to obtain a first coverage rate corresponding to a first random excitation according to a first random excitation, if the first coverage rate exceeds a coverage rate corresponding to a previous excitation, issue the first random excitation to enable a chip to be tested to verify under the first random excitation, and if the first coverage rate does not exceed the coverage rate corresponding to the previous excitation, obtain a second random excitation and issue the second random excitation to enable the chip to be tested to verify under the second random excitation, where the second coverage rate corresponding to the second random excitation exceeds the coverage rate corresponding to the previous excitation, and the implementation method for obtaining the second random excitation includes: continuously generating new random excitation until the coverage rate corresponding to the finally generated random excitation exceeds the coverage rate corresponding to the previous excitation, wherein the finally generated random excitation is the second random excitation;
the output data acquisition module is used for acquiring output data of the chip to be detected and output data of a reference model of the chip to be detected;
The verification result acquisition module is used for comparing the output data of the chip to be tested with the output data of the reference model to acquire a verification result;
The verification system comprises a functional coverage rate component, wherein the rate mode of each port of the chip to be tested comprises 10M, 100M and 1000M, the working mode of each port of the chip to be tested comprises full duplex and half duplex, the coverage points of the functional coverage rate component comprise the ports of the chip to be tested, the rate mode and the working mode, the coverage groups of the coverage rate component comprise the cross coverage among the coverage points, the verification system comprises an excitation generation component, and the coverage rate module comprises: generating, by the stimulus generation component, the first random stimulus; processing the first random excitation through the functional coverage rate component to obtain the first coverage rate, wherein the functional coverage rate component has a functional method of get_coverage (), and the functional method is used for obtaining the coverage rate of the random excitation in the functional coverage rate component;
The coverage driven verification device further includes: if the coverage rate corresponding to the previous excitation exceeds a preset coverage rate, not issuing random excitation, wherein the random excitation comprises the first random excitation and the second random excitation, and generating a stop mark, and the stop mark is used for ending the verification process of the chip to be tested;
The verification system comprises a driving component and an entrance monitoring component, and the implementation method for issuing the first random excitation comprises the following steps: transmitting the first random stimulus to the chip to be tested and the inlet monitoring assembly through the driving assembly; acquiring inlet information of the first random excitation through the inlet monitoring component; transmitting, by the portal monitoring component, the portal information to the reference model;
The verification system comprises an outlet monitoring component, and the implementation method for obtaining the output data of the chip to be tested and the output data of the reference model of the chip to be tested comprises the following steps: if the issued excitation is the first random excitation, acquiring output data of the chip to be tested under the first random excitation and output data of the reference model in real time through the outlet monitoring assembly; if the issued excitation is the second random excitation, acquiring output data of the chip to be tested and output data of the reference model under the second random excitation in real time through the outlet monitoring assembly, wherein the outlet monitoring assembly comprises a first outlet monitoring assembly and a second outlet monitoring assembly, the first outlet monitoring assembly is used for acquiring the output data of the chip to be tested in real time, the second outlet monitoring assembly is used for acquiring the output data of the reference model in real time, and the first outlet monitoring assembly and the second outlet monitoring assembly can be integrated in the outlet monitoring assembly;
The implementation method for acquiring the output data of the chip to be tested and the output data of the reference model under the first random excitation in real time through the outlet monitoring component comprises the following steps: acquiring output data of the chip to be tested under the first random excitation in real time through the first outlet monitoring component; and acquiring output data of the reference model under the first random excitation in real time through the second outlet monitoring component.
4. A computer readable storage medium having stored thereon a computer program, which when executed by a processor implements the coverage driven verification method of any of claims 1-2.
5. An electronic device, the electronic device comprising:
A memory storing a computer program;
A processor, in communication with the memory, which when invoked executes the coverage driven verification method of any one of claims 1-2.
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