CN115794569A - High-speed serial link testing method and device - Google Patents

Abstract

According to the application, a tested device can receive a first test code stream sent by the testing device through a receiver. After receiving the first test code stream, the tested device obtains a test result by analyzing the first test code stream and a reference test code stream, wherein the test result can represent the receiving performance of the high-speed serial interface and the transmission performance of a communication link connected with the high-speed serial interface, and the reference test code stream is configured in advance. The tested equipment can automatically analyze the first test code stream and the reference test code stream to obtain a test result. The received first test code stream does not need to be fed back to the test equipment any more, the test equipment obtains a test result, and the first test code stream does not need to be fed back to the test equipment through a loop, so that the probability of introducing error codes into the first test code stream is reduced, and the test accuracy is ensured.

Description

High-speed serial link testing method and device

Technical Field

The present application relates to the field of communications technologies, and in particular, to a method and an apparatus for testing a high-speed serial link.

Background

The receiving compliance test is used for testing the receiving performance of an interface in the equipment and the transmission performance of a communication link connected with the interface, and judging the receiving performance of the interface in the equipment and the transmission performance of the communication link connected with the interface (especially a channel in the communication link for transmitting data to the interface) by analyzing whether the code stream error rate received by the equipment meets the requirement.

At present, when a reception compliance test is performed, an error code tester may send a test code stream to a device to be tested, after the device to be tested receives the test code stream through a receiver of an interface, the test code stream is fed back to the error code tester through a sender of the interface, and the error code tester obtains a test result of the reception compliance test by comparing the sent test code stream with the received test code stream. It can be seen that the receive compliance test relies on a loop between the device under test and the error tester. Because the test code stream needs to be transmitted back to the error code tester from the tested equipment, the error code is easily introduced in the process, so that the test result obtained by the error code tester has errors, and the accuracy of the receiving compliance test is poor.

Disclosure of Invention

The application provides a high-speed serial link testing method and device, which are used for improving the accuracy of receiving compliance testing.

In a first aspect, an embodiment of the present application provides a high-speed serial link testing method, which may be used to test a receiver of a high-speed serial interface in a device under test. After receiving the first test code stream, the tested device can obtain a test result by analyzing the first test code stream and a reference test code stream, wherein the test result can represent the receiving performance of the high-speed serial interface and the transmission performance of a communication link connected with the high-speed serial interface, and the reference test code stream is configured in advance.

By the method, the tested equipment can automatically analyze the first test code stream and the reference test code stream to obtain a test result. The received first test code stream does not need to be fed back to the test equipment any more, the test equipment obtains a test result, and the first test code stream does not need to be fed back to the test equipment through a loop, so that the probability of introducing error codes into the first test code stream is reduced, and the test accuracy is ensured.

In a possible embodiment, the device under test is further equipped with a presentation function, which is able to present the determined test result.

By the method, the user can know the test result in time by displaying the test result, and the user experience is improved.

In one possible embodiment, the device under test may also send the test results to the test device via a transmitter of the high-speed serial interface.

By the method, the test result is fed back to the test equipment, and the test equipment can accurately obtain the test result without analyzing.

In one possible embodiment, the test results are presented in a variety of formats. The test result may be a difference bit number existing in the first test code stream, and the difference bit number indicates the number of bits in the first test code stream that are different from the reference test code stream. The test result may also be a bit error rate of the first test code stream, where the bit error rate may be equal to a ratio of the difference bit number to a total bit number in the first test code stream.

By the method, the expression form of the test result is flexible and is suitable for different scenes.

In one possible implementation, the reference test code stream may be pre-configured for the device under test. For example, the reference test code stream is default and configured on the device under test. For another example, the reference test code stream may also be notified to the test device by the test device. The device to be tested may store a reference test code stream set, where the reference test code stream set may include a plurality of different reference test code streams. Each reference test code stream corresponds to an identifier. And the corresponding identifications of different reference test code streams are different. The test equipment can send the identifier of the reference test code stream to the test equipment, and after the tested equipment obtains the identifier of the reference test code stream from the test equipment, the tested equipment can determine the reference test code stream corresponding to the identifier from the reference test code stream set according to the identifier of the reference test code stream.

By the method, the reference test code stream can be pre-configured in the tested equipment in different modes, and the application scene is effectively expanded.

In a possible implementation manner, before the device under test receives the first test code stream sent by the test device through the receiver, the device under test may also perform self-test to determine whether the device under test has an error code detection function, that is, whether a difference bit of the code stream can be accurately identified. During self-test, the test device may send a second test code stream (also referred to as a self-test code stream in the embodiment) to the device under test, where the second test code stream may include a target number of difference bits. After the tested equipment receives the second test code stream through the receiver, the difference bit number in the second test code stream can be determined, if the difference bit number in the second test code stream is equal to the target number, the self-checking is passed, and the test equipment can send the first test code stream to the tested equipment. If the number of the different bits in the second test code stream is not equal to the target number, it indicates that the self-checking fails, and the test device may not send the first test code stream to the device under test.

By the method, the tested equipment is self-tested, and the follow-up test result can be ensured to be reliable and accurate.

In a possible implementation manner, when the test device sends the first test code stream to the device under test, the first test code stream may be sent at different transmission rates. That is, the device under test can receive the first test code stream sent by the test device at different transmission rates through the receiver. Therefore, the receiving performance of the high-speed serial interface of the tested device and the transmission performance of the communication link connected with the high-speed serial interface can be tested at different transmission rates.

By the method, test results at different transmission rates can be obtained, and the integrity of the test is ensured.

In a possible implementation manner, before sending the first test code stream to the device under test, the test device may further notify the transmission rate of the first test code stream. For example, the test device may send a notification message to the device under test, which may indicate a transmission rate of the first test codestream. The device to be tested can receive the notification message and determine the transmission rate of the first test code stream according to the notification message. When the test result is displayed subsequently, the transmission rate can also be displayed to indicate that the test result is the test result at the transmission rate.

By the method, the tested equipment can receive the first test code stream at a corresponding rate by determining the transmission rate of the first test code stream, so that the first test code stream and the reference test code stream can be accurately analyzed to obtain a test result.

In a second aspect, an embodiment of the present application further provides a link testing apparatus, where the link testing apparatus has a function of implementing the behavior in the method example of the first aspect, and for beneficial effects, reference may be made to the description of the first aspect, which is not described herein again. The functions can be realized by hardware, and the functions can also be realized by executing corresponding software by hardware. The hardware or software includes one or more modules corresponding to the functions described above. In a possible design, the structure of the link testing apparatus includes a receiving module, an analyzing module, and optionally, a displaying module and a sending module, where these modules may perform corresponding functions in the method example of the first aspect, for which specific reference is made to detailed description in the method example, and details are not repeated here.

In a third aspect, an embodiment of the present application further provides a computing device, where the computing device has a function of implementing the behavior in the method example of the first aspect, and for beneficial effects, reference may be made to the description of the first aspect and details are not repeated here. The structure of the computing device comprises a processor and a memory, wherein the processor is configured to support the computing device to execute the corresponding functions in the method of the first aspect. The memory is coupled to the processor and retains program instructions and data necessary for the computing device. The structure of the computing equipment also comprises a communication interface which is used for communicating with other equipment, such as sending a first test code stream and a second test code stream, and receiving a test result.

In a fourth aspect, the present application further provides a computer-readable storage medium having stored therein instructions, which, when executed on a computer, cause the computer to perform the method described in the first aspect and the various possible implementations of the first aspect.

In a fifth aspect, the present application further provides a computer program product containing instructions that, when executed on a computer, cause the computer to perform the method described in the first aspect and the various possible implementations of the first aspect.

In a sixth aspect, the present application further provides a computer chip, where the chip is connected to a memory, and the chip is configured to read and execute a software program stored in the memory, and perform the method described in the first aspect and each possible implementation manner of the first aspect.

Drawings

FIG. 1 is a schematic view of an eye diagram;

FIG. 2 is a schematic diagram of a test undergoing compliance testing;

FIG. 3 is a schematic diagram of a system architecture provided herein;

FIG. 4 is a schematic diagram of a high-speed serial link testing method according to the present application;

fig. 5 is a schematic structural diagram of a link testing apparatus provided in the present application;

fig. 6 is a schematic structural diagram of a computing device provided in the present application.

Detailed Description

Before explaining a high-speed serial link testing method and device provided by the embodiments of the present application, concepts related to the embodiments of the present application are explained:

1. and (6) code stream.

The plurality of signals transmitted in succession may form a code stream. The code stream may be a signal stream composed of a series of analog signals (e.g., high and low levels), or may be a signal stream composed of a series of digital signals (e.g., 0 and 1).

2. A Compliance Test (Rx Compliance Test) was accepted.

The acceptance compliance test is one of the high-speed link signal quality certification tests, and what is tested by the acceptance compliance test is the receiving performance of the interface under test in the device under test and the transmission performance of the communication link connected with the interface under test.

It should be noted that the communication link connected to the interface to be tested may include two types of channels, one being a channel for transmitting a code stream to the interface to be tested. The other is a channel for transmitting data sent by the tested interface. The transmission performance of the communication link tested by the compliance test mainly focuses on the transmission performance of a channel used for transmitting data to the tested interface in the communication link.

In the compliance test, whether the code stream received by the tested interface meets the requirement of the error rate is judged, for example, whether the difference bit number or the error rate in the received code stream is lower than a threshold value is determined, so that whether the receiver in the tested interface can accurately receive the code stream and whether the communication link can introduce less error codes and accurately transmit the code stream to the tested interface is evaluated. During the receiving compliance test, the testing device (such as an error code tester) can send a code stream meeting the specification requirement to the interface of the tested device through the communication link (for example, the signal can form a minimum eye pattern), and whether the code stream meets the requirement of the signal error rate is determined by analyzing the code stream received by the interface of the tested device.

3. Eye pattern.

An eye diagram is a series of signals superimposed together to form an eye-like image, which may be displayed on an oscilloscope for analyzing whether the signals meet a criterion.

Fig. 1 is a schematic diagram of an eye diagram. The portion of the black line is the eye diagram shown on the oscilloscope. The shaded area may be referred to as a non-standard area. The non-standard area is an area that the eye pattern cannot touch. If the eye pattern touches the shaded area, the signal forming the eye pattern is not qualified. In accepting compliance testing, the eye diagram formed by the signals sent by the test equipment needs to meet the criteria. The criteria that the eye diagram needs to satisfy may be different for different types of communication links and different transmission rates. For example, standards that an eye diagram needs to satisfy, such as height and width of the eye diagram at different transmission rates, are specified in a transmitted bitstream Compliance test (Tx Compliance test) for different transmission rates in a high speed serial computer extension bus (PCIe) and a Serial Advanced Technology Attachment (SATA) bus.

In addition, in order to ensure the accuracy of the compliance test, the eye pattern formed by the signal sent by the test equipment can be a minimum eye pattern, and the minimum eye pattern refers to an eye pattern which is not in contact with the shadow area and is adjacent to the shadow area.

The following describes the procedure for receiving compliance tests:

as shown in fig. 2, a schematic diagram of a test system for receiving compliance tests, the test system includes an error code tester and a device under test. The device under test may be mounted on a test board.

The error code tester can send out a test code stream, and can determine the difference bit number of the fed back code stream relative to the sent test code stream by comparing the code stream fed back by the tested equipment with the sent test code stream, wherein the difference bit refers to the bit of the difference between the fed back code stream and the sent code stream. And further determining whether the interface of the device to be tested and the communication link connected with the interface pass the receiving compliance test or not through the difference bit number, and displaying the test result, such as displaying the difference bit number or whether the interface passes the receiving compliance test or not.

The device under test may be any device having a high speed serial interface. The error tester may establish a channel for communication with the device under test.

Calibration is required before the interface of the device under test performs a receive compliance test.

The calibration includes the following operations:

operation one, establish channel 1 between the error tester and the receiver of the device under test interface. The length of the channel 1 is the maximum length within the standard allowed range.

And secondly, the error code tester can send a test code stream capable of forming a minimum eye pattern at a test point, namely the interface of the tested device, through the channel 1.

After calibration, a formal test procedure may be entered. The receiver and the transmitter of the interface of the device under test can form an inner loop at the time of testing. The error tester may also be connected to the transmitter of the interface via another channel 2 (the length of this channel 2 may be smaller than the channel 1 between the error tester and the receiver of the device under test interface). In the testing process, the error code tester can send a testing code stream to the tested equipment through a channel 1 between the error code tester and the receiver of the interface. The test code stream received by the interface port in the interface can be transmitted to the transmitter through the internal loop, and then the test code stream received by the interface device is transmitted to the error code tester through the transmitter.

The error code tester can obtain a test result by comparing the test code stream fed back by the tested equipment with the sent test code stream, namely, the bit number difference in the test code stream fed back by the tested equipment is displayed.

As can be seen from the above description, the receiving compliance test is currently implemented by a loop between the device under test and the error tester, and the detection result of the error tester is not only related to the channel 1, but also related to the internal loop of the device under test and the channel 2. In the actual testing process, error codes may be introduced into the inner loop or the channel 2, so that the testing result of the error code tester is inaccurate, and the accuracy of the receiving compliance test is affected.

It should be noted that the receive compliance test is one of the tests mentioned in some high speed serial link standards (e.g., PCIe or SATA). Tests used in other communication link standards to evaluate the reception performance of an interface, and the transmission performance of a communication link to which the interface is connected, may also be referred to by other names. The method and the device only provide a test idea for evaluating the receiving performance of the interface and the transmission performance of the communication link connected with the interface, and the test idea can be used in a receiving compliance test and also can be used in other tests. The embodiments of the present application are described only by taking the reception compliance test as an example.

In order to ensure the accuracy of the reception compliance test, the embodiment of the present application provides a high-speed serial link test method, as shown in fig. 3, which is a schematic structural diagram of a system provided by the embodiment of the present application, and the system includes a test device 200 and a device under test 100.

The device under test 100 has a tested interface 110 thereon, the tested interface 110 may be a high-speed serial interface, and the tested interface 110 includes a receiver 111 and a transmitter 112. In the present application, the device under test 100 has an error detection function, and is capable of determining an error state of a code stream (e.g., a test code stream and a self-check code stream) obtained by analyzing the receiver 111 of the interface under test 110, for example, determining a difference bit number or an error rate in the received code stream, where the difference bit number refers to a number of bits that are different between the received code stream and the code stream sent by the actual test device 200. The bit error rate is equal to the ratio of the number of differential bits to the total number of bits of the received code stream. Further, the receiving performance of the interface under test 110 and the transmission performance of the communication link connected to the interface under test 110 are evaluated by the error state of the code stream.

The device under test 100 may also display the determined error code state of the code stream, and the embodiment of the present application does not limit the manner in which the device under test 100 displays the determined error code state of the code stream.

For example, the device under test 100 may also have a display function. For example, a display component 120, such as a display screen, may be included in the device under test 100, and the display component 120 may be capable of displaying the error code status determined by the device under test 100, such as displaying the number of differential bits or the error rate in the received codestream.

For another example, the device under test 100 may also have a voice broadcast function. For example, a voice playing component 130, such as a speaker, may be included in the device under test 100, and the voice playing component 130 may be capable of voice prompting the determined error code status of the device under test 100, such as the number of differential bits or the error rate in the test code stream received by the voice prompt.

For another example, the device under test 100 may also have a document printing function. For example, a printing component 140 may be included in the device under test 100, and the printing component 140 may be capable of printing the error code status determined by the device under test 100 on paper, such as printing a difference bit number or an error rate in the received codestream on paper, through which a user may determine the error code status determined by the device under test 100.

The device under test 100 may also feed back the determined error code status of the code stream to the testing device 200, for example, a feedback channel is established between the transmitter 112 of the interface under test 110 and the testing device 200, and the determined error code status of the code stream is fed back to the testing device 200 through the feedback channel.

The test device 200 is a device that can send out a specific test code stream, the embodiment of the present application does not limit the type of the test device 200, and the test device 200 may be an error code tester or a code pattern generator. Any device capable of sending out a code stream can be used as the test device 200.

Three channels can be established between the device under test 100 and the testing device 200, which are respectively a self-test channel, a testing channel and a feedback channel for performing self-test. Wherein, the length of the test channel can be larger than that of the self-test channel.

The self-test channel communicates the test equipment 200 with the receiver 111 of the interface under test 110. The test device 200 may send the self-test code stream to the device under test 100 through the self-test channel.

The test channel communicates the test equipment 200 with the receiver 111 of the interface under test 110. The test device 200 may send the test code stream to the device under test 100 through the test channel.

Generally, only one of the test path or the self-test path exists between the device under test 100 and the test device 200 at the same time, and for example, when the test path needs to be constructed, the self-test path may be released first. The self-checking channel and the testing channel can be two channels with different lengths, for example, the self-checking channel can be a channel with a smaller length, so as to ensure that error codes are not introduced in the transmission process of the self-checking code stream. The test channel may be a longer length channel to ensure the accuracy of the compliance test. For example, the length of the test channel may be a maximum length specified by a standard. The specific value of the maximum length is not limited in the embodiments of the present application, and the maximum length of the channel may be specified by the transmission loss of the signal in some standards, for example, it is required that the transmission loss of the signal cannot exceed 20 db at 16 giga transmission per second (GT/s).

In some cases, the self-check channel and the test channel may also be the same channel, that is, the channel is generally used for transmitting the self-check code stream and the test code stream.

The feedback channel communicates the test equipment 200 with the transmitter 112 of the interface under test 110. The device under test 100 may send the error code status of the code stream, such as the number of differential bits existing in the code stream (e.g., a self-check code stream or a test code stream) to the test device 200 through the feedback channel.

In the high-speed serial link testing method provided in the embodiment of the present application, the device under test 100 can automatically analyze the test code stream received from the testing device 200 and the reference test code stream configured in advance, and obtain the test result, so as to further determine the receiving performance of the interface under test 110 and the transmission performance of the communication link connected to the interface under test 110, that is, the device under test 100 can automatically implement the reception compliance test to obtain the test result, and the received test code stream does not need to be fed back to the testing device 200, and the testing device 200 analyzes and obtains the test result. The error code possibly introduced in the test process is effectively reduced, and the accuracy of the test result is ensured.

The following describes a high-speed serial link testing method provided in this embodiment with reference to fig. 4, where the method includes two parts, one part is a self-checking process of the device under test 100, and it is determined whether the device under test 100 has an error detection function through the self-checking process, and whether an error state of a received code stream can be accurately analyzed (see steps 401 to 403). The other part is the process of testing the device under test 100 (see steps 404 to 407).

Step 401: a self-test channel is constructed between the test device 200 and the interface under test 110 of the device under test 100, which can connect the device under test 100 with the receiver 111 of the device under test 100. The length of the self-checking channel can be as small as possible, and the self-checking channel with the small length can effectively avoid error codes which are possibly introduced in the follow-up transmission of the self-checking code stream.

Step 402: the test device 200 sends the self-test code stream to the tested interface 110 of the device under test 100 through the self-test channel. The self-check code stream includes the difference bits of the target number. These difference bits may be randomly added by the test device 200 to the original codestream, which may be known to the device under test 100 and the test device 200. If the original code stream can be pre-configured in the device under test 100.

Step 403: the device under test 100 obtains the self-check code stream from the interface under test 110, and determines the number of differential bits in the self-check code stream.

The device under test 100 may compare the self-check code stream with the original code stream to determine the number of bits in the self-check code stream that are different from each other. The device under test 100 may exhibit the determined number of differential bits.

If the difference bit number in the self-check code stream determined by the device under test 100 is not consistent with the target number, it indicates that the device under test 100 cannot accurately analyze the code stream, does not have an error code detection function, and cannot perform subsequent steps. If the difference bit number in the self-check code stream determined by the device under test 100 is not consistent with the target number, it indicates that the device under test 100 has an error code detection function, and can accurately analyze the code stream, and step 404 can be executed.

In step 403, taking the difference bit number as an example for illustration, the device under test 100 may also determine the bit error rate of the self-checking code stream, that is, obtain the bit error rate by using the ratio of the difference bit number to the total bit number of the self-checking code stream, and determine whether the bit error rate is equal to the ratio of the target number to the total bit number of the self-checking code stream.

Step 404: a test channel is constructed before the test device 200 and the interface under test 110 of the device under test 100, which test channel can connect the device under test 100 with the receiver 111 of the device under test 100 and ensure that the transmitted signals can form a minimal eye pattern at the device under test 100 through the test channel.

The length of the test channel can be as long as possible, and the transmission path of the test code stream is increased to a certain extent by the test channel with the longer length, so that the probability of introducing error codes into the test code stream can be greatly increased, and if the test code stream received by the tested interface 110 in the tested device 100 can still meet the requirement of the error code rate under the condition, the receiving performance of the tested interface 110 is better, and the accuracy of the test result is effectively ensured. The length of the test channel may be the maximum length allowed by the standard.

The accuracy of the test results can also be ensured by transmitting a signal capable of forming a minimum eye pattern for the reception compliance test. This is because if the test code stream received by the interface 110 under test in the device under test 100 can still satisfy the requirement of the bit error rate when transmitting the signal capable of forming the minimum eye pattern, the test code stream received by the interface 110 under test can also satisfy the requirement of the bit error rate when transmitting other signals meeting the standard.

Step 405: the test device 200 sends the test code stream to the tested interface 110 of the device under test 100 through the test channel.

When the test device 200 sends the test code stream to the device under test 100, a code stream start flag may be added before the test code stream, where the code stream start flag may be a bit having a first value, and the code stream after the code stream start flag is marked with the code stream start flag is the test code stream. The first value may be pre-agreed.

When the device under test 100 detects the start flag of the code stream through the tested interface 110, the test code stream is received. After the test code stream is sent, the test device 200 may add a code stream end mark after the test code stream. Similar to the code stream start mark, the code stream end mark may be a bit with a second value, the code stream end mark marks that the test code stream has ended, and the test code stream does not exist subsequently.

Step 406: the device under test 100 obtains a test code stream from the interface under test 110, and analyzes the test code stream and the reference test code stream to obtain a test result, such as determining a difference bit number existing in the test code stream or an error rate of the test code stream.

In step 406, the device under test 100 may compare the test code stream with a reference test code stream to determine a difference bit number existing in the test code stream or an error rate of the test code stream, where the reference test code stream may be preconfigured, for example, the reference test code stream may be notified to the device under test 100 in advance by the test device 200, or may be set by default.

The embodiment of the present application does not limit the way in which the test device 200 notifies the device under test 100 in advance of the reference test code stream.

For example, a set of reference test code streams may be stored in the device under test 100, where the reference test code streams include a plurality of different reference test code streams. Each reference test code stream is provided with an identifier, the identifiers of different reference test code streams are different, and one identifier corresponds to one reference test code stream. Before sending the test code stream, the test device 200 may send an identifier of the reference test code stream to the device under test 100. The device under test 100 obtains the reference test code stream corresponding to the identifier from the reference test code stream set through the identifier of the reference test code stream, so as to compare the reference test code stream with the received test code stream.

For another example, the test device 200 may also send the reference test code stream to the test device 200 in advance, for example, the test device 200 may send the reference test code stream to the test device 200 through a previously established self-test channel, so as to avoid introducing unnecessary bit errors into the reference test code stream.

As another example, the reference test code stream is default and is configured in the test device 200.

Step 407: the device under test 100 displays the test result, such as displaying the bit difference or the bit error rate, or feeds back the test result to the test device 200. In the following description, the test result is taken as an example of the differential bit number, and the bit error rate display and the feedback method are similar to those of the differential bit number and are not described herein again. The device under test 100 may also store the test results.

The tested device 100 can display the difference bit number through the display component 120, can play the difference bit number through the voice playing component 130, and can print the difference bit number on paper through the printing component 140, so that the user can know the detection result.

A feedback channel is established between the testing device 200 and the transmitter 112 of the interface under test 110, the device under test 100 can feed back the determined differential bit number to the testing device 200 through the feedback channel, and after receiving the differential bit number, the testing device 200 can display the received differential bit number.

It should be noted that the transmission rate of the code stream may also be a factor of introducing bit errors into the code stream. For example, when the transmission rate of the code stream is too high, the intervals of the signals in the code stream are small, interference easily exists between the signals, and error codes are easily generated. In performing the reception compliance test, the test may be performed at different transmission rates. For example, the test code stream may be sent at different transmission rates, and the detection results at different transmission rates are obtained, that is, the number of differential bits existing in the test code stream at different transmission rates is determined.

When performing the reception compliance test at different transmission rates, the initial transmission rate and the switching manner of the transmission rate may be agreed in advance between the device under test 100 and the testing device 200.

At the start of the test, the transmission rate may be the lowest transmission rate, e.g. 4GT/s, after which the transmission rate may be gradually increased. At the start of the test, the transmission rate may be the highest transmission rate, e.g. 64GT/s, after which the transmission rate may be gradually decreased.

The test device 200 may notify the device under test 100 that the transmission rate needs to be switched by sending a notification message, and may also notify the device under test 100 of a specific value of the transmission rate after switching. The time length for receiving the compliance test at each transmission rate can also be agreed between the testing device 200 and the tested device 100, and after the agreed time length is reached, the next transmission rate is switched to, and the testing code stream is sent at the transmission rate.

Due to the introduction of the reception compliance test at different transmission rates, the device under test 100 may also mark the transmission rate when presenting the test result to indicate that the test result is the test result at the transmission rate. Similarly, when the device under test 100 presents the test result to the test device 200, the transmission rate may also be labeled to indicate that the test result is the test result at the transmission rate.

Based on the same inventive concept as the method embodiment, the embodiment of the present application further provides a link testing apparatus, where the link testing apparatus is configured to execute the method executed by the device under test in the method embodiment shown in fig. 4, and related features may refer to the method embodiment described above, and are not described herein again. As shown in fig. 5, the link test apparatus 500 is capable of testing a receiver of a high-speed serial interface in a device under test, and the link test apparatus 500 is disposed on the device under test 100. The link testing apparatus 500 includes a receiving module 501 and an analyzing module 502.

The receiving module 501 is configured to receive, through a receiver, a first test code stream sent by a test device.

The analysis module 502 is configured to obtain a test result by analyzing the first test code stream and a reference test code stream, where the test result is used to represent a receiving performance of the high-speed serial interface and a transmission performance of a communication link connected to the high-speed serial interface, and the reference test code stream is configured in advance.

In one possible embodiment, the link testing apparatus 500 further includes a presentation module 503. The presentation module 503 may present the test results.

In one possible embodiment, the link testing apparatus 500 further includes a sending module 504. The sending module 504 may send the test result to the test equipment through a transmitter of the high-speed serial interface.

In a possible implementation manner, the test result is a difference bit number existing in the first test code stream or an error rate of the first test code stream.

In one possible embodiment, the reference test code stream is pre-configured to the link test apparatus 500. For example, the parameter test code stream is default and is configured in the link test apparatus 500. For another example, the reference test code stream may be notified to the link test apparatus 500 by the test device. The receiving module 501 may obtain an identifier of a reference test code stream from the test device; then, the analysis module 502 determines a reference test code stream corresponding to the identifier from the reference test code stream set according to the identifier of the reference test code stream, where the reference test code stream includes multiple different reference test code streams, and each reference test code stream corresponds to one identifier.

In a possible implementation manner, before the receiving module 501 receives the first test code stream sent by the error code tester through the receiver, the receiving module may also receive a second test code stream sent by the test equipment through the receiver, where the second test code stream includes the target number of difference bits. The analysis module 502 may determine a difference bit number in the second test code stream, where the difference bit number in the second test code stream is equal to the target number.

In a possible implementation manner, when the receiving module 501 receives the first test code stream sent by the test device through the receiver, the first test code stream sent by the test device at different transmission rates may be received through the receiver.

In a possible implementation manner, the receiving module 501 may further obtain a notification message sent by the test device, where the notification message is used to indicate a transmission rate of the first test code stream.

It should be noted that, in the embodiment of the present application, the division of the module is schematic, and is only one logic function division, and another division manner may be available in actual implementation. Each functional module in the embodiments of the present application may be integrated into one processing module, or each module may exist alone physically, or two or more modules are integrated into one module. The integrated module can be realized in a hardware mode, and can also be realized in a software functional module mode.

The above-described embodiments may be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented in software, the above-described embodiments may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loaded or executed on a computer, cause the flow or functions according to embodiments of the invention to occur, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a network of computers, or other programmable device. The computer instructions may be stored in a computer readable storage medium or transmitted from one computer readable storage medium to another, for example, from one website site, computer, server, or data center to another website site, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital Subscriber Line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device, such as a server, data center, etc., that contains one or more collections of available media. The usable medium may be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium. The semiconductor medium may be a Solid State Drive (SSD).

In a simple embodiment, those skilled in the art will appreciate that the device under test may take the form shown in FIG. 6 in the embodiment shown in FIG. 2.

The management device 600 shown in fig. 6 includes at least one processor 601, a memory 602, and optionally a communication interface 603, where the communication interface 603 may also be referred to as a high-speed serial interface or interface.

The memory 602 may be a volatile memory, such as a random access memory; the memory may also be a non-volatile memory such as, but not limited to, a read-only memory, a flash memory, a Hard Disk Drive (HDD) or solid-state drive (SSD), or the memory 602 is any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer. The memory 602 may be a combination of the above.

The specific connection medium between the processor 601 and the memory 602 is not limited in the embodiments of the present application.

The processor 601 may be a Central Processing Unit (CPU), and the processor 601 may also be other general purpose processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic device, discrete hardware component, artificial intelligence chip, chip on chip, etc. A general purpose processor may be a microprocessor or any conventional processor or the like.

When the link testing apparatus 500 or the device under test takes the form shown in fig. 6, the processor 601 in fig. 6 may execute the instructions by calling a computer stored in the memory 602, so that the link testing apparatus 500 or the device under test may perform the method performed by the device under test in any of the above method embodiments.

Specifically, the functions/implementation processes of the receiving module 501, the analyzing module 502, the presenting module 503 and the sending module 504 in fig. 5 can be implemented by the processor 601 in fig. 6 calling a computer executing instruction stored in the memory 602. Alternatively, the functions/implementation procedures of the analysis module 502 and the presentation module 503 in fig. 5 may be implemented by the processor 601 in fig. 6 calling a computer executing instruction stored in the memory 602, and the functions/implementation procedures of the receiving module 501 or the sending module 504 in fig. 5 may be implemented by the communication interface 603 in fig. 6.

As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.

The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

It will be apparent to those skilled in the art that various changes and modifications may be made in the present application without departing from the scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is intended to include such modifications and variations as well.

Claims (18)

1. A high-speed serial link testing method, for testing a receiver of a high-speed interface in a device under test, the method comprising:

the tested device receives a first test code stream sent by the test device through the receiver;

the tested equipment obtains a test result by analyzing the first test code stream and a reference test code stream, the test result is used for representing the receiving performance of the high-speed serial interface and the transmission performance of a communication link connected with the high-speed serial interface, and the reference test code stream is configured in advance.

2. The method of claim 1, wherein the method further comprises:

and the tested device displays the test result.

3. The method of claim 1 or 2, wherein the method further comprises:

and the tested device sends the test result to the test device through the transmitter of the high-speed serial interface.

4. The method of any one of claims 1-3, wherein the test result is a difference number of bits present in the first test code stream or an error rate of the first test code stream.

5. The method of any of claims 1-4, wherein the reference test codestream is preconfigured, comprising:

the tested equipment acquires the identification of the reference test code stream from the test equipment;

the tested equipment determines a reference test code stream corresponding to the identification from a reference test code stream set according to the identification of the reference test code stream, wherein the reference test code stream comprises a plurality of different reference test code streams, and each reference test code stream corresponds to one identification.

6. The method of any one of claims 1 to 5, wherein before the device under test receives the first test code stream sent by the test device through the receiver, the method comprises:

the tested device receives a second test code stream sent by the test device through the receiver, wherein the second test code stream comprises target number of difference bits;

and the tested equipment determines the difference bit number in the second test code stream, wherein the difference bit number in the second test code stream is equal to the target number.

7. The method of any one of claims 1-6, wherein the receiving, by the device under test, the first test code stream sent by the test device via the receiver comprises:

and the tested device receives the first test code stream sent by the test device at different transmission rates through the receiver.

8. The method of any one of claims 1 to 7, wherein before the device under test receives the first test code stream sent by the test device through the receiver, the method further comprises:

and the tested device acquires a notification message sent by the testing device, wherein the notification message is used for indicating the transmission rate of the first testing code stream.

9. The link testing device is characterized by being used for testing a receiver of a high-speed serial interface in a tested device and comprising a receiving module and an analyzing module;

the receiving module is used for receiving a first test code stream sent by the test equipment through the receiver;

the analysis module is used for obtaining a test result by analyzing the first test code stream and a reference test code stream, wherein the test result is used for representing the receiving performance of the high-speed serial interface and the transmission performance of a communication link connected with the high-speed serial interface, and the reference test code stream is configured in advance.

10. The apparatus of claim 9, wherein the link testing apparatus further comprises a presentation module;

and the display module is used for displaying the test result.

11. The apparatus of claim 9 or 10, wherein the link test apparatus further comprises a transmission module:

and the sending module is used for sending the test result to the test equipment through the sender of the high-speed serial interface.

12. The apparatus of any one of claims 9-11, wherein the test result is a number of differential bits present in the first test code stream or a bit error rate of the first test code stream.

13. The apparatus of any one of claims 9-12,

the receiving module is further configured to obtain an identifier of the reference test code stream from the test device;

the analysis module is further configured to determine a reference test code stream corresponding to the identifier from a reference test code stream set according to the identifier of the reference test code stream, where the reference test code stream includes multiple different reference test code streams, and each reference test code stream corresponds to one identifier.

14. The apparatus of any one of claims 9-13, wherein the receiving module, prior to receiving the first test code stream sent by the error tester via the receiver, is further configured to:

receiving a second test code stream sent by the test equipment through the receiver, wherein the second test code stream comprises a target number of difference bits;

the analysis module is further configured to determine the number of difference bits in the second test code stream, where the number of difference bits in the second test code stream is equal to the target number.

15. The apparatus according to any one of claims 9 to 14, wherein the receiving module, when receiving, by the receiver, the first test code stream sent by the test device, is specifically configured to:

and receiving a first test code stream sent by the test equipment at different transmission rates through the receiver.

16. The apparatus of any one of claims 9-15, wherein the receiving module is further configured to:

and acquiring a notification message sent by the test equipment, wherein the notification message is used for indicating the transmission rate of the first test code stream.

17. An exercise device comprising a memory and a processor; the memory stores program instructions that are executed by the processor to perform the method of any of claims 1-8.

18. A computer-readable storage medium having stored thereon instructions which, when executed on a computer, cause the computer to perform the method of any one of claims 1 to 8.

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