CN115794477B

CN115794477B - Time constraint method and device for program, chip, electronic equipment and storage medium

Info

Publication number: CN115794477B
Application number: CN202310054470.5A
Authority: CN
Inventors: 刘亮; 刘先华; 张茜歌; 赵秀嘉; 李雷; 程旭; 孙玉峰; 周永忠
Original assignee: Peking University; Beijing Smartchip Microelectronics Technology Co Ltd
Current assignee: Peking University; Beijing Smartchip Microelectronics Technology Co Ltd
Priority date: 2023-02-03
Filing date: 2023-02-03
Publication date: 2023-05-23
Anticipated expiration: 2043-02-03
Also published as: CN115794477A

Abstract

The invention discloses a time constraint method, a time constraint device, a time constraint chip, an electronic device and a storage medium of a program. The program comprises a target code block, a first time constraint instruction arranged at the starting position of the target code block and a time detection instruction arranged at the ending position of the target code block, and the method comprises the following steps: executing the first time constraint instruction to obtain the maximum allowable execution duration of the target code block; executing the target code block; and executing a time detection instruction to perform timeout exception reminding when the execution timeout of the target code block is determined based on the maximum allowed execution duration. Therefore, the overtime reminding of the target code block can be timely carried out, the scheduling of resources is more reasonably and efficiently realized, so that the tasks with different key levels can meet the time constraint, and the accuracy of time sequence control is improved.

Description

Time constraint method and device for program, chip, electronic equipment and storage medium

Technical Field

The present invention relates to the field of computer application technologies, and in particular, to a time constraint method and apparatus for a program, a chip, an electronic device, and a storage medium.

Background

With the development of real-time systems, hybrid critical systems that integrate multiple applications in the same system are becoming a research hotspot in the real-time domain. The key levels of the various applications in the hybrid key system are different and the requirements for real-time are also different. One of the important contents of designing a hybrid critical system is to implement resource isolation to reduce interference between tasks, and to ensure that tasks of different critical levels can meet time constraints through efficient task scheduling.

Tasks with different key levels run on the same hardware platform, resources such as processor time, memory, network and the like are shared, for a hybrid key system, the highly integrated hardware platform needs to ensure the efficiency and flexibility of the tasks with different key levels on resource sharing, meets the respective key levels of the tasks, and needs to reduce interference among the tasks caused by resource sharing, so that isolation among the tasks is very important. The common isolation mode is a hardware isolation mode, a software isolation mode and a software-hardware combination isolation mode, but the isolation mode still has the problems of insufficient resource utilization rate, poor time sequence control and the like.

It should be noted that the information disclosed in this background section is only for understanding the background of the present application concept and, therefore, it may contain information that does not constitute prior art.

Disclosure of Invention

The present invention aims to solve at least one of the technical problems in the related art to some extent. Therefore, the invention aims to provide a time constraint method, a device, a chip, electronic equipment and a storage medium of a program, which can timely remind overtime of an object code block, and more reasonably and efficiently realize resource scheduling so as to ensure that tasks with different key levels can meet the time constraint and improve the accuracy of time sequence control.

To achieve the above object, an embodiment of a first aspect of the present invention provides a time constraint method of a program, the program including an object code block, a first time constraint instruction set at a start position of the object code block, and a time detection instruction set at an end position of the object code block, the method including: executing the first time constraint instruction to obtain the maximum allowable execution duration of the target code block; executing the target code block; and executing a time detection instruction to perform timeout exception reminding when the execution timeout of the target code block is determined based on the maximum allowed execution duration.

In some embodiments of the present invention, the time constraint method of the program further includes: acquiring a first execution duration of a target code block; and executing the time detection instruction to judge whether the first execution time length is longer than the maximum allowed execution time length, and determining that the target code block is executed overtime when the first execution time length is longer than the maximum allowed execution time length.

In some embodiments of the present invention, the time constraint method of the program further includes: executing a first time constraint instruction, and obtaining the maximum allowed execution time obtained by the sum of the first current time and the maximum allowed execution time when the first time constraint instruction is executed; and executing the time detection instruction, acquiring a second current time when the time detection instruction is executed, judging whether the second current time is larger than the maximum allowable execution time, and determining that the execution of the target code block is overtime when the second current time is larger than the maximum allowable execution time.

In some embodiments of the present invention, the time constraint method of the program further includes: and executing the overtime instruction codes in the target code block after overtime exception reminding.

In some embodiments of the present invention, the time constraint method of the program further includes: acquiring a second execution duration of the target code block when compiling the program; and comparing the second execution duration with the maximum allowable execution duration, and outputting a comparison result.

In some embodiments of the present invention, the program includes at least one basic block, and the obtaining the second execution duration of the target code block includes: determining that the first time constraint instruction and the time detection instruction are in the same basic block, and obtaining the sum of instruction execution time lengths between the first time constraint instruction and the time detection instruction to obtain a second execution time length.

In some embodiments of the present invention, the program includes at least one basic block, and the obtaining the second execution duration of the target code block includes: determining that a first time constraint instruction and a time detection instruction are in different basic blocks, and acquiring a first basic block in which the first time constraint instruction is located and a second basic block in which the time detection instruction is located; acquiring all paths between a first basic block and a second basic block; and obtaining the maximum value of the sum of the instruction execution time lengths between the first time constraint instruction and the time detection instruction in all paths, and obtaining the second execution time length.

In some embodiments of the present invention, obtaining a maximum value of a sum of instruction execution durations between a first time constraint instruction and a time detection instruction in all paths, to obtain a second execution duration includes: obtaining the sum of the execution time lengths of the basic blocks corresponding to each path in all paths, obtaining the path execution time length of each path, and obtaining a target path with the maximum path execution time length in all paths; acquiring the sum of all instruction execution durations of the first basic block before the first time constraint instruction and the second basic block after the time detection instruction; and obtaining a difference value of the sum of the path execution time length corresponding to the target path and all the instruction execution time lengths to obtain a second execution time length.

In some embodiments of the present invention, obtaining a sum of instruction execution durations between a first time constraint instruction and a time detection instruction includes: acquiring an instruction template corresponding to each instruction in all instructions between the first time constraint instruction and the time detection instruction, and acquiring the execution duration corresponding to each instruction from the instruction template; and summing the execution time length corresponding to each instruction in all the instructions to obtain the sum of the instruction execution time lengths between the first time constraint instruction and the time detection instruction.

In some embodiments of the present invention, a second execution duration of the target code block corresponding to each of the at least one scheduling frequency is obtained; and determining that the maximum allowable execution duration is smaller than the second execution duration of the target code block corresponding to each scheduling frequency, and outputting a comparison result of time length setting errors.

In some embodiments of the invention, the first time constraint instruction is an instruction that sets a maximum allowed execution time length by a register, or the first time constraint instruction is an instruction that sets a maximum allowed execution time length by an immediate in the instruction encoding.

In some embodiments of the invention, the program further comprises a second time constraint instruction and a delay instruction disposed between the target code block and the time detection instruction, the method further comprising: executing the second time constraint instruction to obtain the minimum allowable execution duration of the target code block; the delay instruction is executed such that the first execution time length of the target code block is greater than the minimum allowed execution time length.

To achieve the above object, an embodiment of a second aspect of the present invention proposes a computer-readable storage medium having stored thereon a program which, when executed by a processor, implements the time constraint method of the program of any of the above embodiments.

To achieve the above object, an embodiment of a third aspect of the present invention provides a chip, including: the time constraint method of the program of any of the above embodiments is implemented when the processor executes the program.

To achieve the above object, an embodiment of a fourth aspect of the present invention provides an electronic device including the aforementioned chip.

To achieve the above object, a fifth aspect of the present invention provides a time constraint apparatus of a program including an object code block, a first time constraint instruction provided at a start position of the object code block, and a time detection instruction provided at an end position of the object code block, the apparatus including: the first instruction module is used for executing the first time constraint instruction to obtain the maximum allowable execution duration of the target code block; a second instruction module for executing the target code block; and the third instruction module is used for executing a time detection instruction to carry out overtime abnormal reminding when the execution overtime of the target code block is determined based on the maximum allowable execution duration.

In some embodiments of the invention, the apparatus further comprises: the acquisition module is used for acquiring a first execution duration of the target code block; and the third instruction module is further used for executing a time detection instruction to judge whether the first execution time length is longer than the maximum allowed execution time length, and determining that the execution of the target code block is overtime when the first execution time length is longer than the maximum allowed execution time length.

In some embodiments of the present invention, the first instruction module is further configured to execute a first time constraint instruction, and obtain a maximum allowed execution time by obtaining a sum of a first current time and a maximum allowed execution time when the first time constraint instruction is executed; the third instruction module is further configured to execute the time detection instruction, obtain a second current time when the time detection instruction is executed, determine whether the second current time is greater than a maximum allowable execution time, and determine that the execution of the target code block is overtime when the second current time is greater than the maximum allowable execution time.

In some embodiments of the present invention, the second instruction module is further configured to execute instruction code in the object code block that has timed out after the timeout exception alert is made.

In some embodiments of the invention, the apparatus further comprises: the compiling module is used for acquiring a second execution duration of the target code block when compiling the program; and the comparison module is used for comparing the second execution duration with the maximum allowable execution duration and outputting a comparison result.

In some embodiments of the present invention, the program includes at least one basic block, and the compiling module is specifically configured to: determining that the first time constraint instruction and the time detection instruction are in the same basic block, and obtaining the sum of instruction execution time lengths between the first time constraint instruction and the time detection instruction to obtain a second execution time length.

In some embodiments of the present invention, the program includes at least one basic block, and the compiling module is specifically configured to: determining that a first time constraint instruction and a time detection instruction are in different basic blocks, and acquiring a first basic block in which the first time constraint instruction is located and a second basic block in which the time detection instruction is located; acquiring all paths between a first basic block and a second basic block; and obtaining the maximum value of the sum of the instruction execution time lengths between the first time constraint instruction and the time detection instruction in all paths, and obtaining the second execution time length.

In some embodiments of the present invention, the compiling module is further configured to obtain a second execution duration of the target code block corresponding to each of the at least one scheduling frequency; and the comparison module is also used for determining that the maximum allowable execution duration is smaller than the second execution duration of the target code block corresponding to each scheduling frequency and outputting a comparison result of time length setting errors.

In some embodiments of the invention, the program further comprises a second time constraint instruction and a delay instruction disposed between the target code block and the time detection instruction, the apparatus further comprising: the fourth instruction module is used for executing the second time constraint instruction to obtain the minimum allowable execution duration of the target code block; and the fifth instruction module is used for executing the delay instruction so that the first execution time length of the target code block is longer than the minimum allowed execution time length.

According to the time constraint method, the device, the chip, the electronic equipment and the storage medium of the program, the first time constraint instruction is set at the starting position of the target code block, the time detection instruction is set at the ending position of the target code block, the first time constraint instruction is executed first to obtain the maximum allowable execution duration of the target code block when the program is executed, then the target code block is executed, and finally the time detection instruction is executed to carry out overtime abnormal reminding when the execution timeout of the target code block is determined based on the maximum allowable execution duration, so that resource scheduling can be more effectively realized, tasks with different key levels can meet the time constraint, and the accuracy of time sequence control is improved.

Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.

Drawings

The foregoing and/or additional aspects and advantages of the present application will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings, wherein:

FIG. 1 is a flow diagram of a time constraint method of a program according to one embodiment of the invention.

FIG. 2 is a flow diagram of obtaining a second execution duration during compilation, according to one embodiment of the present invention.

Fig. 3 is a compiled result of a partial program of a time constraint method of a program according to an embodiment of the present invention, in which no timing violation is found.

Fig. 4 is a compiled result of a partial program discovery timing violation of a time constraint method of a program according to an embodiment of the present invention.

Fig. 5 is a schematic diagram of a hardware functional verification test result of a time constraint method of a program according to an embodiment of the present invention.

Fig. 6 is a block diagram of a chip according to one embodiment of the invention.

Fig. 7 is a block diagram of an electronic device according to one embodiment of the invention.

Fig. 8 is a block diagram of a time constraint apparatus of a program according to an embodiment of the present invention.

Detailed Description

Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are illustrative and intended to explain the present invention and should not be construed as limiting the invention.

For hybrid critical systems, the generic instruction system does not provide instructions that constrain the timing behavior of the program, mainly because the constraints on the timing behavior depend on the design of the processor microstructure and the implementation of the software tool chain, and hardware models that accurately describe the timing behavior are often unavailable or difficult to implement. Nevertheless, the program may still specify timing behavior, for example, many processors have externally programmable timers by which interrupts are raised to count, allowing software to learn the current time to control the timing of the program. However, this method is affected by various factors such as implementation and configuration of the hardware timer, and the manner of handling the interrupt.

There are many programming languages and programming models that include timing control features, such as Ada (a computer programming language), real-time electronic (a computer programming language), PTIDES (an embedded model), etc. Implementing timing control in an instruction system also requires hardware implementation and support of a compilation tool chain. Timing instructions in an instruction system are lower than programming languages, can provide guidance for hardware design, and implement more accurate real-time semantics, such as timing instruction read, for specifying the shortest execution time of a piece of code. In order to realize the instruction, a plurality of registers special for timing are added in a processor, the read instruction takes the registers as destination operands, receives a source operand as a count value, and when the read instruction runs, firstly waits for the register to return to zero, then rewrites the source operand as the count value into the registers, and the effect of the read instruction is equivalent to that of running a specified number of idle operation instructions. In a program requiring accurate specification of code timing, compared with manually inserting a plurality of idle operations, the use of the instruction can effectively reduce the code size and simultaneously provide correct and accurate timing semantics, but a processor cannot utilize idle clock cycles, so that the resource utilization rate is not high.

Antolak et al add four timing instructions to its proposed multicore timing predictable processor, respectively: SD (Set Deadline), AD (Activate Deadline) and DD (Deactivate Deadline) and WFD (Wait For Deadline) instructions. The processor is provided with a plurality of deadline counters for each hardware thread, when the counters are activated, the value of each clock cycle counter is reduced by one, and when the counters are reduced to zero, the current thread is suspended, and interrupt processing timeout condition is caused. The user may write deadlines to the specified counter via SD instructions, after which the AD instructions and DD instructions activate and deactivate the specified counter, respectively, and when the counter provided on a thread is decremented to zero, the WFD instructions suspend the thread until the value of the corresponding counter becomes 1. To prevent a timeout condition from occurring, the WFD instruction is immediately followed by the SD instruction to set a new deadline. However, special AD instructions and DD instructions are required to process deadline counters in these four timing instructions, and several deadline counters are required to be provided for each hardware thread, and when the counters are activated, the value of each clock cycle counter is decremented by one, which causes an additional hardware burden.

Based on the above, the embodiment of the invention provides a time constraint method, a device, a chip, electronic equipment and a storage medium of a program, which can timely remind overtime of a target code block, and more reasonably and efficiently realize scheduling of resources so as to ensure that tasks with different key levels can meet the time constraint and improve the accuracy of time sequence control.

The following describes in detail a time constraint method, a device, a chip, an electronic device, and a storage medium of a program according to an embodiment of the present invention with reference to the accompanying drawings.

The program comprises a target code block, a first time constraint instruction arranged at the starting position of the target code block and a time detection instruction arranged at the ending position of the target code block.

Specifically, the first time constraint instruction is used for marking the start of the target code block and giving the maximum allowed execution duration of the target code block, namely, the time limit that the execution duration of the target code block does not exceed at most, and the first time constraint instruction is specifically obtained by performing static analysis on the program in the compiling stage. The time detection instruction is used for marking the end of the target code block, and generating an exception when the execution duration of the target code block exceeds the maximum allowable execution duration of the target code block agreed by the first time constraint instruction.

For example, an expand instruction mtfd (Meet The Final Deadline) instruction may be added, meaning that the last time limit is met. The mtfd instruction is split into a first time constraint instruction mt instruction/mti instruction and a time detection instruction fd instruction. The mt instruction/mti instruction is arranged at the starting position of the target code block of the program to mark the start of the target code block and give out the maximum allowable execution duration of the target code block, and the fd instruction is arranged at the ending position of the target code block to mark the end of the target code block and cause an exception when the execution duration of the target code block exceeds the maximum allowable execution duration.

In some embodiments, the first time constraint instruction is an instruction that sets a maximum allowed execution time length through a register, or the first time constraint instruction is an instruction that sets a maximum allowed execution time length through an immediate in the instruction encoding.

Illustratively, the mt instruction may be set to set the maximum allowable execution time length of the target code block through a register. For example, the mt instruction multiplexes instruction encoding of RISC-V instruction system custom3, accepts only one source operand of rs1, and takes the value of the source operand as the maximum allowed execution time of the target code block.

Mti instructions may be set to give the maximum allowed execution time of the target code block by an immediate within the instruction code. For example, the mti instruction multiplexes the instruction encoding of lui (Load Upper Immediate) and the destination register is set to zero, the 24-bit immediate in the encoding being the maximum allowed execution time of the target code block.

In some embodiments, the time-detecting instruction is an instruction without source and destination operands. For example, the fd instruction has no source and destination operands, but an exception may be raised when the execution duration of the target code block exceeds the maximum allowed execution duration of the target code block set by the mt instruction/mti instruction.

As shown in fig. 1, the time constraint method of the program may include:

s11: and executing the first time constraint instruction to obtain the maximum allowable execution duration of the target code block.

S13: the target code block is executed.

S15: and executing a time detection instruction to perform timeout exception reminding when the execution timeout of the target code block is determined based on the maximum allowed execution duration.

In some embodiments, the instruction code in the target code block that has timed out is executed after the timeout exception alert is made.

In order to ensure that the execution duration of the target code block does not exceed the maximum allowable execution duration, in some embodiments, static analysis and inspection will be performed during the compiling stage of the program, but some information of the program is difficult or even impossible to learn during the compiling stage, for example, for instructions requiring external input of a loop number, etc., so the first time constraint instruction and the time detection instruction described above are introduced into the program, and strict time constraint is given to the program during running, that is, judgment and remedy of timeout are given on the hardware level through the first time constraint instruction and the time detection instruction.

Specifically, when the program runs, a first time constraint instruction, such as an mt instruction/mti instruction, is executed according to an instruction sequence, a maximum allowed execution duration of the target code block can be obtained by executing the first time constraint instruction, then the target code block is executed, after the execution of the target code block is completed, a time detection instruction, such as an fd instruction, is executed, whether the execution duration of the target code block exceeds the maximum allowed execution duration is judged by the execution time detection instruction, and when the execution duration of the target code block exceeds the maximum allowed execution duration, the execution timeout of the target code block is judged, at this time, a timeout abnormality prompt is performed, and the instruction code with the timeout occurring in the target code block can be processed in a turning manner. Thus, judgment and remedy of timeout are given on the hardware level so that program operation satisfies time constraint.

Illustratively, to solve the resource scheduling problem in the hybrid critical system, there is a fixed priority scheduling method based on preemption, and a great deal of research work is focused on the scheduling problem of the hybrid critical system. However, in most of these studies, the execution time of each task is regarded as a certain value, and in actual cases, the execution time of a program is affected by various factors, and the worst-case execution time thereof is difficult to determine. Therefore, as described in the above embodiment, the maximum allowable execution duration of the target code block is obtained through the first time constraint instruction, such as the mt instruction/mti instruction, and then after the execution of the target code block is completed, through the execution time detection instruction, such as the fd instruction, whether the target code block is overtime is judged according to the maximum allowable execution duration, if the target code is overtime, the overtime exception reminding is performed, and the overtime instruction code in the target code block is executed, and if the target code is not overtime, the subsequent code is continuously executed.

In the above embodiment, the first time constraint instruction is set at the start position of the target code block, the time detection instruction is set at the end position of the target code block, and when the program is executed, the first time constraint instruction is executed first to obtain the maximum allowable execution duration of the target code block, then the target code block is executed, and finally the time detection instruction is executed, so that when the execution timeout of the target code block is determined based on the maximum allowable execution duration, the timeout exception reminding is performed, thereby more efficiently realizing the scheduling of resources, ensuring that the tasks of different key levels can meet the time constraint, and improving the accuracy of the time sequence control.

In some embodiments, the time constraint method of the program further comprises: acquiring a first execution duration of a target code block; and executing the time detection instruction to judge whether the first execution time length is longer than the maximum allowed execution time length, and determining that the target code block is executed overtime when the first execution time length is longer than the maximum allowed execution time length.

For example, a first current time acquisition instruction may be set within the first time constraint instruction to acquire a first current time, and a second current time acquisition instruction may be set within the time detection instruction to acquire a second current time. When the program runs, according to the instruction sequence, a first time constraint instruction, such as an mt instruction/mti instruction, is executed, and the maximum allowed execution duration and the first current time of the target code block can be obtained through executing the first time constraint instruction; and then executing the target code block, executing a time detection instruction after the execution of the target code block is completed, obtaining a second current time, obtaining a difference value between the second current time and the first current time to obtain an execution time length of the target code block, marking the execution time length as a first execution time length, judging whether the first execution time length exceeds a maximum allowed execution time length, judging that the execution of the target code block is overtime when the first execution time length exceeds the maximum allowed execution time length, carrying out overtime abnormal reminding at the moment, and turning to processing instruction codes with overtime in the target code block. Thus, judgment and remedy of timeout are given on the hardware level so that program operation satisfies time constraint.

Two 32-bit registers are newly added to each hardware thread for storing the maximum allowed execution duration of the target code block specified by the first time constraint instruction and the first current time, the first time constraint instruction writes the maximum allowed execution duration of the target code block and the first current time into the corresponding registers, and when the time detection instruction executes, the difference between the second current time and the first current time written into the registers is obtained to obtain the first execution duration, and the relation between the first execution duration and the maximum allowed execution duration written into the registers is compared to determine whether to carry out overtime reminding. For ease of unified processing, the time comparisons herein employ unsigned subtraction and signed comparison operations.

In other embodiments, the time constraint method of the program further comprises: executing a first time constraint instruction, and obtaining the maximum allowed execution time obtained by the sum of the first current time and the maximum allowed execution time when the first time constraint instruction is executed; and executing the time detection instruction, acquiring a second current time when the time detection instruction is executed, judging whether the second current time is larger than the maximum allowable execution time, and determining that the execution of the target code block is overtime when the second current time is larger than the maximum allowable execution time.

For example, a first current time acquisition instruction may be set within the first time constraint instruction to acquire a first current time, and a second current time acquisition instruction may be set within the time detection instruction to acquire a second current time. When the program runs, a first time constraint instruction, such as an mt instruction/mti instruction, is executed firstly according to the instruction sequence, the maximum allowed execution duration and the first current time of the target code block can be obtained through executing the first time constraint instruction, and the maximum allowed execution time is obtained by calculating the sum of the first current time and the maximum allowed execution duration; and then, executing the target code block, executing a time detection instruction after the execution of the target code block is completed, obtaining a second current time, judging whether the second current time is larger than the maximum allowable execution time, judging that the execution of the target code block is overtime when the second current time is larger than the maximum allowable execution time, carrying out overtime abnormal reminding at the moment, and turning to processing the overtime instruction codes in the target code block. Thus, judgment and remedy of timeout are given on the hardware level so that program operation satisfies time constraint.

A32-bit register is newly added to each hardware thread for a first time constraint instruction and a time detection instruction, the register is used for storing the sum of the maximum allowed execution duration of a target code block designated by the first time constraint instruction and a first current time, the first time constraint instruction writes the sum of the times into the register, and the time detection instruction compares the magnitude relation between the sum of the times written into the register and a second current time when executing, so that whether overtime reminding is carried out or not is determined. For ease of unified processing, the time comparisons herein employ unsigned subtraction and signed comparison operations.

As a specific example, the procedure based on the first time constraint instruction and the time detection instruction is as follows:

1 mti(10000);

2 // ... computation ...

3 fd();

when the mti instruction of the 1 st line is executed, writing the sum of the maximum allowed execution duration 10us of the target code block and the time of the first current time into a 32-bit register, then executing the target code block computer of the 2 nd line, and finally executing the fd instruction of the 3 rd line, so as to carry out abnormal reminding when the second current time is larger than the sum of the maximum allowed execution duration 10us and the time of the first current time. Therefore, through the mti instruction of the 1 st row and the fd instruction of the 3 rd row, the execution duration of the target code block of the 2 nd row can be ensured not to exceed 10us.

In some embodiments, the time constraint method of the program further comprises: acquiring a second execution duration of the target code block when compiling the program; and comparing the second execution duration with the maximum allowable execution duration, and outputting a comparison result.

Specifically, in order to ensure that the execution duration of the target code block does not exceed the maximum allowable execution duration, static analysis and inspection are performed on the execution duration of the target code block in the compiling stage. For example, the above program may be compiled by the compiler GCC (GNU Compiler Collection), and at the time of compiling, the execution time of each instruction in the target code block may be obtained by a static analysis method, and the execution time may be summed to obtain the execution time of the target code block, which is recorded as a second execution time, and then the second execution time and the maximum allowable execution time are compared, and a comparison result is output, for example, when the second execution time is longer than the maximum allowable execution time, a comparison result of an error setting of the time is output, and at the same time, the second execution time and the maximum allowable execution time may also be output. In this way, by statically analyzing and checking the execution duration of the target code block, the possible timeout of the target code block can be exposed to the user as soon as possible in the compilation phase.

In some embodiments, the program includes at least one basic block, and the obtaining the second execution duration of the target code block includes: determining that the first time constraint instruction and the time detection instruction are in the same basic block, and obtaining the sum of instruction execution time lengths between the first time constraint instruction and the time detection instruction to obtain a second execution time length.

Illustratively, obtaining a sum of instruction execution durations between the first time constraint instruction and the time detection instruction includes: acquiring an instruction template corresponding to each instruction in all instructions between the first time constraint instruction and the time detection instruction, and acquiring the execution duration corresponding to each instruction from the instruction template; and summing the execution time length corresponding to each instruction in all the instructions to obtain the sum of the instruction execution time lengths between the first time constraint instruction and the time detection instruction.

Specifically, the basic block refers to a sentence sequence executed by a program sequentially, the basic block has only one entry and one exit, the entry is the first sentence therein, and the exit is the last sentence therein. A program may be comprised of one or more basic blocks and an object code block may be comprised of instructions for a portion of the basic blocks.

When the second execution duration of the target code block is acquired, whether the first time constraint instruction and the time detection instruction are in the same basic block of the program can be judged first, if yes, a unique path exists between the first time constraint instruction and the time detection instruction, and at the moment, the sum of the instruction execution durations between the first time constraint instruction and the time detection instruction can be directly acquired, so that the second execution duration is acquired, and the accuracy of a comparison result is ensured. For example, an instruction template corresponding to each instruction in all instructions between the first time constraint instruction and the time detection instruction is obtained, an execution duration corresponding to each instruction is obtained from the instruction template, and then the execution durations corresponding to each instruction in all instructions are summed to obtain a sum of instruction execution durations between the first time constraint instruction and the time detection instruction.

In other embodiments, please refer to fig. 2, wherein the obtaining the second execution duration of the target code block includes:

s21: and determining that the first time constraint instruction and the time detection instruction are in different basic blocks, and acquiring a first basic block in which the first time constraint instruction is located and a second basic block in which the time detection instruction is located.

For example, the program includes six basic blocks A-F, a first time constraint instruction is at a first basic block B, and a time detection instruction is at a second basic block F.

S23: all paths between the first basic block and the second basic block are acquired.

For example, three paths are included between the first basic block B and the second basic block F, respectively: a first path formed by the first basic block B, C, D, E and the second basic block F; a second path formed by the first basic block B, C and the second basic block F; a third path formed by the first basic block B, D and the second basic block F.

S25: and obtaining the maximum value of the sum of the instruction execution time lengths between the first time constraint instruction and the time detection instruction in all paths, and obtaining the second execution time length.

For example, the sum of instruction execution time lengths between the first time constraint instruction and the time detection instruction in the first path is obtained, the sum of instruction execution time lengths between the first time constraint instruction and the time detection instruction in the second path is obtained, and the sum of instruction execution time lengths between the first time constraint instruction and the time detection instruction in the third path is obtained, and then the sum of the three instruction execution time lengths is compared to obtain the maximum value of the sum of the three instruction execution time lengths, wherein the maximum value is the second execution time length of the target code block.

Therefore, when the first time constraint instruction and the time detection instruction are in different basic blocks, the maximum value of the sum of instruction execution time durations among the instructions is selected as the second execution time duration, so that the situation that the execution time duration of the target code block is prolonged under the condition that the execution time duration is complex and complicated in the actual application process can be fully considered, and the tasks of different key levels can meet the time constraint as far as possible is ensured.

In some embodiments, obtaining the maximum value of the sum of the instruction execution durations between the first time constraint instruction and the time detection instruction in all paths, to obtain the second execution duration includes: obtaining the sum of the execution time lengths of the basic blocks corresponding to each path in all paths, obtaining the path execution time length of each path, and obtaining a target path with the maximum path execution time length in all paths; acquiring the sum of all instruction execution durations of the first basic block before the first time constraint instruction and the second basic block after the time detection instruction; and obtaining a difference value of the sum of the path execution time length corresponding to the target path and all the instruction execution time lengths to obtain a second execution time length.

For example, the program includes six basic blocks A-F, a first time constraint instruction is at a first basic block B, and a time detection instruction is at a second basic block F. Three paths are included between the first basic block B and the second basic block F, respectively: a first path formed by the first basic block B, C, D, E and the second basic block F; a second path formed by the first basic block B, C and the second basic block F; a third path formed by the first basic block B, D and the second basic block F. Then, the sum of the execution durations of the basic blocks B, C, D, E, F corresponding to the first path is obtained, the path execution duration of the first path is obtained, the sum of the execution durations of the basic blocks B, C, F corresponding to the second path is obtained, the path execution duration of the second path is obtained, and the sum of the execution durations of the basic blocks B, D, F corresponding to the third path is obtained, so that the path execution duration of the third path is obtained. And then comparing the path execution time lengths of the three paths to obtain the maximum value of the path execution time lengths of the three paths, wherein the path corresponding to the maximum value is the target path. And finally, obtaining the sum of all instruction execution time lengths before the first time constraint instruction in the first basic block B and after the time detection instruction in the second basic block F, and obtaining a difference value of the sum of the path execution time length corresponding to the target path and all instruction execution time lengths to obtain a second execution time length.

Illustratively, the support for the first time constraint instruction and the time detection instruction is completed by adding an optimization pass (pass handler) on the compiler, and the specific support flow is as follows:

1) And recording the matching relation between each instruction and the instruction template in the pass_final. The pass_final is an optimization pass for generating assembly language in the GCC, the pass_final selects an instruction template corresponding to each rtl instruction of each basic block in the current function according to a machine description file of the target machine, then an operand is filled to generate the assembly instruction, and in the process, codes are inserted to save the mapping relation between rtl instructions and the instruction templates corresponding to rtl instructions through a hash table. The instruction template stores the execution time of each instruction.

2) Each basic block is scanned in pass_mtfd, and WCET (worst execution time) of each basic block is calculated while searching for a first time constraint instruction and a time detection instruction. Where pass_mtfd is a new optimization pass in the GCC, performed after pass_final. pass_mtfd traverses each rtl instruction of each basic block in the current function to determine rtl whether the instruction is an asm_input type/asm_operations type (both types representing inline assembler instructions in GCC), if so, whether it is a first time constraint instruction or a time detection instruction according to the name of rtl instruction. If the first time constraint instruction and the time detection instruction are successfully queried and the formats of the first time constraint instruction and the time detection instruction are correct, querying the hash table of the previous step to obtain an instruction template corresponding to each rtl instruction in each basic block, obtaining the execution duration corresponding to each rtl instruction based on the instruction template, and summing the execution durations corresponding to all rtl instructions of each basic block to obtain the WCET of each basic block.

It should be noted that if the first time constraint instruction and the time detection instruction are not successfully queried (for example, the two instructions are not included), or if the formats of the first time constraint instruction and the time detection instruction are wrong (for example, the time detection instruction is before the first time constraint instruction, the number of the first time constraint instruction and the time detection instruction is different, the first time constraint instruction and the time detection instruction are nested, etc.), the method directly exits.

3) For each pair of the first time constraint instruction and the time detection instruction, if the first time constraint instruction and the time detection instruction are in the same basic block, only one path exists, and the sum of all instruction execution time lengths from the first time constraint instruction to the time detection instruction is directly calculated; otherwise, performing depth-first search on the control flow graph (ControlFlowGraph, CFG), finding all paths between a first basic block where a first time constraint instruction is located and a second basic block where a time detection instruction is located, accumulating WCET of the basic blocks in the paths to obtain WCET of the whole path, and then recording the maximum value of the WCET of the path. After obtaining the maximum value of the WCET of the path, the sum of the execution durations of all the instructions before the first time constraint instruction and after the time detection instruction in the basic block is also removed, so as to obtain the WCET (i.e., the second execution duration) between the first time constraint instruction and the time detection instruction.

It should be noted that, in the recursive process, if a loop is found in the path between the first basic block where the first time constraint instruction is located and the second basic block where the time detection instruction is located (i.e., there is a loop between the first time constraint instruction and the time detection instruction), the longest path is difficult to obtain at this time, and the flow directly exits.

4) And comparing the WCET between the calculated first time constraint instruction and the time detection instruction with the maximum allowable execution duration given by the first time constraint instruction. If the maximum allowed execution duration given by the first time constraint instruction is less than the WCET between the first time constraint instruction and the time detection instruction, an error prompt is given.

In some embodiments, a second execution duration of the target code block corresponding to each of the at least one scheduling frequency is obtained; and determining that the maximum allowable execution duration is smaller than the second execution duration of the target code block corresponding to each scheduling frequency, and outputting a comparison result of time length setting errors.

Specifically, if the scheduling frequencies are different, the execution time of each instruction under the corresponding scheduling frequency is also different, and the second execution time of the target code block is also different, so that in order to avoid inaccurate comparison results caused by different scheduling frequencies, the second execution time of each target code block corresponding to at least one scheduling frequency (for example, the scheduling frequencies are 1, 1/2, 1/3, 1/4, etc.) can be obtained, and when the maximum allowable execution time of the target code block is smaller than the second execution time of each target code block corresponding to each scheduling frequency, an erroneous comparison result is set for the output time, and meanwhile, the second execution time of each target code block corresponding to each scheduling frequency can be output; in other cases, the second execution duration of the target code block corresponding to each scheduling frequency is directly output for reference by the user.

In some embodiments, the program further comprises a second time constraint instruction and a delay instruction disposed between the target code block and the time detection instruction, the method further comprising: executing the second time constraint instruction to obtain the minimum allowable execution duration of the target code block; the delay instruction is executed such that the first execution time length of the target code block is greater than the minimum allowed execution time length.

Specifically, the second time constraint instruction is configured to give a minimum allowable execution duration of the target code block, i.e. a time limit for which the execution duration of the target code block is at least not lower. The delay instruction is used for delaying.

When the program is running, a first time constraint instruction, such as an mt instruction/mti instruction, is executed according to an instruction sequence, a maximum allowed execution duration of the target code block can be obtained by executing the first time constraint instruction, then the target code block is executed, after the execution of the target code block is completed, a second time constraint instruction is executed, a minimum allowed execution duration of the target code block is obtained, then a delay instruction is executed, so that the first execution duration of the target code block is greater than the minimum allowed execution duration, then a time detection instruction, such as an fd instruction, is executed, whether the execution duration of the target code block exceeds the maximum allowed execution duration is judged by the execution time detection instruction, and when the execution duration of the target code block exceeds the maximum allowed execution duration, an overtime abnormal prompt is performed at this time, and the instruction code which overtime occurs in the target code block can be processed in a turning mode.

As a specific example, a program based on the first time constraint instruction, the time detection instruction, the second time constraint instruction, and the delay instruction is as follows:

1 current_time = get_time();

2 mti(10000);

3 // ... computation ...

4 set_compare(current_time + 5000);

5 delay_until();

6 fd();

the execution time length of the target code block in the 3 rd line can be ensured to be longer than the minimum allowable execution time length by executing the third current time acquisition instruction in the 1 st line, the second time constraint instruction in the 4 th line and the delay instruction in the 5 th line, and if the execution time length of the target code block in the 3 rd line is shorter than 5us, the target code block in the 3 rd line is delayed by the delay instruction in the 5 th line. By executing the first time constraint instruction of the 2 nd line and the time detection instruction of the 6 th line, the execution duration of the target code block of the 3 rd line can be ensured not to exceed the maximum allowable execution duration of 10us.

Therefore, based on the first time constraint instruction, the time detection instruction, the second time constraint instruction and the time delay instruction, the minimum allowed execution duration and the maximum allowed execution duration of the target code block can be ensured at the same time, and finer time sequence control is provided for a user.

In the above embodiment, through the first time constraint instruction and the time detection instruction, clear boundary division is provided for the target code block in the compiling stage of the program, the compiler may obtain the possible execution duration of the target code block in advance, that is, the second execution duration, by means of static analysis, and then determine whether the second execution duration meets the maximum allowable execution duration of the target code block, so as to expose the situation that the target code block may timeout to the user in the compiling stage as far as possible. However, there is a limit to static analysis, for example, in the case that there is a loop in the first time constraint instruction and the time detection instruction, loop boundary analysis is required at this time, and when the sequential boundary analysis depends on an external input, the execution number of the loop itself is unknown; for different scheduling frequencies, the execution time length of the target code block is different, the lower the scheduling frequency is, the longer the execution time length is, and in the compiling stage, the compiler can hardly obtain the relevant information of the scheduling frequency, and the compiler can only make looser limit. Based on the limitation of static analysis, the overtime condition can be judged and remedied on hardware through a first time constraint instruction and a time detection instruction, namely, when the first execution duration of the target code block exceeds the maximum allowable execution duration, an abnormal prompt is triggered for the user to process.

In order to verify the effect of the time constraint method of the program of the embodiment of the present invention, a verification example shown below and a corresponding verification result thereof are given.

For example, correlation evaluation is performed on a time constraint method of a program on a prototype system. The method is realized based on the extended instruction of the RISC-V processor, the specific hardware configuration adopts 8 hardware threads, 64KB instruction SPM and 64KB data SPM, the running main frequency is 100MHz, and the function verification and the performance evaluation are carried out under the configuration. The software evaluation environment is a c++ simulator generated based on Chisel (a hardware description language), can simulate the hardware behavior with accurate period, and meanwhile, performs functional verification on the design in the FPGA environment, and the EDA tool selects a Vivado suite and the FPGA uses an Artix7 development board. The software implementation adopts the matched official test sample of the CMSIS-RTOS2 to perform functional test.

First, the program is modified appropriately, and mt instructions and fd instructions are added. Then, the compiler is used for compiling, and the compiler can give prompt information to inform a user whether the target code blocks from mt instructions to fd instructions exceed the maximum allowed execution duration under different scheduling frequencies. Fig. 3 shows the situation that the compiler does not find a timing violation, and fig. 4 shows the situation that the compiler finds that a timing violation exists in the program and alarms in line 2. It should be noted that, for the case that there is a function call to the target code block between the mt instruction and the fd instruction, the compiler cannot directly calculate the execution duration of the function, but also gives a warning message to prompt the user to pay attention, so that the calculated second execution duration does not include the execution duration of the function, and the user needs to ensure that the execution duration of the function does not exceed the set duration.

Since the compiler cannot statically estimate the execution time length of all cases at compile time, on a hardware implementation, at program run time, it checks based on mt instruction and fd instruction. When the fd instruction is executed, the hardware compares the second current time with the sum of the maximum allowed execution duration specified by the mt instruction and the first current time, and throws an exception if the timeout occurs. For example, the test codes shown below are given:

1 static int osTestMtfdImm(void *arg){

2 uint32_t time = get_time();

3 mt(1000);

4 for (int i = 0; i<100; i++) {}

5 set_compare(time + 500);

6 delay_until();

7 fd();

8 return 1;

9 }

the semantics of the test code implementation are that the for loop of line 4 takes at least 500ns, however, under the constraint of the mt instruction of line 3, the program needs to be guaranteed to be executed within 1000ns, and in fact, the operation time of 100 times of for loops is far more than 1000ns, the code can timeout at runtime, however, due to the existence of the fd instruction of line 7, when the fd instruction is executed, the hardware can compare the sum of the maximum allowed execution duration and the time of the first current time with the second current time, and throw an exception under the condition of timeout, referring to fig. 5, warning information is given in line 7, and the overtime instruction code occurs in the target code block is executed to prompt the user to pay attention.

The result of the WCET analysis compared with the number of cycles of actual execution of the object code is shown in table 1, and the scheduling frequency of the thread is set to 1. It can be seen that the dynamic execution results of the interfaces do not exceed the maximum allowable execution duration, so that the situation that the execution duration of the code blocks is prolonged under the condition of complexity and complexity in the actual application process can be fully considered, and a finer time sequence control function is provided for the user to run each task of the hybrid key system as much as possible.

TABLE 1

Interface name	WCET analysis results (cycle number)	Dynamic execution result (cycle number)
			osKernelInitialize	704	334
osKernelStart	270	265
			osThreadNew	777	427
osThreadGetState	456	21
			osThreadGetPriority	451	21
osThreadSuspend	909	68
			osThreadResume	909	71
osTimerNew	71	39
			osTimerStart	1035	77
osTimerStop	869	65
			osMutexNew	1342	55
osMutexRelease	54	47

In addition, the resource utilization rate and the power consumption of the extended time sequence instruction on the FPGA are evaluated. The method comprises the steps of adding a 32-bit CSR for each hardware thread for realizing an mt instruction and a fd instruction, storing the maximum allowed execution duration designated by the mt instruction, comparing logic of the sum of the second current time and the maximum allowed realization duration with the time of the first current time when the fd instruction is added, adding instruction decoding signals and related control signals of the mt instruction and the fd instruction on a control path, adding logic of causing abnormality by the fd instruction, and adding logic of setting the maximum allowed execution duration of the mt instruction on a data path. Evaluation shows that the increase in the number of LUTs, FFs and power consumption on the chip caused by the added mt and fd instructions can be controlled within a small range.

It is noted that the specific values mentioned above are only for the purpose of illustrating the implementation of the present invention in detail and are not to be construed as limiting the present invention. In other examples or embodiments or examples, other values may be selected according to the present invention, without specific limitation.

Corresponding to the above embodiments, the embodiments of the present invention also provide a computer readable storage medium having stored thereon a program which, when executed by a processor, implements the time constraint method of the program of any of the above embodiments.

According to the computer readable storage medium, the first time constraint instruction is set at the starting position of the target code block, the time detection instruction is set at the ending position of the target code block, and when the program is executed, the first time constraint instruction is executed first to obtain the maximum allowable execution duration of the target code block, then the target code block is executed, and finally the time detection instruction is executed, so that when the execution timeout of the target code block is determined based on the maximum allowable execution duration, timeout abnormal reminding is carried out, and therefore scheduling of resources can be achieved more efficiently, tasks of different key levels can meet time constraint, and accuracy of time sequence control is improved.

For example, in the case where the program is executed by a processor, a time constraint method of the following program is implemented:

S13: the target code block is executed.

It should be noted that the above explanation of the embodiments and advantageous effects of the time constraint method of the program is also applicable to the computer readable storage medium of the embodiments of the present invention, and is not developed in detail herein to avoid redundancy.

Corresponding to the above embodiment, the embodiment of the present invention also proposes a chip, and fig. 6 is a block diagram of the structure of the chip according to one embodiment of the present invention. As shown in fig. 6, the chip 20 includes a memory 202, a processor 204, and a program 206 stored in the memory 202 and executable on the processor 204, and when the processor 204 executes the program 206, the time constraint method of the program of any of the above embodiments is implemented.

According to the chip provided by the embodiment of the invention, the first time constraint instruction is set at the starting position of the target code block, the time detection instruction is set at the ending position of the target code block, and when the program is executed, the first time constraint instruction is executed first to obtain the maximum allowable execution duration of the target code block, then the target code block is executed, and finally the time detection instruction is executed, so that when the execution timeout of the target code block is determined based on the maximum allowable execution duration, the timeout abnormal reminding is carried out, thereby more efficiently realizing the scheduling of resources, ensuring that the tasks with different key levels can meet the time constraint, and improving the accuracy of time sequence control.

For example, where the program 206 is executed by the processor 204, a time constraint method of the following program is implemented:

S13: the target code block is executed.

It should be noted that the above explanation of the embodiments and advantageous effects of the time constraint method of the program is also applicable to the chip 20 of the embodiment of the present invention, and is not developed in detail here to avoid redundancy.

Corresponding to the above embodiment, the embodiment of the present invention further proposes an electronic device, and fig. 7 is a block diagram of the electronic device according to one embodiment of the present invention. As shown in fig. 7, the electronic device 30 includes the aforementioned chip 20.

According to the electronic equipment provided by the embodiment of the invention, the first time constraint instruction is set at the starting position of the target code block, the time detection instruction is set at the ending position of the target code block, and when the program is executed, the first time constraint instruction is executed first to obtain the maximum allowable execution duration of the target code block, then the target code block is executed, and finally the time detection instruction is executed, so that when the execution timeout of the target code block is determined based on the maximum allowable execution duration, the timeout abnormal reminding is carried out, and therefore, the scheduling of resources can be more effectively realized, the time constraint can be met for tasks with different key levels, and the accuracy of time sequence control is improved.

It should be noted that the above explanation of the embodiments and advantageous effects of the time constraint method of the program is also applicable to the electronic device 30 according to the embodiment of the present invention, and is not developed in detail herein to avoid redundancy.

Corresponding to the above embodiment, the embodiment of the present invention also provides a time constraint device of a program, where the program includes an object code block, a first time constraint instruction set at a start position of the object code block, and a time detection instruction set at an end position of the object code block. Fig. 8 is a block diagram of a time constraint apparatus of a program according to an embodiment of the present invention. As shown in fig. 8, the time constraint device 40 of the program includes: a first instruction module 401, a second instruction module 402, and a third instruction module 403. The first instruction module 401 is configured to execute a first time constraint instruction, to obtain a maximum allowable execution duration of the target code block; the second instruction module 402 is used for executing the target code block; the third instruction module 403 is configured to execute a time detection instruction to perform a timeout exception alert when it is determined that the target code block is performing a timeout based on the maximum allowable execution duration.

According to the time constraint device of the program, the first time constraint instruction is set at the starting position of the target code block, the time detection instruction is set at the ending position of the target code block, and when the program is executed, the first time constraint instruction is executed first to obtain the maximum allowable execution duration of the target code block, then the target code block is executed, and finally the time detection instruction is executed, so that when the execution timeout of the target code block is determined based on the maximum allowable execution duration, timeout abnormal reminding is carried out, and therefore scheduling of resources can be achieved more efficiently, tasks of different key levels can meet time constraint, and accuracy of time sequence control is improved.

In some embodiments of the present invention, the time constraint device 40 of the program further comprises: the acquiring module 404, the acquiring module 404 is configured to acquire a first execution duration of the target code block; the third instruction module 403 is further configured to execute a time detection instruction to determine whether the first execution duration is greater than a maximum allowed execution duration, and determine that the execution of the target code block is overtime when the first execution duration is greater than the maximum allowed execution duration.

In some embodiments of the present invention, the first instruction module 401 is further configured to execute a first time constraint instruction, obtain a sum of a first current time when the first time constraint instruction is executed and a maximum allowed execution duration, and obtain a maximum allowed execution time; the third instruction module 403 is further configured to execute the time detection instruction, obtain a second current time when the time detection instruction is executed, determine whether the second current time is greater than a maximum allowable execution time, and determine that the target code block is executed over time when the second current time is greater than the maximum allowable execution time.

In some embodiments of the present invention, the second instruction module 402 is further configured to execute instruction code in the object code block that has timed out after the timeout exception alert is made.

In some embodiments of the present invention, the time constraint device 40 of the program further comprises: the compiling module 405 and the comparing module 406, the compiling module 405 is configured to obtain a second execution duration of the target code block when compiling the program; the comparison module 406 is configured to compare the second execution duration with the maximum allowable execution duration, and output a comparison result.

In some embodiments of the present invention, the program includes at least one basic block, and the compiling module 405 is specifically configured to: determining that the first time constraint instruction and the time detection instruction are in the same basic block, and obtaining the sum of instruction execution time lengths between the first time constraint instruction and the time detection instruction to obtain a second execution time length.

In some embodiments of the present invention, the program includes at least one basic block, and the compiling module 405 is specifically configured to: determining that a first time constraint instruction and a time detection instruction are in different basic blocks, and acquiring a first basic block in which the first time constraint instruction is located and a second basic block in which the time detection instruction is located; acquiring all paths between a first basic block and a second basic block; and obtaining the maximum value of the sum of the instruction execution time lengths between the first time constraint instruction and the time detection instruction in all paths, and obtaining the second execution time length.

In some embodiments of the present invention, the compiling module 405 is further configured to obtain a second execution duration of the target code block corresponding to each of the at least one scheduling frequency; the comparing module 406 is further configured to determine that the maximum allowable execution duration is smaller than the second execution duration of the target code block corresponding to each scheduling frequency, and output a comparison result of the time duration setting error.

In some embodiments of the invention, the program further comprises a second time constraint instruction and a delay instruction disposed between the target code block and the time detection instruction, the apparatus further comprising: a fourth instruction module 407 and a fifth instruction module 408, where the fourth instruction module 407 is configured to execute the second time constraint instruction to obtain a minimum allowable execution duration of the target code block; the fifth instruction module 408 is configured to execute the delay instruction such that the first execution time length of the target code block is greater than the minimum allowable execution time length.

It should be noted that the above explanation of the embodiments and advantageous effects of the time constraint method of the program is also applicable to the time constraint device 40 of the program according to the embodiment of the present invention, and is not developed in detail here to avoid redundancy.

It should be noted that the logic and/or steps represented in the flowcharts or otherwise described herein, for example, may be considered as a ordered listing of executable instructions for implementing logical functions, and may be embodied in any computer-readable medium for use by or in connection with an instruction execution system, apparatus, or device, such as a computer-based system, processor-containing system, or other system that can fetch the instructions from the instruction execution system, apparatus, or device and execute the instructions. For the purposes of this description, a "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of the computer-readable medium would include the following: an electrical connection (electronic device) having one or more wires, a portable computer diskette (magnetic device), a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disc read-only memory (CDROM). In addition, the computer readable medium may even be paper or other suitable medium on which the program is printed, as the program may be electronically captured, via, for instance, optical scanning of the paper or other medium, then compiled, interpreted or otherwise processed in a suitable manner, if necessary, and then stored in a computer memory.

It is to be understood that portions of the present invention may be implemented in hardware, software, firmware, or a combination thereof. In the above-described embodiments, the various steps or methods may be implemented in software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, may be implemented using any one or combination of the following techniques, as is well known in the art: discrete logic circuits having logic gates for implementing logic functions on data signals, application specific integrated circuits having suitable combinational logic gates, programmable Gate Arrays (PGAs), field Programmable Gate Arrays (FPGAs), and the like.

In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings are merely for convenience in describing the present invention and simplifying the description, and do not indicate or imply that the device or element being referred to must have a specific orientation, be configured and operated in a specific orientation, and therefore should not be construed as limiting the present invention.

Furthermore, the terms "first," "second," and the like, as used in embodiments of the present invention, are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or as implying any particular number of features in the present embodiment. Thus, a feature of an embodiment of the invention that is defined by terms such as "first," "second," etc., may explicitly or implicitly indicate that at least one such feature is included in the embodiment. In the description of the present invention, the word "plurality" means at least two or more, for example, two, three, four, etc., unless explicitly defined otherwise in the embodiments. Relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

In this specification, each embodiment is described in a related manner, and identical and similar parts of each embodiment are all referred to each other, and each embodiment mainly describes differences from other embodiments. In particular, for apparatus, electronic devices, and computer-readable storage medium embodiments, the description is relatively simple, as it is substantially similar to method embodiments, with reference to portions of the description of method embodiments being relevant.

While embodiments of the present invention have been shown and described above, it will be understood that the above embodiments are illustrative and not to be construed as limiting the invention, and that variations, modifications, alternatives and variations may be made to the above embodiments by one of ordinary skill in the art within the scope of the invention.

Claims

1. A time constraint method of a program, the program including an object code block, a first time constraint instruction provided at a start position of the object code block, and a time detection instruction provided at an end position of the object code block, the method comprising:

executing the first time constraint instruction to obtain the maximum allowable execution duration of the target code block;

Executing the target code block;

executing the time detection instruction to perform timeout exception reminding when the execution timeout of the target code block is determined based on the maximum allowable execution duration;

acquiring a second execution duration of the target code block when compiling the program;

comparing the second execution duration with the maximum allowable execution duration, and outputting a comparison result; when the second execution time length is longer than the maximum allowable execution time length, outputting a comparison result of time length setting errors;

the program includes at least one basic block, and the acquiring the second execution duration of the target code block includes:

determining that the first time constraint instruction and the time detection instruction are in the same basic block, and obtaining the sum of instruction execution time lengths between the first time constraint instruction and the time detection instruction to obtain the second execution time length.

2. The method according to claim 1, wherein the method further comprises:

acquiring a first execution duration of the target code block;

executing the time detection instruction to judge whether the first execution duration is longer than the maximum allowed execution duration, and determining that the target code block is executed overtime when the first execution duration is longer than the maximum allowed execution duration.

3. The method according to claim 1, wherein the method further comprises:

executing the first time constraint instruction, and obtaining the maximum allowed execution time obtained by the sum of the first current time and the maximum allowed execution time when the first time constraint instruction is executed;

executing the time detection instruction, acquiring a second current time when the time detection instruction is executed, judging whether the second current time is larger than the maximum allowed execution time, and determining that the execution of the target code block is overtime when the second current time is larger than the maximum allowed execution time.

4. The method according to claim 1, wherein the method further comprises:

and executing the overtime instruction codes in the target code block after overtime abnormal reminding.

5. The method of claim 1, wherein the obtaining the second execution duration of the target code block further comprises:

determining that the first time constraint instruction and the time detection instruction are in different basic blocks, and acquiring a first basic block in which the first time constraint instruction is located and a second basic block in which the time detection instruction is located;

Acquiring all paths between the first basic block and the second basic block;

and obtaining the maximum value of the sum of the instruction execution time durations between the first time constraint instruction and the time detection instruction in all paths, and obtaining the second execution time duration.

6. The method of claim 5, wherein the obtaining the maximum value of the sum of the instruction execution durations between the first time constraint instruction and the time detection instruction in all paths, to obtain the second execution duration, includes:

obtaining the sum of the execution time lengths of the basic blocks corresponding to each path in all paths, obtaining the path execution time length of each path, and obtaining a target path with the maximum path execution time length in all paths;

acquiring the sum of all instruction execution durations of the first basic block, which are positioned before the first time constraint instruction and positioned after the time detection instruction, in the second basic block;

and obtaining a difference value of the sum of the path execution time length corresponding to the target path and the instruction execution time length to obtain the second execution time length.

7. The method of any of claims 5-6, wherein obtaining a sum of instruction execution durations between the first time constraint instruction and the time detection instruction comprises:

Acquiring an instruction template corresponding to each instruction in all instructions between the first time constraint instruction and the time detection instruction, and acquiring execution time corresponding to each instruction from the instruction template;

and summing the execution time length corresponding to each instruction in all the instructions to obtain the sum of the instruction execution time lengths between the first time constraint instruction and the time detection instruction.

8. The method according to any one of claims 1-6, further comprising:

acquiring a second execution duration of the target code block corresponding to each scheduling frequency in at least one scheduling frequency;

and determining that the maximum allowed execution duration is smaller than the second execution duration of the target code block corresponding to each scheduling frequency, and outputting a comparison result of time length setting errors.

9. The method of any of claims 1-6, wherein the first time constraint instruction is an instruction that sets the maximum allowed execution time period via a register or wherein the first time constraint instruction is an instruction that sets the maximum allowed execution time period via an immediate in instruction encoding.

10. The method of any of claims 1-6, wherein the program further comprises a second time constraint instruction and a delay instruction disposed between the target code block and the time detection instruction, the method further comprising:

Executing the second time constraint instruction to obtain the minimum allowable execution duration of the target code block;

and executing the delay instruction to enable the first execution time length of the target code block to be longer than the minimum allowed execution time length.

11. A computer readable storage medium, characterized in that a program is stored thereon, which program, when being executed by a processor, implements a time constraint method of the program according to any of claims 1-10.

12. A chip, comprising: memory, a processor and a program stored on the memory and executable on the processor, the processor implementing the time constraint method of the program according to any of claims 1-10 when the program is executed.

13. An electronic device comprising a chip according to claim 12.

14. A time constraint device of a program, the program including an object code block, a first time constraint instruction provided at a start position of the object code block, and a time detection instruction provided at an end position of the object code block, the device comprising:

the first instruction module is used for executing the first time constraint instruction to obtain the maximum allowable execution duration of the target code block;

A second instruction module for executing the target code block;

the third instruction module is used for executing the time detection instruction to carry out overtime abnormal reminding when the execution overtime of the target code block is determined based on the maximum allowable execution duration;

the compiling module is used for acquiring a second execution duration of the target code block when compiling the program;

the comparison module is used for comparing the second execution duration with the maximum allowable execution duration and outputting a comparison result;

the program comprises at least one basic block, and the compiling module is specifically configured to: determining that the first time constraint instruction and the time detection instruction are in the same basic block, and obtaining the sum of instruction execution time lengths between the first time constraint instruction and the time detection instruction to obtain the second execution time length.

15. The apparatus of claim 14, wherein the apparatus further comprises:

the acquisition module is used for acquiring a first execution duration of the target code block;

the third instruction module is further configured to execute the time detection instruction, so as to determine whether the first execution duration is greater than the maximum allowed execution duration, and determine that the target code block is executed over time when the first execution duration is greater than the maximum allowed execution duration.

16. The apparatus of claim 14, wherein the device comprises a plurality of sensors,

the first instruction module is further configured to execute the first time constraint instruction, and obtain a maximum allowed execution time by obtaining a sum of a first current time and the maximum allowed execution time when the first time constraint instruction is executed;

the third instruction module is further configured to execute the time detection instruction, obtain a second current time when the time detection instruction is executed, determine whether the second current time is greater than the maximum allowed execution time, and determine that the target code block is executed over time when the second current time is greater than the maximum allowed execution time.

17. The apparatus of claim 14, wherein the second instruction module is further configured to execute instruction code in the object code block that has timed out after the timeout exception alert.

18. The apparatus according to claim 14, wherein the compiling module is further specifically configured to:

Acquiring all paths between the first basic block and the second basic block;

19. The device according to any one of claims 14 to 18, wherein,

the compiling module is further configured to obtain a second execution duration of the target code block corresponding to each scheduling frequency in at least one scheduling frequency;

the comparison module is further configured to determine that the maximum allowed execution duration is smaller than a second execution duration of the target code block corresponding to each scheduling frequency, and output a comparison result of time length setting errors.

20. The apparatus of any of claims 14-18, wherein the first time constraint instruction is an instruction that sets the maximum allowed execution time period via a register or wherein the first time constraint instruction is an instruction that sets the maximum allowed execution time period via an immediate in instruction encoding.

21. The apparatus according to any of claims 14-18, wherein the program further comprises a second time constraint instruction and a delay instruction disposed between the target code block and the time detection instruction, the apparatus further comprising:

A fourth instruction module, configured to execute the second time constraint instruction to obtain a minimum allowable execution duration of the target code block;

and a fifth instruction module, configured to execute the delay instruction, so that the first execution time of the target code block is longer than the minimum allowed execution time.