CN115793956A - Control method of storage device, and computer-readable storage medium - Google Patents
Control method of storage device, and computer-readable storage medium Download PDFInfo
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Abstract
The application relates to the technical field of storage devices, and discloses a control method of a storage device, the storage device and a computer readable storage medium. The method comprises the following steps: receiving a target instruction sent by external control equipment; determining an instruction type of a target instruction; at least one of a processor frequency, an encoding speed, a decoding speed, a bus transfer rate of the memory device is adjusted according to the instruction type to reduce power consumption of the memory device in executing the target instruction. By the method, the power consumption of the storage device during the execution of the target instruction can be reduced, and further the power consumption is reduced.
Description
Technical Field
The present application relates to the field of storage device technologies, and in particular, to a control method for a storage device, and a computer-readable storage medium.
Background
The storage device may be used solely for data storage, such as a removable hard drive. And can also cooperate with other devices to complete the reading and writing of data. Such as a storage device used on a mobile device to store user data, program data, etc. for the mobile device.
At present, more and more storage devices are developed towards high performance, the high performance is often accompanied with high power consumption, and the high power consumption needs to consume more electric quantity.
Disclosure of Invention
The technical problem mainly solved by the application is to provide a control method of a storage device, the storage device and a computer readable storage medium, which can reduce power consumption of the storage device when executing a target instruction, thereby reducing power consumption.
In order to solve the above problem, one technical solution adopted by the present application is to provide a method for controlling a storage device, including: receiving a target instruction sent by external control equipment; determining an instruction type of a target instruction; at least one of a processor frequency, an encoding speed, a decoding speed, a bus transfer rate of the memory device is adjusted according to the instruction type to reduce power consumption of the memory device in executing the target instruction.
Wherein adjusting at least one of a processor frequency, an encoding speed, a decoding speed, and a bus transfer rate of the storage device according to the instruction type comprises: if the instruction type is sequential read, the processor frequency is decreased.
Wherein adjusting at least one of a processor frequency, an encoding speed, a decoding speed, and a bus transfer rate of the storage device according to the instruction type comprises: if the instruction type is random reading, the decoding speed and the bus transmission rate of the storage device are reduced.
Wherein, the method also comprises: the processor of the storage device responds to the target instruction and sends a data reading request to a storage controller of the storage device; the storage controller responds to the data reading request and sends the data to be read corresponding to the data reading request to a cache array of the storage array; decoding the data to be read in the cache array, and transmitting the data to be read to a read cache module of the storage device through a bus; and sending the data to be read in the read cache module to the external control equipment.
Wherein adjusting at least one of a processor frequency, an encoding speed, a decoding speed, and a bus transfer rate of the storage device according to the instruction type comprises: if the instruction type is sequential write, the processor frequency is decreased.
Wherein adjusting at least one of a processor frequency, an encoding speed, a decoding speed, and a bus transfer rate of the storage device according to the instruction type comprises: if the command type is random writing, the coding speed and the bus transmission rate of the storage device are reduced.
Wherein, the method also comprises: responding to the target instruction by the processor of the storage device, and sending a data write request to a storage controller of the storage device; the storage controller receives data to be written sent by external control equipment and caches the data to be written in a write cache module; the storage controller sends the data to be written from the write cache module to the cache array; and writing the data to be written in the cache array into the storage array.
In order to solve the above problem, another technical solution adopted by the present application is to provide a storage device, where the storage device includes a processor and a memory coupled to the processor; wherein the memory is used for storing computer programs, and the processor is used for executing the computer programs so as to realize the method provided by the technical scheme.
The storage device is a solid state disk, a U disk, an SD card, a TF card or an eMMC storage device.
In order to solve the above problems, an aspect adopted by the present application is to provide a computer-readable storage medium for storing a computer program, which when executed by a processor is used to implement the method provided by the above technical solution.
The beneficial effect of this application is: different from the prior art, the control method of the storage device, the storage device and the computer-readable storage medium are provided by the application. The method comprises the following steps: receiving a target instruction sent by external control equipment; determining an instruction type of a target instruction; at least one of a processor frequency, an encoding speed, a decoding speed, a bus transfer rate of the memory device is adjusted according to the instruction type to reduce power consumption of the memory device in executing the target instruction. Through the mode, on the premise of not influencing the read-write performance of the storage device, at least one of the processor frequency, the encoding speed, the decoding speed and the bus transmission rate of the storage device is adjusted, so that the power consumption of the storage device when the storage device executes a target instruction can be reduced, and the power consumption is further reduced.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the description below are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings without creative efforts. Wherein:
FIG. 1 is a schematic flow chart diagram illustrating an embodiment of a method for controlling a storage device provided in the present application;
FIG. 2 is a flow chart illustrating a method for controlling a storage device according to another embodiment of the present disclosure;
FIG. 3 is a schematic structural diagram of an embodiment of a memory device provided herein;
FIG. 4 is a schematic flow chart of a read instruction executed by the storage device provided in the present application;
FIG. 5 is a flow chart illustrating a method for controlling a storage device according to another embodiment of the present disclosure;
FIG. 6 is a flow chart illustrating a method for controlling a storage device according to another embodiment of the present disclosure;
FIG. 7 is a flowchart illustrating a method for controlling a storage device according to another embodiment of the present disclosure;
FIG. 8 is a schematic flow chart of a write instruction executed by the storage device provided by the present application;
FIG. 9 is a flow chart illustrating a method for controlling a storage device according to another embodiment of the present disclosure;
FIG. 10 is a flow chart illustrating a method for controlling a storage device according to another embodiment of the present disclosure;
FIG. 11 is a schematic structural diagram of an embodiment of a memory device provided herein;
FIG. 12 is a schematic structural diagram of an embodiment of a computer-readable storage medium provided in the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the specific embodiments described herein are merely illustrative of the application and are not limiting of the application. It should be further noted that, for the convenience of description, only some of the structures related to the present application are shown in the drawings, not all of the structures. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The terms "first", "second", etc. in this application are used to distinguish between different objects and not to describe a particular order. Furthermore, the terms "include" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements listed, but may alternatively include other steps or elements not listed, or inherent to such process, method, article, or apparatus.
Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein can be combined with other embodiments.
Referring to fig. 1, fig. 1 is a schematic flowchart illustrating a control method of a storage device according to an embodiment of the present disclosure. The method comprises the following steps:
step 11: and receiving a target instruction sent by the external control equipment.
In some embodiments, the storage device is generally used with an external control device, and if the external control device sends a data reading instruction to the storage device, the storage device reads data corresponding to the data reading instruction and sends the data to the external control device. The external control device may calculate or present the data.
Specifically, the target instruction may be generated according to actual requirements, and if data needs to be read, a read instruction is generated, where the read instruction may be sequential read or random read; and generating a write instruction when the data needs to be written, wherein the write instruction can be sequential write or random write, and if the data needs to be erased, generating an erase instruction.
Step 12: an instruction type of the target instruction is determined.
Step 13: at least one of a processor frequency, an encoding speed, a decoding speed, a bus transfer rate of the memory device is adjusted according to the instruction type to reduce power consumption of the memory device in executing the target instruction.
In some embodiments, a storage device generally includes a processor, a storage controller, a codec module, a bus, a host interface, a storage array, and a cache module.
The host interface is connected with an external control device and a processor, and the processor is connected with a storage controller and a storage module; the memory controller is connected with the memory array and the coding and decoding module through a bus.
Usually, a target instruction sent by the external control device is received by the host interface and then sent to the processor, and the processor controls the storage controller to perform a corresponding operation based on the target instruction.
For example, the target instruction is an erase instruction, and the processor frequency, the encoding speed, the decoding speed, and the bus transmission rate can all be adjusted to be low, so as to reduce the power consumption of the storage device when executing the erase instruction.
For example, the target instruction is a write instruction, and the specific adjustment object may be determined according to the instruction type of the write instruction, so as to reduce power consumption of the storage device when executing the erase instruction.
For example, the target instruction is a read instruction, and the specific adjustment object may be determined according to an instruction type of the read instruction, so as to reduce power consumption of the storage device when the erase instruction is executed.
In the embodiment, the target instruction sent by the external control device is received; determining an instruction type of a target instruction; according to the instruction type, at least one of the processor frequency, the encoding speed, the decoding speed and the bus transmission rate of the storage device is adjusted to reduce the power consumption of the storage device when executing the target instruction, and the power consumption of executing the target instruction can be reduced on the premise of not influencing the read-write performance of the storage device, so that the power consumption is reduced.
Referring to fig. 2, fig. 2 is a schematic flowchart of another embodiment of a control method of a storage device provided in the present application. The method comprises the following steps:
step 21: and receiving a target instruction sent by the external control equipment.
Step 22: an instruction type of the target instruction is determined.
Step 23: if the instruction type is sequential read, the processor frequency is decreased.
The description is made with reference to fig. 3 and 4:
as shown in fig. 3, the storage device mainly includes a host interface, a processor, a memory, a storage controller, and a storage array.
The host interface is used for communicating with the external control device, such as receiving commands and data from the external control device or transmitting data or command status to the external control device.
The processor is used to run firmware to implement communication protocols, manage storage, schedule tasks, etc. with the external control device, which is the brain of the storage device. The memory is primarily used to store firmware code and data, and also as a data buffer between the external control device and the memory array. The storage controller is used for communicating with the storage array. The flash memory controller sends control instructions, writes data and reads data through the bus. On the data path between the memory controller and the memory array, there is an ECC (Error Correcting Code) engine for Correcting erroneous data on the memory array. On the path of the write data, ECC check data will be generated and written to the memory array. On the read path, the ECC engine will check and correct the error bits according to the ECC check. The memory array is typically a NAND flash memory for storing user data or system data.
The storage device may be a mobile storage device.
The storage device may also be applied to a mobile device, such as a mobile phone, a tablet computer, or a notebook computer. For a memory device, there are several core indicators, such as performance, reliability, endurance, and power consumption. As the battery of a mobile device becomes a bottleneck of the mobile device, a storage device having lower power consumption is more and more competitive in the market.
While high performance and low power consumption are two important goals for device vendors. However, high performance generally means high power consumption. The present application proposes the following way to reduce the operating power consumption of a memory device at the expense of not sacrificing system performance.
As shown in fig. 4, when processing a read instruction of an external control device, the following flow is generally included:
scheme A: the processor receives and parses the read command and then sends a data read request to the memory controller.
And (B) a process: the storage controller executes a data read request to read data from the storage array into a cache array in the storage array.
And (C) a process C: the DMA engine transfers data from the cache array to a read cache module in the memory via ECC decoding.
And (3) a process D: and the data in the read cache module is sent to the external control equipment through the DMA engine.
In some embodiments, the storage protocol in the storage device supports instruction queues, which means that multiple read instructions can be processed simultaneously.
If the time required to complete step a, step B, step C and step D is denoted by tA, tB, tC and tD respectively, the read performance = each read instruction block size/MAX (tA, tB, tC, tD).
This means that the read performance is limited by the slowest of the 4 steps a, B, C and D described above.
Where tA depends strongly on the processor speed. The faster the processor speed, the faster the firmware can process the read instruction. tB depends on data read performance, i.e. data read time in the memory array. tC depends on the bus transfer rate and ECC decoding speed. tD depends on the host interface speed between the external control device and the storage device.
Long-term studies by the applicant have found that for sequential reads, the data read is typically large, e.g., 128KB, 256KB, 512KB, etc., requiring high data throughput, which depends largely on host interface speed, decoding speed, and bus transfer rate. Therefore, the processing speed of the processor generally does not become a performance bottleneck for sequential reading, and therefore, when the instruction type is detected as sequential reading, the processor frequency can be reduced, and then the sequential reading instruction can be executed at a lower processor frequency.
In this embodiment, on the premise of not affecting the performance of the storage device, by determining that the instruction type is sequential read, the power consumption of the storage device when executing the sequential read instruction can be reduced in a manner of reducing the frequency of the processor, thereby reducing the power consumption.
Referring to fig. 5, fig. 5 is a schematic flowchart illustrating a control method of a storage device according to another embodiment of the present disclosure. The method comprises the following steps:
step 51: and receiving a target instruction sent by the external control equipment.
Step 52: an instruction type of the target instruction is determined.
Step 53: if the instruction type is random reading, the decoding speed and the bus transmission rate of the storage device are reduced.
Applicants have long studied that for random reading, the size of the data read is typically small, such as 4KB or 8KB. Read performance is typically dependent on the speed at which the firmware processes the read instruction, and therefore, it is desirable to keep the processor running at high speed. Therefore, when the instruction type is detected to be random reading, the decoding speed and the bus transmission rate of the memory device can be reduced, so that the power consumption of the memory device can be saved. Then the random read command is executed at a lower decoding speed and bus transfer rate.
In this embodiment, on the premise that the performance of the storage device is not affected, by determining that the type of the instruction is random-read, the decoding speed and the bus transmission rate of the storage device are reduced, so that power consumption of the storage device during execution of the random-read instruction can be reduced, thereby reducing power consumption.
Referring to fig. 6, fig. 6 is a schematic flowchart of another embodiment of a control method of a storage device provided in the present application. The method comprises the following steps:
step 61: the processor of the storage device sends a data read request to a storage controller of the storage device in response to the target instruction.
In the process, the type of the data reading request is identified, and if the data reading request is random reading, the decoding speed and the bus transmission rate of the storage device are reduced. If the reading is sequential, the processor frequency is reduced.
Step 62: and the memory controller responds to the data reading request and sends the data to be read corresponding to the data reading request to a cache array of the memory array.
It will be appreciated that the cache memory array in the memory array is capable of caching write data or read data in such a way that multiple read instructions are processed simultaneously.
And step 63: and decoding the data to be read in the cache array, and transmitting the data to be read to a read cache module of the storage device through a bus.
And decoding the data to be read by utilizing the ECC engine.
The bus is a NAND Flash bus and is connected with the storage array and the storage controller. And the storage controller sends data or instructions to the storage array through the NAND Flash bus.
Step 64: and sending the data to be read in the read cache module to external control equipment.
And the data to be read in the read cache module is sent to the external control equipment through the DMA engine.
It can be understood that, in the above process, if the read command is a random read, the decoding speed and the bus transfer rate of the storage device are reduced, and the above steps are performed at the reduced decoding speed and the reduced bus transfer rate. If the read instruction is sequential read, the processor frequency is decreased, and the steps are executed with the decreased processor frequency.
By the mode, the power consumption of the storage device during the execution of the read instruction can be reduced, and therefore the power consumption is reduced.
Referring to fig. 7, fig. 7 is a schematic flowchart illustrating a control method of a storage device according to another embodiment of the present disclosure. The method comprises the following steps:
step 71: and receiving a target instruction sent by the external control equipment.
Step 72: an instruction type of the target instruction is determined.
Step 73: if the instruction type is sequential write, the processor frequency is decreased.
The description is made with reference to fig. 3 and 8:
as shown in fig. 8, when processing a write command of an external control device, the following flow is generally included:
step E: the processor receives and parses the write instruction.
Step F: the storage controller receives data sent by an external control device and buffers the data in a write buffer module of the storage.
G: the storage controller transfers data from the write buffer module to a buffer array of the storage array.
It will be appreciated that encoding by the DMA engine is required during the transfer.
Step H: the data in the cache array will eventually be programmed into the memory array.
Typically storage protocols (such as UFS) support instruction queues, which means that multiple host write instructions can be handled simultaneously. We then have the following host write instruction processing pipeline.
If tE, tF, tG and tH respectively represent the time required for completing the steps E, F, G and H.
Write performance = per write instruction block size/MAX (tA, tB, tC, tD).
This means that the performance is limited by the slowest of the 4 steps E, F, G and H described above.
Where tE depends strongly on the processor speed. The faster the processor speed, the faster the firmware can process the write instructions. tF depends on the host interface speed between the external control device and the storage device. tG depends on the bus transfer speed and ECC encoding speed. tH depends on the data writing performance, i.e. the programming time, of the memory array.
Applicants have long studied that once the storage array and host interface of a storage device are determined, firmware cannot dynamically change their parameters, however, for the speed of the processor and bus, firmware can dynamically reduce them to reduce the operating power consumption of the device.
For example, if write performance is limited by flash performance (tB) or host interface speed (tD), the firmware may reduce the operating frequency of the processor (affecting tA), or the bus transfer rate and ECC encoding speed (affecting tC).
Based on this, for sequential writes, a higher data throughput is required, which depends largely on the host interface speed, the encoding speed, and the bus transfer rate. Therefore, the processing speed of the processor generally does not become a performance bottleneck of sequential reading, and therefore, when the instruction type is detected to be sequential writing, the frequency of the processor can be reduced, so that the power consumption of the storage device when the sequential writing instruction is executed can be reduced.
In this embodiment, on the premise that the performance of the storage device is not affected, by determining that the instruction type is sequential write, the power consumption of the storage device when executing the sequential write instruction can be reduced in a manner of reducing the frequency of the processor, so that the power consumption of the storage device is reduced.
Referring to fig. 9, fig. 9 is a schematic flowchart of another embodiment of a control method of a storage device provided in the present application. The method comprises the following steps:
step 91: and receiving a target instruction sent by the external control equipment.
And step 92: an instruction type of the target instruction is determined.
Step 93: if the command type is random writing, the coding speed and the bus transmission rate of the storage device are reduced.
The applicant has long studied that for random writing, the write performance depends on the speed at which the firmware processes the write instruction, and therefore it is desirable to keep the processor running at high speed. Conversely, when the type of instruction is detected as random write, the encoding speed and the bus transfer rate of the memory device may be reduced to reduce the power consumption of the memory device.
In this embodiment, on the premise of not affecting the performance of the storage device, by determining that the instruction type is random write, the encoding speed and the bus transmission rate of the storage device are reduced, so that the power consumption of the storage device when executing the random write instruction can be reduced, and the power consumption of the storage device is reduced.
Referring to fig. 10, fig. 10 is a schematic flowchart illustrating a control method of a storage device according to another embodiment of the present disclosure. The method comprises the following steps:
step 101: the processor of the storage device responds to the target instruction and sends a data write request to the storage controller of the storage device.
In the process, the type of the data writing request is identified, and if the data writing request is random writing, the coding speed and the bus transmission rate of the storage device are reduced. If the write is sequential, the processor frequency is decreased.
Step 102: the storage controller receives data to be written sent by the external control equipment and caches the data to be written in the write cache module.
It is understood that the write cache module belongs to the memory shown in fig. 3 described above.
Step 103: and the storage controller sends the data to be written from the write cache module to the cache array.
It will be appreciated that the cache memory array in the memory array is capable of caching write data or read data in such a way that multiple read instructions are processed simultaneously.
And encoding the data to be written in the write cache module by using the ECC engine.
Step 104: and writing the data to be written in the cache array into the storage array.
It can be understood that, in the above process, if the write command is random write, the encoding speed and the bus transfer rate of the storage device are reduced, and the above steps are performed at the reduced encoding speed and the reduced bus transfer rate. If the write instruction is a sequential write, the processor frequency is decreased, and the steps are executed with the decreased processor frequency.
By the mode, the power consumption of the storage device during the execution of the writing instruction can be reduced, and therefore the power consumption is reduced.
Referring to fig. 11, fig. 11 is a schematic structural diagram of an embodiment of a memory device provided in the present application. The storage device 110 includes a processor 111 and a memory 112 coupled to the processor 111; wherein the memory 112 is used for storing computer programs and the processor 111 is used for executing the computer programs to realize the following methods:
receiving a target instruction sent by external control equipment; determining an instruction type of a target instruction; at least one of a processor frequency, an encoding speed, a decoding speed, a bus transfer rate of the memory device is adjusted according to the instruction type to reduce power consumption of the memory device in executing the target instruction.
It is understood that the processor 111 is also used for executing a computer program to implement the method provided by any of the above embodiments, and the details are not described here.
The storage device 110 may be a solid state disk, a usb disk, an SD card, a TF card, or an eMMC storage device.
Wherein the storage device 110 may be a storage device as shown in fig. 3.
Referring to fig. 12, fig. 12 is a schematic structural diagram of an embodiment of a computer-readable storage medium provided in the present application. The computer-readable storage medium 120 is for storing a computer program 121, the computer program 121, when executed by a processor, being adapted to carry out the method of:
receiving a target instruction sent by external control equipment; determining an instruction type of a target instruction; at least one of a processor frequency, an encoding speed, a decoding speed, a bus transfer rate of the memory device is adjusted according to the instruction type to reduce power consumption of the memory device in executing the target instruction.
It is to be understood that the computer program 121, when being executed by a processor, is also used for implementing the method of any of the above embodiments, and is not described here in detail.
The computer readable storage medium 120 is a memory as in fig. 3 or the memory 112 in fig. 11.
In summary, performance and power consumption are two important metrics for measuring the performance of a mobile storage device. They appear to be contradictory, in that high performance generally means high power consumption. By means of the statements of any embodiment, the working power consumption of the storage device is reduced on the premise that the performance is not reduced.
In the several embodiments provided in the present application, it should be understood that the disclosed method and apparatus may be implemented in other manners. For example, the above-described device embodiments are merely illustrative, and for example, the division of the modules or units is only one type of logical functional division, and other divisions may be realized in practice, for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not executed.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one position, or may be distributed on multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the embodiment.
In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each of the units may exist alone physically, or two or more units may be integrated into one unit. The integrated unit may be implemented in the form of hardware, or may also be implemented in the form of a software functional unit.
The integrated unit in the other embodiments described above may be stored in a computer-readable storage medium if it is implemented in the form of a software functional unit and sold or used as a separate product. Based on such understanding, the technical solution of the present application may be substantially implemented or contributed by the prior art, or all or part of the technical solution may be embodied in a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, a network device, or the like) or a processor (processor) to execute all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.
The above description is only for the purpose of illustrating embodiments of the present application and is not intended to limit the scope of the present application, and all modifications of equivalent structures and equivalent processes, which are made by the contents of the specification and the drawings of the present application or are directly or indirectly applied to other related technical fields, are also included in the scope of the present application.
Claims (10)
1. A method of controlling a storage device, the method comprising:
receiving a target instruction sent by external control equipment;
determining an instruction type of the target instruction;
and adjusting at least one of the processor frequency, the encoding speed, the decoding speed and the bus transmission rate of the storage device according to the instruction type so as to reduce the power consumption of the storage device when the target instruction is executed.
2. The method of claim 1,
the adjusting at least one of the processor frequency, the encoding speed, the decoding speed and the bus transmission rate of the storage device according to the instruction type comprises:
if the instruction type is sequential read, the processor frequency is decreased.
3. The method of claim 1,
the adjusting at least one of the processor frequency, the encoding speed, the decoding speed and the bus transmission rate of the storage device according to the instruction type comprises:
if the instruction type is random reading, the decoding speed and the bus transmission rate of the storage device are reduced.
4. The method of claim 2 or 3,
the method further comprises the following steps:
the processor of the storage device responds to the target instruction and sends a data reading request to a storage controller of the storage device;
the storage controller responds to the data reading request and sends data to be read corresponding to the data reading request to a cache array of a storage array;
decoding the data to be read in the cache array, and transmitting the data to be read to a read cache module of the storage equipment through a bus;
and sending the data to be read in the read cache module to the external control equipment.
5. The method of claim 1,
the adjusting at least one of the processor frequency, the encoding speed, the decoding speed and the bus transmission rate of the storage device according to the instruction type comprises:
if the instruction type is sequential write, reducing the processor frequency.
6. The method of claim 1,
the adjusting at least one of the processor frequency, the encoding speed, the decoding speed and the bus transmission rate of the storage device according to the instruction type comprises:
and if the instruction type is random writing, reducing the coding speed and the bus transmission rate of the storage device.
7. The method according to claim 5 or 6,
the method further comprises the following steps:
responding to the target instruction by the processor of the storage device, and sending a data write request to a storage controller of the storage device;
the storage controller receives data to be written sent by the external control equipment and caches the data to be written in a write cache module;
the storage controller sends the data to be written from the write cache module to a cache array;
and writing the data to be written in the cache array into a storage array.
8. A storage device, comprising a processor and a memory coupled to the processor;
wherein the memory is adapted to store a computer program and the processor is adapted to execute the computer program to implement the method of any of claims 1-7.
9. The storage device of claim 8,
the storage device is a solid state disk, a U disk, an SD card, a TF card or an eMMC storage device.
10. A computer-readable storage medium, characterized in that the computer-readable storage medium is used to store a computer program which, when being executed by a processor, is used to carry out the method according to any one of claims 1-7.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202111058019.8A CN115793956A (en) | 2021-09-09 | 2021-09-09 | Control method of storage device, and computer-readable storage medium |
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| CN202111058019.8A CN115793956A (en) | 2021-09-09 | 2021-09-09 | Control method of storage device, and computer-readable storage medium |
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