CN115793302A - Common electrode output circuit, display panel and display device - Google Patents

Abstract

The application discloses public electrode output circuit, display panel and display device, public electrode output circuit includes: a common electrode main channel; at least three mutually parallel public electrode sub-channels which are respectively connected with the public electrode main channel; at least two of the common electrode sub-channels are respectively connected with a capacitor so as to keep the stability of the common voltage on each common electrode sub-channel. By the above structure, the problem of horizontal crosstalk is solved.

Description

Common electrode output circuit, display panel and display device

Technical Field

The invention relates to the field of display panels, in particular to a common electrode output circuit, a display panel and a display device.

Background

At present, an LCD (Liquid Crystal Display) is the most widely used Display in various industries, and has the advantages of thin appearance, light weight, and the like. The LCD display panel mainly includes a backlight module, an Array Substrate (thin film transistor Array Substrate), a Color filter Substrate (Color filter Substrate, CFSubstrate), and a Liquid Crystal Layer (Liquid Crystal Layer) disposed between the two substrates, wherein the Array Substrate is provided with a DATA line for transmitting a DATA voltage DATA, a pixel electrode for receiving the DATA voltage DATA, an Array common electrode for receiving an Array Substrate common voltage a-COM, and a light shielding electrode for receiving a light shielding common voltage DBS-COM, and the light shielding electrode covers the DATA line. And a color film common electrode for receiving a color film substrate common voltage CF-COM is arranged in the color film substrate.

The working principle of the LCD display panel is as follows: applying data voltage to a pixel electrode of the TFT substrate, and applying common voltage to a color film common electrode of the CF substrate to control the rotation of liquid crystal molecules of the liquid crystal layer, and refracting light of the backlight module to generate a picture; meanwhile, DBS-COM equal to CF-COM is provided to the shading electrode, so that the liquid crystal molecules corresponding to the position of the shading electrode are kept in a non-deflection state, and the aim of shading the data line is fulfilled.

Most of the conventional power ICs (Integrated circuits) of LCD display panels only have one common voltage output channel, so that the A-COM, CF-COM and DBS-COM are limited by the influence of the number of the IC output channels, and the COM signals are shorted together to be common potential. Due to the fact that coupling capacitance between the a-COM and DBS-COM and the data line on the array substrate is large, voltage variation of the a-COM and DBS-COM can cause CF-COM variation, instability of voltage on the CF-COM can cause degradation of panel performance, such as Greenish (Greenish) phenomenon and Image Sticking (Image Sticking) and the like, and further luminance of a pixel unit is deviated, and the phenomenon is also called horizontal crosstalk (H-cross talk).

Disclosure of Invention

The application provides a public electrode output circuit, a display panel and a display device to reduce the influence that the voltage of a public electrode receives data voltage, thereby solving the problem of horizontal crosstalk.

To solve the above problem, a first aspect of the present application provides a common electrode output circuit, including: a common electrode main channel; at least three mutually parallel public electrode sub-channels which are respectively connected with the public electrode main channel; at least two of the common electrode sub-channels are respectively connected with a capacitor so as to keep the stability of the common voltage on each common electrode sub-channel.

Preferably, the common electrode sub-channel includes a first common electrode, a second common electrode, and a third common electrode, and the first common electrode and the second common electrode are coupled with a metal trace to form the capacitor.

In order to solve the above problem, a second aspect of the present application provides a display panel, including an array substrate, the array substrate is provided with a first common electrode and a second common electrode, wherein, the array substrate is provided with a metal routing that overlaps with the first common electrode and the second common electrode, the metal routing with the first common electrode forms a first capacitor, and the second common electrode forms a second capacitor.

Preferably, the display panel further includes a display area and a non-display area located around the display area, and the metal trace and the first common electrode are overlapped in the non-display area; the metal routing and the second common electrode are arranged in the non-display area in an overlapped mode.

Preferably, the metal trace, the first common electrode and the second common electrode are located at different layers of the array substrate.

Preferably, the array substrate is further provided with a pixel electrode and a data line, the first common electrode is located on one side of the data line, which is far away from the pixel electrode, the second common electrode is located on the same layer as the pixel electrode, and the second common electrode covers the surface of the data line and is arranged at an interval with the pixel electrode.

Preferably, the metal trace includes a metal line for maintaining a constant voltage in the data line jumping process in the display panel.

Preferably, the display panel further includes a color filter substrate, and a third common electrode is further disposed on the color filter substrate, and the third common electrode is electrically connected to the first common electrode and the second common electrode on the array substrate.

The present application also provides a display device comprising the display panel of the second aspect and a driving circuit for driving the display panel.

Preferably, the non-display area of the display panel further includes a circuit board and a chip on film, and the third common electrode is electrically connected to the first common electrode and the second common electrode at the position of the chip on film or the circuit board.

The beneficial effect of this application is: the voltage on the first common electrode and the second common electrode is kept stable by connecting a capacitor on the first common electrode and the second common electrode which are connected with the third common electrode line respectively, so that the voltage on the first common electrode connected with the first common electrode is kept stable.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

FIG. 1 is a schematic diagram of an embodiment of a common electrode output circuit according to the present application;

FIG. 2 is a schematic top view of a display panel according to an embodiment of the present disclosure;

FIG. 3 is a schematic cross-sectional view of a display panel according to an embodiment of the present disclosure;

FIG. 4 is a schematic overall structure diagram of a display panel according to an embodiment of the present disclosure;

FIG. 5 is a schematic circuit diagram of a display panel according to a first embodiment of the present application;

FIG. 6 is a circuit diagram of a display panel according to a second embodiment of the present invention;

fig. 7 is a schematic diagram of a frame structure of an embodiment of a display device of the present application.

11 an array substrate; A-COM/111 first common electrode; DBS-COM/112 second common electrode; 12, a color film substrate; a CF-COM/121 third common electrode; 101, metal routing; a data line; 1 a display area; 2 a non-display area; pixel electrodes; an FPC circuit board; COF chip on film; 100 a display panel; 200 drive the circuit.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The terminology used in the embodiments of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in the examples of this application and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise, the "plural" includes at least two in general, but does not exclude the presence of at least one.

It should be understood that the term "and/or" as used herein is merely one type of association that describes an associated object, meaning that three relationships may exist, e.g., a and/or B may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein generally indicates that the former and latter associated objects are in an "or" relationship.

It should be understood that the terms "comprises," "comprising," or any other variation thereof, as used herein, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrases "comprising 8230; \8230;" comprises 8230; "does not exclude the presence of additional like elements in a process, method, article, or apparatus that comprises the element.

It should be noted that if directional indications (such as up, down, left, right, front, back, 8230; \8230;) are referred to in the embodiments of the present application, the directional indications are only used to explain the relative positional relationship between the components, the motion situation, etc. in a specific posture (as shown in the attached drawings), and if the specific posture is changed, the directional indications are correspondingly changed.

Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein can be combined with other embodiments.

The design idea of the application is as follows: the A-COM and DBS-COM on the array substrate are easy to form coupling capacitance with the data line and change along with voltage jump on the data line, and the CF-COM voltage on the CF side is connected with the A-COM and DBS-COM, so that the CF-COM voltage is influenced by the coupling capacitance, and the stability of the CF-COM is influenced. According to the scheme, the influence of data voltage on the A-COM and DBS-COM on the Array side (Array substrate) is reduced, so that the influence of CF-COM is reduced, and the stability of CF-COM is improved.

It should be noted that, in the existing solution, there are liquid crystal and thick PFA (passivation layer) between the data on the Array substrate (Array substrate) and the CF-COM of the CF substrate, so the effect of direct coupling to the CF-COM electrode when the data jumps is very little and can be ignored. However, the data and the common electrodes A-COM and DBS-COM of the Array substrate are direct coupling capacitors.

Referring to fig. 1, fig. 1 is a schematic structural diagram of a common electrode output circuit according to an embodiment of the present disclosure. As shown in fig. 1, the common electrode output circuit includes a common electrode main channel COM and at least three common electrode sub-channels connected in parallel. In this embodiment, the common electrode sub-channels comprise A-COM, DBS-COM and CF-COM, respectively. The common electrode sub-channels are respectively connected with the common electrode main channel COM. At least two common electrode sub-channels in the common electrode sub-channels are respectively connected with a capacitor, so that the stability of common voltage on each common electrode sub-channel is kept.

Specifically, the common electrode sub-channel includes a first common electrode A-COM, a second common electrode DBS-COM, and a third common electrode CF-COM. The first common electrode A-COM, the second common electrode DBS-COM and the third common electrode CF-COM are connected with a common electrode main channel COM, and the first common electrode A-COM and the second common electrode DBS-COM are respectively connected with a capacitor C1 and a capacitor C2. One end of the capacitor is connected with the first common electrode A-COM and the second common electrode DBS-COM respectively, and the other end of the capacitor is connected with a metal wire. When the voltage on the metal wire is not changed, the capacitance value of the capacitor is not changed, that is, the voltage on the first common electrode a-COM and the second common electrode DBS-COM can be kept unchanged, and the voltage on the third common electrode CF-COM connected with the first common electrode a-COM and the second common electrode DBS-COM can also be kept unchanged.

The beneficial effect of this embodiment is: the first capacitor C1 is additionally arranged on the A-COM wire, the second capacitor C2 is additionally arranged on the DBS-COM wire, so that the voltage stability of the A-COM wire and the DBS-COM wire is improved, when data jumps, the voltages of the A-COM wire and the DBS-COM wire are difficult to change, the voltage fluctuation of the CF-COM is reduced, and the stability of the CF-COM is improved. The first polar plate of the first capacitor C1 is connected to the a-COM, and the second polar plate is connected to the metal trace 101, so as to form the first capacitor C1. The first plate of the second capacitor C2 is connected to DBS-COM, and the second plate is connected to the same metal trace 101.

It should be noted that: the display panel can have a plurality of A-COM lines, DBS-COM lines and CF-COM lines, so that the number of the common electrode sub-channels is more than 3, and the number of the common electrode sub-channels can be multiple, and the types of the common electrode sub-channels include three types. In this embodiment, three lines are taken as an example for description, and when each type of COM line is multiple, each a-COM line and each DBS-COM line may be connected to a capacitor, which is not limited herein.

Referring to fig. 2, fig. 2 is a schematic top view structure diagram of an embodiment of a display panel according to the present application. As shown in fig. 2, the display panel includes an array substrate 11, and a first common electrode 111 and a second common electrode 112 are disposed on the array substrate 11. In this embodiment, the first common electrode 111 refers to a-COM, the second common electrode 112 refers to DBS-COM, and in other embodiments, the first common electrode 111 and the second common electrode 112 may be interchanged and are not limited herein.

In the present embodiment, a metal trace 101 (not shown) overlapping the first common electrode 111 and the second common electrode 112 is disposed on the array substrate 11. The overlapping part of the metal trace 101 and the first common electrode 111 forms a first capacitor C1, and the overlapping part of the metal trace 101 and the second common electrode 112 forms a second capacitor C2. In this embodiment, voltage fluctuations on the first common electrode 111 and the second common electrode 112 are reduced by the first capacitor C1 and the second capacitor C2, so that stability of COM routing is increased, and lateral crosstalk is improved.

The overlapping area of the metal trace 101 and the first common electrode 111 is not smaller than the overlapping area of the first common electrode 111 and the data line data. The capacitance value of the first capacitor C1 is larger than the capacitance value of the first common electrode 111 and the data line data to form a first coupling capacitor, so that the influence of the first coupling capacitor on the first common electrode 111 is smaller than the influence of the first capacitor C1 on the first common electrode 111. Similarly, the overlapping area of the metal trace 101 and the second common electrode 112 is not smaller than the overlapping area of the second common electrode 112 and the data line, so that the capacitance of the second capacitor C2 is larger than the capacitance of the second coupling capacitor formed by the second common electrode 112 and the data line data.

The metal trace 101 may be any one of LC1, LC2, VSS1, VSS2, STV, RST, VPC, and S-COM traces in the display panel. The metal trace 101 overlaps with the first common electrode 111 and the second common electrode 112 to form a capacitor, and the voltage is kept unchanged during the data line data transition process.

In this embodiment, the first common electrode 111 and the second common electrode 112 are located on different layers of the array substrate 11, so that the first common electrode 111 and the second common electrode 112 do not intersect in the display panel, and the first common electrode 111 and the second common electrode 112 are prevented from being shorted in the display panel. And, the first and second common electrodes 111 and 112 are located at different layers from the data line data. The metal trace 101 and the first and second common electrodes 111 and 112 are also located at different layers.

In one embodiment, the first common electrode 111 is located in the first metal layer, the data line data is located in the second metal layer, and the second common electrode 112 is located in the third metal layer. The array substrate 11 is further provided with Pixel electrodes Pixel, and the first common electrode 111 is located on a side of the data line data departing from the Pixel electrodes Pixel. In one embodiment, the first common electrode 111 is disposed around the Pixel electrode Pixel, and partially overlaps the Pixel electrode Pixel. The second common electrode line 112 is located at the same layer as the Pixel electrodes Pixel and is spaced apart from the Pixel electrodes Pixel. Specifically, the second common electrode line 112 covers the data line data and is parallel to the data line data without intersecting. The array substrate 11 is further provided with a gate line, and the first common electrode line 111 is further parallel to the gate line and does not intersect the gate line, which is not limited herein.

In this embodiment, the display panel further includes a color film substrate 12, specifically referring to fig. 3, and fig. 3 is a schematic cross-sectional structure diagram of the display panel according to an embodiment of the present disclosure. As shown in fig. 3, the display panel includes an array substrate 11, a color filter substrate 12, and a liquid crystal layer 13 between the array substrate 11 and the color filter substrate 12. A third common electrode 121 is disposed on the color filter substrate 12, and the third common electrode 121 is electrically connected to the first common electrode 111 and the second common electrode 112 on the array substrate 11. In the present embodiment, the third common electrode 121 is CF-COM. The voltages of the first and second common electrodes 111 and 112 affect the voltage on the third common electrode 121. The first common electrode 111 and the second common electrode 112 are located at different layers of the array substrate 11.

The beneficial effect of this embodiment is: the metal wiring is arranged on the array substrate to form a first capacitor and a second capacitor on the first common electrode and the second common electrode, and when the data line jumps, the voltage of the metal wiring is kept constant, so that the influence of the voltage on the first common electrode and the second common electrode on the voltage on the data line is reduced, the stability of the voltage on the third common electrode is further kept, and the transverse crosstalk phenomenon is improved.

Referring to fig. 4, fig. 4 is a schematic view of an overall structure of an embodiment of a display panel according to the present application. As shown in fig. 4, the display panel further includes a display area 1 and a non-display area 2, and the non-display area 2 is disposed around the display area 1. The display area 1 is used for displaying a picture, wherein a first common electrode 111 and a second common electrode 112 are disposed on the array substrate 11 of the display area 1, and a third common electrode 121 is disposed on the color film substrate 12 of the display area 1.

The first common electrode 111, the second common electrode 112 and the third common electrode 121 do not intersect in the display area 1, are electrically connected in the non-display area 2, and are combined to form a common electrode main channel COM.

In one embodiment, the non-display area 2 further includes a circuit board FPC and a chip on film COF.

In the first embodiment, the third common electrode 121 is merged with the first and second common electrodes 111 and 112 into one main channel COM in a region corresponding to the circuit board FPC. Specifically, as shown in fig. 5, fig. 5 is a schematic circuit diagram of a display panel according to a first embodiment of the present application.

In the second embodiment, the third common electrode 121, the first common electrode 111 and the second common electrode 112 are combined into a main channel COM in a region corresponding to the chip on film COF. Specifically, as shown in fig. 6, fig. 6 is a schematic circuit diagram of a display panel according to a second embodiment of the present application.

The beneficial effect of this embodiment is: the IC driving part combines A-COM, DBS-COM and CF-COM into one COM, so that the number of IC Pin signals is reduced, more IC channels can be compatible, and the cost is easier to control.

Fig. 7 is a schematic view of a frame structure of an embodiment of the display device of the present application. As shown in fig. 7, the display device includes a display panel 100 and a driving circuit 200 for driving each metal trace on the display panel. The driving circuit 200 is connected to each trace in the display panel 100, and is configured to provide a driving signal to each metal trace of the display panel 100 to control the display panel 100 to display normally. The driving circuit 200 includes a control chip, an MCU controller, and the like, which is not limited herein. A display panel of the display device includes a display area 1 and a non-display area 2, and refer to fig. 4 specifically. The third common electrode 121, the first common electrode 111 and the second common electrode 112 may be electrically connected at a position corresponding to the chip on film, or may be electrically connected at a position corresponding to the circuit board, where the electrical connection includes merging into a common electrode main channel COM.

The above embodiments are merely examples, and not intended to limit the scope of the present application, and all modifications, equivalents, and flow charts using the contents of the specification and drawings of the present application, or those directly or indirectly applied to other related arts, are included in the scope of the present application.

Claims (10)

1. A common electrode output circuit, comprising:

a common electrode main channel;

at least three mutually parallel public electrode sub-channels which are respectively connected with the public electrode main channel;

at least two of the common electrode sub-channels are respectively connected with a capacitor so as to keep the stability of the common voltage on each common electrode sub-channel.

2. The common electrode output circuit of claim 1, wherein the common electrode sub-channel comprises a first common electrode, a second common electrode, and a third common electrode, and the first common electrode and the second common electrode are coupled with a metal trace to form the capacitor.

3. A display panel comprises an array substrate, wherein a first common electrode and a second common electrode are arranged on the array substrate, and the display panel is characterized in that a metal wiring which is overlapped with the first common electrode and the second common electrode is arranged on the array substrate, the metal wiring and the first common electrode form a first capacitor, and the metal wiring and the second common electrode form a second capacitor.

4. The display panel according to claim 3, wherein the display panel further comprises a display area and a non-display area located around the display area, and the metal trace and the first common electrode are disposed in an overlapping manner in the non-display area; the metal routing and the second common electrode are arranged in the non-display area in an overlapping mode.

5. The display panel according to claim 3, wherein the metal traces and the first and second common electrodes are located at different layers of the array substrate.

6. The display panel according to claim 3, wherein a pixel electrode and a data line are further disposed on the array substrate, the first common electrode is disposed on a side of the data line away from the pixel electrode, the second common electrode and the pixel electrode are disposed on the same layer, and the second common electrode covers a surface of the data line and is spaced apart from the pixel electrode.

7. The display panel according to claim 3, wherein the metal traces comprise metal lines in the display panel that maintain a constant voltage during the data line jumping.

8. The display panel according to claim 3, further comprising a color film substrate, wherein a third common electrode is further disposed on the color film substrate, and the third common electrode is electrically connected to the first common electrode and the second common electrode on the array substrate.

9. A display device comprising the display panel according to any one of claims 3 to 8 and a driver circuit for driving the display panel.

10. The display device according to claim 9, wherein the non-display region of the display panel further comprises a circuit board and a flip-chip film, and the third common electrode is electrically connected to the first common electrode and the second common electrode at a position of the flip-chip film or the circuit board.

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