CN115776483A - VPX architecture-based worldwide gigabit network lead-out system and server - Google Patents

Abstract

The invention relates to a VPX architecture-based worldwide gigabit network lead-out system and a server. The system comprises: the computing board comprises a domestic central processing unit, a domestic MAC controller connected with the domestic central processing unit through a PCIE bus, and a pair of first domestic PHY transceivers connected with the domestic MAC controller through an SMI bus and an RGMII bus; the interface board comprises a pair of second domestic PHY transceivers, a pair of domestic network transformers correspondingly connected with each second domestic PHY transceiver through an MDI bus, and a pair of RJ45 interfaces correspondingly connected with each domestic network transformer; the VPX backplane provides a pair of first gigabit Serdes interfaces, each connecting a first domestic PHY transceiver and a second domestic PHY transceiver. The scheme of the invention adopts nationwide chips to lead out a kilomega Serdes interface which accords with the VPX standard framework.

Description

VPX architecture-based worldwide gigabit network lead-out system and server

Technical Field

The invention relates to the field of servers, in particular to a worldwide gigabit network leading-out system and a server based on a VPX framework.

Background

The OpenVPX standard is an industry technical standard issued by the VITA organization in 2010, mainly for military embedded computer market applications, and is one of the most successful embedded computer bus standards. China defines a detailed domestic computer development hardware system architecture specification on the basis of the standard. However, when four Serdes interfaces are designed after a computing board is designed, the current domestic devices cannot completely replace non-domestic devices, so that a developing party changes and self-defines the VPX interface definition, or other bus expansion modes are adopted to bypass the Serdes interfaces, and the compatibility problem of different products or the problem of system resource waste are caused.

At present, when a domestic computer develops a hardware system architecture standard and is customized, aiming at a design scheme after four kilomega Serdes, an I350 four-port gigabit Ethernet control chip of an Intel company is generally adopted, and the requirements on functions and performance can be completely met. The external interfaces are as follows: the system comprises an uplink PCIe interface V2.1 x4/x2/x1, four paths of 10/100/1000M BASE-T communication, four paths of Serdes 1000BASE-SX optical fiber communication, four paths of Serdes 1000BASE-KS backboard application, four paths of SGMII for external PHY connection and NC-SI. However, when 100% localization is promoted, I350 of Intel cannot be used, and is generally replaced by WX1860 of beijing web technologies ltd, where the external interface of WX1860 is as follows: upstream PCIe V2.1 x4/x2/x1, support four lanes of 10/100/1000M BASE-T communications, support four lanes of RGMII external PHY connections. However, the wrx 1860 chip does not support the Serdes interface, so that nationwide production cannot be realized when the network is brought out, and improvement is urgently needed.

Disclosure of Invention

In view of the above, there is a need to provide a VPX architecture-based gigabit network egress system and server.

According to a first aspect of the present invention, there is provided a VPX architecture-based worldwide gigabit network egress system, the system comprising:

the computing board comprises a domestic central processing unit, a domestic MAC controller connected with the domestic central processing unit through a PCIE bus, and a pair of first domestic PHY transceivers connected with the domestic MAC controller through an SMI bus and an RGMII bus, wherein each first domestic PHY transceiver works in an RGMII-SGMII mode;

an interface board, which comprises a pair of second domestic PHY transceivers, a pair of domestic network transformers correspondingly connected with each second domestic PHY transceiver through an MDI bus, and a pair of RJ45 interfaces correspondingly connected with each domestic network transformer, wherein each second domestic PHY transceiver works in an SGMII power outlet mode;

a VPX backplane providing a pair of first Gm Serdes interfaces, each first Gm Serdes interface connecting a first domestic PHY transceiver and a second domestic PHY transceiver.

In some embodiments, the system further comprises a SWITCH board having a domestic SWITCH chip;

the computing board further comprises a PCIe bridge chip arranged between the domestic central processing unit and the domestic MAC controller, and the PCIe bridge chip is configured to provide a PCIE X2 bus for the domestic MAC controller;

the computing board further comprises a pair of third domestic PHY transceivers connected with the domestic MAC controller through an SMI bus and an RGMII bus, wherein each third domestic PHY transceiver works in an RGMII optical outlet mode;

the backboard is further provided with a pair of second gigabit Serdes interfaces, and the pair of second gigabit Serdes interfaces are connected with the domestic SWITCH chip and the pair of third domestic PHY transceivers.

In some embodiments, the PCIe X2 bus from the PCIe bridge is PCI Express version 2.0.

In some embodiments, each first gigaSerdes interface and each second gigaSerdes interface support 10/100/1000M rate adaptation.

In some embodiments, each second-homed PHY transceiver is configured by default as rate-adaptive, full-duplex.

In some embodiments, after the interface board is plugged into the network cable to establish the external physical connection, each second domestic PHY transceiver performs a first rate duplex auto-negotiation with the corresponding first domestic PHY transceiver of the computing board through the SGMII bus.

In some embodiments, when the first rate duplex auto-negotiation is complete, the first domestic PHY transceiver performs a second rate duplex auto-negotiation with the domestic MAC controller over the RGMII bus and the SMI bus.

In some embodiments, the domestic central processing unit employs a Feiteng D2000/8 chip.

In some embodiments, the domestic MAC controller employs a WX1860AL4 chip, and the first domestic PHY transceiver, the second domestic PHY transceiver, and the third domestic PHY transceiver each employ a YT8531S chip.

According to a second aspect of the present invention, there is provided a server comprising the above-described VPX architecture-based worldwide gigabit network bring-out system.

The system and the server for leading out the worldwide gigabit network based on the VPX framework have the following beneficial effects: under the design requirement of hundreds of nationwide products, four gigabit Serdes interfaces are led out based on an OpenVPX standard framework, wherein two paths are used as system interconnection interfaces, two paths are used as rear outlet interfaces, and the four Serdes interfaces all support a 10/100/1000M self-adaptive full/half-duplex mode, so that the problem that the existing nationwide scheme cannot completely replace a non-nationwide scheme is solved, a nationwide chip is adopted to lead out the gigabit Serdes interfaces meeting the VPX standard framework specification, and the gigabit Serdes interfaces have better universality.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other embodiments can be obtained by using the drawings without creative efforts.

Fig. 1 is a schematic structural diagram of a global gigabit network egress system based on a VPX architecture according to an embodiment of the present invention;

fig. 2 is a schematic diagram of another connection line of a global gigabit network outgoing system based on a VPX architecture according to another embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention are described in further detail with reference to the accompanying drawings.

It should be noted that all expressions using "first" and "second" in the embodiments of the present invention are used for distinguishing two entities with the same name but different names or different parameters, and it should be noted that "first" and "second" are only used for convenience of expression and should not be construed as a limitation to the embodiments of the present invention, and no description is given in the following embodiments.

First, the terms involved are explained below for ease of understanding:

SMI refers to a Serial Management Interface (Serial Management Interface), also called MII Management Interface (MII Management Interface), and includes two signal lines, MDC and MDIO. The MDIO is a management interface of the PHY, which is used to read/write the registers of the PHY to control the behavior of the PHY or to obtain the state of the PHY, and the MDC provides the clock for the MDIO.

MDIs (Media Dependent Interface, media Dependent/related Interface), also known as uplink ports, are commonly used for NIC (network Interface card) on PCs or ethernet port connections that integrate NIC ports. When the transmission signal of the NIC is to be transmitted to the reception signal of the hub or the network switch, the MDIX port is connected through a through cable.

RGMII, reduced GMII, is a simplified version of RGMII, reducing the number of interface signal lines from 24 to 14 (COL/CRS port status indication signals, not shown here), still with a clock frequency of 125mhz, with a tx/RX data width of from 8 to 4 bits, and in order to keep the transmission rate at 1000Mbps constant, the RGMII interface samples data on both the rising and falling edges of the clock.

SGMII, serial GMII, transceives a pair of differential signal lines, has a clock frequency of 625MHz, samples on both rising and falling edges of a clock signal, and a reference clock RX _ CLK is provided by the PHY, is optional, and is mainly used in the case where the MAC side has no clock, and is not used in general. Both transceivers may recover the clock from the data.

The MII (Media Independent interface) is a Media Independent interface, which is an industry standard defined by IEEE-802.3 and is an interface between MAC and PHY.

The MAC, i.e., media Access controller, refers to a Media Access control sublayer protocol, and the MAC has two concepts: the MAC may be a hardware controller and MAC communication protocol. The protocol is located in the lower half of the data link layer in the OSI seven-layer protocol and is mainly responsible for controlling and connecting the physical medium of the physical layer.

PHY, a Port Physical Layer, connects a data link Layer device (MAC) to a Physical medium, such as an optical fiber or copper cable. Typical PHYs include PCS (Physical Coding Sublayer) and PMD (Physical Media Dependent Sublayer). The PCS encodes and decodes the transmitted and received information in order to make it easier for the receiver to recover the signal.

In one embodiment, referring to fig. 1, the present invention provides a worldwide gigabit network outbound system based on VPX architecture, specifically, the system includes the following structures:

a computing board, wherein the computing board includes a domestic Central Processing Unit (CPU), a domestic MAC (Media Access Control) controller connected to the domestic CPU via a PCIE bus, and a pair of first domestic PHY transceivers connected to the domestic MAC controller via an SMI bus and an RGMII bus, and each first domestic PHY transceiver operates in an RGMII to SGMII mode;

an interface board, which comprises a pair of second domestic PHY transceivers, a pair of domestic network transformers correspondingly connected with each second domestic PHY transceiver through an MDI bus, and a pair of RJ45 interfaces correspondingly connected with each domestic network transformer, wherein each second domestic PHY transceiver works in an SGMII power outlet mode;

a VPX backplane providing a pair of first gigaserdes interfaces (not shown), each first gigaserdes interface connecting one first and one second domestic PHY transceiver.

The domestic gigabit network lead-out system based on the VPX framework has the following beneficial effects: under the design requirement of hundreds of nationwide products, four gigabit Serdes interfaces are led out based on an OpenVPX standard framework, two of the gigabit Serdes interfaces are used as system interconnection interfaces, two of the gigabit Serdes interfaces are used as rear outlet interfaces, and the four Serdes interfaces all support a 10/100/1000M self-adaptive full/half-duplex mode, so that the problem that the existing nationwide scheme cannot completely replace a non-nationwide scheme is solved, a nationwide chip is adopted to lead out the gigabit Serdes interfaces meeting the VPX standard framework specification, and the gigabit Serdes interfaces have better universality.

In some embodiments, the system further comprises a SWITCH board having a domestic SWITCH chip;

the computing board further comprises a PCIe bridge chip arranged between the domestic central processing unit and the domestic MAC controller, and the PCIe bridge chip is configured to provide a PCIE X2 bus for the domestic MAC controller;

the computing board further comprises a pair of third domestic PHY transceivers connected to the domestic MAC controller via a SMI bus, a RGMII bus, wherein each third domestic PHY transceiver operates in RGMII optical outlet mode;

the backplane is further provided with a pair of second gigabit Serdes interfaces (not shown in the figure), and the pair of second gigabit Serdes interfaces is connected with the domestic SWITCH chip and a pair of third domestic PHY transceivers.

In some embodiments, the PCIe X2 bus from the PCIe bridge is PCI Express version 2.0.

In some embodiments, each first gigaSerdes interface and each second gigaSerdes interface support 10/100/1000M rate adaptation.

In some embodiments, each second domestic PHY transceiver is configured by default as rate-adaptive, full-duplex.

In some embodiments, after the interface board is plugged into the network cable to establish the external physical connection, each second domestic PHY transceiver performs a first rate duplex auto-negotiation with the corresponding first domestic PHY transceiver of the computing board through the SGMII bus.

In some embodiments, when the first rate duplex auto-negotiation is complete, the first domestic PHY transceiver performs a second rate duplex auto-negotiation with the domestic MAC controller over the RGMII bus and the SMI bus.

In some embodiments, the domestic central processing unit is a Feiteng D2000/8 chip.

In some embodiments, the domestic MAC controller employs a WX1860AL4 chip, and the first, second, and third domestic PHY transceivers each employ a YT8531S chip.

In another embodiment, please refer to fig. 2, in order to facilitate understanding of the solution of the present invention, a soar D2000/8 chip is taken as a central processing unit, a WX1860AL4 chip of beijing network communication technology ltd is taken as a MAC controller, and a YT8531S gigabit ethernet transceiver of suto yutai microelectronics ltd is taken as a PHY transceiver, for example, in this embodiment, another kind of global gigabit network lead-out system based on VPX architecture is provided, which has the following principles: WX1860 can replace I350 for MDI (wrapper) electrical port applications, and also has RGMII communication functionality, but lacks Serdes (SGMII) communication functionality. The interface definition of the domestic VPX specification specifies that a Serdes signal is required to be used for penetrating through a VPX connector and being interconnected with an interface board; although the VPX specification requirements cannot be directly met using WX1860, since WX1860 supports RGMII, we can reach the homemade VPX specification interface requirements by connecting to an external PHY through RGMII, and extending the Serdes interface out of the external PHY.

The YT831S support operation modes include: mode 0: UTP < - > RGMII: RGMII power outlet; mode 1: fiber < - > RGMII: RGMII light outlet; mode 2: UTP/Fiber < - > RGMII: the RGMII power outlet and the optical port are automatically detected; mode 3: UTP < - > SGMII: an SGMII power outlet; mode 4: SGMII (PHY) < - > RGMII (MAC): SGMII is converted into RGMII, and MAC is arranged on the SGMII side; mode 5: SGMII (MAC) < - > RGMII (PHY): RGMII is converted into SGMII, and MAC is on the RGMII side; mode 6: UTP < - > Fiber (AUTO): self-adaptive rate of an electric port to an optical port; mode 7: UTP < - > Fiber (FORCE): the electrical port to optical port forces giga-rate.

The system adopts 6 YT8531S chips recorded as A to F and a WX1860AL4 chip, YT8531S C and YT8531S D as first domestic PHY transceivers, YT8531S E and YT8531S F as second domestic PHY transceivers, YT8531S A and YT8531S B as third domestic PHY transceivers, and the concrete connection relations of all parts are as follows: YT8531S chips A to D are connected with WX1860AL4 chips through SMI buses and RGMII buses, YT8531S A, YT8531SB, YT8531S C and YT8531S D are respectively connected to four kilomega Serdes interfaces of the back plate through SGMII buses, two kilomega Serdes interfaces corresponding to YT8531S A and YT8531S B are connected to a SWITCH chip of the exchange plate through two SGMII buses, two kilomega Serdes interfaces corresponding to YT8531SC and YT8531S D are respectively connected to YT8531S E and YT8531S F through two SGMII buses, YT8531S E and YT8531S F are respectively connected to two network transformers through MDI buses, and RJ45 interfaces are led out from the two network transformers.

Note that, in the present embodiment, YT8531S C and YT8531S D are set to operate in the mode 5 state, YT8531S E and YT8531S F are set to operate in the mode three state, and YT8531SA and YT8531S B are set to operate in the mode 1 state. YT8531S a and YT8531S B need to be connected to the switch board (like a network switch), so using mode 1, after RGMII is converted to Serdes, the switch board is connected. YT8531S C and YT831S D need to be connected to an interface board and output two electrical ports (UTP), and since the VPX backplane can only pass Serdes signals (standard limit), the interface board needs one PHY chip to convert Serdes into an electrical port, so that two PHY chips are connected in series on one network channel of WX1860AL4, which is different from the conventional architecture. This uses the YT8531 mode 5, which is a rarely used mode of operation. This mode is connected to the MAC (WX 1860) with RGMII, which is the role of PHY; and then the SGMII is connected with PHY (YT 8531) of the interface board, which is the role of MAC. YT8531S of the interface board converts SGMII coming from the VPX backplane into an electrical port leading-out device by using a conventional mode 3. Therefore, the extraction of four gigabit network ports under a VPX frame is realized, the rate adaptation of 10/100/1000M is supported, and the network port is realized by using domestic devices.

The establishing process YT8531S E/F of the data link is configured as rate self-adaption and full duplex by default, SMI management is not needed, and PHY (YT 8531 SE) completes rate duplex self-negotiation with YT8531S C of the computing board through SGMII bus after the interface board is inserted into a network cable and external physical connection is established. YT8531SC completes the rate duplex auto-negotiation with WX1860AL4X chip through RGMII bus and SMI bus, thereby opening the path of physical layer and data link layer.

The system for leading out the gigabit network based on the VPX framework has the following beneficial technical effects that under the OpenVPX standard framework, four paths of gigabit Serdes are realized by using the components made in China, the definition of standard interface signals is completely followed, basic functions of 10/100/1000M self-adaption, full/half duplex modes and the like of a gigabit network port are realized, and the bandwidth test reaches the standard.

In yet another embodiment, the present invention further provides a server, where the server includes the VPX architecture-based gigabit network egress system according to the above embodiment.

All possible combinations of the technical features in the above embodiments may not be described for the sake of brevity, but should be considered as being within the scope of the present disclosure as long as there is no contradiction between the combinations of the technical features.

The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is specific and detailed, but not to be understood as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, and these are all within the scope of protection of the present application. Therefore, the protection scope of the present patent application shall be subject to the appended claims.

Claims (10)

1. A worldwide gigabit network (GVG) pull-out system based on VPX architecture, the system comprising:

a computing board comprising a domestic central processor, a domestic MAC controller connected to the domestic central processor via a PCIE bus, and a pair of first domestic PHY transceivers connected to the domestic MAC controller via an SMI bus and an RGMII bus, wherein each first domestic PHY transceiver operates in an RGMII to SGMII mode;

an interface board, which comprises a pair of second domestic PHY transceivers, a pair of domestic network transformers correspondingly connected with each second domestic PHY transceiver through an MDI bus, and a pair of RJ45 interfaces correspondingly connected with each domestic network transformer, wherein each second domestic PHY transceiver works in an SGMII power outlet mode;

a VPX backplane providing a pair of first Gm Serdes interfaces, each first Gm Serdes interface connecting a first domestic PHY transceiver and a second domestic PHY transceiver.

2. The VPX architecture based gigabit network capable of always being brought out according to claim 1, further comprising a switchboard with a local SWITCH chip;

the computing board further comprises a PCIe bridge chip arranged between the domestic central processing unit and the domestic MAC controller, and the PCIe bridge chip is configured to provide a PCIE X2 bus for the domestic MAC controller;

the computing board further comprises a pair of third domestic PHY transceivers connected with the domestic MAC controller through an SMI bus and an RGMII bus, wherein each third domestic PHY transceiver works in an RGMII optical outlet mode;

the backboard is further provided with a pair of second kilomega Serdes interfaces, and the second kilomega Serdes interfaces are connected with the domestic SWITCH chip and the third domestic PHY transceiver.

3. The VPX architecture-based gigabit network capable system according to claim 2, wherein the PCIe X2 bus capable of being exported by the PCIe bridge is PCI Express version 2.0.

4. The VPX architecture based gigabit network capable system according to claim 2, wherein each first and second gigabit Serdes interface supports 10/100/1000M rate adaptation.

5. The VPX architecture-based worldwide gigabit network capable system according to claim 4, wherein each second domestic PHY transceiver is configured by default as rate adaptive, full duplex.

6. The VPX architecture-based gigabit network egress system according to claim 5, wherein each second home PHY transceiver performs a first rate duplex auto-negotiation with the corresponding first home PHY transceiver of the computing board via the SGMII bus after the interface board is plugged into a network cable to establish an external physical connection.

7. The VPX architecture-based legacy gigabit network egress system according to claim 6, wherein said first native PHY transceiver performs a second rate duplex auto-negotiation with said native MAC controller via RGMII bus and SMI bus when said first rate duplex auto-negotiation is completed.

8. A VPX architecture-based gigabit network capable of being brought out by any one of claims 1 to 7, wherein the domestic central processing unit is a Feiteng D2000/8 chip.

9. The VPX architecture based gigabit network capable of being brought out according to one of claims 2 to 7, wherein the domestic MAC controller employs WX1860AL4 chips, and wherein the first, second and third domestic PHY transceivers each employ YT8531S chips.

10. A server, characterized in that it comprises a VPX architecture based gigabit network capable egress system according to one of the claims 1 to 9.

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