CN115775783A

CN115775783A - Chip-on-board module

Info

Publication number: CN115775783A
Application number: CN202111037171.8A
Authority: CN
Inventors: 周晏铃; 纪柏任; 张威廷
Original assignee: Winbond Electronics Corp
Current assignee: Winbond Electronics Corp
Priority date: 2021-09-06
Filing date: 2021-09-06
Publication date: 2023-03-10

Abstract

A chip-on-board module comprises a chip and a substrate. The chip includes a plurality of chip contacts. The substrate comprises a plurality of first pins and a plurality of second pins, wherein the plurality of first pins and the plurality of second pins are respectively coupled with the plurality of chip contacts of the part, the plurality of first pins are arranged along a first axis, the plurality of second pins are arranged along a second axis, a first axis included angle is formed between the first axis and the second axis, and the first axis included angle is between 100 degrees and 170 degrees.

Description

Chip-on-board module

Technical Field

Embodiments of the present invention relate to a chip-on-board module, and more particularly, to a chip-on-board module with a large number of chip contacts.

Background

A known chip-on-board module has a chip and a substrate. The chip comprises a plurality of chip contacts and is arranged in the opening of the substrate. The substrate includes a plurality of pins disposed adjacent to the opening. Each chip contact is coupled to one pin by wire bonding. As the functional requirements of the chip become higher, the number of chip contacts also becomes higher. Due to the limitations of the line width and the pitch of the leads, the size of the substrate is increased to match the number of chip contacts, which increases the size of the product. In addition, since the production line equipment must be modified in accordance with the size of the substrate, the equipment cost is increased.

In the prior art, there is a configuration in which the leads are arranged around the opening, thereby reducing the size of the substrate. However, since the arrangement of the chip contacts is not necessarily a proper arrangement of pins arranged around the chip, the problems of wire bonding interference or wire crossing often occur.

Disclosure of Invention

Embodiments of the present invention provide a chip-on-board module, which includes a chip and a substrate. The chip includes a plurality of chip contacts. The substrate comprises a plurality of first pins and a plurality of second pins, wherein the first pins and the second pins are respectively coupled with the plurality of chip contacts of the part, the first pins are arranged along a first axis, the second pins are arranged along a second axis, and a first axis included angle between 100 degrees and 170 degrees is formed between the first axis and the second axis.

In the chip-on-board module according to the embodiment of the invention, the pins are arranged around the chip, so that the size of the substrate is reduced or maintained. In addition, because the first pins and the second pins are arranged in a specific way (the first axis included angle is between 100 degrees and 170 degrees), the problems of wire bonding interference or wire crossing and the like can be avoided, the pin density can be increased, and the wire bonding distance can be further shortened. The chip-on-board module of the embodiment of the invention can maintain or lighten the size of a product and can save equipment cost.

Drawings

Fig. 1 shows a chip-on-board module according to a first embodiment of the invention.

Fig. 2 shows a chip-on-board module according to a second embodiment of the invention.

Reference numbers:

m1, M2 chip-on-board module 231 third axis

101. 102, chips 24, 24', a fourth pin

10 chip contact 241 fourth axis

11. 11' first chip contact 25, fifth lead

111. 111' first straight line 26: sixth pin

12. 12', second chip contact 27, seventh lead

121, second straight line 28, eighth pin

151. 151' first chip edge 29 ninth lead

152 second chip edge 20 tenth lead

153 third chip edge 30 wire bonding

154 fourth chip edge θ 11 first axis fillet

19. 19' bisector theta 12 second axis line clip angle

201. 202 substrate theta 21 first lead inclination angle

2011 opening theta 22 and second lead inclination angle

21. 21', a first lead theta 23, a third lead inclination angle

211 first axis theta 24 fourth pin inclination

22. 22' the second lead B is a blank area

221 second axis B1 first blank area

23. 23' a third pin B2 and a second blank area

Detailed Description

Referring to fig. 1, a chip-on-board module M1 according to a first embodiment of the present invention includes a chip 101 and a substrate 201. The chip 101 is disposed in the opening 2011 of the substrate 201. The chip 101 comprises a plurality of chip contacts 10. The substrate 201 includes a plurality of first pins 21 and a plurality of second pins 22, the first pins 21 and the second pins 22 are respectively coupled to the corresponding chip contacts 10, wherein the first pins 21 are arranged along a first axis 211, the second pins 22 are arranged along a second axis 221, a first axis included angle θ 11 is formed between the first axis 211 and the second axis 221, and the first axis included angle θ 11 is between 100 ° and 170 °. In an embodiment, the first included angle θ 11 is between 115 ° and 155 °, and the first included angle θ 11 may be, for example, 135 °.

In the drawings of the embodiments of the present invention, the size of the plurality of chip contacts is enlarged and some chip contacts are omitted with dots for clarity, and the size, angle, length, etc. of the drawings are not intended to limit the present invention.

Referring to fig. 1, in one embodiment, the first leads 21 and the second leads 22 are disposed adjacent to a first edge of the opening 2011 and are disposed corresponding to the first chip edge 151 of the chip 101.

In one embodiment, a first lead inclination angle θ 21 between each first lead 21 and the first chip edge 151 is between 20 ° and 70 °. A second lead inclination angle theta 22 between each second lead 22 and the first chip edge 151 is between 20 DEG and 70 deg. In one embodiment, the first lead inclination angle θ 21 is equal to the second lead inclination angle θ 22, such as 30 °

In one embodiment, each of the first leads 21 is a linear structure inclined to the first chip edge 151, and the first leads 21 are parallel to each other. Each second lead 22 is a straight structure inclined to the first chip edge 151, and the second leads 22 are parallel to each other. In an embodiment, the first axis 211 is parallel to the first chip edge 151.

Referring to fig. 1, in an embodiment, the substrate 201 further includes a plurality of third leads 23 and a plurality of fourth leads 24. The third leads 23 and the fourth leads 24 are respectively coupled to the corresponding chip contacts 10, and are disposed adjacent to one of the sides of the opening 2011, while being disposed corresponding to the first chip edge 151 of the chip 201. A third lead inclination angle theta 23 is formed between each third lead 23 and the first chip edge 151, a fourth lead inclination angle theta 24 is formed between each fourth lead 24 and the first chip edge 151, the third lead inclination angle theta 23 is different from the first lead inclination angle theta 21 and the second lead inclination angle theta 22, and the fourth lead inclination angle theta 24 is different from the first lead inclination angle theta 21 and the second lead inclination angle theta 22. In one embodiment, the third pin inclination angle θ 23 is equal to the fourth pin inclination angle θ 24.

In one embodiment, each of the third leads 23 is a straight structure inclined to the first chip edge 151, and the third leads 23 are parallel to each other. Each fourth lead 24 is a straight structure inclined to the first chip edge 151, and the fourth leads 24 are parallel to each other.

In one embodiment, the third pins 23 are arranged along a third axis 231, the fourth pins 24 are arranged along a fourth axis 241, and a second axial included angle θ 12 between the third axis 231 and the fourth axis 241 is between 100 ° and 170 °. In one embodiment, the second line clip angle θ 12 is between 115 ° and 155 °, such as 135 °.

In one embodiment, the first axis 211 and the third axis 231 are parallel to the first chip edge 151. In one embodiment, the second axis 221 and the fourth axis 241 are symmetrical to the bisector 19 of the chip 101, and the bisector 19 is perpendicular to the first chip edge 151.

In one embodiment, the chip contacts 10 include a plurality of first chip contacts 11 and a plurality of second chip contacts 12, the first chip contacts 11 are arranged along a first straight line 111, and the second chip contacts 12 are arranged along a second straight line 121. The chip 101 includes a second chip edge 152 and a third chip edge 153, the second chip edge 152 is perpendicular to the first chip edge 151, the third chip edge 153 is perpendicular to the first chip edge 151, the first line 111 is parallel to the second chip edge 152, and the second line 121 is parallel to the third chip edge 153. The first leads 21 and the second leads 22 are respectively coupled to the corresponding first chip contacts 11, and the third leads 23 and the fourth leads 24 are respectively coupled to the corresponding second chip contacts 12.

In one embodiment, as shown in fig. 2, each pin is coupled to an adjacent chip contact by way of a wire bond 30 (in fig. 2, the wire bond 30 is shown by way of example, and the disclosure is not intended to limit the invention). The first leads 21 and the second leads 22 'disposed adjacent to the first chip edge 151' are coupled to the chip contacts 11 'disposed relatively close to the first chip edge 151'. The third leads 23' and the fourth leads 24' disposed adjacent to the first chip edge 151' are coupled to the chip contacts 12' disposed relatively close to the first chip edge 151'. For example, the total number of N first leads and the total number of M second leads are respectively coupled to the N + M first chip contacts closer to the edge of the first chip by wire bonding.

Referring to fig. 1, in one embodiment, the first chip contacts 11 are disposed adjacent to the second chip edge 152, and the second chip contacts 12 are disposed adjacent to the third chip edge 153. The first leads 21 are closer to one of the first chip contacts 11 closest to the first chip edge 151 than the second leads 22; the third lead 23 is closer to one of the second chip contacts 12 closest to the first chip edge 151 than the fourth lead 24.

In one embodiment, the substrate 201 further includes a first blank area B1 and a second blank area B2. The first blank area B1 is disposed on the extension line of the first straight line 111, the second blank area B2 is disposed on the extension line of the second straight line 121, and the first blank area B1 and the second blank area B2 do not have a pin therein. The width of the first blank area B1 is greater than twice the width of the first chip contact 11, and the width of the second blank area B2 is greater than twice the width of the second chip contact 12.

In one embodiment, the substrate 201 further includes a plurality of fifth leads 25 and a plurality of sixth leads 26, wherein the fifth leads 25 are disposed adjacent to the second edge of the opening 2011 and correspond to the second chip edge 152, and the sixth leads 26 are disposed adjacent to the third edge of the opening 2011 and correspond to the third chip edge 153. The fifth leads 25 are parallel to each other, and the extending direction of the fifth leads 25 is perpendicular to the second chip edge 152. The sixth leads 26 are parallel to each other, and the extending direction of the sixth leads 26 is perpendicular to the third chip edge 153. The fifth leads 25 are respectively coupled to the central portions of the first chip contacts 11. The sixth pins 26 are respectively coupled to the portions of the second chip contacts 12 near the center. As shown in fig. 2, the leads extending perpendicular to the second chip edge 152 are coupled to the first chip contacts 11 'and the second chip contacts 12' at the middle portion by wire bonding.

Referring to fig. 1, in an embodiment, the substrate 201 further includes a plurality of seventh pins 27, a plurality of eighth pins 28, a plurality of ninth pins 29, and a plurality of tenth pins 20. The seventh lead 27, the eighth lead 28, the ninth lead 29 and the tenth lead 20 are disposed adjacent to the fourth edge of the opening 2011, and correspond to the fourth chip edge 154. The structures of the seventh lead 27, the eighth lead 28, the ninth lead 29 and the tenth lead 20 are similar to the first lead 21, the second lead 22, the third lead 23 and the fourth lead 24, and therefore are not described in detail.

Referring to fig. 2, a chip-on-board module M2 according to a second embodiment of the present invention includes a chip 102 and a substrate 202. The chip 102 comprises a plurality of first chip contacts 11 'and a plurality of second chip contacts 12'. The substrate 202 includes a plurality of first leads 21', a plurality of second leads 22', a plurality of third leads 23', and a plurality of fourth leads 24'. In one embodiment, the first chip contact 11' and the second chip contact 12' are symmetrical to a bisector 19' of the chip 102, and the bisector 19' is perpendicular to the first chip edge 151' of the chip 102. The first chip contact 11' and the second chip contact 12' are both arranged adjacent to the bisector 19 '. The first leads 21 'are closer to one of the first chip contacts 11' closest to the first chip edge 151 'than to the second leads 22'. The third leads 23 'are closer to one of the second chip contacts 12' that is closest to the first chip edge 151 'than to the fourth leads 24'.

In one embodiment, the substrate 202 further includes a blank region B without leads. The first chip contacts 11 'are arranged along a first line 111' and the second chip contacts 12 'are arranged along a second line 121'. The extension lines of the first straight line 111 'and the second straight line 121' pass through the blank area B, and the blank area B is located between the first lead 21 'and the third lead 23'. The width of the blank region B is greater than the distance between the first straight line 111 'and the second straight line 121'.

Although the present invention has been described with reference to particular preferred embodiments, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. A chip-on-board module, comprising:

a chip including a plurality of chip contacts; and

the substrate comprises a plurality of first pins and a plurality of second pins, wherein the plurality of first pins and the plurality of second pins are respectively coupled with the plurality of chip contacts of the part, the plurality of first pins are arranged along a first axis, the plurality of second pins are arranged along a second axis, a first axis included angle is formed between the first axis and the second axis, and the first axis included angle is between 100 and 170 degrees.

2. The chip-on-board module of claim 1, wherein the first plurality of leads and the second plurality of leads simultaneously correspond to a first chip edge of the chip, and the first plurality of leads and the second plurality of leads are configured to be respectively coupled to the plurality of chip contacts disposed relatively close to the first chip edge.

3. The chip-on-board module of claim 2, wherein each of the first leads has a first lead inclination angle with respect to the first chip edge, the first lead inclination angle is between 20 ° and 70 °, and each of the second leads has a second lead inclination angle with respect to the first chip edge, the second lead inclination angle is between 20 ° and 70 °.

4. The chip-on-board module of claim 3, wherein the first pin angle is equal to the second pin angle.

5. The chip-on-board module of claim 3, wherein the first axis is parallel to the first chip edge.

6. The chip-on-board module of claim 3, wherein the substrate further comprises a plurality of third pins and a plurality of fourth pins, the plurality of third pins and the plurality of fourth pins are respectively coupled to the plurality of chip contacts of the portion, the plurality of third pins and the plurality of fourth pins simultaneously correspond to the first chip edge of the chip, each third pin has a third pin inclination with the first chip edge, each fourth pin has a fourth pin inclination with the first chip edge, the third pin inclination is different from the first pin inclination and the second pin inclination, and the fourth pin inclination is different from the first pin inclination and the second pin inclination.

7. The chip-on-board module of claim 6, wherein the third plurality of leads are aligned along a third axis, the fourth plurality of leads are aligned along a fourth axis, and the third axis and the fourth axis have a second clip angle therebetween, the second clip angle being between 100 ° and 170 °.

8. The chip-on-board module of claim 7, wherein the third pin angle of inclination is equal to the fourth pin angle of inclination, the first axis is parallel to the first chip edge, and the third axis is parallel to the first chip edge.

9. The chip-on-board module of claim 7, wherein the second and fourth axes are symmetric to an bisector of the chip, and the plurality of bisectors are perpendicular to the first chip edge.

10. The chip-on-board module of claim 7, wherein the plurality of chip contacts includes a plurality of first chip contacts and a plurality of second chip contacts, the plurality of first chip contacts being arranged along a first line, the plurality of second chip contacts being arranged along a second line, the chip including a second chip edge and a third chip edge, the second chip edge being perpendicular to the first chip edge, the third chip edge being perpendicular to the first chip edge, the first line being parallel to the second chip edge, the second line being parallel to the third chip edge, the plurality of first pins and the plurality of second pins respectively coupling a portion of the plurality of first chip contacts, the plurality of third pins and the plurality of fourth pins respectively coupling a portion of the plurality of second chip contacts.

11. The chip-on-board module of claim 10, wherein the first plurality of chip contacts and the second plurality of chip contacts are symmetric about an bisector of the chip, the bisector is perpendicular to the first chip edge, the first plurality of chip contacts and the second plurality of chip contacts are each disposed adjacent to the bisector, the first plurality of pins are closer to the first plurality of chip contacts relative to the second plurality of pins, and the third plurality of pins are closer to the second plurality of chip contacts relative to the fourth plurality of pins.

12. The chip-on-board module of claim 11, wherein the substrate further comprises a blank area without pins, the extension lines of the first straight line and the second straight line pass through the blank area, the blank area is located between the first pins and the third pins, and the width of the blank area is greater than the distance between the first straight line and the second straight line.

13. The chip-on-board module of claim 10, wherein the first plurality of chip contacts is adjacent the second chip edge, the second plurality of chip contacts is adjacent the third chip edge, the first plurality of pins are closer to the first plurality of chip contacts than the second plurality of pins, and the third plurality of pins are closer to the second plurality of chip contacts than the fourth plurality of pins.

14. The chip-on-board module of claim 13, wherein the substrate further comprises a first blank area and a second blank area, the first blank area is located on the extension of the first straight line, the second blank area is located on the extension of the second straight line, neither of the first blank area nor the second blank area has leads therein, the width of the first blank area is greater than twice the width of the first chip contact, and the width of the second blank area is greater than twice the width of the second chip contact.