CN115775583A - Programming dependent biasing of unselected sub-blocks - Google Patents

Abstract

An apparatus includes a control circuit configured to be connected to a first wordline of a first vertical sub-block and a second wordline of a second vertical sub-block. The first vertical sub-block and the second vertical sub-block include memory cells connected in series in NAND strings, each NAND string including memory cells coupled to a first word line in series with memory cells connected to a second word line. The control circuit is configured to program or sense the memory cells along a selected first word line of the first vertical sub-block while applying a first voltage to a second word line connected to the programmed memory cells and applying a second voltage to a second word line connected to the unprogrammed memory cells.

Description

Programming dependent biasing of unselected sub-blocks

Background

Semiconductor memories are widely used in a variety of electronic devices such as cellular telephones, digital cameras, personal digital assistants, medical electronics, mobile computing devices, servers, solid state drives, non-mobile computing devices, and other devices. The semiconductor memory may include a nonvolatile memory or a volatile memory. Non-volatile memory allows information to be stored and retained even when the non-volatile memory is not connected to a power source (e.g., a battery).

One type of non-volatile memory has a string of non-volatile memory cells with a select transistor at each end of the string. Typically, such strings are referred to as NAND strings. A NAND string may have a drain-side select transistor at one end that connects the string to a bit line. A NAND string may have a source side select transistor at one end that connects the string to a source line. The non-volatile memory cells may also be referred to as non-volatile memory cell transistors, where the channels of the non-volatile memory cell transistors are collectively referred to as a NAND string channel.

Drawings

Like numbered elements refer to common features in different figures.

FIG. 1 is a functional block diagram of a memory device.

Fig. 2A-2B are block diagrams depicting an implementation of a memory system.

Figure 3 is a perspective view of a portion of one embodiment of a monolithic three-dimensional memory structure.

FIG. 4A is a block diagram of a memory structure having two planes.

FIG. 4B depicts a top view of a portion of a block of memory cells.

Fig. 4C depicts a stacked embodiment, showing a cross-sectional view along line AA of fig. 4B.

Fig. 4D depicts an alternative view of the select gate layer and the word line layer of stack 435 of fig. 4C.

Fig. 4E depicts a view of region 445 of fig. 4C.

FIG. 4F is a schematic of a plurality of NAND strings, showing a plurality of horizontal sub-blocks.

FIG. 4G is a schematic of a plurality of NAND strings, showing one horizontal sub-block.

FIG. 4H is a schematic of a NAND string extending through multiple vertical sub-blocks.

FIG. 5 illustrates exemplary threshold voltage distributions for the memory array when each memory cell stores three bits of data.

Fig. 6A-6B illustrate examples of connected sub-blocks and corresponding biasing schemes.

Fig. 7A to 7D illustrate a method including applying different voltages on different word lines of an unselected sub-block.

Fig. 8A to 8C illustrate a method of finding a boundary between a programmed part and an unprogrammed part of an open sub-block.

FIG. 9 is an exemplary timing diagram for programming memory cells along a selected word line.

FIG. 10 is an exemplary timing diagram for sensing memory cells along a selected word line.

Detailed Description

Techniques are provided for accessing word lines in a selected vertical sub-block, the word lines connected to one or more unselected sub-blocks, such that the word lines of the unselected sub-blocks receive different voltages depending on whether the word lines are connected to programmed or unprogrammed memory cells. The voltage applied to the word lines of the unselected sub-blocks connected to the un-programmed (erased) memory cells may be lower than the voltage applied to the programmed memory cells of the unselected sub-blocks, which may be lower than the voltage applied to the unselected memory cells of the selected sub-block. Before biasing the word lines of the unselected sub-blocks, the boundary between the programmed and unprogrammed portions of the sub-blocks may be looked up (e.g., from control information or by searching the word lines of the unselected sub-blocks). The word lines on either side of the boundary are biased at different voltages (e.g., a lower voltage is applied on the word line on the unprogrammed side, a higher voltage is applied on the word line on the programmed side).

In some memory structures, the NAND strings are located in blocks that are divided into vertical sub-blocks. In one implementation, the NAND string passes vertically through a stack of alternating horizontal conductive layers and horizontal dielectric layers. In one implementation, the stack includes a hierarchy (also referred to as a vertical sub-block). Thus, each NAND string in the block resides in multiple vertical sub-blocks. In one embodiment, there are two such connected vertical sub-blocks. In one embodiment, there are at least three vertical sub-blocks.

In one implementation, the different vertical sub-blocks may be considered as separate cells for erase/programming purposes. For example, the data in different vertical sub-blocks may be logically unrelated such that connected sub-blocks (sub-blocks connected by a shared NAND string) may be programmed and erased at different times. Memory cells in one vertical sub-block may be independently erased while valid data remains in other connected vertical sub-blocks. The memory cells in the erased vertical sub-block may then be programmed while the valid data remains in the other vertical sub-blocks. Thus, different connected sub-blocks may have different numbers of write-erase cycles. The data in one vertical sub-block may remain for a period of time during which the connected vertical sub-block is repeatedly written and erased, which may cause the data to be severely disturbed. Because valid data is located in other vertical sub-blocks, there are technical challenges to programming the memory cells in the selected vertical sub-block. This can be particularly challenging in certain memory systems (e.g., it can be more challenging in memory cells that store more than one bit of data per cell).

In one implementation, while accessing a selected word line in a selected vertical sub-block, an overdrive voltage is applied to some memory cells and a bypass voltage is applied to other memory cells connected to one or more unselected vertical sub-blocks of the selected vertical sub-block. An overdrive voltage is defined herein as a voltage having a magnitude such that when the overdrive voltage is applied to the control gate of a memory cell, the memory cell will operate (e.g., conduct current or "turn on") as a pass gate regardless of whether the memory cell is in a programmed state or an erased state. A bypass voltage is defined herein as a voltage having a magnitude such that when the bypass voltage is applied to the control gate of a memory cell, the memory cell will operate (e.g., conduct current or "turn on") as a pass gate if the memory cell is in an erased state, but for at least one programmed state, the memory cell will not operate as a pass gate. The overdrive voltage applied to the memory cells in the unselected vertical sub-blocks may be different from (e.g., less than) the overdrive voltage applied to the memory cells in the selected vertical sub-block. The bypass voltage applied to the memory cells in the unselected vertical sub-block may be different from (e.g., less than) the bypass voltage applied to the memory cells in the selected vertical sub-block.

Fig. 1-4H depict examples of memory systems that may be used to implement the techniques presented herein. FIG. 1 is a functional block diagram of an exemplary memory system 100. The components depicted in fig. 1 are circuits. The memory system 100 includes one or more memory dies 108. The one or more memory dies 108 may be full memory dies or partial memory dies. In one embodiment, each memory die 108 includes a memory structure 126, control circuitry 110, and read/write circuits 128. The memory structure 126 is addressable by word lines via a row decoder 124 and by bit lines via a column decoder 132. The read/write/erase circuitry 128 includes multiple sense blocks 150 that include SB1, SB2, SB, SBp (sensing circuitry) and allows a page of memory cells to be read or programmed in parallel. Also, many strings of memory cells may be erased in parallel.

In some systems, the controller 122 is included in the same package (e.g., a removable storage card) as the one or more memory dies 108. However, in other systems, the controller may be separate from the memory die 108. In some embodiments, the controller will be located on a different die than the memory die 108. In some embodiments, one controller 122 will communicate with multiple memory dies 108. In other embodiments, each memory die 108 has its own controller. Commands and data are transferred between the host 140 and the controller 122 via the data bus 120, and between the controller 122 and the one or more memory dies 108 via the lines 118. In one embodiment, the memory die 108 includes a set of input and/or output (I/O) pins connected to the lines 118.

The control circuitry 110 cooperates with the read/write circuits 128 to perform memory operations (e.g., write, read, erase, etc.) on the memory structures 126 and includes a state machine 112, an on-chip address decoder 114 and power control circuitry 116. In one embodiment, the control circuit 110 includes buffers such as registers, ROM fuses, and other storage devices for storing default values such as base voltage and other parameters.

The on-chip address decoder 114 provides an address interface between that used by the host 140 or controller 122 to the hardware address used by the decoder 124 and decoder 132. Power control circuit 116 controls the power and voltages supplied to the word lines, bit lines, and select lines during memory operations. In one embodiment, power control circuit 116 includes a voltage circuit. The power control circuit 116 may include a charge pump for generating the voltage. The sense block includes a bit line driver. In one embodiment, the power control circuit 116 executes under the control of the state machine 112.

The state machine 112 and/or controller 122 (or equivalent functional circuitry) in combination with all or a subset of the other circuitry depicted in fig. 1 may be considered control circuitry that performs the various functions described herein.

The control circuitry may comprise hardware only or a combination of hardware and software, including firmware. For example, a controller programmed by firmware to perform the functions described herein is one example of a control circuit.

The control circuitry may include a processor, PGA (programmable gate array), FPGA (field programmable gate array), ASIC (application specific integrated circuit), integrated circuit, or other type of circuitry.

The controller 122 (which in one embodiment is circuitry) may include one or more processors 122c, ROM122a, RAM122b, memory Interface (MI) 122d, and Host Interface (HI) 122e (on-chip or off-chip), all interconnected. The storage devices (ROM 122a, RAM122 b) store code (software) such as a set of instructions (including firmware), and the one or more processors 122c are operable to execute the set of instructions to provide the functionality described herein. Alternatively or in addition, the one or more processors 122c may access code from a storage device in a memory structure, such as a reserved area of memory cells connected to one or more word lines. The RAM122b may be used to store data for the controller 122, including cache program data (discussed below). The memory interface 122d, which is in communication with the ROM122a, RAM122b, and processor 122c, is circuitry that provides an electrical interface between the controller 122 and the one or more memory dies 108. For example, the memory interface 122d may change the format or timing of signals, provide buffers, isolate from surges, latch I/O, and so forth. The one or more processors 122c may place commands to the control circuit 110 (or another component of the memory die 108) through the memory interface 122 d. The host interface 122e provides an electrical interface with the host 140 data bus 120 to receive commands, addresses, and/or data from the host 140 to provide data and/or status to the host 140.

In one implementation, the memory structure 126 includes a three-dimensional memory array of non-volatile memory cells in which multiple memory levels are formed above a single substrate, such as a wafer. The memory structure may include any type of non-volatile memory that is monolithically formed in one or more physical layers of a memory cell array, having an active region disposed above a silicon (or other type) substrate. In one example, a non-volatile memory cell includes a vertical NAND string having a charge trapping material.

In another embodiment, memory structure 126 includes a two-dimensional memory array of non-volatile memory cells. In one example, the non-volatile memory cells are NAND flash memory cells that utilize floating gates. Other types of memory cells (e.g., NOR type flash memory) may also be used. The exact type of memory array architecture or memory cells included in memory structure 126 is not limited to the examples described above.

FIG. 2A is a block diagram of an exemplary memory system 100 depicting more details of one embodiment of the controller 122. The controller in FIG. 2A is a flash memory controller, but it should be noted that the non-volatile memory die 108 is not limited to flash memory. Thus, the controller 122 is not limited to the example of a flash memory controller. As used herein, a flash memory controller is a device that manages data stored on a flash memory and communicates with a host, such as a computer or electronic device. The flash memory controller may have various functions in addition to the specific functions described herein. For example, the flash memory controller may format the flash memory to ensure that the memory is functioning properly, map out bad flash memory cells, and allocate spare memory cells to replace future failed cells. Some of the spare cells may be used to house firmware to operate the flash memory controller and implement other features. In operation, when a host needs to read data from or write data to the flash memory, it will communicate with the flash memory controller. If the host provides a logical address to read/write data, the flash memory controller may translate the logical address received from the host to a physical address in the flash memory. (alternatively, the host may provide the physical address). The flash memory controller may also perform various memory management functions such as, but not limited to, wear leveling (allocating writes to avoid wearing a particular memory block that would otherwise be repeatedly written) and garbage collection (moving only valid data pages to a new block after the block is full, so the entire block can be erased and re-used).

The interface between the controller 122 and the non-volatile memory die 108 may be any suitable flash interface, such as the switching modes 200, 400, or 800. In one implementation, the memory system 100 may be a card-based system, such as a Secure Digital (SD) or micro-SD card. In an alternative embodiment, the memory system 100 may be part of an embedded memory system. For example, the flash memory may be embedded within the host. In other examples, the memory system 100 may be in the form of a Solid State Drive (SSD).

In some embodiments, the non-volatile memory system 100 includes a single channel between the controller 122 and the non-volatile memory die 108, and the subject matter described herein is not limited to having a single memory channel. For example, in some memory system architectures, there are 2, 4, 8, or more channels between the controller and the memory die, depending on the capabilities of the controller. In any of the embodiments described herein, even though a single channel is shown in the figures, there may be more than a single channel between the controller and the memory die.

As depicted in fig. 2A, the controller 122 includes a front-end module 208 that interacts with a host, a back-end module 210 that interacts with one or more non-volatile memory dies 108, and various other modules that perform functions that will now be described in detail.

The components of the controller 122 depicted in fig. 2A may take the form of, for example, packaged-function hardware units (e.g., circuits) designed for use with other components, portions of program code (e.g., software or firmware) that can be executed by a (micro) processor or processing circuit that typically performs the specified function of the associated function, or separate hardware or software components that interact with a larger system. For example, each module may include an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA), a circuit, a digital logic circuit, an analog circuit, a discrete circuit, a combination of gates or any other type of hardware, or a combination thereof. Alternatively or in addition, each module may include software stored in a processor readable device (e.g., memory) to program the processor to cause the controller 122 to perform the functions described herein. The architecture depicted in fig. 2A is one exemplary implementation that may (or may not) use the components (i.e., RAM, ROM, processor, interfaces) of the controller 122 depicted in fig. 1.

Referring again to the modules of the controller 122, the buffer manager/bus controller 214 manages buffers in a Random Access Memory (RAM) 216 and controls internal bus arbitration by the controller 122. A Read Only Memory (ROM) 218 stores system boot code. Although shown in fig. 2A as being located separately from the controller 122, in other implementations, one or both of the RAM216 and the ROM 218 may be located within the controller. In still other embodiments, portions of the RAM and ROM may be located within the controller 122 and external to the controller. Further, in some implementations, the controller 122, the RAM216, and the ROM 218 may be located on separate semiconductor dies.

The front end module 208 includes a host interface 220 and a physical layer interface (PHY) 222 that provides an electrical interface with a host or a next level memory controller. The type of host interface 220 may be selected depending on the type of memory used. Examples of host interface 220 include, but are not limited to, SATA Express, SAS, fibre channel, USB, PCIe, and NVMe. Host interface 220 generally facilitates the transfer of data, control signals, and timing signals.

The back end module 210 includes an Error Correction Code (ECC) engine 224 that encodes data bytes received from the host, and decodes and error corrects data bytes read from the non-volatile memory. The command sequencer 226 generates command sequences, such as a program command sequence and an erase command sequence, for transmission to the non-volatile memory die 108. A RAID (redundant array of independent die) module 228 manages the generation of RAID parity and the recovery of failed data. RAID parity may be used as an additional level of integrity protection for data written into the non-volatile memory system 100. In some cases, RAID module 228 may be part of ECC engine 224. It should be noted that RAID parity may be added as an additional die or dies, as the common name implies, but may also be added within existing dies, e.g., as an additional plane, or an additional block, or an additional WL within a block. The memory interface 230 provides command sequences to the non-volatile memory die 108 and receives status information from the non-volatile memory die 108. In one embodiment, memory interface 230 may be a Double Data Rate (DDR) interface, such as a switched mode 200, 400, or 800 interface. Flash control layer 232 controls the overall operation of back end module 210.

Additional components of the system 100 shown in FIG. 2A include a media management layer 238 that performs wear leveling of the memory cells of the non-volatile memory die 108. The system 100 also includes other discrete components 240, such as an external electrical interface, external RAM, resistors, capacitors, or other components that may interface with the controller 122. In alternative embodiments, one or more of the physical layer interface 222, RAID module 228, media management layer 238, and buffer management/bus controller 214 are optional components that are not required in the controller 122.

A Flash Translation Layer (FTL) or a Media Management Layer (MML) 238 may be integrated as part of flash management that can handle flash errors and interface with a host. In particular, the MML may be a module in flash management and may be responsible for the inside of NAND management. In particular, the MML 238 may include an algorithm in the memory device firmware that converts writes from the host to writes to the memory 126 of the memory die 108. MML 238 may be required because: 1) Memory may have limited endurance; 2) The memory 126 may be written to only a plurality of pages; and/or 3) memory 126 may not be written to unless erased as a block (or in some embodiments as a layer within a block). MML 238 understands these potential limitations of memory 126 that may not be visible to the host. Accordingly, MML 238 attempts to convert writes from the host to writes into memory 126.

The controller 122 may interface with one or more memory dies 108. In one embodiment, the controller 122 and the plurality of memory dies (together comprising the nonvolatile storage system 100) implement a Solid State Drive (SSD) that can emulate, replace, or replace hard disk drive usage within a host (e.g., a NAS device), in a laptop computer, in a tablet computer, in a server, or the like. Additionally, SSDs need not operate as hard disk drives.

Some embodiments of the non-volatile storage system will include a memory die 108 connected to a controller 122. However, other embodiments may include multiple memory dies 108 in communication with one or more controllers 122. In one example, a plurality of memory dies may be grouped into a group of memory packages. Each memory package includes one or more memory dies in communication with the controller 122. In one embodiment, a memory package includes a printed circuit board (or similar structure) on which one or more memory dies are mounted. In some embodiments, a memory package may include a molding material to encapsulate a memory die of the memory package. In some embodiments, the controller 122 is physically separate from any memory enclosures.

In one embodiment, the control circuitry (e.g., control circuitry 110) is formed on a first die, referred to as a control die, and the memory array (e.g., memory structure 126) is formed on a second die, referred to as a memory die. For example, some or all of the control circuitry associated with the memory (e.g., control circuitry 110, row decoder 124, column decoder 132, and read/write circuits 128) may be formed on the same control die. The control die may be bonded to one or more corresponding memory dies to form an integrated memory assembly. The control die and the memory die may have bond pads arranged for electrical connection to each other. The bond pads of the control die and the memory die may be aligned and bonded together by any of a variety of bonding techniques, depending in part on the bond pad size and bond pad spacing (i.e., bond pad pitch). In some embodiments, the bond pads are bonded directly to each other without solder or other additional material in a so-called Cu-Cu bonding process. In some examples, the dies are bonded in a one-to-one arrangement (e.g., one control die to one memory die). In some examples, there may be more than one control die and/or more than one memory die in the integrated memory assembly. In some embodiments, an integrated memory assembly includes a plurality of control dies and/or a stack of a plurality of memory dies. In some embodiments, the control die is connected to or otherwise in communication with a memory controller. For example, a memory controller may receive data to be programmed into a memory array. The memory controller forwards the data to the control die so that the control die can program the data into the memory array on the memory die.

Fig. 2B shows an alternative arrangement to that of fig. 2A, which may be implemented using wafer-to-wafer bonding to provide bonded die pairs. FIG. 2B depicts a functional block diagram of one embodiment of an integrated memory component 307. One or more integrated memory components 307 may be used in a memory package in memory system 100. The integrated memory assembly 307 includes two types of semiconductor dies (or more succinctly, "dies"). Memory die 301 includes a memory array 326 (memory structure 326, which may be any suitable memory as described with respect to memory structure 126). The memory array 326 may include non-volatile memory cells.

The control die 311 includes column control circuitry 364, row control circuitry 320, and system control logic 360 (including state machine 312, power control module 316, storage 366, and memory interface 368). In some embodiments, control die 311 is configured to connect to memory array 326 in memory die 301. Fig. 2B shows an example of peripheral circuitry, including control circuitry formed in peripheral circuitry or control die 311, which is coupled to memory array 326 formed in memory die 301. System control logic 360, row control circuitry 320, and column control circuitry 364 are located in control die 311. In some embodiments, all or a portion of column control circuitry 364 and all or a portion of row control circuitry 320 are located on memory die 301. In some embodiments, some of the circuitry in system control logic 360 is located on memory die 301.

System control logic 360, row control circuitry 320, and column control circuitry 364 may be formed from conventional processes (e.g., CMOS processes) such that adding elements and functions more commonly found on memory controller 102, such as ECC, may require few or no additional process steps (i.e., the same process steps used to manufacture controller 102 may also be used to manufacture system control logic 360, row control circuitry 320, and column control circuitry 364). Thus, although removing such circuitry in a die (such as memory die 301) may reduce the number of steps required to manufacture such a die, adding such circuitry to a die (such as control die 311) may not require many additional process steps.

FIG. 2B shows column control circuitry 364 on the control die 311, including the sense block 350, coupled to the memory array 326 on the memory die 301 by an electrical path 370. For example, electrical path 370 may provide an electrical connection between column decoder 332, driver circuit 372, block selector 373, and bit lines of memory array (or memory structure) 326. Electrical paths may extend from column control circuitry 364 in control die 311 through pads on control die 311 that are bonded to corresponding pads of memory die 301 that are connected to bit lines of memory structure 326. Each bit line of memory structure 326 may have a corresponding one of electrical paths 370, including a pair of bond pads connected to column control circuitry 364. Similarly, row control circuitry 320 (including row decoder 324, array driver 374, and block selector 376) is coupled to memory array 326 by electrical path 308. Each of electrical paths 308 may correspond to a word line, a dummy word line, or a select gate line. Additional electrical paths may also be provided between the control die 311 and the memory die 301.

In some embodiments, there is more than one control die 311 and/or more than one memory die 301 in integrated memory assembly 307. In some embodiments, integrated memory component 307 includes a stack of multiple control die 311 and multiple memory die 301. In some embodiments, each control die 311 is attached (e.g., bonded) to at least one of the memory dies 301.

The exact type of memory array architecture or memory cells included in memory structure 326 is not limited to the examples described above. Many different types of memory array architectures or memory cell technologies may be used to form memory structure 326. No particular non-volatile memory technology is required to implement the new embodiments claimed herein. Other examples of technologies suitable for the memory cells of memory structure 326 include ReRAM memory, magnetoresistive memory (e.g., MRAM, spin transfer torque MRAM, spin orbit torque MRAM), phase change memory (e.g., PCM), and the like. Examples of suitable techniques for the architecture of memory structure 326 include two-dimensional arrays, three-dimensional arrays, cross-point arrays, stacked two-dimensional arrays, vertical bit line arrays, and the like.

One example of ReRAM, or PCMRAM, cross-point memory includes reversible resistance-switching elements arranged in a cross-point array accessed by X-lines and Y-lines (e.g., word lines and bit lines). In another embodiment, the memory cell may include a conductive bridge memory element. The conductive bridge memory elements may also be referred to as programmable metallization cells. Based on the physical relocation of ions within the solid electrolyte, the conductive bridge memory element may function as a state-change element. In some cases, a conductive bridge memory element may include two solid metal electrodes, one being relatively inert (e.g., tungsten) and the other being electrochemically active (e.g., silver or copper), with a thin film of solid electrolyte between the two electrodes. As temperature increases, the mobility of the ions also increases, which results in a lower programming threshold for the conductive bridge memory cell. Thus, the conductive bridge memory element can have a wide range of programming thresholds over the entire temperature range.

Magnetoresistive memories (MRAMs) store data through magnetic storage elements. The element is formed from two ferromagnetic plates, each of which can be kept magnetized, separated by a thin insulating layer. One of the two plates is a permanent magnet set to a particular polarity; the magnetization of the other plate can be changed to match the magnetization of the external magnetic field to store the memory. The memory device is constructed from a grid of such memory cells. In one embodiment for programming, each memory cell is located between a pair of write lines arranged at right angles to each other, parallel to the cell, one above the cell and one below the cell. When a current is passed through them, an induced magnetic field is generated.

Phase Change Memories (PCMs) take advantage of the unique properties of chalcogenide glasses. One embodiment uses a GeTe-Sb2Te3 superlattice to achieve a non-thermal phase change by simply changing the coordination state of the germanium atoms with a laser pulse (or a light pulse from another source). Thus, the programmed dose is a laser pulse. The memory cells may be inhibited by preventing the memory cells from receiving light. It should be noted that the use of "pulses" in this document does not require square pulses, but includes (continuous or discontinuous) vibrations or pulse trains of sound, current, voltage light or other waves.

Those of ordinary skill in the art will recognize that the techniques described herein are not limited to a single particular memory structure, but encompass many related memory structures within the spirit and scope of the techniques described herein and as understood by those of ordinary skill in the art.

FIG. 3 is a perspective view of a portion of one exemplary embodiment of a monolithic three dimensional memory array that may include memory structure 126 or 326, which includes a plurality of non-volatile memory cells. For example, FIG. 3 shows a portion of one block of memory. The depicted structure includes a set of bit lines BL located over a stack of alternating dielectric and conductive layers. For example, one of the dielectric layers is labeled D and one of the conductive layers (also referred to as a wordline layer) is labeled W. The number of alternating dielectric and conductive layers may vary based on the particular implementation requirements. One set of embodiments includes between 108 and 300 alternating dielectric and conductive layers. One example embodiment includes 96 data word line layers, 8 select layers, 6 dummy word line layers, and 110 dielectric layers. More or less than 108 to 300 layers may also be used. The data word line layer has data memory cells. The dummy word line layer has dummy memory cells. As will be explained below, the alternating dielectric and conductive layers are divided into four "fingers" by local interconnects LI. Fig. 3 shows two fingers and two local interconnects LI. The source line layer SL is located below the alternating dielectric and word line layers. A memory hole is formed in the stack of alternating dielectric and conductive layers. For example, one of these memory holes is labeled MH. It should be noted that in fig. 3, the dielectric layers are depicted as a perspective view so that the reader can see the memory holes positioned in the stack of alternating dielectric and conductive layers. In one implementation, a NAND string is formed by filling a memory hole with a material including a charge trapping material to form a vertical column of memory cells. Each memory cell may store one or more bits of data. More details of a three-dimensional monolithic memory array including memory structure 126 or 326 are provided below with respect to fig. 4A-4H.

One of the local interconnects LI divides the block into two horizontal sub-blocks HSB0, HSB1. The block includes a plurality of vertical sub-blocks VSB0, VSB1, VSB2. The vertical sub-blocks VSB0, VSB1, VSB2 may also be referred to as "levels". In one embodiment, each vertical sub-block extends across the block. Each horizontal sub-block HSB0, HSB1 in the block is part of a vertical sub-block VSB 0. Likewise, each horizontal sub-block HSB0, HSB1 in the block is part of the vertical sub-block VSB 1. Likewise, each horizontal sub-block HSB0, HSB1 in the block is part of the vertical sub-block VSB2. For purposes of discussion, the vertical sub-block VSB0 will be referred to as a lower vertical sub-block, the vertical sub-block VSB1 will be referred to as a middle vertical sub-block, and VSB2 will be referred to as an upper vertical sub-block. In one implementation, there are two vertical sub-blocks in a block. There may be four or more vertical sub-blocks in a block.

Memory operations for the vertical sub-blocks may be performed on memory cells in one or more horizontal sub-blocks. For example, the programming operation of the memory cells in the vertical subblock VSB0 may include: programming memory cells in horizontal sub-block HSB0, but not in horizontal sub-block HSB 1; programming memory cells in horizontal sub-block HSB1, but not in horizontal sub-block HSB 0; or to program memory cells in both horizontal sub-block HSB0 and horizontal sub-block HSB1.

In one embodiment, the different vertical sub-blocks VSB0, VSB1, VSB2 are considered as separate units for erasure/programming purposes. For example, memory cells in one vertical sub-block may be erased while valid data is retained in other vertical sub-blocks. The memory cells in the erased vertical sub-block may then be programmed while valid data remains in the other vertical sub-blocks. In some cases, the memory cells in the middle vertical sub-block VSB1 are programmed when valid data exists in the lower vertical sub-block VSB0 and/or the upper vertical sub-block VSB2.

FIG. 4A is a block diagram illustrating an exemplary organization of a memory structure 126 or 326, which is divided into two planes 302 and 304. Then, each plane is divided into M blocks. In one example, each plane has about 2000 blocks. However, a different number of blocks and planes may be used. In one implementation, the block of memory cells is the unit of erase. That is, all memory cells of a block are erased together. In other embodiments, the memory cells may be grouped into blocks for other reasons, such as to organize the memory structure 126 to enable signaling and selection circuitry. In some implementations, a block represents a group of connected memory cells because the memory cells of the block share a common set of word lines.

Fig. 4B-4F depict an exemplary three-dimensional ("3D") NAND structure, which corresponds to the structure of fig. 3, and which may be used to implement the memory structure 126 of fig. 2A or the memory structure 326 of fig. 2B. Fig. 4B is a block diagram depicting a top view of a portion of one block from memory structure 126. The portion of the block depicted in fig. 4B corresponds to portion 306 in block 2 of fig. 4A. As can be seen in FIG. 4B, the blocks depicted in FIG. 4B extend in the direction of 332. In one implementation, the memory array has a number of layers; however, fig. 4B shows only the top layer.

FIG. 4B depicts a plurality of circles representing vertical columns. Each of these vertical columns includes a plurality of select transistors (also referred to as select gates or select gates) and a plurality of memory cells. In one embodiment, one NAND string is implemented per vertical column. For example, fig. 4B depicts vertical columns 422, 432, 442, and 452. Vertical columns 422 implement NAND strings 482. Vertical column 432 implements NAND string 484. Vertical column 442 implements NAND string 486. Vertical column 452 implements NAND string 488. More details of these vertical columns are provided below. Since the block depicted in fig. 4B extends in the direction of arrow 333, the block includes more vertical columns than depicted in fig. 4B.

Fig. 4B also depicts a set of bitlines 415, including bitlines 411, 412, 413, 414, an. Fig. 4B shows twenty-four bit lines, as only a portion of the block is depicted. It is contemplated that more than twenty-four bit lines are connected to vertical columns of the block. Each circle representing a vertical column has an "x" to indicate that it is connected to a bit line. For example, bit line 414 is connected to vertical columns 422, 432, 442, and 452.

The block depicted in fig. 4B includes a set of local interconnects 402, 404, 406, 408, and 410 that connect the various layers to the source lines below the vertical columns. The local interconnects 402, 404, 406, 408, and 410 also serve to divide each layer of the block into four regions; for example, the top layer depicted in FIG. 4B is divided into regions 420, 430, 440, and 450, which are referred to as fingers. In the layer implementing the block of memory cells, these four regions are referred to as word line fingers, and these regions are separated by local interconnects. In one embodiment, word line fingers on a common level of a block are connected together to form a single word line. In another embodiment, word line fingers on the same level are not connected together. In one exemplary implementation, the bit lines are connected to only one vertical column in each of the regions 420, 430, 440, and 450. In this implementation, each block has sixteen rows of active columns, and each bit line is connected to four rows in each block. In one embodiment, all four rows connected to a common bit line are connected to the same word line (via different word line fingers on the same level connected together); thus, the system uses the source side select line and the drain side select line to select one (or another subset) of the four to be subjected to memory operations (programming, verifying, reading and/or erasing).

Although fig. 4B shows each region having four vertical rows, four regions, and sixteen vertical rows in the block, these exact numbers are exemplary implementations. Other embodiments may include more or fewer regions per block, more or fewer vertical columns of rows per region, and more or fewer vertical columns of rows per block.

Fig. 4B also shows that the vertical columns are staggered. In other embodiments, different interleaving patterns may be used. In some embodiments, the vertical columns are not staggered.

Fig. 4C depicts an embodiment of a stack 435, showing a cross-sectional view along line AA of fig. 4B. In addition to the data word line layers WLL0 to WLL95, two SGD layers (SGD 0, SDG 1), two SGS layers (SGS 0, SGS 1), and six dummy word line layers DWLD0, DWLD1, DWLM0, DWLS0, and DWLS1 are provided. Each NAND string has a drain-side select transistor at the SGD0 level and a drain-side select transistor at the SGD1 level. In operation, the same voltage may be applied to each layer (SGD 0, SGD 1) such that the control terminal of each transistor receives the same voltage. Each NAND string has a source side select transistor at the SGS0 level and a drain side select transistor at the SGS1 level. In operation, the same voltage may be applied to each layer (SGS 0, SGS 1) such that the control terminal of each transistor receives the same voltage. Dielectric layers DL0-DL106 are also depicted.

Columns 432, 434 of memory cells are depicted in the multi-layer stack. The stack includes a substrate 303, an insulating film 250 on the substrate, and a part of the source line SL. A portion of a bit line 414 is also depicted. Note that NAND string 484 is connected to bit line 414. The NAND string 484 has a source terminal 439 at the bottom of the stack and a drain terminal 438 at the top of the stack. The source terminal 439 is connected to a source line SL. A conductive via 441 connects the drain terminal 438 of the NAND string 484 to the bit line 414. Local interconnects 404 and 406 from fig. 4B are also depicted.

The stack 435 is divided into three vertical sub-blocks (VSB 0, VSB1, VSB 2). The vertical sub-blocks VSB0 include WLL0 to WLL31. The lower layers may also be considered part of the vertical sub-block VSB0 (SGS 0, SGS1, DWLS0, DWLS 1). The vertical sub-blocks VSB1 include WLL32 to WLL63. The vertical sub-block VSB2 includes WLL64 to WLL95. The following layers may also be considered part of vertical sub-block VSB2 (SGD 0, SGD1, DWLD0, DWLD 1). Each NAND string has a set of data memory cells in each vertical sub-block. The dummy word line layer DMLM0 is located between the vertical sub-block VSB0 and the vertical sub-block VSB 1. The dummy word line layer DMLM1 is located between the vertical sub-blocks VSB1 and VSB2. The dummy word line layer has dummy memory cells that may be used to electrically isolate a first set of memory cell transistors within the memory string (e.g., corresponding to the vertical sub-block VSB0 word lines WLL 0-WLL 31) from a second set of memory cell transistors within the memory string (e.g., corresponding to the vertical sub-block VSB1 word lines WLL 32-WLL 63) during a memory operation (e.g., an erase operation or a program operation).

In another embodiment, stack 435 is divided into vertical sub-blocks using one or more intermediate bonded transistor layers. The intermediate junction transistor layers that comprise the junction transistors do not necessarily comprise charge storage regions. Thus, the junction transistor is not generally considered a dummy memory cell. Both the pass transistor and the dummy memory cell may be referred to herein as a "non-data transistor". As the term is used herein, a non-data transistor is a transistor on a NAND string, where the transistor is configured to store no user data or system data, or operates in a manner that the transistor is not used to store user data or system data. The word lines connected to the non-data transistors are referred to herein as non-data word lines. Examples of non-data word lines include, but are not limited to, dummy word lines and select lines in the middle junction transistor layer.

The stack 435 may have more than three vertical sub-blocks. For example, the stack 435 may be divided into four, five, or more vertical sub-blocks. Each vertical sub-block includes at least one data memory cell. Additional layers similar to the intermediate dummy word line layer DWLM may be present in order to divide the stack 435 into additional vertical sub-blocks. In one embodiment, the stack has two vertical sub-blocks.

Fig. 4D depicts an alternative view of the SG layer and the word line layer of the stack 435 of fig. 4C. SGD layers SGD0 and SGD0 (drain-side SG layers) each include parallel SG line rows associated with the drain side of a group of NAND strings. For example, SGD0 includes drain side SG regions 420, 430, 440, and 450 consistent with fig. 4B.

Below the SGD layer is a drain side dummy word line layer. In one approach, each dummy word line layer represents a word line and is connected to a group of dummy memory cells at a given height in the stack. For example, DWLD0 includes word line layer regions 451, 453, 455, and 457. Dummy memory cells (also referred to as non-data memory cells) do not store data and cannot store data, while data memory cells are eligible to store data. Furthermore, the Vth of a dummy memory cell is typically fixed at the time of manufacture or may be adjusted periodically, while the Vth of a data memory cell changes more frequently, e.g., during erase and program operations of the data memory cell.

Below the dummy word line layer is a data word line layer. For example, WLL95 includes word line layer regions 471, 472, 473, and 474.

Below the data word line layer is a source side dummy word line layer.

Below the source side dummy word line layer is an SGS layer. SGS layers SGS0 and SGS1 (source side SG layers) each include parallel SG line rows associated with the source side of a set of NAND strings. For example, SGS0 includes source side SG lines 475, 476, 477, and 478. In one approach, each SG line may be independently controlled. Alternatively, these SG lines may be connected and controlled collectively.

Fig. 4E depicts a view of region 445 of fig. 4C. Data memory cell transistors 520 and 521 are located above dummy memory cell transistor 522. Data memory cell transistors 523 and 524 are located below dummy memory cell transistor 522. Multiple layers may be deposited along the Sidewalls (SW) of the memory holes 444 and/or within each word line layer, for example, using atomic layer deposition. For example, each column (e.g., pillar formed of material within a memory hole) may include a blocking oxide/bulk high-k material 470, a charge trapping layer or film 463 (such as SiN or other nitride), a tunneling layer 464, a polysilicon body or channel 465, and a dielectric core 466. The word line layer may include a conductive metal 462 (such as tungsten) as a control gate. For example, control gates 490, 491, 492, 493, and 494 are provided. In this example, all layers except metal are provided in the memory hole. In other approaches, some of the layers may be in the control gate layer. Additional pillars are similarly formed in different memory holes. The pillars may form pillar Active Areas (AA) of the NAND string.

When programming the data memory cell transistor, electrons are stored in a portion of the charge trapping layer associated with the data memory cell transistor. These electrons are attracted from the channel into the charge trapping layer and pass through the tunnel layer. The Vth of the data memory cell transistor increases in proportion to the amount of charge stored. During an erase operation, electrons are returned to the channel.

The non-data transistors (e.g., select transistors, dummy memory cell transistors) may also include a charge trapping layer 463. In fig. 4E, dummy memory cell transistor 522 includes a charge trapping layer 463. Thus, the threshold voltage of at least some of the non-data transistors may also be adjusted by storing or removing electrons from the charge trapping layer 463. It is not necessary that all non-data transistors have an adjustable Vth. For example, the charge trapping layer 463 need not be present in each select transistor.

Each of the memory holes may be filled with a plurality of ring layers including a blocking oxide layer, a charge trapping layer, a tunnel layer, and a channel layer. The core region of each of the memory holes is filled with a body material, and a plurality of ring-shaped layers are located between the core region in each of the memory holes and the WLL.

In some cases, tunneling layer 464 may include multiple layers, such as in an oxide-nitride-oxide configuration.

Fig. 4F is a schematic diagram of a portion of the memory depicted in fig. 3-4E. Fig. 4F shows physical word lines WL0 to WL95 extending across the entire block. The structure of fig. 4F corresponds to portion 306 in block 2 of fig. 4A-4E, including bit lines 411, 412, 413, 414. Within the block, each bit line is connected to four NAND strings. Drain-side select lines SGD0, SGD1, SGD2, and SGD3 are used to determine which of the four NAND strings are connected to an associated bit line. Source side select lines SGS0, SGS1, SGS2 and SGS3 are used to determine which of the four NAND strings is connected to the common source line. It is also contemplated that the block is divided into four horizontal sub-blocks HSB0, HSB1, HSB2, and HSB3. Horizontal sub-block HSB0 corresponds to those vertical NAND strings controlled by SGD0 and SGS0, horizontal sub-block HSB1 corresponds to those vertical NAND strings controlled by SGD1 and SGS1, horizontal sub-block HSB2 corresponds to those vertical NAND strings controlled by SGD2 and SGS2, and horizontal sub-block HSB3 corresponds to those vertical NAND strings controlled by SGD3 and SGS 3.

Fig. 4G is a schematic diagram of horizontal sub-block HSB 0. The horizontal sub-blocks HSB1, HSB2 and HSB3 have a similar structure. Fig. 4G shows physical word lines WL0 to WL95 extending across the entire sub-block S0. All NAND strings of sub-block S0 are connected to SGD0 and SGS0. FIG. 4G depicts only six NAND strings 501, 502, 503, 504, 505, and 506; however, the horizontal sub-block HSB0 will have thousands of NAND strings (e.g., 15,000 or more).

FIG. 4G is used to explain the concept of a selected memory cell. Memory operations are operations designed for the purpose of using memory and include one or more of reading data, writing/programming data, erasing memory cells, refreshing data in memory cells, and the like. During any given memory operation, a subset of memory cells will be identified as being subject to one or more portions of the memory operation. These memory cells identified as being subject to a memory operation are referred to as selected memory cells. These memory cells that are not identified as being subject to a memory operation are referred to as unselected memory cells. Depending on the memory architecture, memory type, and memory operation, unselected memory cells may be actively or passively excluded from undergoing memory operations.

As an example of selected memory cells and unselected memory cells, during programming, a group of memory cells that are intended to adopt new electrical characteristics (or other characteristics) to reflect a changed programming state are referred to as selected memory cells, while memory cells that are not intended to adopt new electrical characteristics (or other characteristics) to reflect a changed programming state are referred to as unselected memory cells. In some cases, the unselected memory cells may be connected to the same word line as the selected memory cells. The unselected memory cells may also be connected to a different word line than the selected memory cells. Similarly, in a read process, a group of memory cells to be read is referred to as selected memory cells, and memory cells that are not intended to be read are referred to as unselected memory cells.

To better understand the concept of selected and unselected memory cells, assume that a programming operation is to be performed, and for exemplary purposes only, word line WL94 and horizontal sub-block HSB0 are selected for programming (see fig. 4G). This means that all memory cells connected to WL94 in horizontal sub-blocks HSB1, HSB2, and HSB3 (the other horizontal sub-blocks) are unselected memory cells. Some of the memory cells connected to WL94 in horizontal sub-block HSB0 are selected memory cells and some of the memory cells connected to WL94 in horizontal sub-block HSB0 are unselected memory cells, depending on how the programming operation is performed and how the data pattern is programmed. For example, those memory cells that are to remain in the erased state S0 will be unselected memory cells because their programmed states do not change in order to store the desired data pattern, while those memory cells that are intended to adopt new electrical (or other) characteristics to reflect the changed programmed states (e.g., programmed to states S1-S7) are selected memory cells. Referring to FIG. 4G, assume for exemplary purposes that memory cells 511 and 514 (which are connected to word line WL 94) remain in the erased state; thus, memory cells 511 and 514 are unselected memory cells (labeled unsel in FIG. 4G). In addition, assume for exemplary purposes that memory cells 510, 512, 513, and 515 (which are connected to word line WL 94) are to be programmed to any of data states S1 through S7; thus, memory cells 510, 512, 513, and 515 are selected memory cells (labeled sel in fig. 4G). Although some memory cells along WL94 may be considered unselected memory cells because these memory cells are for remaining in an erased state, in this case, WL94 may be considered a "selected word line" because selected memory cells 510, 512, 513, and 515 are connected to WL94 and accessed via WL 94.

FIG. 4H is a schematic of a NAND string. NAND string 600 is similar to NAND string 484 of figure 4C, but with intervening junction transistors to separate the vertical sub-blocks. The NAND string 600 includes: a first portion of the NAND string (e.g., corresponding to the vertical sub-block VSB 0), a second portion of the NAND string (e.g., corresponding to the vertical sub-block VSB 1), a third portion of the NAND string (corresponding to the vertical sub-block VSB 2), an intermediate junction transistor (MJT 1) 614 disposed between the first portion of the NAND string and the second portion of the NAND string, and an intermediate junction transistor (MJT 2) 620 disposed between the second portion of the NAND string and the third portion of the NAND string.

The first portion of the NAND string has memory cells 610-612 connected to word lines WLL 0-WLL 31. The second portion of the NAND string has memory cells 616-618 connected to word lines WLL 32-WLL 63. The third portion of the NAND string has memory cells 622-624 connected to word lines WLL 64-WLL 96. Not all of the memory cells of NAND string 600 are depicted in figure 4H. Also included on NAND string 600 are: a first source side select gate transistor 602 connected to SGS0, a second source side select gate transistor 604 connected to SGS1, two dummy memory cell transistors 606, 608 connected to DWLS0 and DWLS1, respectively, two dummy memory cell transistors 626, 628 connected to DWLD0 and DWLD1, respectively, a drain side select gate transistor 630 connected to SGD1, a drain side select gate transistor 632 connected to SGD 0. The drain-side select gate transistor 632 is connected to a Bit Line (BL). The first source side select gate transistor 602 is connected to a Source Line (SL). In one implementation, there is a dummy memory cell transistor on each side of each middle junction transistor 614, 618.

Each intermediate junction transistor 614, 618 may be a programmable transistor (such as a floating gate transistor or a charge trapping transistor), or a non-programmable transistor (such as an NMOS transistor or a PMOS transistor), according to different embodiments. Each intermediate junction transistor 614, 618 may comprise an NMOS transistor without a charge trapping layer between the channel of the NMOS transistor and the gate of the NMOS transistor. In some embodiments, one intermediate junction transistor 614, 618 may comprise a programmable transistor, and the other intermediate junction transistor 614, 618 may comprise a non-programmable transistor. Each intermediate junction transistor 614, 618 may have a transistor channel length that is different from the transistor channel length for the memory cell transistor. The channel length may be greater than any transistor channel length for the memory cell transistor. For example, the channel length may be greater than twice the transistor channel length for the memory cell transistor. Each intermediate junction transistor 614, 618 may electrically isolate memory cell transistors in different vertical sub-blocks when the intermediate junction transistor is set to a non-conductive state.

Although the example memory system of fig. 3-4H is a three-dimensional memory structure including vertical NAND strings with charge-trapping material, other (2D and 3D) memory structures may also be used with the techniques described herein. The different operations (e.g., read, program verify) described below for accessing data in non-volatile memory cells may be applied to one or more of the example memory systems described above with respect to fig. 1-4H.

Typically, the program voltage applied to the control gate (via the selected word line) during a program operation is applied as a series of program pulses. Between the programming pulses is a set of verify pulses to perform the verify. In many implementations, the magnitude of the program pulse is increased with each successive pulse by a predetermined step size.

In one implementation, a group of memory cells selected to be programmed (referred to herein as selected memory cells) are programmed at the same time and all connected to the same word line (selected word line). There may be other memory cells that are not selected for programming (unselected memory cells) also connected to the selected word line. That is, the selected word line will also be connected to memory cells that should be program inhibited. For example, when data is written to a group of memory cells, some memory cells will need to store data associated with the erased state so that these memory cells will not be programmed. In addition, when the memory cells reach their intended target data state, they will be inhibited from further programming. These NAND strings (e.g., unselected NAND strings) have their channels boosted to inhibit programming, including the memory cells connected to the selected word line that are to be inhibited from programming. When the channel has an elevated voltage, the voltage difference between the channel and the word line is insufficient to cause programming.

FIG. 5 shows threshold voltage distributions for eight data states S0 through S7, corresponding to three bits of data per cell (three level cell or TLC). Seven read reference voltages Vr1, vr2, vr3, vr4, vr5, vr6 and Vr7 are also shown for reading data from the memory cells. By testing (e.g., performing a sensing operation) whether the threshold voltage of a given memory cell is above or below seven read reference voltages, the system can determine the data state (i.e., S0, S1, S2, S3.. Times.) that the memory cell is in.

FIG. 5 also shows seven verify reference voltages, vv1, vv2, vv3, vv4, vv5, vv6 and Vv7, used in a read verify step during a program operation. When programming memory cells to data state S1, the system will test whether the memory cells have threshold voltages greater than or equal to Vv 1. When programming memory cells to data state S2, the system will test whether the memory cells have threshold voltages greater than or equal to Vv 2. When programming memory cells to data state S3, the system will determine whether memory cells have their threshold voltage greater than or equal to Vv 3. When programming memory cells to data state S4, the system will test whether the memory cells have threshold voltages greater than or equal to Vv 4. When programming memory cells to data state S5, the system will test whether the memory cells have threshold voltages greater than or equal to Vv 5. When programming memory cells to data state S6, the system will test whether those memory cells have a threshold voltage greater than or equal to Vv 6. When programming memory cells to data state S7, the system will test whether those memory cells have a threshold voltage greater than or equal to Vv7. FIG. 6 also shows Vev, which is a voltage level used to test whether a memory cell has been properly erased (e.g., whether the memory cell is in the S0 data state).

In one implementation, referred to as full sequence programming, memory cells can be programmed from the erased data state S0 directly to any of the programmed data states S1-S7. For example, a population of memory cells to be programmed may first be erased so that all memory cells in the population are in erased data state S0. The programming process is then used to program the memory cells directly into data states S1, S2, S3, S4, S5, S6, and/or S7. For example, while some memory cells are being programmed from data state S0 to data state S1, other memory cells are being programmed from data state S0 to data state S2 and/or from data state S0 to data state S3, and so on. The arrows in fig. 5 indicate full sequence programming. In some embodiments, data states S1-S7 may overlap, with controller 122 relying on error correction to identify the correct data being stored.

In addition to full sequence programming, the techniques described herein may also be used with other types of programming (including, but not limited to, multi-level programming/multi-phase programming). In one implementation of multi-level programming/multi-phase programming, in a first phase, all memory cells to end with any of data states S4-S7 are programmed to an intermediate state no higher than S4. In the first phase, memory cells that are to end in any of data states S0-S3 do not receive programming. In the second phase, memory cells to end up in either data state S2 or S3 are programmed to a state no higher than S2; memory cells that are to end up in either data state S6 or S7 are programmed to a state no higher than S6. In the third phase, the memory cells are programmed to their final state. In one embodiment, a first page is programmed in a first phase, a second page is programmed in a second phase, and a third page is programmed in a third phase. Herein, once a page has been programmed into a group of memory cells, a read memory cell can be returned to retrieve the page. Thus, the intermediate states associated with multi-phase programming are referred to herein as programmed states.

Generally, during verify operations and sensing of read operations, the selected word line is connected to a voltage (one example of a reference signal) whose level is specified for each read operation (e.g., see read compare levels Vr1, vr2, vr3, vr4, vr5, vr6, and Vr7 of FIG. 5) or verify operation (e.g., see verify target levels Vv1, vv2, vv3, vv4, vv5, vv6, and Vv7 of FIG. 5) in order to determine whether the threshold voltage of the relevant memory cell has reached this level. After the word line voltage is applied, the conduction current of the memory cell is measured to determine whether the memory cell turned on (conducted current) in response to the voltage applied to the word line. If the conduction current is measured to be greater than a certain value, then it is assumed that the memory cell is turned on and the voltage applied to the word line is greater than the threshold voltage of the memory cell. If the conduction current is not measured to be greater than a particular value, then it is assumed that the memory cell did not turn on and the voltage applied to the word line is not greater than the threshold voltage of the memory cell. During a read or verify process, the unselected memory cells are provided with one or more read pass voltages (also referred to as bypass voltages) at their control gates so that these memory cells will operate as pass gates (e.g., conduct current regardless of whether they are programmed or erased).

There are many methods for measuring the conduction current of a memory cell during sensing in a read or verify operation. In one example, the conduction current of a memory cell is measured at the rate that the memory cell discharges or charges a dedicated capacitor in the sense amplifier. In another example, the conduction current of the selected memory cell allows (or disallows) the NAND string that includes the memory cell to discharge to the corresponding bit line. The voltage on the bit line is measured after a certain period of time to see if it has discharged. It should be noted that the techniques described herein may be used with different methods known in the art for sensing during a verify or read operation. Other reading and verification techniques known in the art may also be used.

FIG. 5 also shows two examples of overdrive voltages V _ OD1 and V _ OD2 that may be applied to the control gates of the data memory cells. Both overdrive voltages are higher than all data states S0 to S7. Thus, these overdrive voltages will be higher than the threshold voltages of the data memory cells in any of the data states S0-S7. During a memory access (e.g., during a program step or a program verify step of a program operation, or during a read step of a read operation), when an overdrive voltage is applied to the control gate of a data memory cell, whether the memory cell is in a programmed state (e.g., S1-S7) or an erased state (e.g., S0), the overdrive voltages are sufficient to cause the memory cell to operate as a pass gate (e.g., conduct current or "turn on"). In some examples, during a program or sense (read or verify) operation, two different overdrive voltages (e.g., V _ OD1 and V _ OD 2) are applied to different word lines connected to the same NAND string. For example, in accessing memory cells connected to a selected word line in a selected subblock, a first overdrive voltage V _ OD1 may be applied to unselected word lines connected to memory cells in the selected subblock, while a second (e.g., lower) overdrive voltage V _ OD2 may be applied to unselected word lines connected to programmed memory cells in one or more unselected subblocks.

In one embodiment, the system uses one or more "bypass voltages" during memory accesses. In one embodiment, the bypass voltage is at least Vev, but not greater than Vv7. For example, these bypass voltages may be Vr1, vv2, etc. Thus, during the precharge phase of a programming operation, when bypass voltages are applied to the control gates of data memory cells, these bypass voltages will cause the memory cell to operate (e.g., become conductive or "on") as a pass gate if the memory cell is in the erased state, but for at least one programmed state, the memory cell will not operate as a pass gate.

FIG. 6A shows an example of a portion of a memory structure (e.g., a portion of memory structure 126 or 326) that includes two vertical sub-blocks VSB0 and VSB1 comprising non-volatile memory cells connected in series in NAND strings 811, 815, 817, 819. The first vertical sub-block VSB0 includes first word lines WL0 to WL5. The second vertical sub-block VSB1 includes second word lines WL6 to WL11. The first and second word lines WL0 to WL5 and WL6 to WL11 are data word lines, and the first and second word lines are separated by a non-data word line (dummy word line DWL 1) coupled to a non-data transistor. NAND strings 811, 815, 817, 819 are connected to a Bit Line (BL) at the top and to a Source Line (SL) at the bottom.

In the example of fig. 6A, the first vertical sub-block VSB0 includes the selected word line WL3, and may thus be referred to as a selected sub-block. VSB0 includes unselected word lines WL4 and WL5 connected to programmed memory cells, and unselected word lines WL 0-WL 2 connected to unprogrammed memory cells (memory cells along the selected word line WL3 may be programmed, unprogrammed, or partially programmed, e.g., WL3 may be undergoing a program operation, which may include a program step and a verify step).

In this example, the second vertical sub-block VSB1 is an unselected sub-block. Because the NAND strings 811, 815, 817, 819 extend through the first sub-block VSB0 and the second sub-block VSB1, these sub-blocks are concatenated and the two sub-blocks (not just the selected sub-block) may be appropriately biased when accessing the selected sub-block. For example, when accessing the selected word line WL3 in VSB0, appropriate voltages may be applied to the second word lines WL 6-WL 11 of VSB1 to ensure that the NAND strings 811, 815, 817, 819 are sufficiently conductive. Similarly, when accessing word lines in VSB1, appropriate voltages may be applied to the first word lines WL 0-WL 5 to ensure that the NAND strings 811, 815, 817, 819 are sufficiently conductive.

Accessing (e.g., reading or programming) memory cells along a NAND string can affect other memory cells along the NAND string. In architectures that include NAND strings that extend between two or more sub-blocks, accessing memory cells in one sub-block may affect the memory cells in a connected sub-block. For example, repeated reading (read disturb) or repeated writing (write disturb) may cause the stored data to be disturbed. These effects can be particularly problematic when the sub-blocks are managed separately (e.g., contain logically unrelated data and are written and erased independently). In this case, one sub-block may be repeatedly written, read, and erased while the connected sub-block continues to store the same data, which may be disturbed by repeated accesses to adjacent sub-blocks of the connected sub-block. Disturb can have a greater impact on memory structures that store more than one bit per cell (e.g., because the threshold voltage ranges for different data states are narrow). Therefore, reducing the interference effects may be particularly beneficial for such a configuration: arranged in sub-blocks, and arranged in memory structures that store more than one bit per cell (e.g., the TLC arrangement shown in fig. 5).

Fig. 6A shows an example of voltages that may be applied to the unselected word lines of both the selected sub-block (VSB 0) and the unselected sub-block (VSB 1) in order to mitigate interactions between sub-blocks. For example, using a biasing scheme according to the examples shown herein may solve a technical problem of interference in a memory structure having multiple subblocks. The voltages applied to the different lines are shown to the left of the corresponding lines. In the selected sub-block, all unselected word lines (WL 0-WL 2 and WL 4-WL 5) receive the applied first overdrive voltage V _ OD1, so that all memory cells along these unselected word lines are turned on (regardless of whether the memory cells are programmed or not). V _ OD1 may be a relatively high voltage that raises the channel voltage along either side of the selected word line WL3 in the selected stator block.

In the unselected sub-block VSB1, the second overdrive voltage V _ OD2 is applied to all word lines (WL 6 to WL 8) connected to the program memory cells. The second overdrive voltage V _ OD2 may be a lower voltage than the first overdrive voltage V _ OD1 (e.g., as shown in fig. 5). The word lines (WL 9 to WL 11) connected to the unprogrammed memory cells receive a bypass voltage (Vbypass) sufficient to turn on the unprogrammed memory cells found along WL9 to WL11. As shown, the use of relatively low voltages in the unselected sub-blocks VSB1 (V _ OD2 is less than V _ OD1, and Vbypass is less than V _ OD2 and V _ OD 1) may generally reduce unwanted interactions between sub-blocks and result in less interference, providing a lower error rate (particularly in memory structures that store more than one bit per cell).

Although fig. 6A shows an example of two connected sub-blocks, VSB0 and VSB1, programmed with an intermediate output sequence (programmed from DWL 1), aspects of the present technique may be applied to any suitable memory, e.g., any number of connected sub-blocks, any number of word lines per sub-block, any number of bits stored per cell, and using any suitable programming sequence.

Fig. 6B shows an example of a portion of a memory structure (e.g., a portion of memory structure 126 or 326) that includes NAND strings 811, 815, 817, 819 that extend through three vertical sub-blocks VSB0, VSB1, and VSB2. The first vertical sub-block VSB0 includes first word lines WL0 to WL5. The second vertical sub-block VSB1 includes second word lines WL6 to WL11. The third vertical sub-block VSB2 includes third word lines WL12 to WL17. The first and second word lines WL0 to WL5 and WL6 to WL11 are data word lines, and the first and second word lines are separated by a non-data word line (dummy word line DWL 1) coupled to a non-data transistor. The third word lines WL12 to WL17 are data word lines, and are separated from the second word lines WL6 to WL11 by a non-data word line (dummy word line DWL 2) coupled to non-data transistors. NAND strings 811, 815, 817, 819 are connected to a Bit Line (BL) at the top and to a Source Line (SL) at the bottom.

In the example shown in fig. 6B, the selected word line WL7 (e.g., for the target of reading or writing) is located in VSB1, such that VSB1 is the selected sub-block, and VSB0 and VSB2 are the unselected sub-blocks. The control circuit applies a first overdrive voltage V _ OD1 on the unselected word lines (WL 6 and WL8 to WL11 of VSB 1) of the selected sub-block to turn on the corresponding memory cells and boost the channel in the selected sub-block VSB 1. In both the unselected sub-blocks VSB0 and VSB2, the word line connected to the programmed memory cell receives the second overdrive voltage V _ OD2, and the word line connected to the unprogrammed memory cell receives the bypass voltage Vbypass. For example, in VSB0, WL0 to WL3 receive V _ OD2, and WL4 to WL5 receive Vbypass. In VSB2, WL12 to WL14 receive V _ OD2, and WL15 to WL17 receive Vbypass. Thus, in this example, the same biasing scheme is applied to all unselected sub-blocks (the biasing scheme has different voltages for programmed and unprogrammed memory cells). In other examples, different biases may be applied to the word lines of different sub-blocks. Such biasing schemes may be extended to any number of sub-blocks, each containing any number of word lines, NAND strings, and other components, and the present techniques are not limited to the examples shown.

Fig. 7A illustrates an example of accessing a selected word line in a selected vertical sub-block of any suitable memory structure (e.g., memory structure 126 or 326) that applies at least two different voltages to the word lines of one or more unselected vertical sub-blocks (e.g., as shown in fig. 6A-6B). The steps illustrated in this and other methods described below may be performed by one or more suitable control circuits (e.g., control circuit 110 and/or read/write circuit 128; system control logic 360, row control circuit 320 and/or column control circuit 364; or other suitable control circuits, which may be on the same die as the memory structure being accessed, may be on different dies, or some combination). The method comprises the following steps: selected word lines 7002 in the selected sub-blocks (e.g., word lines connected to memory cells to be programmed or read) are identified, and unselected sub-blocks 7004 connected to the selected sub-blocks are identified (e.g., as shown in fig. 6A-6B). The method further comprises the following steps: finding a boundary 7006 between the written portion and the unwritten portion of the unselected sub-block; applying a first voltage 7008 to the word lines of the written portions of the unselected sub-blocks; a second voltage 7010 is applied to the word lines of the unwritten portions of the unselected sub-blocks. The boundaries may be found by any suitable method, and examples are described below. In some cases, a sub-block may be completely written or not written at all, in which case a single voltage (first voltage or second voltage, as the case may be) may be applied to all word lines of the sub-block. The method further comprises the following steps: the selected word line 7012 in the selected stator block is accessed while the first and second voltages are applied to the word lines of the unselected blocks (although steps 7008, 7010, and 7012 are shown in sequence, the first and second voltages are maintained for a period of time including accessing the selected stator block). Access may mean: such as programming the memory cell along the selected word line (e.g., by applying one or more programming pulses to the selected word line), or sensing the memory cell along the selected word line (e.g., as a program verify step during a program operation, or as part of a read operation to obtain the data requested by a read command). During such an access operation, appropriate voltages may be applied to other components (e.g., unselected word lines, dummy word lines, select lines, bit lines, and select lines of the selected stator block).

FIG. 7B shows an example of the method of FIG. 7A for programming memory cells connected to a selected word line. Step 7002 includes identifying a selected word line in the selected sub-block for programming (e.g., in response to a program command designating a particular word line in the memory structure as a data storage destination). The method comprises the following steps: identifying an unselected subblock 7004 connected to the selected subblock; finding a boundary 7006 between the written portion and the unwritten portion of the unselected sub-block; applying a first voltage 7008 to the word lines of the written portions of the unselected sub-blocks; and applying a second voltage 7010 to the word lines of the unwritten portions of the unselected sub-blocks, as previously described. The method further comprises the following steps: a series of programming pulses 7014 are applied on the selected word line while the first and second voltages are applied to the word lines of the unselected sub-blocks. For example, while V _ OD2 and Vbypass are applied (as shown in FIGS. 6A-6B), one or more programming pulses are applied to raise the threshold voltage of the memory cell (as shown in FIG. 5).

FIG. 7C illustrates an example of the method of FIG. 7A for verifying or reading a memory cell connected to a selected word line. Step 7002 includes identifying a selected word line in the selected sub-block for verification or reading. For example, after a programming step such as that shown in FIG. 7B, such a verification step can occur during programming of the memory cells connected to the selected word line, such that the selected word line is indicated by the program command. Such programming steps and verification steps may be performed alternately until the programming operation is completed. The selected word line for reading can be indicated by a read command (e.g., a command to read and return data stored in the memory cell along a particular word line). The method comprises the following steps: identifying an unselected subblock 7004 connected to the selected subblock; finding a boundary 7006 between the written portion and the unwritten portion of the unselected sub-block; applying a first voltage 7008 to the word lines of the written portions of the unselected sub-blocks; and applying a second voltage 7010 to the word lines of the unwritten portions of the unselected sub-blocks, as previously described. The method further comprises the following steps: memory cells connected to the selected word line are sensed while the first voltage and the second voltage are applied to the word lines of the unselected sub-blocks. For example, memory cells are sensed along a selected word line by applying one or more verify voltages Vv 1-Vv 7 of FIG. 5 on the selected word line while applying V _ OD2 and Vbypass as shown in FIGS. 6A-6B, while sensing current through NAND strings 811, 815, 817, 819 in a verify step, or by applying one or more read voltages Vr 1-Vr 7 on the selected word line while sensing current through NAND strings 811, 815, 817, 819 in a read step.

Fig. 7D shows an example of a method of using the present technology in a structure such as that shown in the examples of fig. 6A-6B. The method comprises the following steps: in a non-volatile memory array that includes NAND strings that extend through two or more vertical sub-blocks, identifying one or more unselected vertical sub-blocks 7020 that are connected to the selected vertical sub-block; finding a boundary 7022 between the programmed portion and the unprogrammed portion of the one or more unselected vertical sub-blocks; and during programming or sensing of the non-volatile memory cells in the selected vertical sub-block, applying a first voltage to word lines of the unselected vertical sub-block connected to programmed non-volatile memory cells and applying a second voltage 7024 to word lines of the unselected vertical sub-block connected to unprogrammed non-volatile memory cells.

The steps shown in fig. 7D may be performed by any suitable control circuitry, including, for example, control circuitry 110 and/or read/write circuits 128; system control logic 360, row control circuitry 320, and/or column control circuitry 364. Such control circuitry may be considered as means for: a read voltage or a programming pulse is applied on a selected word line of a first set of data word lines for reading or programming memory cells along the selected word line, while an overdrive voltage is applied to all programmed data word lines in a second set of data word lines and a bypass voltage is applied to all unprogrammed data word lines in the second set of data word lines.

The boundary between the written portion and the unwritten portion of the unselected sub-block may be looked up in any suitable manner. In some memory systems, control information may be maintained to indicate specific information about the sub-blocks. For example, the control information may indicate whether the block is fully programmed (closed), partially programmed (open), or completely unprogrammed (erased). Where an unselected sub-block is closed or erased, all word lines may be similarly processed, and the same voltage may be applied to all such word lines (e.g., a suitable overdrive voltage (such as V _ OD 2) may be applied to all word lines of the closed block, and a suitable bypass voltage (such as Vbypass) may be applied to all word lines of the erase block). In the case of an open sub-block, the control information may indicate where the boundary between the written portion and the unwritten portion is located. In this case, finding the boundary may include accessing the relevant control information. In other cases, such control information is not available or reliable (e.g., after an unexpected power loss, when the control information may not have been saved from volatile memory to non-volatile memory prior to the power loss), and the unselected subblocks may be searched for boundaries.

Fig. 8A shows a first example of a method of searching for an unselected subblock connected to a selected subblock (e.g., a method for finding a boundary in step 7006 of fig. 7A to 7C). The method includes applying an overdrive voltage 830 to all word lines of the selected subblock (e.g., applying a first overdrive voltage V _ OD1 to WL6 to WL11 of VSB1 in fig. 6B). An overdrive voltage (e.g., 7 volts) may also be applied to all word lines of any other unselected sub-block other than the searched sub-block, so that all memory cells of connected NAND strings outside the searched sub-block are conductive (e.g., when searching for boundaries in the unselected sub-block VSB0 of fig. 6A, word lines WL 12-WL 17 of the unselected sub-block VSB2 may receive an overdrive voltage such as V _ OD1 or V _ OD 2). The method comprises the following steps: set the variable "n" to zero (n = 0) 832, where n indicates the word line checked as programmed/unprogrammed; applying a bypass voltage (e.g., 0 volts) 834 to WLn of the unselected sub-blocks; and applying an overdrive voltage (e.g., 7 volts) 836 to all other word lines of the unselected sub-blocks. It is then determined whether the NAND string is conducting 838 (e.g., by measuring the current flowing through the NAND string 811, 815, 817, 819). Because some memory cells remain in the S0 data state even when the memory cells are programmed, a single conductive NAND string may not be sufficient to indicate the unprogrammed state of the memory cells along a word line. The results of sensing multiple NAND strings (e.g., average current, number of NAND strings exceeding the expected current, or some other combination of results) may be used. If the NAND string conducts when a bypass voltage is applied across WLn, then WLn is connected to an unprogrammed memory cell, and the boundary is between WLn and WLn 1 840. If the NAND string conducts when n =0 (the first word line of the sub-block), then when the selected word line of the selected sub-block is accessed, the block is erased and a bypass voltage (e.g., vbypass) may be applied to all word lines of the unselected sub-block. If the NAND string is non-conductive, then it is determined whether word line WLn is the last word line of the sub-block, n = maximum? 842. If n = maximum, the unselected sub-block is fully programmed (closed) 844 and an overdrive voltage (e.g., V _ OD 2) may be applied to all word lines of the unselected sub-block while the selected word line of the selected sub-block is accessed. If WLn is not the last word line (n ≠ Max), then n is incremented to n +1 846 and the next word line is checked until a boundary is found or the last word line is reached.

The sequence of checking the word lines proceeds in the programming sequence. Thus, for example, in fig. 6B, the first word line examined in the unselected sub-block VSB0 may be WL0, then WL1, WL2, etc., such that the numbers shown indicate the order of examination. The bypass voltage applied to any of WL 0-WL 3 is insufficient to make NAND strings 811, 815, 817, 819 conductive (at least on average) because these NAND strings are programmed and have higher threshold voltages (e.g., corresponding to data states S1-S7 of fig. 5). The bypass voltage applied to WL4 is sufficient to make NAND strings 811, 815, 817, 819 conductive because only the unprogrammed memory cells are connected to WL4. Thus, applying the method of fig. 8A to VSB0 of fig. 6B includes incrementing n until n =4, and finding the boundary between WL3 and WL4. In searching for a boundary in the unselected sub-block VSB2, WL12 may be the first word line to be checked, followed by WL13, WL14, etc. The value of n may be biased accordingly (e.g., n may be initialized to 12 instead of zero). In some cases (e.g., using center output programming), the wordlines may be checked in different orders, with some sub-blocks being checked from the lowest wordline to the highest wordline according to the programming order and other sub-blocks being checked from the highest wordline to the lowest wordline according to the programming order (e.g., n may be offset and may be decreasing instead of increasing in some sub-blocks).

While sequentially proceeding one word line at a time is one way of finding boundaries, another way of finding boundaries uses a binary search tree, which may reduce the number of steps to find boundaries, as shown in fig. 8A. According to this method, the wordline in the middle of a sub-block is first examined to determine which half of the sub-block contains a boundary. Then, the wordline in the middle of the half of the sub-block is examined to determine which quarter contains the boundary. Successive steps reduce the search area by half until a boundary is found.

FIG. 8B shows a sub-block of 34 word lines, including 7 word lines (0 to 6) connected to programmed memory cells and 25 word lines (7 to 33) connected to unprogrammed memory cells. Using sequential searching may require seven sense operations corresponding to word lines 0 through 7 (in the programming order from word line 0). If the boundary is higher, then a greater number of steps will be required (e.g., if the boundary location is random, then on average the boundary will be between wordlines 16 through 17, requiring 18 sequential steps to be found). In contrast, using the binary search method involves a first check made at the center of the sub-block, i.e., at wordline 16, which is not programmed, indicating that the boundary is at the lower half of the sub-block (between 0 and 16). The second check, centered at the bottom half, at wordline 8, indicates that the boundary is in the lower quarter of the sub-block (between 0 and 8). A third check, made in the middle of the lower quarter, i.e. at word line 4, indicates that the border is located in the upper part of the lower quarter (between 4 and 8). A fourth check, made at the middle of the upper part of the lower quarter, i.e. at word line 6, indicates that the boundary is higher than word line 6 (between 6 and 8). The fifth check of word line 7 indicates that the boundary is lower than word line 7, such that the boundary is determined to be between word lines 6-7 (e.g., word lines 0-6 are connected to programmed memory cells and word lines 7-33 are connected to unprogrammed memory cells).

Fig. 8C illustrates a method of implementing a binary search operation (e.g., applying the binary search operation illustrated in fig. 8B to the unselected subblocks of fig. 6A or 6B). The method comprises the following steps: applying an overdrive voltage 850 to all word lines of a selected sub-block (e.g., a sub-block including a selected word line for programming or sensing); and setting the first variable L to 0 and the second variable H to N: l =0 is set and H = N852 is set. These variables correspond to the lowest word line (WLL) and the highest Word Line (WLH) within the range to be searched, respectively. These variables may be initialized to the lowest wordline in the sub-block (WL 0) and the highest wordline in the sub-block (WLN, where there are N +1 wordlines in the sub-block, e.g., N =33 in the example of fig. 8B). Thus, the initial range to be searched includes all the word lines of the sub-block. It is determined whether L +1 is smaller than H854, and if so (e.g., L +1=1, 1-straw 34 at initialization), the variable n (corresponding to the word line to be checked) is set to (L + H)/2 856 (e.g., WL16, which is the target of the first check in fig. 8A). The method comprises the following steps: apply a bypass voltage (e.g., 0 volts) 858 to WLn; applying an overdrive voltage (e.g., 7 volts) 860 to all other word lines of the unselected sub-blocks; and determining whether the NAND string is conductive 862 (e.g., by sensing current through the NAND string). If the NAND string is conducting, WLn is connected to the unprogrammed memory cells so that the boundary is below WLn, and the upper boundary of the next search area is set at WLn 864 by setting H = n. If the NAND string is not conducting, WLn is connected to the programmed memory cell so that the boundary is above WLn, and the lower boundary of the next search area is set at WLn 866 by setting L = n. The new values of H or L are then used to determine whether L +1 s are woven into H854. If L +1 remains less than H (e.g., 1 straw 16 after the first check of FIG. 8B), then n is set to (L + H)/2 with the new value (e.g., n =8 for the second check of FIG. 8B) and WLn is sensed by applying a bypass voltage 858 to WLn, applying an overdrive voltage 860 to all other word lines of the unselected sub-block, and determining if the NAND string is conducting 862. If the NAND string is conductive, H is set to n 846 (e.g., after the second check of FIG. 8B, n is set to 8, such that the range is WL0 to WL 8), and if the NAND string is non-conductive, L is set to n 866 (e.g., after the third check of WL4 of FIG. 8A, L is set to 4, such that the range is from WL4 to WL 8). The method continues until it is determined at step 854 that L +1 woven is not true (e.g., when H is set to 7 after the fifth check and L is set to 6 after the fourth check, then L +1= H), and then it is determined that the boundary is located 868 between WLL to WLH (e.g., between WL6 to WL7 of fig. 8B).

In some embodiments, the results of the boundary search may be stored such that the search does not have to be repeated (e.g., as shown in fig. 8A-8C). For example, in a programming operation that includes multiple programming steps and verification steps, once a boundary is found in a sub-block, the boundary may be used throughout the programming operation (e.g., the location of the boundary may be stored and retrieved by the control circuitry as needed). Control circuitry (such as control circuitry 110 and/or read/write circuits 128) may be configured to store such location information and apply the word line voltage in accordance with the stored location information.

FIG. 9 is an exemplary timing diagram illustrating particular voltages that may be applied by control circuitry (e.g., by control circuitry 110 and/or read/write circuits 128; system control logic 360, row control circuitry 320 and/or column control circuitry 364; or other suitable control circuitry, which may be on the same die as the memory structure being accessed, may be on a different die, or some combination) to program memory cells in the memory structure. The voltages shown include: a voltage applied to a word line of the selected vertical sub-block, and a voltage applied to a word line connected to one or more unselected vertical sub-blocks of the selected vertical sub-block (e.g., as shown in fig. 6A-6B). Initially, at time T0, all illustrated voltages are 0 volts. Subsequently, at time T1, the bit line voltage (BL or Vbl) is increased to VDDSA (e.g., approximately 2-2.5 volts), the drain select gate voltage (SGD or Vsgd) is increased to Vsgd (e.g., 2.5 volts), the source select gate voltage SGS is held at 0 volts, and the source line voltage (CELSRC or Vcsrc) is increased to VDDSA (e.g., approximately 2-2.5 volts).

In the selected vertical sub-block (e.g., VSB0 of fig. 6A), the voltage on the selected word line (e.g., WL 3) is increased to VPGM (e.g., a programming pulse), the voltage on the programmed word line (e.g., word lines WL 4-WL 5 connected to programmed memory cells) is increased to a first overdrive voltage V _ OD1 (e.g., between 8-10 volts or about 9 volts), and the voltage on the unprogrammed word line (e.g., word lines WL 0-WL 2 connected to unprogrammed memory cells) is also increased to V _ OD1. In other examples, different voltages may be applied to the word lines connected to programmed memory cells and the word lines connected to unprogrammed memory cells in the selected sub-block.

In the unselected vertical sub-block (e.g., VSB1 of FIG. 6A), the word lines (e.g., WL 6-WL 8) connected to the programmed memory cells and the word lines (e.g., WL 9-WL 11) connected to the unprogrammed memory cells receive different voltages. The programmed and unprogrammed portions of such unselected sub-blocks may be identified by any suitable method, including searching as described with respect to fig. 8A-8C. An overdrive voltage V _ OD2 (e.g., a voltage less than the first overdrive voltage V _ OD1, such as between 6 volts and 8 volts, or about 7 volts) is applied on the program word line. A bypass voltage (e.g., between 4-6 volts or about 5 volts) is applied across the unprogrammed word lines. All illustrated voltages return to 0 volts at time t2 and remain at 0 volts until at least time t3 is reached, at which point subsequent steps (e.g., a verify step to determine whether a programming step is sufficient or whether another programming step is required) may be performed.

FIG. 10 is an exemplary timing diagram illustrating particular voltages that may be applied by control circuitry (e.g., by control circuitry 110 and/or read/write circuits 128; system control logic 360, row control circuitry 320 and/or column control circuitry 364; or other suitable control circuitry, which may be on the same die as the memory structure being accessed, may be on a different die, or some combination) to sense memory cells in the memory structure (e.g., during read or verify). The voltages shown include: a voltage applied to the word line of the selected sub-block, and a voltage applied to the word lines connected to one or more unselected sub-blocks of the selected sub-block (e.g., as shown in fig. 6A-6B). Initially, at time T0, all illustrated voltages are 0 volts. Subsequently, at time T1, the bit line voltage (BL or Vbl) is increased to Vbl (e.g., about 3 volts), the drain select gate voltage (SGD or Vsgd) is increased to VSG (e.g., 8 volts), the source select gate voltage SGS is also increased to VSG, and the source line voltage (CELSRC or Vcsrc) remains at 0 volts.

In the selected vertical sub-block (e.g., VSB0 of fig. 6A), the voltage on the selected word line (e.g., WL 3) is increased to VCG (e.g., read voltages Vr 1-Vr 7 or verify voltages Vv 1- Vv 7, 1 volt in this example), the voltage on the programmed word line (e.g., word lines WL 4-WL 5 connected to the programmed memory cells) is increased to an overdrive voltage V _ OD2 (e.g., between 6 volts-8 volts or about 7 volts), and the voltage on the unprogrammed word line (e.g., word lines WL 0-WL 2 connected to the unprogrammed memory cells) is also increased to V _ OD2. In other examples, different voltages may be applied to the word lines connected to programmed memory cells and the word lines connected to unprogrammed memory cells in the selected sub-block.

In the unselected vertical sub-block (e.g., VSB1 of FIG. 6A), the word lines (e.g., WL 6-WL 8) connected to the programmed memory cells and the word lines (e.g., WL 9-WL 11) connected to the unprogrammed memory cells receive different voltages. The programmed and unprogrammed portions of such unselected sub-blocks may be identified by any suitable method, including searching as described with respect to fig. 8A-8C. An overdrive voltage V _ OD2 (e.g., between 6 volts and 8 volts, or about 7 volts) is applied to the program word line. A bypass voltage (e.g., between 2 volts to 4 volts or about 3 volts) is applied on the unprogrammed word line. All illustrated voltages return to 0 volts at time t2 and remain at 0 volts until at least time t3 is reached, at which point subsequent steps may be performed (e.g., if verify indicates that further programming is required, a subsequent programming step is performed; or a subsequent read step is performed using a VCG at a different level).

One embodiment includes an apparatus comprising a control circuit configured to be connected to a first word line of a first vertical sub-block and a second word line of a second vertical sub-block, the first vertical sub-block and the second vertical sub-block comprising memory cells connected in series in NAND strings, each NAND string comprising memory cells coupled to the first word line in series with memory cells connected to the second word line, the control circuit configured to: memory cells are programmed or sensed along a selected first word line of the first vertical sub-block while a first voltage is applied to one or more second word lines of the second vertical sub-block connected to programmed memory cells and a second voltage is applied to one or more second word lines of the second vertical sub-block connected to unprogrammed memory cells.

The control circuitry may be further configured to identify a boundary between a second wordline connected to programmed memory cells and a second wordline connected to unprogrammed memory cells of the second vertical sub-block. The control circuit may be further configured to identify the boundary by sensing the second wordlines of the second vertical sub-block in a binary search of the second wordlines. The control circuit may be further configured to identify the boundary by sensing the second wordlines of the second vertical sub-block in a sequential search of the second wordlines. The first voltage may be an overdrive voltage sufficient to turn on memory cells programmed to all data states, and the second voltage may be a bypass voltage sufficient to turn on unprogrammed memory cells, but insufficient to turn on memory cells programmed to one or more data states. The control circuit may be further configured to apply a third voltage to the unselected first word lines of the first vertical sub-block, the third voltage may be an overdrive voltage sufficient to turn on the memory cells programmed to all of the data states, and the third voltage may be greater than the first voltage. The control circuitry may be further configured to program the memory cells along the selected first word line of the first vertical sub-block while applying a first voltage of about 6-8 volts, a second voltage of about 4-6 volts, and a third voltage of about 8-10 volts. The control circuitry may be further configured to sense the memory cells along the selected first word line of the first vertical sub-block while applying a first voltage of about 6-8 volts, a second voltage of about 2-4 volts, and a third voltage of about 6-8 volts. The control circuit may be further configured to erase the first vertical sub-block and the second vertical sub-block independently, and to allocate logically unrelated data to the first vertical sub-block and the second vertical sub-block such that the write-erase cycle counts of the first vertical sub-block and the second vertical sub-block are independent of each other.

An exemplary method comprises: in a non-volatile memory array including NAND strings extending through two or more vertical sub-blocks, identifying one or more unselected vertical sub-blocks connected to a selected vertical sub-block; finding a boundary between a programmed portion and an unprogrammed portion of the one or more unselected vertical sub-blocks; and during programming or sensing of the non-volatile memory cells in the selected vertical sub-block, applying a first voltage to the word lines of the unselected vertical sub-blocks in the programmed portion and applying a second voltage to the word lines of the unselected vertical sub-blocks in the unprogrammed portion.

The first voltage may be higher than the second voltage. The method may also include applying one or more programming pulses to a selected word line of the selected vertical sub-block while applying a third voltage to unselected word lines of the selected vertical sub-block, the third voltage being higher than the first voltage and the second voltage, during programming of the non-volatile memory cell. The method may also include applying a third voltage to the unselected word lines of the selected vertical sub-block when sensing the non-volatile memory cell, the third voltage being equal to or greater than the first voltage. The method may also include applying, during programming or sensing, a first voltage to a word line connected to programmed non-volatile memory cells and applying a second voltage to a word line connected to unprogrammed non-volatile memory cells in one or more additional vertical sub-blocks that share a NAND string with the selected vertical sub-block. Finding the boundary may include performing a binary search on the word lines of the unselected vertical sub-blocks. Finding the boundary may include performing a sequential search on the wordlines of the unselected vertical sub-blocks.

An exemplary non-volatile storage device includes: a plurality of NAND strings of memory cells, each NAND string having a first set of data memory cells, a second set of data memory cells, and a first non-data transistor located between the first set of data memory cells and the second set of data memory cells; a plurality of word lines connected to data memory cells, the word lines including a first set of data word lines connected to the first set of data memory cells and a second set of data word lines connected to the second set of data memory cells; and means for: a read voltage or programming pulse is applied to a selected word line of the first set of data word lines to read or program memory cells along the selected word line, while an overdrive voltage is applied to all programmed data word lines in the second set of data word lines and a bypass voltage is applied to all unprogrammed data word lines in the second set of data word lines.

The non-volatile storage device may further comprise means for: the programmed data word lines and the unprogrammed data word lines in the second set of data word lines are identified by searching the second set of data word lines in a serial or binary search pattern. Each of the plurality of NAND strings may further include at least a third group of data memory cells and a second non-data transistor between the second group of data memory cells and the third group of data memory cells; the plurality of word lines may also include a third set of data word lines connected to the third set of data memory cells. The overdrive voltage may be about 7 volts, and the bypass voltage may be in a range of about 3 volts to about 5 volts.

For the purposes of this document, references in the specification to "an embodiment," "one embodiment," "some embodiments," or "another embodiment" may be used to describe different embodiments or the same embodiment.

For purposes of this document, a connection may be a direct connection or an indirect connection (e.g., via one or more other components). In some cases, when an element is referred to as being connected or coupled to another element, the element may be directly connected to the other element or indirectly connected to the other element via an intervening element. When an element is referred to as being directly connected to another element, there are no intervening elements between the element and the other element. Two devices are "in communication" if they are directly or indirectly connected, such that they can communicate electronic signals between them.

For the purposes of this document, the term "based on" may be understood as "based at least in part on".

For purposes of this document, the use of digital terms such as "first" object, "second" object, and "third" object, without additional context, may not imply a ranking of the objects, but may be used for identification purposes to identify different objects.

For purposes of this document, the term "group" of objects may refer to a "group" of one or more objects.

The foregoing detailed description has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. The described embodiments were chosen in order to best explain the principles of the proposed technology and its practical application to thereby enable others skilled in the art to best utilize it in various embodiments and with various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims appended hereto.

Claims (20)

1. An apparatus, the apparatus comprising:

a control circuit configured to connect to a first word line of a first vertical sub-block and a second word line of a second vertical sub-block, the first and second vertical sub-blocks comprising memory cells connected in series in NAND strings, each NAND string comprising memory cells coupled to the first word line in series with memory cells connected to the second word line, the control circuit configured to:

programming or sensing memory cells along a selected first word line of the first vertical sub-block while applying a first voltage to one or more second word lines of the second vertical sub-block connected to programmed memory cells and applying a second voltage to one or more second word lines of the second vertical sub-block connected to unprogrammed memory cells.

2. The apparatus of claim 1, wherein:

the control circuitry is further configured to identify a boundary between a second word line of the second vertical sub-block connected to programmed memory cells and a second word line connected to unprogrammed memory cells.

3. The apparatus of claim 2, wherein:

the control circuit is further configured to identify the boundary by sensing a second wordline of the second vertical sub-block in a binary search of the second wordline.

4. The apparatus of claim 2, wherein:

the control circuitry is further configured to identify the boundary by sensing a second wordline of the second vertical sub-block in a sequential search of the second wordline.

5. The apparatus of claim 1, wherein:

the first voltage is an overdrive voltage sufficient to turn on memory cells programmed to all data states, and the second voltage is a bypass voltage sufficient to turn on unprogrammed memory cells, but insufficient to turn on memory cells programmed to one or more data states.

6. The apparatus of claim 5, wherein:

the control circuit is further configured to apply a third voltage to the unselected first word lines of the first vertical sub-block, the third voltage being an overdrive voltage sufficient to turn on the memory cells programmed to all data states, and the third voltage being greater than the first voltage.

7. The apparatus of claim 6, wherein:

the control circuitry is further configured to program the memory cells along the selected first word line of the first vertical sub-block while applying a first voltage of about 6-8 volts, a second voltage of about 4-6 volts, and a third voltage of about 8-10 volts.

8. The apparatus of claim 6, wherein:

the control circuitry is further configured to sense the memory cells along the selected first word line of the first vertical sub-block while applying a first voltage of about 6-8 volts, a second voltage of about 2-4 volts, and a third voltage of about 6-8 volts.

9. The apparatus of claim 1, wherein:

the control circuitry is further configured to independently erase the first vertical sub-block and the second vertical sub-block, and to allocate logically unrelated data to the first vertical sub-block and the second vertical sub-block such that the write-erase cycle counts of the first vertical sub-block and the second vertical sub-block are independent of each other.

10. A method, the method comprising:

in a non-volatile memory array including NAND strings extending through two or more vertical sub-blocks, identifying one or more unselected vertical sub-blocks connected to a selected vertical sub-block;

finding a boundary between a programmed portion and an unprogrammed portion of the one or more unselected vertical sub-blocks; and

during programming or sensing of the non-volatile memory cells in the selected vertical sub-block, a first voltage is applied to the word lines of the unselected vertical sub-block in the programmed portion, and a second voltage is applied to the word lines of the unselected vertical sub-block in the unprogrammed portion.

11. The method of claim 10, wherein the first voltage is higher than the second voltage.

12. The method of claim 11, further comprising:

during programming of the non-volatile memory cell, one or more programming pulses are applied to a selected word line of the selected vertical sub-block while a third voltage is applied to unselected word lines of the selected vertical sub-block, the third voltage being higher than the first voltage and the second voltage.

13. The method of claim 11, further comprising:

while sensing the non-volatile memory cell, applying a third voltage to the unselected word lines of the selected vertical sub-block, the third voltage being equal to or greater than the first voltage.

14. The method of claim 10, further comprising:

during programming or sensing, the first voltage is applied to word lines connected to programmed non-volatile memory cells and the second voltage is applied to word lines connected to unprogrammed non-volatile memory cells in one or more additional vertical sub-blocks that share the NAND string with the selected vertical sub-block.

15. The method of claim 10, wherein finding the boundary comprises performing a binary search on a wordline of the unselected vertical sub-block.

16. The method of claim 10, wherein finding the boundary comprises performing a sequential search on wordlines of the unselected vertical sub-block.

17. A non-volatile storage device, the non-volatile storage device comprising:

a plurality of NAND strings of memory cells, each NAND string having a first set of data memory cells, a second set of data memory cells, and a first non-data transistor located between the first and second sets of data memory cells;

a plurality of word lines connected to the data memory cells, the word lines including a first group of data word lines connected to the first group of data memory cells and a second group of data word lines connected to the second group of data memory cells; and

apparatus for: applying a read voltage or a programming pulse on a selected word line of the first set of data word lines to read or program memory cells along the selected word line, while applying an overdrive voltage to all programmed data word lines of the second set of data word lines and applying a bypass voltage to all unprogrammed data word lines of the second set of data word lines.

18. The non-volatile storage device of claim 17, further comprising means for: identifying programmed data word lines and unprogrammed data word lines in the second set of data word lines by searching the second set of data word lines in a serial or binary search pattern.

19. The non-volatile storage device of claim 17, wherein:

each of the plurality of NAND strings further comprises at least a third group of data memory cells and a second non-data transistor located between the second and third groups of data memory cells; and is

The plurality of word lines also includes a third set of data word lines connected to the third set of data memory cells.

20. The non-volatile storage device of claim 17, wherein:

the overdrive voltage is about 7 volts and the bypass voltage is in a range of about 3 volts to about 5 volts.

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