CN115775295A - Apparatus and method for tile-based deferred rendering - Google Patents

Abstract

The present disclosure provides an apparatus for tile-based deferred rendering, comprising: a visibility engine configured to generate primitive visibility information for each tile in a stage related to location-only; and a scheduler configured to perform scheduling for the plurality of processor cores based on the primitive visibility information prior to a rendering phase. By the method and the device, the processing period, the memory space and the power of the GPU system are saved, and better GPU utilization rate is realized by load balancing scheduling.

Description

Apparatus and method for tile-based deferred rendering

technical field

The present disclosure relates to apparatus, methods, devices, and computer-readable media for tile-based deferred rendering (TBDR), and more particularly to multi-stage with dead primitive removal and load balancing for TBDR architectures Rendering architecture.

Background technique

TBDR is a popular modern graphics processing unit (GPU) architecture due to its advantages in power and efficiency. TBDR mode divides the screen into tiles. When rendering geometry, each primitive falls into one of the screen tiles, forming a primitive-per-tile list. Later in the pixel shader stage, the rasterizer fetches a list of primitives to generate pixels. After the optional Hidden Surface Removal (HSR) unit, only visible pixels are delivered to the shading unit for texturing and shading. Thus, texturing and shading processing is delayed until primitive visibility is known, ensuring the lowest possible bandwidth usage and the lowest processing cycles per frame compared to undelayed tile-based rendering.

However, in TBDR mode, the geometry pipeline processes all raw primitives and writes them to the corresponding primitive list based on the tile position. The entire geometry process has to deal with dead primitives that will eventually be rejected by the HSR unit. These dead primitives waste a lot of computing resources/cycles on geometry operations such as vertex transformation, attribute interpolation, clipping, and primitive assembly. Additionally, dead primitives will take up device memory space to form primitive lists, which can trigger out-of-memory issues that stop or restart the geometry process.

On the other hand, load balancing is a very important research topic for optimal rendering latency when multiple processors are enabled. Typically, a central dispatch unit is employed to preprocess vertex buffers and dispatch primitives to each processor for load balancing. In most cases, this central scheduling unit ends up being the bottleneck of the entire pipeline. Furthermore, if geometry magnification like tessellation is enabled, it is impossible for the scheduling unit to predict how many sub-primitives will be generated from the geometry data of the original primitive, making load balancing an intractable problem.

Contents of the invention

The present disclosure provides a new architecture for rendering using the TBDR mode, which can avoid wasting geometry processing resources on dead primitives, and can save unnecessary memory occupation for dead primitives. Additionally, load balancing can be implemented for multi-processor GPU systems.

According to a first aspect of the present disclosure, there is provided an apparatus for tile-based deferred rendering, the apparatus comprising: a visibility engine configured to generate, in a position-only phase, a Primitive visibility information; and a scheduler configured to perform scheduling for the plurality of processor cores based on the primitive visibility information prior to a rendering stage.

According to a second aspect of the present disclosure, there is provided a method for tile-based deferred rendering, the method comprising: generating primitive visibility information for each tile in a position-only phase; and Scheduling for multiple processor cores is performed based on the primitive visibility information prior to a rendering stage.

According to a third aspect of the present disclosure, there is provided an apparatus for tile-based deferred rendering, the apparatus comprising: a processor; and a memory communicatively connected to the processor and adapted to store instructions , the instructions, when executed by the processor, cause the device to perform operations according to the method described in the second aspect above.

According to a fourth aspect of the present disclosure, there is provided a computer-readable medium having stored thereon instructions which, when executed, cause a processor of an apparatus for tile-based deferred rendering to perform the method described in accordance with the above-mentioned second aspect. described method.

Through the present disclosure, the waste of computing resources for dead primitives caused during the geometry processing stage is eliminated, thereby saving processing cycles, memory space and power of the GPU system; moreover, utilizing load balancing scheduling to achieve better GPU utilization , both geometry workload and pixel shader workload can be evenly distributed across multiprocessor systems.

Description of drawings

Exemplary embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, this disclosure may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. The terminology used in the detailed description of the exemplary embodiments illustrated in the accompanying drawings is not intended to limit the present disclosure. In the drawings, like numerals refer to like parts.

FIG. 1 shows a schematic block diagram of dead primitive removal in TBDR mode according to an embodiment of the present disclosure.

Fig. 2 shows a schematic block diagram of load balancing using live graph element information in a TBDR mode according to an embodiment of the present disclosure.

Fig. 3 shows a block diagram of an apparatus for TBDR according to an embodiment of the present disclosure.

Fig. 4 shows a flowchart of a method for TBDR according to an embodiment of the present disclosure.

Fig. 5 shows a block diagram of a device for TBDR according to an embodiment of the present disclosure.

Detailed ways

Devices, methods and apparatus for TBDR are described below. In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which are shown by way of illustrations specific embodiments in which the disclosure may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the disclosure, and it is to be understood that other embodiments may be utilized and that structural, logical and electrical changes. Therefore, the following detailed description should not be regarded as limiting, but illustrative. The scope of the present disclosure is defined by the appended claims and their equivalents.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present disclosure. As used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It should also be understood that the term "comprising" indicates the presence of stated features, integers, steps, operations, elements and/or components, but does not exclude the presence of one or more other features, integers, steps, operations, elements, components.

Unless otherwise defined, terms used herein have the same meaning as commonly understood by those skilled in the art to which this disclosure belongs. Terms used herein should be interpreted as having meanings consistent with their meanings in the context of this specification and in the relevant art, unless otherwise defined herein.

The present disclosure is described below with reference to block diagrams and/or flowchart illustrations of methods, apparatuses and/or computer program products according to embodiments of the disclosure. It will be understood that one block and combinations of blocks of the block diagrams and/or flowchart illustrations can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general-purpose computing device, a special-purpose computing device, and/or other programmable data processing means, such that the instructions executed via the computing device processor and/or other programmable data processing means create a Methods of function/acts specified in block diagrams and/or flowcharts.

Accordingly, the present disclosure may also be implemented in hardware and/or software (including firmware, resident software, microcode, etc.). Still further, the present disclosure may take the form of a computer program product on a computer-usable or computer-readable storage medium having computer-usable or computer-readable program code embodied in the medium, for use by an instruction execution system or in conjunction with the instruction used to execute the system. In the context of this disclosure, a computer-usable or computer-readable medium may be any medium that can contain, store, communicate, transmit, or deliver a program for use by or in connection with instruction execution systems, apparatus, or devices System, device or equipment use.

Electronic devices use machine-readable media (also known as computer-readable media) to store and transmit (internally and/or over a network with other electronic devices) code (including software instructions and may be referred to as computer program code or computer programs) and/or data, such as machine-readable storage media (e.g., magnetic disks, optical disks, read-only memory (ROM), flash memory, phase-change memory, etc.) and machine-readable transmission media (also known as Carrier) (for example, electrical, optical, radio frequency, acoustic or other form of propagating signal - such as carrier wave, infrared signal, etc.). Accordingly, an electronic device (e.g., a computer) includes hardware and software, such as one or more processors, coupled to one or more machine-readable storage media to store code for execution by the one or more processors and/or Storing data. For example, an electronic device may include non-volatile memory that can maintain code/data when the electronic device is off, and when the electronic device is on, the portion of the code to be executed by the processor typically starts from The slow non-volatile memory is copied to the electronic device's volatile memory (eg, dynamic random access memory (DRAM), static random access memory (SRAM), etc.). Typically, electronic devices also include a set of physical network interfaces to network with other electronic devices (to transmit/receive code and/or data using propagated signals). One or more portions of the present disclosure may be implemented using various combinations of software, firmware, and/or hardware.

Fig. 1 schematically shows a schematic block diagram of invisible primitive removal in TBDR mode according to an embodiment of the present disclosure.

As shown in FIG. 1 , the position-only phase of preprocessing is used to collect primitive visibility information for each TBDR tile, while also accumulating the number of live primitives for each tile. Hereinafter, live primitives are called visible primitives, and correspondingly, dead primitives are called invisible primitives.

The position-only related stages have geometry shading, clipping, projection, culling, and rasterization stages, which include vertex shader processing, tessellation, geometry shader processing, and more. After tiling (that is, concatenating primitives into a screen tile), the rasterization and depth testing unit is activated, since the position of the rasterized pixel can be used to determine whether the primitive falls into a tile , and whether the primitive is completely occluded by another primitive so that it can be discarded in a later rendering pass. Finally, primitive visibility information for each tile is generated and output by the visibility engine. The primitive visibility information may include the number of visible primitives for each tile.

During the entire stage, only vertex positions are fetched and used to save bandwidth and computational resources, primitive visibility information for each tile is the output of this stage, pixel shading is skipped entirely, and at the end of this stage no Generate additional information.

In subsequent rendering stages, primitive visibility information generated in position-only stages is extracted to align with geometry data. As can be seen in Figure 1, only visible primitives are passed to the pipeline for clipping and projection processing. The culling operation is skipped in this phase because invisible primitives are marked and discarded as described above.

The position-only phase and rendering phase described above generate per-tile primitive visibility information, skipping invisible primitives, and are inexpensive. In this preprocessing stage, primitive information per tile, such as the number of visible primitives, is accumulated. With this process, unnecessary resource consumption of invisible primitives, such as invisible primitive assembly, projection, clipping, and memory space will be saved, so that geometry overhead and memory usage of invisible primitives can be avoided.

Fig. 2 schematically shows a schematic block diagram of utilizing primitive visibility information for load balancing in a TBDR mode according to an embodiment of the present disclosure.

In the case of a GPU system with multiple processors, the central dispatch unit can read the visible primitive information generated by the position-only related stages. This information can include the number of visible primitives per screen tile, which the GPU scheduler can process through a dynamic scheduling algorithm to output the best tile group options for scheduling.

As shown in Figure 2, the respective operations of GPU instance 0, GPU instance 1, ..., GPU instance N correspond to the operations of the rendering stage shown in Figure 1, and the GPU scheduler can receive the number of visible primitives in each tile , and then schedule according to the number of visible primitives. For example, in one example, the system has 2 processor cores, and the screen is divided into 4 tiles - tile 0 to tile 3, and the number of visible primitives of each tile is 100, 200, 300 and 400 respectively , then the GPU scheduler may dispatch tiles 0 and 3 to processor core 0 and tiles 1 and 2 to processor core 1 . Therefore, each processor core will process 500 primitives.

Scheduling is performed at a tile-based granularity, i.e., the GPU scheduler dispatches to individual GPU instances in units of tiles (e.g., one or more tiles), which is much more efficient than complex vertex buffer preprocessing .

The GPU scheduler can efficiently use per-tile visible primitive information to schedule geometry workloads to multiple processors for load balancing. Thanks to the position-only phase, the GPU scheduler can have final sub-primitive visibility even with geometry magnification (tessellation or geometry shading) enabled for better load-balanced scheduling, avoiding vertex buffers scanning.

Therefore, in a multi-processor GPU system, the process shown in Figure 2 makes better use of GPU computing resources and achieves higher geometry processing performance.

Fig. 3 schematically shows a block diagram of an apparatus 300 for TBDR according to an embodiment of the present disclosure.

Referring to FIG. 3 , an apparatus 300 for TBDR may at least include a visibility engine 301 and a scheduler 302 . In one example, the visibility engine 301 may be a visibility engine as shown in FIG. 1 , which is configured to generate primitive visibility information for each tile in a position-only phase. In one example, the scheduler 302 may be a GPU scheduler as shown in FIG. 2, which is configured to perform scheduling for multiple processor cores based on primitive visibility information from the visibility engine 301 before the rendering stage. .

As an example, the visibility engine 301 may be further configured to accumulate the number of visible primitives for each tile and include the number in the primitive visibility information. Scheduling by scheduler 302 may be performed based on the number included in the primitive visibility information.

As a further example, the scheduler 302 may be further configured to evenly distribute the total number of visible primitives on the plurality of processor cores.

As an example, scheduling by scheduler 302 may be performed at a tile-based granularity.

As an example, scheduler 302 may extract primitive visibility information for individual tiles to align it with geometry data such that only visible primitives enter the rendering stage.

As an example, the rendering stage may include clipping and projection operations, but not culling operations, since invisible primitives were previously discarded.

Some components are illustrated as separate units in FIG. 3 . However, this only indicates that the functionality is separated. These units may be provided as separate elements. However, other arrangements are also possible, eg some of them can be combined into one unit. Any combination of elements may be implemented in any combination of software, hardware and/or firmware, where appropriate. For example, there could be more controllers configured separately, or only one controller for all components.

The components shown in FIG. 3 may constitute machine-executable instructions embodied, for example, on a machine-readable medium, which, when executed by a machine, will cause the machine to perform the operations described. Furthermore, any of these units may be implemented as hardware, such as an Application Specific Integrated Circuit (ASIC), Digital Signal Processor (DSP), Field Programmable Gate Array (FPGA), or the like.

Fig. 4 schematically shows a flowchart of a method 400 for TBDR according to an embodiment of the present disclosure.

In one example, at block 401 , primitive visibility information for each tile is generated in a position-only phase. At block 402, scheduling for multiple processor cores is performed based on primitive visibility information prior to a rendering stage.

As an example, generating the primitive visibility information may further include accumulating the number of visible primitives for each tile and including the number in the primitive visibility information. Scheduling can be performed based on this number.

As a further example, scheduling may be performed by evenly distributing the total number of visible primitives across the plurality of processor cores.

As an example, scheduling may be performed at a tile-based granularity.

As an example, primitive visibility information may be extracted to align with geometry data such that only visible primitives enter the rendering stage.

As an example, the rendering stage may include clipping and projection operations, but not culling operations.

Fig. 5 schematically shows a block diagram of a device 500 for TBDR according to an embodiment of the present disclosure.

Referring to FIG. 5 , an apparatus 500 for TBDR may include at least a processor 501 , a memory 502 , an interface 503 and a communication medium 504 . Processor 501 , memory 502 and interface 503 may be communicatively coupled to each other via communication medium 504 .

Processor 501 may include one or more processing units. A processing unit may be a physical device or article of manufacture comprising one or more integrated circuits that read data and instructions from a computer-readable medium, such as memory 502 , and selectively execute the instructions. In various embodiments, the processor 501 may be implemented in various ways. As an example, processor 501 may be implemented as one or more processing cores. As another example, processor 501 may include one or more discrete microprocessors. In yet another example, the processor 501 may include an Application Specific Integrated Circuit (ASIC) that provides specific functions. In yet another example, the processor 501 may provide specific functions by using an ASIC and/or by executing computer-executable instructions.

Memory 502 may include one or more computer-usable or computer-readable storage media capable of storing data and/or computer-executable instructions. It should be understood that preferably, the storage medium may be a non-transitory storage medium.

The interface 503 may be a device or an article of manufacture that enables the device for TBDR 500 to transmit data to or receive data from an external device.

Communication medium 504 may facilitate communication between processor 501 , memory 502 and interface 503 . Communications medium 504 can be implemented in various ways. For example, communication media 504 may include a Peripheral Component Interconnect (PCI) bus, a PCI Express bus, an Accelerated Graphics Port (AGP) bus, a Serial Advanced Technology Attachment (ATA) interconnect, a Parallel ATA interconnect, a Fiber Channel interconnect, a USB bus, Small Computing System Interface (SCSI) interface, or other type of communication medium.

In the example of FIG. 5 , the instructions stored in the memory 502 may include instructions that when executed by the processor 501 cause the apparatus for TBDR 500 to implement the method described with respect to FIG. 4 .

Embodiments of the present disclosure may be articles of manufacture in which one or more signal processing components (generally referred to herein as "processors") programmed to perform the operations described above are stored on a non-transitory machine-readable medium, such as a microelectronic memory. instructions (for example, computer code). In other embodiments, some of these operations may be performed by specific hardware components containing hardwired logic (eg, dedicated digital filter blocks and state machines). Alternatively, these operations may be performed by any combination of programmed signal processing components and fixed hardwired circuit components.

It should be appreciated that certain features of the application which are, for clarity, described in the context of separate embodiments, may also be provided in combination in a single embodiment. Conversely, various features of the application which are, brevity, described in the context of a single embodiment, may also be provided separately or in any suitable subcombination or as appropriate in any other embodiment of the application. Certain features described in the context of various embodiments should not be considered essential features of those embodiments, unless the embodiment is not effective without those elements.

In the foregoing detailed description, embodiments of the present disclosure have been described with reference to specific exemplary embodiments thereof. It will be apparent that various modifications may be made to the embodiments of the present disclosure without departing from the spirit and scope of the present disclosure as set forth in the appended claims. Accordingly, the specification and drawings are to be regarded as illustrative rather than restrictive.

Throughout the specification, some embodiments of the disclosure have been presented through flow diagrams. It should be understood that the order of operations depicted in these flowcharts is for illustration purposes only and is not intended as a limitation of the present disclosure. Those skilled in the art will appreciate that changes to the flow diagrams can be made without departing from the spirit and scope of the present disclosure as set forth in the appended claims.

Claims (14)

1. A device for delayed rendering based on tiles, characterized in that the device comprises: a visibility engine configured to generate primitive visibility information for each tile in the position-only phase; and A scheduler configured to perform scheduling for multiple processor cores based on the primitive visibility information before a rendering stage. 2. The apparatus of claim 1, wherein the visibility engine is further configured to accumulate a number of visible primitives per tile and include the number in the primitive visibility information, and wherein The scheduling is performed based on the number. 3. The apparatus of claim 2, wherein the scheduler is further configured to evenly distribute the total number of visible primitives across the plurality of processor cores. 4. The apparatus of any one of claims 1 to 3, wherein scheduling for the plurality of processor cores is performed at a tile-based granularity. 5. The apparatus of any one of claims 1 to 3, wherein the primitive visibility information is extracted to align with geometric data such that only visible primitives enter the rendering stage. 6. The apparatus of any one of claims 1 to 3, wherein the rendering stage includes clipping and projection, but not culling. 7. A method for deferred rendering based on tiles, characterized in that the method comprises: Generating primitive visibility information for each tile in a position-only phase; and Scheduling for multiple processor cores is performed based on the primitive visibility information prior to a rendering stage. 8. The method of claim 7, wherein generating primitive visibility information for each tile further comprises accumulating a number of visible primitives per tile and including the number in the primitive visibility information, and wherein performing scheduling for the plurality of processor cores further includes performing scheduling based on the number. 9. The method of claim 8, wherein performing scheduling for the plurality of processor cores further comprises evenly distributing a total number of visible primitives across the plurality of processor cores. 10. The method of any one of claims 7 to 9, wherein performing scheduling for the plurality of processor cores further comprises performing scheduling at a tile-based granularity. 11. The method of any one of claims 7 to 9, wherein the primitive visibility information is extracted to align with geometric data such that only visible primitives enter the rendering stage. 12. A method according to any one of claims 7 to 9, wherein the rendering stage comprises clipping and projection but not culling. 13. A device for tile-based deferred rendering, characterized in that the device comprises: processor; and a memory, communicatively connected to the processor and adapted to store instructions which, when executed by the processor, cause the device to perform the steps of the method according to any one of claims 7 to 12 operate. 14. A computer-readable medium having stored thereon instructions which, when executed, cause a processor of an apparatus for tile-based deferred rendering to perform the method of any one of claims 7 to 12 .

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