CN115774972A - System and method for consistency check of system-in-package design - Google Patents

System and method for consistency check of system-in-package design Download PDF

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CN115774972A
CN115774972A CN202211535990.XA CN202211535990A CN115774972A CN 115774972 A CN115774972 A CN 115774972A CN 202211535990 A CN202211535990 A CN 202211535990A CN 115774972 A CN115774972 A CN 115774972A
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integrated circuit
data
design
package
parameter
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CN115774972B (en
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徐利锋
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Xinyaohui Technology Co ltd
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Xinyaohui Technology Co ltd
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Abstract

The application relates to the technical field of computers, and provides a system and a method for consistency check of system-in-package design. The system comprises: a processor; and a memory coupled with the processor, the memory storing executable instructions, the processor causing the system to perform the following by executing the executable instructions: obtaining a first parameter item and a second parameter item of a parameter indicative of a same physical layout characteristic of a same integrated circuit, wherein the first parameter item and the second parameter item are based on design data and package data of the integrated circuit, respectively; and calculating a consistency check result between the design data and the packaging data according to a first confidence score and a second confidence score which respectively correspond to the first parameter item and the second parameter item of the parameters. Thus, the complexity and cost of chip packaging are reduced, and the overall efficiency of chip design and manufacture is improved.

Description

System and method for consistency check of system-in-package design
Technical Field
The present application relates to the field of computer technologies, and in particular, to a system and method for consistency check of system-in-package design.
Background
The chip design stage is upstream relative to the chip manufacturing stage. The chip design data after the chip design is completed is transmitted to a chip manufacturer located downstream, also called a foundry. The chip manufacturing process can be further divided into wafer on-chip circuit processing and packaging test. The packaging test refers to cutting a wafer silicon wafer with a processed circuit into individual chip particles and completing shell packaging and terminal test to obtain a chip finished product. With the development of chip manufacturing processes and packaging processes, in a packaging test link, packaging cost and packaging connection complexity are both improved, for example, a packaging process standard is developed from a 2.5D packaging technology to a 3D packaging technology, and the 3D packaging technology refers to a packaging technology in which more than two chips are stacked in a vertical direction in the same package on the premise of not changing the size of the package. In addition, new packaging technologies, such as chip (chiplet) packaging, are rapidly developing, wherein the chip packaging technology is to divide each component originally integrated in a single system-on-chip into a plurality of functional chips, and separately manufacture the functional chips and then interconnect and package the functional chips into a system-on-chip set.
To this end, the embodiments of the present application provide a system and a method for consistency check of a system-in-package design, so as to reduce the complexity and cost of a chip package and improve the overall efficiency of chip design and manufacturing.
Disclosure of Invention
The embodiment of the application provides a system and a method for consistency check of a system-in-package design, which are used for reducing the complexity and cost of chip packaging and improving the overall efficiency of chip design and manufacture.
In a first aspect, the present application provides a system. The system comprises: a processor; and a memory coupled with the processor, the memory storing executable instructions, the processor causing the system to perform the following by executing the executable instructions: obtaining a first parameter item and a second parameter item of a parameter indicative of a same physical layout characteristic of a same integrated circuit, wherein the first parameter item and the second parameter item are based on design data and package data of the integrated circuit, respectively; and calculating a consistency check result between the design data and the packaging data according to a first confidence score and a second confidence score which respectively correspond to the first parameter item and the second parameter item of the parameter.
Through the first aspect of the application, the complexity and the cost of chip packaging are reduced, and the overall efficiency of chip design and manufacture is improved.
In one possible implementation form of the first aspect of the present application, the parameter is a data format, the first parameter item is a data format of design data of the integrated circuit, and the second parameter item is a data format of package data of the integrated circuit.
In one possible implementation of the first aspect of the present application, the parameter is a boundary layer size, the first parameter item is a boundary layer size indicated by design data of the integrated circuit, and the second parameter item is a boundary layer size indicated by package data of the integrated circuit.
In one possible implementation of the first aspect of the application, the parameter is a boundary layer shape, the first parameter item is a boundary layer shape indicated by design data of the integrated circuit, and the second parameter item is a boundary layer shape indicated by package data of the integrated circuit.
In a possible implementation manner of the first aspect of the present application, the physical layout characteristics are associated with a physical layout of the integrated circuit, the parameters include a data format, a boundary layer size, and a boundary layer shape, the first parameter items include a data format of design data of the integrated circuit, a boundary layer size indicated by the design data of the integrated circuit, and a boundary layer shape indicated by the design data of the integrated circuit, and the second parameter items include a data format of package data of the integrated circuit, a boundary layer size indicated by the package data of the integrated circuit, and a boundary layer shape indicated by the package data of the integrated circuit.
In one possible implementation of the first aspect of the present application, the design data of the integrated circuit includes a signature graph data system, and the package data of the integrated circuit includes a package graph data system.
In one possible implementation manner of the first aspect of the present application, the operations further include: and merging the signoff graphic data system included in the design data of the integrated circuit and the packaging graphic data system included in the packaging data of the integrated circuit so as to obtain a merged graphic data system.
In one possible implementation of the first aspect of the present application, the parameter is a port number, the first parameter item is a port number indicated by design data of the integrated circuit, and the second parameter item is a port number indicated by package data of the integrated circuit.
In a possible implementation manner of the first aspect of the present application, the parameter is an inter-port connection relationship, the first parameter item is an inter-port connection relationship indicated by design data of the integrated circuit, and the second parameter item is an inter-port connection relationship indicated by package data of the integrated circuit.
In one possible implementation manner of the first aspect of the present application, the parameter is a port naming rule, the first parameter item is a port naming rule of design data of the integrated circuit, and the second parameter item is a port naming rule of package data of the integrated circuit.
In a possible implementation manner of the first aspect of the present application, the physical layout characteristics are associated with a circuit diagram of the integrated circuit, the first parameter item includes the number of ports indicated by the design data of the integrated circuit, the connection relationship between ports indicated by the design data of the integrated circuit, and a port naming rule of the design data of the integrated circuit, and the second parameter item includes the number of ports indicated by the package data of the integrated circuit, the connection relationship between ports indicated by the package data of the integrated circuit, and a port naming rule of the package data of the integrated circuit.
In one possible implementation of the first aspect of the present application, the design data of the integrated circuit includes an integrated circuit design netlist of the integrated circuit, and the package data of the integrated circuit includes a port mapping file of the integrated circuit.
In one possible implementation manner of the first aspect of the present application, the operations further include: and merging the integrated circuit design netlist of the integrated circuit included in the design data of the integrated circuit and the port mapping file of the integrated circuit included in the packaging data of the integrated circuit so as to obtain a merged netlist file.
In one possible implementation manner of the first aspect of the present application, calculating a consistency check result between the design data and the package data includes: and comparing the port quantity and the connection relation among the ports indicated by the integrated circuit design netlist of the integrated circuit and the port quantity and the connection relation among the ports indicated by the port mapping file of the integrated circuit so as to determine whether a port merging operation and/or a port deleting operation exists or not.
In a possible implementation manner of the first aspect of the present application, the design data of the integrated circuit further includes a check graph data system, the package data of the integrated circuit further includes a package graph data system, the check graph data system included in the design data of the integrated circuit and the package graph data system included in the package data of the integrated circuit are merged to obtain a merged graph data system, where calculating a consistency check result between the design data and the package data further includes: when it is determined that the port merging operation and/or the port deleting operation exist, determining the reasonableness of the port merging operation and/or the port deleting operation based on the merged graphic data system.
In a possible implementation manner of the first aspect of the present application, the physical layout characteristics further relate to a circuit layout matching LVS of the integrated circuit, the design data of the integrated circuit further includes a design rule manual of the integrated circuit, the package data of the integrated circuit further includes a signature circuit layout matching LVS rule of the integrated circuit, the first parameter item includes a plurality of package levels determined based on the design rule manual of the integrated circuit and a through hole connection relationship between the plurality of package levels, and the second parameter item includes a signature LVS rule based on the integrated circuit and a LVS check rule determined based on a package process standard.
In a possible implementation manner of the first aspect of the present application, the physical layout characteristics are associated with a physical layout of the integrated circuit, a circuit diagram of the integrated circuit, and an LVS of the integrated circuit, the design data of the integrated circuit includes a signature graph data system, an integrated circuit design netlist of the integrated circuit, and a design rule manual of the integrated circuit, and the package data of the integrated circuit includes a package graph data system, a port mapping file of the integrated circuit, and a signature LVS rule of the integrated circuit.
In a second aspect, the present application provides a method for consistency checking of a system-in-package design. The method comprises the following steps: obtaining a first parameter item and a second parameter item for each of a plurality of parameters, wherein each of the plurality of parameters indicates one of a plurality of physical layout characteristics of the same integrated circuit, the first parameter item and the second parameter item for each of the plurality of parameters being based on design data and package data, respectively, of the integrated circuit; for each of the plurality of parameters, calculating a consistency check result between the design data and the package data according to a first confidence score and a second confidence score corresponding to a first parameter item and a second parameter item of the parameter, respectively.
In one possible implementation manner of the second aspect of the present application, the plurality of physical layout characteristics are respectively associated with a physical layout of the integrated circuit, a circuit diagram of the integrated circuit, and an LVS of the integrated circuit, and the plurality of parameters include: data format, boundary layer size, boundary layer shape, port number, connection relation between ports and port naming rule.
In one possible implementation manner of the second aspect of the present application, the design data of the integrated circuit includes a signature graph data system, an integrated circuit design netlist of the integrated circuit, and a design rule manual of the integrated circuit, and the package data of the integrated circuit includes a package graph data system, a port mapping file of the integrated circuit, and a signature LVS rule of the integrated circuit.
In one possible implementation manner of the second aspect of the present application, the first parameter item of a given parameter in the plurality of parameters includes a plurality of package levels determined based on a design rule manual of the integrated circuit and a via connection relationship between the plurality of package levels, and the second parameter item of the given parameter includes an LVS check rule determined based on a signature LVS rule and a package process standard of the integrated circuit.
In a third aspect, an embodiment of the present application further provides a computer device, where the computer device includes a memory, a processor, and a computer program stored on the memory and executable on the processor, and the processor implements the method according to any implementation manner of any one of the above aspects when executing the computer program.
In a fourth aspect, embodiments of the present application further provide a computer-readable storage medium storing computer instructions that, when executed on a computer device, cause the computer device to perform the method according to any one of the implementation manners of any one of the above aspects.
In a fifth aspect, the present application further provides a computer program product, which includes instructions stored on a computer-readable storage medium, and when the instructions are run on a computer device, the computer device is caused to execute the method according to any one of the implementation manners of any one of the above aspects.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic diagram of an overall process of chip design and manufacture according to an embodiment of the present application;
fig. 2 is a schematic diagram of a system for consistency checking of a system-in-package design according to an embodiment of the present application;
fig. 3 is a schematic flowchart of a method for checking consistency of a system in package design according to an embodiment of the present application;
fig. 4 is a schematic structural diagram of a computing device according to an embodiment of the present application.
Detailed Description
Embodiments of the present application will be described in further detail below with reference to the accompanying drawings.
The embodiment of the application provides a system and a method for consistency check of system-in-package design, which are used for solving the problems in the prior art, namely how to reduce the complexity and cost of chip packaging and improve the overall efficiency of chip design and manufacture. The method and the device provided by the embodiment of the application are based on the same inventive concept, and because the principles of solving the problems of the method and the device are similar, the embodiments, the implementation modes, the examples or the implementation modes of the method and the device can be mutually referred, and repeated parts are not described again.
It should be understood that in the description of the present application, "at least one" means one or more than one, and "a plurality" means two or more than two. Additionally, the terms "first," "second," and the like, unless otherwise indicated, are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or order.
Fig. 1 is a schematic diagram of an overall process of chip design and manufacturing according to an embodiment of the present disclosure. A chip is also called an Integrated Circuit (IC), and refers to a circuit in which a large number of various elements such as transistors, diodes, resistors, capacitors, and inductors, and wiring are integrated on a wafer by a semiconductor process to have a specific function. Wherein Very Large Scale Integration (VLSI) circuits can integrate millions of transistors on a micron-sized silicon die and the complex wiring between these transistors. As shown in FIG. 1, the overall process of chip design manufacturing includes specification definition 102, system design 104, front-end design 106, back-end design 108, front-end production 110, and back-end production 112. The specification definition 102 refers to setting the purpose and performance of the chip and the protocol standard that needs to be satisfied, that is, determining the requirement analysis of the chip and determining the overall design direction, such as determining the cost control level, the power consumption sensitivity, the supported connection mode, the system security level, etc. The system design 104 refers to further determining the chip architecture, the service module, the power supply system, and other designs based on the purpose, performance, and requirement of the chip determined in the specification definition 102, that is, performing function allocation and unit division, for example, determining the interaction between various systems, specific interfaces, and the like. The front-end design 106 refers to a specific circuit design for each module according to the scheme determined in the system design 104, and specifically includes: code description of Register Transfer Level (RTL) is performed on hardware behaviors, structures and data streams of a circuit system by using a Hardware Description Language (HDL) such as Verilog HDL; after the code is generated, performing simulation verification according to a previously established specification standard, for example, verifying the correctness of the code design through an Electronic Design Automation (EDA) tool; finally, the code description of the RTL is converted into a gate-level netlist (netlist) through the automatic synthesis function of a logic synthesis tool such as an EDA tool, and whether circuit parameters such as time sequence, area and the like reach the standard or not is determined. The back-end design 108 refers to performing circuit layout (floor plan) and routing (routing) according to a given silicon wafer area on the basis of the netlist obtained by converting the front-end design 106 to obtain a specific circuit wiring structure, and performing various verification of functions and timing sequences on a physical layout of the circuit wiring structure. The specification definition 102, the system design 104, the front-end design 106 and the back-end design 108 are collectively referred to as a chip design link, and chip design data obtained by completing the chip design in the chip design link is transmitted to a downstream chip manufacturer. The chip manufacturing process includes a front end 110 and a back end 112. Front End Of Line (FEOL) 110 refers to a series Of processes including photolithography, thin film processing, etching, cleaning, implantation, etc. performed on a silicon wafer (wafer) to process and create a circuit on the wafer. Back End Of Line (BEOL) 112 refers to filling through holes and manufacturing electrical connection lines between transistors on the basis Of the processed silicon wafer obtained in the front End Of Line 110, and performing cutting and packaging to obtain a finished chip. In the back-end production 112, as the packaging process is developed, the packaging complexity and the packaging cost are both increased. For example, recently developed 3D packaging technology, the 3D packaging technology refers to a packaging technology in which two or more chips are stacked in a vertical direction in the same package without changing the size of the package, and for example, a chip (chip) is also called a small chip packaging technology, the chip packaging technology refers to a technology in which each component originally integrated in a single system chip is divided into a plurality of chips with specific functions, and the chips are separately manufactured and then interconnected and packaged into a system chip set. Chip packaging and testing involved in back-end production 112 is increasingly important to ensure the quality of the final chip product, and sometimes chip packaging and testing are separately divided into chip packaging and testing, so that the whole process of chip product is divided into chip design, chip manufacturing and chip packaging and testing.
Referring to fig. 1, the whole process of the chip finished product has definite division of labor and is often entrusted to different manufacturers, the chip design process is generally handed to the Semiconductor Company without factory (the factory Semiconductor Company) to design the circuit of the hardware chip, the chip manufacturing or front-end production 110 is handed to the foundry for wafer fabrication to manufacture the chip finished product, and the chip encapsulation or back-end production 112 is also responsible for manufacturers and encapsulation engineers who specially perform chip encapsulation. Therefore, chip design data obtained after the chip design is completed in the chip design link may be handed to a packaging and testing manufacturer who adopts different packaging technologies and different packaging process standards, and therefore, a technical problem that whether the chip design data is adapted to the packaging and testing manufacturer who is specifically responsible for chip packaging may be faced. For example, in a chip design link, connection holes for subsequent chip packaging are generally well arranged, but a packaging engineer of a packaging manufacturer who is particularly responsible for chip packaging may adjust the well arranged connection holes, for example, re-connect the connection holes, according to a specific packaging requirement, for example, a specific packaging technology adopted by the packaging manufacturer. In addition, there are often various sign off checks in the chip design data, which represent the final checks after the front-end design 106 and the back-end design 108 are completed, but these sign off checks are still limited to the information that can be obtained in the chip design link, for example, the back-end design 108 is a specific circuit wiring structure obtained by performing circuit layout (floor plan) and routing (routing) according to a given silicon wafer area on the basis of a netlist obtained by converting the front-end design 106, and performs various verifications of functions and timing sequences on a physical layout of the circuit wiring structure. Therefore, various signing checks and information contained in the chip design data generally cannot reflect the packaging requirements caused by the specific packaging technology and packaging process standard adopted by the subsequent chip packaging. In addition, circuit Layout matching (LVS) check is generally performed in a chip design link, but the LVS check mainly compares connectivity, output and the like between a circuit or a logic diagram and a Layout, and is still limited to information that can be obtained in the chip design link, and therefore, a package requirement caused by a specific package technology and a package process standard adopted by subsequent chip packaging cannot be reflected. To this end, the present application provides a system and method for consistency checking of a system-in-package design, which can ensure consistency from chip design data to chip package data for chip package testing, as described in further detail below with reference to fig. 2.
Fig. 2 is a schematic diagram of a system for consistency check of a system-in-package design according to an embodiment of the present application. As shown in fig. 2, the system includes: a processor 202; and a memory 204 coupled to the processor 202, the memory 204 storing executable instructions 206, the processor 202 by executing the executable instructions 206 to cause the system to: obtaining a first parameter item 210 and a second parameter item 212 of parameters indicative of a same physical layout characteristic of a same integrated circuit, wherein the first parameter item 210 and the second parameter item 212 are based on design data and package data, respectively, of the integrated circuit; calculating a consistency check result between the design data and the package data according to a first confidence score and a second confidence score corresponding to the first parameter item 210 and the second parameter item 212 of the parameter, respectively. As exemplarily shown in fig. 2, a first parameter item 210 and a second parameter item 212 are also stored in the memory 204. It should be understood that in some embodiments, the first parameter item 210 and the second parameter item 212 may be stored separately in a dedicated memory, possibly in the same data memory, or in different data memories, respectively. In some embodiments, the system may include a first data store for storing first parameter items 210 based on design data of the integrated circuit, and a second data store for storing second parameter items 212 based on packaging data of the integrated circuit. In addition, the system may obtain a plurality of parameters each indicative of a physical layout characteristic of the integrated circuit, wherein two parameters may be indicative of the same physical layout characteristic or different physical layout characteristics. And for the plurality of parameters, obtaining a first parameter item and a second parameter item for each of the plurality of parameters. The first parameter item and the second parameter item of each of the plurality of parameters thus obtained may be stored and processed with reference to the first parameter item 210 and the second parameter item 212 described above.
With reference to fig. 2, the chip design data of the same integrated circuit refers to the chip design data obtained after the circuit design of the integrated circuit is completed in the chip design link, including the completion of the specification definition, the system design, the front-end design and the back-end design of the integrated circuit, and specific details may refer to the specification definition 102, the system design 104, the front-end design 106 and the back-end design 108 shown in fig. 1, which are not described herein again. The chip design data of the integrated circuit obtained in this way, referred to as the design data of the integrated circuit for short, contains information such as various check checks and well-laid connection holes. The package data of the integrated circuit refers to chip package data used for a package test of the integrated circuit, which embodies the package requirements caused by a specific package technology and a package process standard used for the integrated circuit. Here, by obtaining a first parameter item 210 and a second parameter item 212 indicating parameters of the same physical layout characteristic of the same integrated circuit, wherein the first parameter item 210 and the second parameter item 212 are based on design data and package data of the integrated circuit, respectively, a consistency check of the design data and the package data for the same physical layout characteristic of the integrated circuit is achieved. Specifically, the physical layout characteristics of the integrated circuit may be divided into three dimensions of consideration, which may be performed separately, together, in parallel, or not in parallel. These three dimensions of consideration are the physical Layout of the integrated circuit, the circuit diagram of the integrated circuit and the circuit Layout matching of the integrated circuit (LVS), respectively. The physical layout of the integrated circuit is related to a silicon wafer used for processing and manufacturing the integrated circuit, and includes information such as a layer defining a boundary of the integrated circuit, that is, a boundary layer (Chip boundary layer), a size of the boundary layer, a shape of the boundary layer, and the like. The circuit diagram of the integrated circuit is related to the circuit logic diagram of the integrated circuit, and comprises information such as port number and port name respectively embodied in design data and packaging data. The LVS of the integrated circuit relates to LVS inspection performed in a chip design link, but as described above, the LVS inspection mainly compares connectivity, output, and the like between a circuit and a layout, and is still limited to information that can be obtained in the chip design link, and thus, a packaging requirement caused by a specific packaging technology and a packaging process standard adopted by subsequent chip packaging cannot be reflected. Therefore, the LVS of the integrated circuit also relates to how to make LVS check rules applicable to the encapsulation link for the integrated circuit by combining with specific packaging process standards.
In summary, the system shown in fig. 2 enables a consistency check of design data and package data for the same physical layout characteristic of the integrated circuit by obtaining a first parameter item 210 and a second parameter item 212 indicating parameters of the same physical layout characteristic of the same integrated circuit, wherein the first parameter item 210 and the second parameter item 212 are based on design data and package data, respectively, of the integrated circuit. The same physical layout characteristic may be one, two, or all three dimensions selected from three dimensions (the physical layout of the integrated circuit, the circuit diagram of the integrated circuit, and the LVS of the integrated circuit), which may be performed separately, together, in parallel, or not in parallel, so that the obtained first parameter item 210 and the second parameter item 212 indicating the parameter of the same physical layout characteristic of the same integrated circuit respectively represent the consistency of the design data and the package data in the selected dimension. And further, the system shown in fig. 2 calculates the consistency check result between the design data and the package data based on the first confidence score and the second confidence score corresponding to the first parameter item 210 and the second parameter item 212 of the parameter, respectively, so that it is possible to judge whether the design data and the package data are matched based on a specific flexible judgment criterion. Therefore, the system shown in fig. 2 provides a technical solution for consistency check of a system-in-package design, which can ensure consistency from chip design data to chip package data for chip package testing, and is beneficial to reducing complexity and cost of chip packaging and improving overall efficiency of chip design and manufacturing, and can flexibly adapt to specific packaging technologies and packaging process standards adopted by different chip package testing manufacturers and adapt to specific evaluation standards, and is beneficial to dealing with characteristics of high division of labor in the integrated circuit industry and a trend of rapid development of packaging processes.
In one possible implementation, the physical layout characteristics are associated with a physical layout of the integrated circuit, the parameters include a data format, a boundary layer size, and a boundary layer shape, the first parameter items include a data format of design data of the integrated circuit, a boundary layer size indicated by the design data of the integrated circuit, and a boundary layer shape indicated by the design data of the integrated circuit, and the second parameter items include a data format of package data of the integrated circuit, a boundary layer size indicated by the package data of the integrated circuit, and a boundary layer shape indicated by the package data of the integrated circuit. Here, the physical layout of the integrated circuit is associated with a silicon wafer used to process and manufacture the integrated circuit, and a boundary layer (Chip boundary layer) refers to a layer that defines a boundary of the integrated circuit. The data format refers to a data format adopted by each of the design data and the package data, and may be a GDS format or an OASIS format, or another format. By obtaining a first parameter item and a second parameter item of a parameter corresponding to a physical layout characteristic associated with the physical layout of the integrated circuit, and calculating a consistency check result between the design data and the packaging data according to a first confidence score and a second confidence score respectively corresponding to the first parameter item and the second parameter item, consistency between the design data and the packaging data is ensured in the dimension of the physical layout of the integrated circuit.
In some embodiments, the parameter is a data format, the first parameter item is a data format of design data of the integrated circuit, and the second parameter item is a data format of package data of the integrated circuit. In this manner, the data format can be considered separately and consistency between the design data and the package data can be ensured.
In some embodiments, the parameter is boundary layer size, the first parameter item is boundary layer size indicated by design data of the integrated circuit, and the second parameter item is boundary layer size indicated by packaging data of the integrated circuit. In this manner, boundary layer size can be considered separately and consistency between design data and package data is ensured.
In some embodiments, the parameter is a boundary layer shape, the first parameter item is a boundary layer shape indicated by design data of the integrated circuit, and the second parameter item is a boundary layer shape indicated by packaging data of the integrated circuit. In this way, the boundary layer shape can be considered separately and consistency between design data and package data can be ensured.
In one possible implementation, the design data for the integrated circuit includes a signature graph data system and the package data for the integrated circuit includes a package graph data system. Here, the sign off graphics data system (sign off GDS) refers to a Graphics Data System (GDS) for final sign off in design data, and represents a circuit layout of each level as an input data of an EDA tool as a data conversion format of the circuit layout. The signature and verification graphic data system of design data is sign off GDS or signature and verification GDS which is checked in the chip design link. A package graphics data system (package GDS) refers to a GDS for package inspection of package data. Therefore, the design data includes a signature graphic data system, i.e., a signature GDS, which is checked by signature in a chip design step, and the package data includes a GDS for package check in a chip package test step. In some embodiments, the operations further comprise: and merging the signoff graphic data system included in the design data of the integrated circuit and the packaging graphic data system included in the packaging data of the integrated circuit so as to obtain a merged graphic data system. Therefore, the GDSs of the design data and the package data are combined to obtain a combined GDS. And, the GDS of the design data and the GDS of the package data are used together to consider the data format, the boundary layer size, and the boundary layer shape and to ensure consistency between the design data and the package data. That is, the first parameter item is based on the GDS of the design data, i.e., the signed GDS, and the second parameter item is based on the GDS of the package data, i.e., the packaged GDS, by performing a consistency check and answering the following questions: whether the data formats are consistent (e.g., both GDS format or OASIS format), whether the boundary layer sizes are consistent, and whether the boundary layer shapes are consistent. Therefore, consistency between design data and packaging data is ensured on the dimensionality of the physical layout of the integrated circuit, and a signoff graph data system included by the design data of the integrated circuit and a packaging graph data system included by the packaging data of the integrated circuit are further merged to obtain a merged graph data system.
In one possible implementation, the physical layout characteristics are associated with a circuit diagram of the integrated circuit, the first parameter items include the number of ports indicated by design data of the integrated circuit, inter-port connection relationships indicated by the design data of the integrated circuit, and port naming rules of the design data of the integrated circuit, and the second parameter items include the number of ports indicated by package data of the integrated circuit, inter-port connection relationships indicated by the package data of the integrated circuit, and port naming rules of the package data of the integrated circuit. The circuit diagram of the integrated circuit is related to the circuit logic diagram of the integrated circuit, and specifically includes the number of ports, the connection relationship between the ports and the port naming rule. With respect to the above-mentioned ensuring of consistency between design data and package data in dimensions of a physical layout of the integrated circuit, here, by the first parameter items including the number of ports indicated by the design data of the integrated circuit, the inter-port connection relationship indicated by the design data of the integrated circuit, and the port naming rule of the design data of the integrated circuit, and the second parameter items including the number of ports indicated by the package data of the integrated circuit, the inter-port connection relationship indicated by the package data of the integrated circuit, and the port naming rule of the package data of the integrated circuit, the ensuring of consistency between design data and package data in dimensions of a circuit diagram of the integrated circuit is achieved.
In some embodiments, the parameter is a number of ports, the first parameter item is a number of ports indicated by design data of the integrated circuit, and the second parameter item is a number of ports indicated by package data of the integrated circuit. In this manner, the number of ports can be considered individually and consistency between design data and package data can be ensured. For example, when the port number is inconsistent, if the port number indicated by the encapsulation data is greater than the port number indicated by the design data, it means that at least one port is added, and therefore an error or warning must be issued, because the encapsulation cannot add a port, and only merge ports or delete ports.
In some embodiments, the parameter is an inter-port connection relationship, the first parameter item is an inter-port connection relationship indicated by design data of the integrated circuit, and the second parameter item is an inter-port connection relationship indicated by package data of the integrated circuit. In this way, the connection relationship between ports can be considered separately and consistency between design data and package data can be ensured. For example, assuming that the ports VSS1 and VSS2 exist in the design data, but the interfaces corresponding to the two ports VSS1 and VSS2 are connected together in the package data, the schematic diagram may need to be modified and adjustments made accordingly.
In some embodiments, the parameter is a port naming convention, the first parameter item is a port naming convention for design data of the integrated circuit, and the second parameter item is a port naming convention for package data of the integrated circuit. In this manner, port naming rules can be considered separately and consistency between design data and encapsulation data is ensured.
In one possible embodiment, the design data of the integrated circuit includes an integrated circuit design netlist of the integrated circuit, and the package data of the integrated circuit includes a port map file of the integrated circuit. Here, the integrated circuit design netlist (IC design netlist) refers to a netlist obtained from the front-end design 106 shown in fig. 1, for example, that is, the code description of RTL is converted into a gate-level netlist by a logic synthesis tool for determining whether circuit parameters such as timing and area meet the standards. A port mapping file (port mapping file) refers to a file for encapsulation design in encapsulation data, which embodies an entity port mapping relationship. The first parameter item mentioned above includes the number of ports indicated by the design data of the integrated circuit, the inter-port connection relationship indicated by the design data of the integrated circuit, and the port naming rule of the design data of the integrated circuit, and may be based on an integrated circuit design netlist of the integrated circuit. The second parameter items comprise the number of ports indicated by the packaging data of the integrated circuit, the connection relation among the ports indicated by the packaging data of the integrated circuit and the port naming rule of the packaging data of the integrated circuit, and can be based on a port mapping file of the integrated circuit. In some embodiments, the operations further comprise: and merging the integrated circuit design netlist of the integrated circuit included in the design data of the integrated circuit and the port mapping file of the integrated circuit included in the packaging data of the integrated circuit so as to obtain a merged netlist file. Here, the merged netlist file represents an interconnection relationship between elements on the basis of the integrated circuit design netlist of the integrated circuit and the port mapping file of the integrated circuit.
In some embodiments, calculating the consistency check result between the design data and the package data comprises: and comparing the port number and the inter-port connection relation indicated by the integrated circuit design netlist of the integrated circuit and the port number and the inter-port connection relation indicated by the port mapping file of the integrated circuit so as to determine whether a port merging operation and/or a port deleting operation exist or not. Specifically, the encapsulation process may merge two different ports in the design data or connect one port to another port and then perform a port deletion operation. In some cases, it may be difficult to determine the correspondence between ports, and therefore, in combination with the merged graphic data system mentioned above, that is, after consistency between design data and package data is ensured in the dimension of the physical layout of the integrated circuit, the merged GDS obtained by merging the GDS of the design data and the GDS of the package data is used, and then the port of the original design data is used, the rationality of the port merging operation and/or the port deletion operation may be determined. In some embodiments, the design data of the integrated circuit further includes a signature graph data system, the package data of the integrated circuit further includes a package graph data system, and the signature graph data system included in the design data of the integrated circuit and the package graph data system included in the package data of the integrated circuit are merged to obtain a merged graph data system, where calculating the consistency check result between the design data and the package data further includes: when it is determined that the port merging operation and/or the port deleting operation exist, determining reasonableness of the port merging operation and/or the port deleting operation based on the merged graphic data system. Thus, after the consistency between the design data and the package data is ensured on the dimension of the physical layout of the integrated circuit, the consistency between the design data and the package data is further ensured on the dimension of the circuit diagram of the integrated circuit, and the merged GDS obtained by merging the GDS of the design data and the GDS of the package data after the consistency between the design data and the package data is ensured on the dimension of the physical layout of the integrated circuit is utilized, so that the technical problem that the corresponding relation between the ports is difficult to determine is overcome.
In a possible implementation manner, the physical Layout characteristics are further associated with a circuit Layout matching (LVS) of the integrated circuit, the design data of the integrated circuit further includes a design rule manual (design rule) of the integrated circuit, the package data of the integrated circuit further includes a signature circuit Layout matching LVS rule (signature off LVS rule) of the integrated circuit, the first parameter item includes a plurality of package levels determined based on the design rule manual of the integrated circuit and a through hole connection relationship between the plurality of package levels, and the second parameter item includes a LVS check rule determined based on the signature LVS rule and a package process standard of the integrated circuit. Here, the LVS of the integrated circuit relates to the LVS check performed in the chip design link, but as described above, the LVS check mainly compares connectivity, output, and the like between the circuit and the layout, and is still limited to information that can be obtained in the chip design link, and therefore, the packaging requirements caused by the specific packaging technology and the packaging process standard adopted in the subsequent chip packaging cannot be reflected. Therefore, the LVS of the integrated circuit also relates to how to make LVS check rules applicable to the encapsulation link for the integrated circuit by combining with specific packaging process standards. Specifically, the design data includes a design rule manual (design rule manual) of the integrated circuit, and the first parameter item based on the design data includes a plurality of package levels determined based on the design rule manual of the integrated circuit and via connection relationships between the plurality of package levels. For example, the first parameter item defines four package levels (package layers), and then defines three vias and the communication relationship of the three vias among the four package levels. The packaging data comprises a signature and verification LVS rule, and the second parameter item can establish an LVS check rule according to the signature and verification LVS rule and by combining with a specific packaging process standard of a foundry responsible for packaging and testing. The second parameter item thus represents how the specific foundry responsible for the sealing and testing implements the structure of multiple levels in the design data and the connection relationship between the levels.
In one possible implementation, the physical layout characteristics are associated with a physical layout of the integrated circuit, a circuit diagram of the integrated circuit, and an LVS of the integrated circuit, the design data of the integrated circuit includes a signature graph data system, an integrated circuit design netlist of the integrated circuit, and a design rule manual of the integrated circuit, and the package data of the integrated circuit includes a package graph data system, a port mapping file of the integrated circuit, and a signature LVS rule of the integrated circuit. As mentioned above, the consistency between design data and package data can be ensured from three dimensions of consideration, including the physical layout of the integrated circuit, the circuit diagram of the integrated circuit and the LVS of the integrated circuit, which can be performed together. Accordingly, the design data may include a signature graphic data system, an integrated circuit design netlist of the integrated circuit, and a design rule manual of the integrated circuit, and the package data may include a package graphic data system, a port mapping file of the integrated circuit, and a signature LVS rule of the integrated circuit. Thus, by considering the physical layout of the integrated circuit and the first parameter item and the second parameter item of the related parameters, the consistency between design data and packaging data on a macroscopic scale is ensured due to the alignment data format, the boundary layer size and the boundary layer shape; by considering the circuit diagram of the integrated circuit and the first parameter item and the second parameter item of the related parameters, the method realizes the alignment of the number of ports, the connection relation among the ports and the port naming rule, can further determine the reasonability of no new port in the packaging link and port merging operation and/or port deleting operation, and also ensures the consistency between design data and packaging data on the scale of the circuit logic diagram and the port interface; by considering the integrated circuit signature LVS rule and the first parameter item and the second parameter item of the related parameters, the solid geometry relationship between the alignment design data and the package data, including the connection relationship between the layers, is realized, and thus, the method can be applied to emerging packaging technologies such as a 3D packaging technology and a core packaging technology, and can also be applied to other packaging technologies appearing at the date of filing of the present application, as long as the operation principle does not conflict with the disclosure of the embodiments of the present application.
Fig. 3 is a flowchart illustrating a method for consistency check of a system-in-package design according to an embodiment of the present application. As shown in fig. 3, the method includes the following steps.
Step S310: a first parameter item and a second parameter item for each of a plurality of parameters are obtained, wherein each of the plurality of parameters is indicative of one of a plurality of physical layout characteristics of the same integrated circuit, the first parameter item and the second parameter item for each of the plurality of parameters being based on design data and package data, respectively, of the integrated circuit.
Step S320: for each of the plurality of parameters, calculating a consistency check result between the design data and the package data according to a first confidence score and a second confidence score corresponding to a first parameter item and a second parameter item of the parameter, respectively.
The method of fig. 3 enables a consistency check of design data and package data for the same physical layout characteristic of the integrated circuit by obtaining a first parameter item and a second parameter item for each parameter indicative of the same physical layout characteristic of the same integrated circuit, wherein the first parameter item and the second parameter item are based on design data and package data, respectively, of the integrated circuit. The same physical layout characteristic may be one, two, or all three dimensions selected from three dimensions (the physical layout of the integrated circuit, the circuit diagram of the integrated circuit, and the LVS of the integrated circuit), which may be performed separately, together, in parallel, or not in parallel, so that the obtained first parameter item and the second parameter item indicating the parameter of the same physical layout characteristic of the same integrated circuit respectively represent the consistency of the design data and the package data in the selected dimensions. And further, the method shown in fig. 3 calculates the consistency check result between the design data and the package data according to the first confidence score and the second confidence score respectively corresponding to the first parameter item and the second parameter item of the parameter, so that it is possible to judge whether the design data and the package data are matched according to a specific flexible judgment criterion. Therefore, the method shown in fig. 3 provides a technical solution for consistency check of a system-in-package design, which can ensure consistency from chip design data to chip package data for chip package testing, and is beneficial to reducing complexity and cost of chip packaging and improving overall efficiency of chip design and manufacturing, and can flexibly adapt to specific packaging technologies and packaging process standards adopted by different chip package testing manufacturers and adapt to specific evaluation standards, and is beneficial to dealing with characteristics of high division of labor in the integrated circuit industry and a trend of rapid development of packaging processes.
In one possible implementation, the plurality of physical layout characteristics are respectively associated with a physical layout of the integrated circuit, a circuit diagram of the integrated circuit, and an LVS of the integrated circuit, and the plurality of parameters include: data format, boundary layer size, boundary layer shape, port number, connection relation between ports and port naming rule.
In one possible implementation, the design data of the integrated circuit includes a signature graphic data system, an integrated circuit design netlist of the integrated circuit, and a design rule manual of the integrated circuit, and the package data of the integrated circuit includes a package graphic data system, a port mapping file of the integrated circuit, and a signature LVS rule of the integrated circuit.
In one possible implementation, the first parameter item of a given parameter of the plurality of parameters includes a plurality of package levels and via connection relationships between the plurality of package levels, which are determined based on a design rule manual of the integrated circuit, and the second parameter item of the given parameter includes an LVS check rule, which is determined based on a signature LVS rule and a package process standard of the integrated circuit.
Referring to fig. 4, fig. 4 is a schematic structural diagram of a computing device provided in an embodiment of the present application, where the computing device 400 includes: one or more processors 410, a communication interface 420, and a memory 430. The processor 410, communication interface 420, and memory 430 are interconnected by a bus 440. Optionally, the computing device 400 may further include an input/output interface 450, and the input/output interface 450 is connected with an input/output device for receiving parameters set by a user, and the like. The computing device 400 can be used to implement some or all of the functionality of the device embodiments or system embodiments described above in this application; the processor 410 can also be used to implement some or all of the operational steps of the method embodiments described above in the embodiments of the present application. For example, specific implementations of the computing device 400 to perform various operations may refer to specific details in the above-described embodiments, such as the processor 410 being configured to perform some or all of the steps or some or all of the operations in the above-described method embodiments. For another example, in this embodiment, the computing device 400 may be used to implement part or all of the functions of one or more components in the apparatus embodiments, in addition, the communication interface 420 may be specifically used to implement the communication functions and the like necessary for the functions of these apparatuses and components, and the processor 410 may be specifically used to implement the processing functions and the like necessary for the functions of these apparatuses and components.
It should be understood that the computing device 400 of fig. 4 may include one or more processors 410, and the processors 410 may cooperatively provide processing capabilities in a parallelized, serialized, deserialized, or any connection, or the processors 410 may form a processor sequence or an array of processors, or the processors 410 may be separated into a main processor and an auxiliary processor, or the processors 410 may have different architectures such as employing heterogeneous computing architectures. Further, the computing device 400 shown in FIG. 4, the associated structural and functional descriptions are exemplary and non-limiting. In some example embodiments, computing device 400 may include more or fewer components than shown in FIG. 4, or combine certain components, or split certain components, or have a different arrangement of components.
The processor 410 may be implemented in various specific forms, for example, the processor 410 may include one or more combinations of a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), a neural-Network Processing Unit (NPU), a Tensor Processing Unit (TPU), or a Data Processing Unit (DPU), and the embodiments of the present application are not limited in particular. Processor 410 may also be a single core processor or a multi-core processor. The processor 410 may be a combination of a CPU and a hardware chip. The hardware chip may be an application-specific integrated circuit (ASIC), a Programmable Logic Device (PLD), or a combination thereof. The PLD may be a Complex Programmable Logic Device (CPLD), a field-programmable gate array (FPGA), a General Array Logic (GAL), or any combination thereof. The processor 410 may also be implemented as a single logic device with built-in processing logic, such as an FPGA or a Digital Signal Processor (DSP). The communication interface 420 may be a wired interface, such as an ethernet interface, a Local Interconnect Network (LIN), or the like, or a wireless interface, such as a cellular network interface or a wireless lan interface, for communicating with other modules or devices.
The memory 430 may be a non-volatile memory, such as a read-only memory (ROM), a Programmable ROM (PROM), an erasable programmable PROM (EPROM), an Electrically Erasable Programmable ROM (EEPROM), or a flash memory. The memory 430 may also be volatile memory, which may be Random Access Memory (RAM), which acts as external cache memory. By way of example, but not limitation, many forms of RAM are available, such as Static Random Access Memory (SRAM), dynamic Random Access Memory (DRAM), synchronous Dynamic Random Access Memory (SDRAM), double data rate SDRAM, enhanced SDRAM, SLDRAM, synchronous Link DRAM (SLDRAM), and direct rambus RAM (DR RAM). The memory 430 may also be used to store program codes and data for the processor 410 to call the program codes stored in the memory 430 to perform some or all of the operational steps of the above-described method embodiments or to perform corresponding functions in the above-described apparatus embodiments. Moreover, computing device 400 may contain more or fewer components than shown in FIG. 4, or have a different arrangement of components.
The bus 440 may be a peripheral component interconnect express (PCIe) bus, an Extended Industry Standard Architecture (EISA) bus, a unified bus (unibus, UBs or UB), a computer express link (CXL), a cache coherent interconnect protocol (CCIX) bus, or the like. The bus 440 may be divided into an address bus, a data bus, a control bus, and the like. The bus 440 may include a power bus, a control bus, a status signal bus, and the like, in addition to a data bus. However, for clarity, only one thick line is shown in FIG. 4, but this does not represent only one bus or one type of bus.
Embodiments of the present application further provide a system, where the system includes a plurality of computing devices, and the structure of each computing device may refer to the structure of the computing device described in fig. 4 above. The functions or operations that can be implemented by the system may refer to specific implementation steps in the above method embodiments and/or specific functions described in the above apparatus embodiments, which are not described in detail herein.
Embodiments of the present application further provide a computer-readable storage medium, in which computer instructions are stored, and when the computer instructions are executed on a computer device (such as one or more processors), the method steps in the above method embodiments may be implemented. The specific implementation of the processor of the computer-readable storage medium in executing the above method steps may refer to the specific operations described in the above method embodiments and/or the specific functions described in the above apparatus embodiments, which are not described herein again.
As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. The present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Embodiments of the application may be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented in software, the above-described embodiments may be implemented in whole or in part in the form of a computer program product. The present application may take the form of a computer program product embodied on one or more computer-usable storage media having computer-usable program code embodied in the medium. The computer program product includes one or more computer instructions. When loaded or executed on a computer, cause the processes or functions described in accordance with the embodiments of the application to occur, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a network of computers, or other programmable device. The computer instructions may be stored on a computer readable storage medium or transmitted from one computer readable storage medium to another, for example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by wire (e.g., coaxial cable, fiber optic, digital subscriber line) or wirelessly (e.g., infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. that contains one or more collections of available media. The usable medium may be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium, or a semiconductor medium. The semiconductor medium may be a solid state disk, or may be a random access memory, flash memory, read only memory, erasable programmable read only memory, electrically erasable programmable read only memory, registers, or any other form of suitable storage medium.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. Each flow and/or block in the flow charts and/or block diagrams, and combinations of flows and/or blocks in the flow charts and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks. These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks. These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
In the above embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments. It will be apparent to those skilled in the art that various changes and modifications may be made in the embodiments of the present application without departing from the spirit and scope of the embodiments of the present application. The steps in the method of the embodiment of the application can be sequentially adjusted, combined or deleted according to actual needs; the modules in the system of the embodiment of the application can be divided, combined or deleted according to actual needs. If these modifications and variations of the embodiments of the present application fall within the scope of the claims of the present application and their equivalents, then the present application is intended to include these modifications and variations as well.

Claims (23)

1. A system, characterized in that the system comprises:
a processor; and
a memory coupled with the processor, the memory storing executable instructions, the processor causing the system to perform the following by executing the executable instructions:
obtaining a first parameter item and a second parameter item of a parameter indicative of a same physical layout characteristic of a same integrated circuit, wherein the first parameter item and the second parameter item are based on design data and package data of the integrated circuit, respectively;
and calculating a consistency check result between the design data and the packaging data according to a first confidence score and a second confidence score which respectively correspond to the first parameter item and the second parameter item of the parameter.
2. The system of claim 1, wherein the parameter is a data format, the first parameter item is a data format of design data for the integrated circuit, and the second parameter item is a data format of package data for the integrated circuit.
3. The system of claim 1, wherein the parameter is boundary layer size, wherein the first parameter item is boundary layer size indicated by design data for the integrated circuit, and wherein the second parameter item is boundary layer size indicated by packaging data for the integrated circuit.
4. The system of claim 1, wherein the parameter is a boundary layer shape, wherein the first parameter item is a boundary layer shape indicated by design data for the integrated circuit, and wherein the second parameter item is a boundary layer shape indicated by packaging data for the integrated circuit.
5. The system of claim 1, wherein the physical layout characteristics are associated with a physical layout of the integrated circuit, the parameters include a data format, a boundary layer size, and a boundary layer shape, the first parameter items include a data format of design data for the integrated circuit, a boundary layer size indicated by the design data for the integrated circuit, and a boundary layer shape indicated by the design data for the integrated circuit, and the second parameter items include a data format of package data for the integrated circuit, a boundary layer size indicated by the package data for the integrated circuit, and a boundary layer shape indicated by the package data for the integrated circuit.
6. The system of claim 5, wherein the design data for the integrated circuit comprises a signature graph data system and the packaging data for the integrated circuit comprises a packaging graph data system.
7. The system of claim 6, wherein the operations further comprise:
and merging the signoff graphic data system included in the design data of the integrated circuit and the packaging graphic data system included in the packaging data of the integrated circuit so as to obtain a merged graphic data system.
8. The system of claim 1, wherein the parameter is a number of ports, wherein the first parameter item is a number of ports indicated by design data for the integrated circuit, and wherein the second parameter item is a number of ports indicated by package data for the integrated circuit.
9. The system according to claim 1, wherein the parameter is an inter-port connection relationship, the first parameter item is an inter-port connection relationship indicated by design data of the integrated circuit, and the second parameter item is an inter-port connection relationship indicated by package data of the integrated circuit.
10. The system of claim 1, wherein the parameter is a port naming convention, wherein the first parameter item is a port naming convention for design data of the integrated circuit, and wherein the second parameter item is a port naming convention for package data of the integrated circuit.
11. The system according to claim 1, wherein the physical layout characteristics are associated with a circuit diagram of the integrated circuit, the first parameter items include the number of ports indicated by design data of the integrated circuit, inter-port connection relationships indicated by the design data of the integrated circuit, and port naming rules of the design data of the integrated circuit, and the second parameter items include the number of ports indicated by package data of the integrated circuit, inter-port connection relationships indicated by the package data of the integrated circuit, and port naming rules of the package data of the integrated circuit.
12. The system of claim 11, wherein the design data for the integrated circuit comprises an integrated circuit design netlist for the integrated circuit and the package data for the integrated circuit comprises a port map file for the integrated circuit.
13. The system of claim 12, wherein the operations further comprise:
and merging the integrated circuit design netlist of the integrated circuit included in the design data of the integrated circuit and the port mapping file of the integrated circuit included in the packaging data of the integrated circuit so as to obtain a merged netlist file.
14. The system of claim 13, wherein computing consistency check results between the design data and the package data comprises:
and comparing the port number and the inter-port connection relation indicated by the integrated circuit design netlist of the integrated circuit and the port number and the inter-port connection relation indicated by the port mapping file of the integrated circuit so as to determine whether a port merging operation and/or a port deleting operation exist or not.
15. The system of claim 14, wherein the design data of the integrated circuit further includes a signoff graphic data system, the package data of the integrated circuit further includes a package graphic data system, the signoff graphic data system included in the design data of the integrated circuit and the package graphic data system included in the package data of the integrated circuit are merged to obtain a merged graphic data system, wherein calculating the consistency check result between the design data and the package data further comprises:
when it is determined that the port merging operation and/or the port deleting operation exist, determining reasonableness of the port merging operation and/or the port deleting operation based on the merged graphic data system.
16. The system of claim 1, wherein the physical layout characteristics are further associated with a circuit layout matching LVS of the integrated circuit, the design data of the integrated circuit further includes a design rule manual of the integrated circuit, the package data of the integrated circuit further includes a signature circuit layout matching LVS rule of the integrated circuit, the first parameter item includes via connection relationships between a plurality of package levels determined based on the design rule manual of the integrated circuit and the plurality of package levels, and the second parameter item includes a LVS check rule determined based on the signature LVS rule and a package process standard of the integrated circuit.
17. The system of claim 1, wherein the physical layout characteristics are associated with a physical layout of the integrated circuit, a circuit diagram of the integrated circuit, and an LVS of the integrated circuit, wherein the design data of the integrated circuit includes a signature graph data system, an integrated circuit design netlist of the integrated circuit, and a design rule manual of the integrated circuit, and wherein the package data of the integrated circuit includes a package graph data system, a port mapping file of the integrated circuit, and a signature LVS rule of the integrated circuit.
18. A method for consistency checking of a system-in-package design, the method comprising:
obtaining a first parameter item and a second parameter item for each of a plurality of parameters, wherein each of the plurality of parameters indicates one of a plurality of physical layout characteristics of the same integrated circuit, the first parameter item and the second parameter item for each of the plurality of parameters being based on design data and package data, respectively, of the integrated circuit;
for each of the plurality of parameters, calculating a consistency check result between the design data and the package data according to a first confidence score and a second confidence score corresponding to a first parameter item and a second parameter item of the parameter, respectively.
19. The method of claim 18, wherein the plurality of physical layout characteristics are associated with a physical layout of the integrated circuit, a circuit diagram of the integrated circuit, and an LVS of the integrated circuit, respectively, and wherein the plurality of parameters comprise: data format, boundary layer size, boundary layer shape, port number, connection relation between ports and port naming rule.
20. The method of claim 19, wherein the design data of the integrated circuit comprises a signature graphic data system, an integrated circuit design netlist of the integrated circuit, and a design rule manual of the integrated circuit, and wherein the package data of the integrated circuit comprises a package graphic data system, a port mapping file of the integrated circuit, and a signature LVS rule of the integrated circuit.
21. The method of claim 20, wherein a first parameter item of a given parameter of the plurality of parameters comprises a plurality of package levels determined based on a design rule manual of the integrated circuit and via connection relationships between the plurality of package levels, and a second parameter item of the given parameter comprises a LVS check rule determined based on a signature LVS rule and package process criteria of the integrated circuit.
22. A non-transitory computer readable storage medium storing computer instructions which, when executed by a processor, implement the method of any one of claims 18 to 21.
23. An electronic device, characterized in that the electronic device comprises:
a processor;
a memory for storing processor-executable instructions;
wherein the processor implements the method of any one of claims 18 to 21 by executing the executable instructions.
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