CN115766555A - TTE switch network test architecture and method - Google Patents
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Abstract
The invention belongs to the technical field of avionics, and discloses a TTE switch network test architecture and a method, which comprises the following steps: the system comprises a tested multi-port switch, multi-port switch testing equipment, a network analyzer and an upper computer; the tested multi-port switch is a device to be tested and comprises a plurality of switching ports; the multi-port switch test equipment comprises a plurality of TTE network nodes and management nodes; the multi-port switch testing equipment is interacted with the upper computer through the management node; the analyzer comprises a plurality of flow monitoring ports which are connected in series between the tested multi-port switch and the multi-port switch testing equipment; the number of the switching ports on the tested multi-port switch is the same as that of TTE network nodes on the multi-port switch testing equipment. The method is used for solving the test problem of the multi-port TTE switch; the workload of testing personnel is reduced, and the testing efficiency is increased.
Description
Technical Field
The invention belongs to the technical field of avionics, and particularly relates to a TTE switch network test architecture and a TTE switch network test method.
Background
TTE (time triggered Ethernet) is an Ethernet-based bus protocol developed by TTtech corporation in Europe, and enhances the real-time capability of the network by introducing a time synchronization and time scheduling mechanism. TTE is currently used in a wide variety of aerospace devices. In 2014, the Hunter manned spacecraft carries a time-triggered hybrid safety critical system network developed by Honeywell and TTTech companies for NASA cooperation, and the network combines the characteristics of masterless time triggering, high performance and high safety and meets the requirement of the endogenous function of aerospace models. In the same year, the high-performance helicopter S-97 of the Western science base carries a dual redundant time-triggered hybrid network, and the network greatly improves the multi-source information fusion capability of the helicopter and completes flight verification. An upgraded version of Raider X from S-97 in 2022 has participated in bidding for the United states FARA (future attack scout for the army of the United states) program and is scheduled to complete flight verification in 2022.
At present, TTE switches at home and abroad do not have mature shelf products, and TTE switch test products with open frameworks are lacking at home and abroad. In order to complete the multi-port TTE switch and network level simulation test, equal amount of end nodes are needed for flow injection, and if a traditional end node card mode is used, the cost and the space are greatly improved.
Disclosure of Invention
Aiming at the problems in the background art, the invention aims to provide a TTE switch network testing architecture and a method, which are used for solving the testing problem of a multi-port TTE switch; the workload of testing personnel is reduced, and the testing efficiency is increased.
In order to achieve the purpose, the invention is realized by adopting the technical scheme.
The technical scheme I is as follows:
a TTE switch network test architecture, the test architecture comprising: the system comprises a tested multi-port switch, multi-port switch testing equipment, a network analyzer and an upper computer;
the tested multi-port switch is a device to be tested and comprises a plurality of switching ports;
the multi-port switch test equipment comprises a plurality of TTE network nodes and management nodes; the multi-port switch testing equipment is interacted with the upper computer through the management node;
the analyzer comprises a plurality of flow monitoring ports which are connected in series between the tested multi-port switch and the multi-port switch testing equipment;
the number of the switching ports on the tested multi-port switch is the same as that of TTE network nodes on the multi-port switch testing equipment.
The first technical scheme of the invention has the characteristics and further improvements that:
(1) The multi-port switch testing equipment is used for carrying out flow generation, flow injection and fault injection on the TTE switch network;
the network analyzer is used for completing the capturing, flow searching and filtering, flow forwarding and flow analysis of synchronous flow and data flow in the TTE switch network;
and the upper computer is used for providing required hardware drive and multi-core task scheduling for the application of the multi-port switch test equipment and providing distributed middleware service for upper application.
(2) Network configuration tables are stored in the tested multi-port switch and the multi-port switch test equipment;
the network configuration table stores the message scheduling time and configuration parameters of the multi-port switch testing equipment and the tested multi-port switch in the TTE switch network, and is used for completing network time-triggered hybrid flow scheduling and realizing time slot allocation of TT messages, RC messages and BE messages.
(3) The network configuration table of the multi-port switch test equipment comprises N sub-tables, and global parameters, TT sending scheduling time, TT receiving scheduling time and sending framing configuration information are respectively stored;
the network configuration table of the tested multi-port switch comprises M sub-tables, and global parameters, TT receiving inspection and TT output gating switch time information are respectively stored;
and the message planning results in the network configuration table of the tested multi-port switch correspond to the message planning results in the network configuration table of the multi-port switch test equipment one by one, and the message planning results are path planning and scheduling time planning of TT messages, RC messages and BE messages.
The second technical scheme is as follows:
a TTE switch network test method is realized based on the test architecture of the first technical scheme, and comprises the following steps:
s1, generating a network configuration table;
s2, the upper computer software completes burning of the tested multi-port switch, the multi-port switch test equipment network configuration table and the test logic through the management node;
s3, then, carrying out mode selection by upper computer software; the modes include: the method comprises the steps that a flow generation mode and a fault injection mode are adopted, the flow generation mode is used for testing the switching and forwarding performance of a tested multi-port switch and a TTE switch network, and the fault injection mode is used for testing the fault tolerance performance of the tested multi-port switch and the TTE switch network;
s4, in the fault injection mode, modifying the content of the configuration table through interactive operation by using a configuration table conversion tool, further modifying the flow information and the synchronous information of the multi-port switch test equipment, and issuing the modified configuration table to test logic to complete fault injection;
s5, the test logic completes interaction between the internal data of the test logic and the software through the PCIE-DMA host interface logic module, acquires mode information and completes data interaction;
and S6, finally starting a test logic to start testing, finishing framing, sending, receiving, verifying, fault injecting and statistic statistics of the data frames by the test logic according to the information of the S4 and the S5, performing grouping operation on the statistic information, and uploading the statistic information to an upper computer in a TT multicast message mode according to a preset TT time slot.
The second technical scheme of the invention has the characteristics and further improvements that:
(1) S1 specifically comprises the following steps: and realizing scheduling and planning of TT messages, RC messages and BE messages according to network topology, network planning constraints, data flow and flow specification information, and generating a network configuration table.
(2) S4 specifically comprises the following steps:
the configuration table conversion tool completes data frame data integrity, time integrity and network synchronization level fault design for three layers of MAC, IP and UDP in the network configuration table of the multi-port switch test equipment by modifying the content of the configuration table, and completes fault injection.
(3) S5 specifically comprises the following steps:
s51, a PCIE-DMA host interface is adopted between a management node and upper computer software in the multi-port switch test equipment, and an active DMA interaction mechanism and memory allocation between the management node and the software are realized;
s52, the PCIE-DMA host interface finishes the interaction between the internal data of the test logic and the software, and finishes the writing of the logic receiving message data into the corresponding space of the memory in the data receiving direction; and in the data sending direction, carrying the data from the memory to a buffer unit where the message in the data frame sending logic is located.
(4) S6 specifically comprises the following steps:
s61, the multi-port switch testing equipment completes the flow generation of TT messages, RC messages and BE messages according to a predefined network configuration table and sends the TT messages, the RC messages and the BE messages to the multi-port switch to BE tested;
s62, the tested multi-port switch forwards TT messages, RC messages and BE messages according to a network configuration table;
s63, a network analyzer captures synchronous flow and data flow in the TTE switch network, searches and filters the flow, forwards the flow and analyzes the flow;
and S64, the multi-port switch testing equipment performs statistical analysis on the received synchronous flow and data flow and generates a test report.
The technical scheme of the invention changes the traditional mode that the TTE switch uses the end node card for testing, and uses 1 multi-port switch to replace a plurality of end node cards, thereby obviously reducing the space and the cost. A brand-new multi-port switch logic is designed, the number of end nodes can be freely cut, and the expandability and the multiplexing capability of equipment are improved. Flow generation and fault injection logic are designed, and completeness of network testing of the switch is improved.
Drawings
Fig. 1 is a schematic diagram of a network test architecture of a TTE switch according to an embodiment of the present invention.
Detailed Description
The technical scheme of the invention is explained in detail in the following with the accompanying drawings.
The embodiment of the invention provides a TTE switch network test architecture. As shown in fig. 1, the test architecture is mainly divided into 4 parts: the system comprises a tested multi-port switch, multi-port switch testing equipment, a network analyzer and an upper computer.
The tested multi-port switch is a device to be tested and comprises a plurality of switching ports;
the multi-port switch test equipment comprises a plurality of TTE network nodes and management nodes; the multi-port switch testing equipment is interacted with the upper computer through the management node;
the analyzer comprises a plurality of flow monitoring ports which are connected in series between the tested multi-port switch and the multi-port switch testing equipment;
the number of the switching ports on the tested multi-port switch is the same as that of TTE network nodes on the multi-port switch testing equipment.
The tested multi-port switch is a device to be tested, and the functions of switching, forwarding, fault tolerance and the like of the device are not verified;
the multi-port switch testing equipment is responsible for completing the functions of flow generation, injection, fault injection and the like according to testing software and testing logic;
the analyzer finishes the grabbing, forwarding and analyzing of the flow in the network and is used for monitoring and analyzing the condition of the network;
the upper computer uses test software to complete the management of the test logic, the test software mainly provides mode and starting information for the test logic, and finally reads the statistic information of the logic.
Network configuration tables are stored in the tested multi-port switch and the multi-port switch test equipment;
the network configuration table stores the message scheduling time and configuration parameters of the multi-port switch testing equipment and the tested multi-port switch in the TTE switch network, and is used for completing network time-triggered hybrid flow scheduling and realizing time slot allocation of TT messages, RC messages and BE messages.
When the test framework is tested, the upper computer completes burning of the test equipment and the configuration table and the test logic of the tested switch through the management node, then the upper computer software performs mode selection, and finally the test logic is started to complete testing.
The invention designs a brand-new network configuration table, test logic and test software. The configuration table is used for completing message scheduling and parameter configuration between the nodes and the switch. The test software mainly provides mode and starting information for the logic, and finally reads the statistic information of the logic. And the test logic performs data framing, sending, receiving, checking and statistics according to the mode and the starting information and the configuration table.
1. And (4) configuring a table. The configuration table stores the time schedule and configuration parameters of message scheduling of nodes and switches in the network. The node configuration table comprises N sub-tables, and global parameters, TT sending scheduling time, TT receiving scheduling time, sending framing configuration and a message information table special for software are respectively stored; the switch configuration table and the node configuration table are in one-to-one correspondence, and the switch configuration table comprises M sub-tables, and information such as global parameters, TT receiving inspection, TT output gating switch time and the like is stored respectively. And the message planning results in the network configuration table of the tested multi-port switch correspond to the message planning results in the network configuration table of the multi-port switch test equipment one by one, and the message planning results are path planning and scheduling time planning of TT messages, RC messages and BE messages.
When the test software reads the configuration table, the information of the type, the length and the quantity of the messages sent and received by the node is obtained, and the information is transmitted to the test logic; and the test logic reads the information transmitted by the configuration table and the software to complete framing, sending, receiving, checking and counting of the data frames.
2. The test software supports two mode options: and the traffic generation mode and the fault injection mode are respectively used for testing the switching and forwarding capacity and the fault tolerance capacity of the switch and the network.
3. When the software is configured to be in a flow generation mode, when the software receives the data, the logic uploads the statistical data after self-reset work to a memory designated space in an active DMA mode, and the software reads and analyzes the message state statistical quantity from the memory space.
In the flow generation mode, when software is transmitted,
the software writes the message sending number and length in the register in an IO operation mode, the message sending register group is divided into N groups according to N port nodes, each group sets the message sending number and the message sending length register aiming at each message (Q messages are sent in total), the software needs to set the register group of at least 1 port node for each sending, and the message sending number and the message sending length of Q messages are written in respectively.
After the writing is finished, after the enabling switch of the logic is started by software, the logic sends a message according to the configuration table from the beginning of the next cluster period, and the flow generation and injection are finished.
After the writing is finished, software circularly inquires the register corresponding to the sending port, and inquires whether the sending of the message is finished.
4. When the software is configured to be a fault injection mode, the software can self-define a plurality of fault modes, including TT flow configuration table forwarding inconsistent fault test, sending delay fault test, receiving window boundary receiving error and the like. And modifying the configuration table by test logic or test software according to the fault mode, completing flow injection in an error scene, and capturing whether the data forwarded by the tested switch is normal or not by using an analyzer.
The invention discloses a TTE switch network testing method, which is characterized in that a multi-port TTE switch is transformed into a switch testing device, a brand-new configuration table, testing logic and testing software are designed, each transformed switch port can simulate an independent end node, SM and SC nodes are simulated according to the configuration table, and the testing of the multi-port switch can be completed by using two multi-port switches. Compared with the traditional test method, the method greatly reduces the number of test equipment, greatly reduces the workload of burning the logic and configuration table in the test process, and supports switch and network-level simulation test.
In the using process of the invention, under the condition of ensuring the stable and synchronous network, each port of the test equipment simulates an independent node, and each node generates and sends the flow of three messages according to a configuration table and strictly according to the time sequence: (1) A time-triggered TT message with low jitter and bounded end-to-end delay; (2) rate-constrained RC messages that limit end-to-end delay; (3) messages and "best effort" BE messages without real time guarantees. Each port independently receives and transmits data, the length and the quantity of the transmitted data are controlled by application layer software, and the main control processor does not directly generate data streams. Protocols such as IP/UDP are generated by logic based on configuration tables.
The technical scheme of the invention changes the traditional mode that the TTE switch uses the end node card for testing, and uses 1 multi-port switch to replace a plurality of end node cards, thereby obviously reducing the space and the cost. 2. A brand-new multi-port switch logic is designed, the number of end nodes can be freely cut, and the expandability and the multiplexing capability of equipment are improved. 3. Flow generation and fault injection logic are designed, and completeness of switch network test is improved.
Claims (9)
1. A TTE switch network test architecture, the test architecture comprising: the system comprises a tested multi-port switch, multi-port switch testing equipment, a network analyzer and an upper computer;
the tested multi-port switch is a device to be tested and comprises a plurality of switching ports;
the multi-port switch test equipment comprises a plurality of TTE network nodes and management nodes; the multi-port switch testing equipment is interacted with the upper computer through the management node;
the analyzer comprises a plurality of flow monitoring ports which are connected in series between the tested multi-port switch and the multi-port switch testing equipment;
the number of the switching ports on the tested multi-port switch is the same as that of TTE network nodes on the multi-port switch testing equipment.
2. The TTE switch network test architecture of claim 1,
the multi-port switch testing equipment is used for carrying out flow generation, flow injection and fault injection on the TTE switch network;
the network analyzer is used for completing the capturing, flow searching and filtering, flow forwarding and flow analysis of synchronous flow and data flow in the TTE switch network;
and the upper computer is used for providing required hardware drive and multi-core task scheduling for the application of the multi-port switch test equipment and providing distributed middleware service for upper-layer application.
3. The TTE switch network test architecture of claim 1, wherein network configuration tables are stored in the multi-port switch under test and the multi-port switch test equipment;
the network configuration table stores a multi-port switch testing device in the TTE switch network and a time schedule and configuration parameters of message scheduling of the tested multi-port switch, and is used for completing mixed flow scheduling triggered by network time and realizing time slot allocation of TT messages, RC messages and BE messages.
4. The TTE switch network test architecture of claim 3,
the network configuration table of the multi-port switch test equipment comprises N sub-tables, and global parameters, TT sending scheduling time, TT receiving scheduling time and sending framing configuration information are respectively stored;
the network configuration table of the tested multi-port switch comprises M sub-tables, and global parameters, TT receiving inspection and TT output gating switch time information are respectively stored;
and the message planning results in the network configuration table of the tested multi-port switch correspond to the message planning results in the network configuration table of the multi-port switch test equipment one by one, and the message planning results are path planning and scheduling time planning of TT messages, RC messages and BE messages.
5. A TTE switch network test method, the test method being implemented based on the test architecture of any of claims 1-4, the test method comprising:
s1, generating a network configuration table;
s2, the upper computer software completes burning of the tested multi-port switch, the multi-port switch test equipment network configuration table and the test logic through the management node;
s3, then, mode selection is carried out by upper computer software; the modes include: the method comprises the steps that a flow generation mode and a fault injection mode are adopted, wherein the flow generation mode is used for testing the switching and forwarding performance of a tested multi-port switch and a TTE switch network, and the fault injection mode is used for testing the fault tolerance performance of the tested multi-port switch and the TTE switch network;
s4, in the fault injection mode, modifying the content of the configuration table by using a configuration table conversion tool through interactive operation, further modifying the flow information and the synchronous information of the multi-port switch test equipment, and issuing the modified configuration table to test logic to complete fault injection;
s5, the test logic completes interaction between the internal data of the test logic and the software through the PCIE-DMA host interface logic module, acquires mode information and completes data interaction;
and S6, finally starting a test logic to start testing, finishing framing, sending, receiving, verifying, fault injecting and statistic statistics of the data frames by the test logic according to the information of the S4 and the S5, performing framing operation on the statistic information, and uploading the statistic information to an upper computer in a TT multicast message mode according to a preset TT time slot.
6. The TTE switch network test method of claim 5,
s1 specifically comprises the following steps: and according to the network topology, the network planning constraint, the data flow and the flow specification information, realizing the scheduling and planning of the TT message, the RC message and the BE message data flow and generating a network configuration table.
7. The TTE switch network test method of claim 5,
s4 specifically comprises the following steps: the configuration table conversion tool completes data frame data integrity, time integrity and network synchronization level fault design for three layers of MAC, IP and UDP in the network configuration table of the multi-port switch test equipment by modifying the content of the configuration table, and completes fault injection.
8. The TTE switch network test method of claim 5, wherein S5 specifically is:
s51, a PCIE-DMA host interface is adopted between a management node and upper computer software in the multi-port switch testing equipment to realize an active DMA interaction mechanism and memory allocation between the management node and the software;
s52, the PCIE-DMA host interface finishes the interaction between the internal data of the test logic and the software, and finishes the writing of the logic receiving message data into the corresponding space of the memory in the data receiving direction; and in the data sending direction, carrying the data from the memory to a buffer unit where the message in the data frame sending logic is located.
9. The TTE switch network test method of claim 5, wherein S6 specifically is:
s61, the multi-port switch testing equipment completes the flow generation of TT messages, RC messages and BE messages according to a predefined network configuration table and sends the TT messages, the RC messages and the BE messages to the multi-port switch to BE tested;
s62, the tested multi-port switch forwards TT messages, RC messages and BE messages according to a network configuration table;
s63, a network analyzer captures synchronous flow and data flow in the TTE switch network, searches and filters the flow, forwards the flow and analyzes the flow;
and S64, the multi-port switch testing equipment performs statistical analysis on the received synchronous flow and data flow and generates a test report.
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