CN115766521A

CN115766521A - Full-link delay measurement method and system based on FPGA

Info

Publication number: CN115766521A
Application number: CN202211536529.6A
Authority: CN
Inventors: 迈涛; 乔晓冬
Original assignee: Ehiway Microelectronic Science And Technology Suzhou Co ltd
Current assignee: Ehiway Microelectronic Science And Technology Suzhou Co ltd
Priority date: 2022-12-02
Filing date: 2022-12-02
Publication date: 2023-03-07

Abstract

The invention provides a full link delay measuring method based on an FPGA (field programmable gate array), which comprises the following steps of: setting an FPGA recording device; copying the output data of the monitoring point into a plurality of parts in a mode of not introducing extra time delay, wherein one part is sent to the FPGA recording device, and recording message data on a link and stamping a hardware timestamp according to the internal time of the FPGA recording device; extracting the effective load of the message data to obtain service data; analyzing the service data according to an agreed service layer protocol, transmitting a hardware timestamp of the message data to correspond to analysis result data, and generating a result file tray; and analyzing and calculating based on the hardware timestamp to obtain the delay of each network device on the link. The method and the device can accurately capture each data packet and obtain the time consumption of the data packet in each device in the network topology, and can accurately evaluate the performance of each network device of the market decoding system.

Description

Full-link delay measurement method and system based on FPGA

Technical Field

The invention belongs to the technical field of data processing, and particularly relates to a full-link delay measuring method and a corresponding measuring system for multi-channel market information analyzing equipment based on an FPGA (field programmable gate array).

Background

In the field of financial security trading, market data is changed instantly, and a user can grasp the opportunity of buying and selling, accurately grasp the opportunity and the point location, and can realize a larger profit. Thus lower transaction latency is one of the core objectives for all financial transactions. The conventional market analysis processing and transaction system is mostly based on the conventional CPU _ x86 architecture, and the main frequency of the CPU has become the bottleneck of speed increase. Meanwhile, with the development of financial science and technology, various algorithm transactions and quantitative transactions are started, and greater challenges are provided for financial systems.

Based on the characteristics of FPGA customizability, parallel operation, low delay and stable performance, at present, more and more tasks of software processing such as market analysis and the like are gradually unloaded into an FPGA board card for acceleration, the delay comparison of the FPGA processing of different manufacturers is difficult to have a standard test environment and method for performing performance test, and the FPGA serving as a sub-device (such as an FPGA in a decoding device) in a market analysis system is difficult to judge the delay performance of the FPGA in the whole link and the delay performance of other network devices in the whole link, and the delay of the whole link can only be measured in a software test mode. Except for the market analysis field, the field with higher delay requirement has the requirement of evaluating the delay performance of the whole full link. The software test can only test the full link, and can not test the independent delay of any network device in the network topology, and in addition, the software test result is not accurate enough, and because extra jitter time is introduced by system scheduling and load conditions, the test result often has a plurality of singular values. Therefore, there is an obvious defect in measuring the full link delay by a software test mode, and the application requirement in the field with higher delay requirement cannot be met.

In some better prior arts, a switch is used for monitoring and analyzing network data packets in real time, but only a TCP/UDP layer is available, a service layer (application layer) protocol above the TCP/UDP layer cannot process the network data packets, that is, only general network devices can be monitored, and device data packets obtained after the network data is subjected to service processing cannot be mapped into original data, so that delay of each part of the whole system cannot be analyzed, and the monitored data packets cannot be landed.

Therefore, it is urgently needed to research a full-link delay measurement method and a corresponding measurement system for a multi-channel market analysis device based on an FPGA, so as to further meet practical application in the field with higher delay requirement.

Disclosure of Invention

The invention provides a full link delay measuring method based on FPGA on one hand and a full link delay measuring system based on FPGA on the other hand, which utilizes the characteristics of the accuracy and the processing parallelism of FPGA hardware time stamps and simultaneously receives network data packets of each link of the full link of a market analysis system, wherein each data packet of a landed disk has a corresponding hardware time stamp and can be accurate to ns (nanosecond) level. The delay of each data packet in each network device of the full link is accurately measured, and the performance of the multi-channel market decoding device can be measured simultaneously.

The invention provides a full link delay measuring method based on an FPGA, which comprises the following steps: setting an FPGA recording device; copying output data of a monitoring point into a plurality of parts in a mode of not introducing extra time delay, wherein one part is sent to the FPGA recording device, message data on a link is recorded, and a hardware timestamp is marked according to the internal time of the FPGA recording device; extracting the effective load of the message data to obtain service data; analyzing the service data according to an agreed service layer protocol, transmitting a hardware timestamp of the message data to correspond to analysis result data, and generating a result file tray; and analyzing and calculating based on the hardware timestamp to obtain the delay of each network device on the link. By arranging the FPGA recording device, message data on a link is recorded, all monitoring data packets can be landed, and directly correspond to an analysis result receiving end after analysis processing of a service layer protocol, processing and analysis of each data packet and a corresponding hardware timestamp of a TCP/UDP and a service layer can be completed, and delay of service processing equipment and all other general network equipment can be measured.

In a general case, the method for measuring full link delay based on the FPGA further includes: selecting a plurality of monitoring points in a network topology; the monitoring points refer to the access nodes of the key equipment, and comprise an exit of the market gateway, an entrance and an exit of the decoding equipment, an entrance of the receiving server and an exit of the switch. By selecting a plurality of monitoring points, the performance of the target equipment in the network topology can be analyzed according to the test requirement.

The method comprises the step of arranging an optical splitter at the monitoring point in a mode of not introducing extra time delay.

The accuracy of the hardware time stamp is set to be in nanoseconds.

When the message data is TCP data, reconstructing the TCP data before extracting the payload of the message data, including: reordering and de-duplication. Considering that the TCP data packets may have disorder and retransmission situations, the TCP data monitored for the disk dropping needs to be reconstructed, the disorder packets are reordered, and the duplicate packets are removed. The TCP is beneficial to processing the abnormal packets because retransmission packets and out-of-order packets are involved in protocol characteristic data streams, and the data streams which are completely consistent from the service sending end are reconstructed for analysis, so that the situation that the analyzed data streams are in disorder and have a lot of repeated packets is further avoided.

The extracting the payload of the message data comprises: and extracting the payload in the TCP data according to a TCP protocol.

And analyzing the service data according to an agreed service layer protocol comprises filtering and analyzing the reconstructed TCP data according to an original market protocol.

When the message data is UDP data, packet cutting (cutting a large packet into independent final result data packets) is performed after extracting the payload of the message data.

And the formats of the result files of different monitoring points are consistent. And a result file with a uniform format is generated, comparison is convenient, and the file is provided with a hardware timestamp. One is to find the time stamps of the same packet data in different result files, so as to calculate the time stamps to obtain the time delay of each network device, such as the format: the package number, hardware timestamp, service timestamp, stock code, price, volume, etc. other fields, the same package data can be found in multiple files through key fields such as service timestamp and stock code.

And the step of generating a result file falling plate refers to the step of generating the analysis result data into a result file falling plate according to the interface format of the output result.

The obtaining of the delay of each network device on the link includes comparing a difference between hardware timestamps in the analysis results of the two monitoring points, and the obtained delay includes: delay within a network device, and sequential delay to the same network device.

The measurement system provided by the invention can execute the FPGA-based full link delay measurement method on one aspect of the invention, and comprises an FPGA recording device and a plurality of network devices; the network equipment is in a network topology structure, and the FPGA recording device is in communication connection with a plurality of nodes of the network topology structure.

Compared with the prior art, the invention has the main beneficial effects that:

1. the FPGA-based full-link delay measurement method can drop all monitoring data packets, the equipment data packets subjected to service processing on network data correspond to the original data, the delay of each part of the whole system can be effectively analyzed, each data packet can be accurately captured, the time consumption of each equipment of the data packet in network topology can be obtained, and the performance of each network equipment of a market decoding system can be accurately evaluated.

2. The measurement system of the invention has corresponding advantages because the FPGA-based full link delay measurement method of the invention can be implemented.

Drawings

Fig. 1 is a schematic diagram of a topology structure of a market forwarding service network according to an embodiment of the present invention.

Fig. 2 is a schematic diagram of a full link delay measurement system of a multi-channel market analysis device according to an embodiment of the present invention.

Fig. 3 is a schematic diagram of a hardware topology for delay measurement according to an embodiment of the present invention.

Fig. 4 is a schematic process diagram of a full link delay measurement method according to an embodiment of the present invention.

Fig. 5 is a block diagram of TCP data analysis according to an embodiment of the present invention.

Fig. 6 is a block diagram of UDP data analysis according to an embodiment of the present invention.

Detailed Description

The technical solutions in the specific embodiments of the present invention will be clearly and completely described below, and it should be understood that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

In the embodiment of the present invention, two decoding apparatuses are used as an example for illustration, but not limited thereto. The network topology of the generic market forwarding service, which is commonly used, is shown in fig. 1, and examples include market gateways, switches, decoding devices (including FPGA or other software), and receiving servers. In an example case, the market gateway establishes a TCP connection with the decoding device, and sends the original market data to the decoding device after the connection is established; the decoding equipment decodes the market data to realize a specific data interface and sends the market data in a TCP or multicast UDP mode; and the receiving server analyzes the received data according to the interface protocol and generates result data. Taking the above full link of the multi-channel market analyzing device as an example, the present embodiment provides a measurement system, as shown in fig. 2, including an FPGA recording device and n network devices. The n network devices comprise a general network device and a service processing device, and form a network topology, and the FPGA recording device is in communication connection with a plurality of nodes of the network topology. In this embodiment, the measurement system executes full link delay measurement, drops all monitoring data packets into a disk, and after analysis processing of a service layer protocol, directly corresponds to an analysis result receiving end to measure the delay of service processing equipment and all other general network equipment. In the embodiment of the invention, the full link delay of the market condition decoding system is measured, the measured data result is analyzed and analyzed through software, the delay data of each data packet result can be finally obtained, and the FPGA recording device is utilized to evaluate the performance of the market condition decoding system to be tested.

An exemplary time delay measurement hardware topology architecture is shown in fig. 3, a corresponding measurement method process is shown in fig. 4, and an FPGA recording device is set; respectively copying the output data of the selected monitoring points into two parts in a mode of not introducing extra time delay, wherein one part is respectively sent to the FPGA recording device so as to record message data on a link and stamp a hardware timestamp according to the internal time of the FPGA recording device; extracting the effective load of the message data to obtain service data; analyzing the service data according to an agreed service layer protocol, transmitting the hardware timestamp of the message data to correspond to the analysis result data, and generating a result file falling plate; and analyzing and calculating based on the hardware timestamp to obtain the delay of each network device on the link. In an example case, a monitoring point is selected from a network topology, and a plurality of representative monitoring points such as an exit of a market gateway, an entrance and an exit of an FPGA or other decoding equipment, an entrance of a receiving server and the like are selected as a plurality of monitoring points; utilizing an FPGA recording module to perform storage of the network messages of each monitoring point in the network topology structure; and after the data is stored in a falling disk, a hardware time stamp is marked according to the internal time of the FPGA, and the hardware time stamp is placed in each data packet. The selection of the monitoring points may be determined according to actual test requirements, and in the example method, all the monitoring points are selected to analyze the performance of all the devices in the topology at one time, and the specific situation is not limited herein. Referring to fig. 3, by adding an FPGA recording device, optical splitters are added at positions such as an exit of a context gateway, an exit of a switch, and an exit of a decoding device, so as to copy data into multiple copies, wherein one copy is used for decoding subsequent network devices, and the other copy is used for recording network message data on the link for the FPGA recording device. The device can divide the output data into the same multiple copies without introducing extra time delay, and the mode of adopting the optical splitter is not limited. After the FPGA recording device records the message, high-precision (nanosecond, several nanoseconds) hardware timestamps are stamped according to the time inside the FPGA, and the timestamps of all the network equipment are on the same time axis to form data of the timestamps T1, T2, T3, T4, T5 and T6.

As in the case illustrated in fig. 5, since the data of T1, T2, and T3 are all the original market data, the original market data needs to be analyzed, and considering that the TCP data packet may have disorder and retransmission situations, the TCP data monitored for a disk drop needs to be reconstructed, the disorder message is reordered, and the duplicate data packet is deduplicated. In the example case, duplicate packets and erroneous packets are not reconstructed, the duplicate packets cause the same packet data to have multiple timestamps, which cannot be determined by the true service end, and the erroneous packets cause some packets to be lost or to be analyzed incorrectly, which do not correspond to the correct packets. In a better method, the TCP data analysis block diagram mainly comprises four modules, and the reconstructed TCP market data is filtered and analyzed according to the original market protocol to be in an interface form of an output result, and the interface form corresponds to the analysis result according to the hardware timestamp. The TCP stream reconstruction module reconstructs TCP data; after the TCP data stream is reconstructed, a data load extraction module extracts the load in the TCP data stream to obtain service data; and the market analysis module analyzes the market of the service data according to an agreed protocol, generates a result file, falls to a disk, transmits a hardware timestamp of the original TCP data packet and corresponds to each data packet result. The FPGA packet capture is a hardware timestamp taking a TCP data packet as a unit, and the hardware timestamp is required to be corresponding to the data packet analyzed according to the service protocol, so that the hardware timestamp is required to be transmitted in the analyzing process. In the example case, reconstructed TCP data needs to be analyzed at a service end, the analysis depends on service requirements, a hardware timestamp needs to be followed while the analysis is performed, each analyzed data packet, such as a TCP data packet a1 and a hardware timestamp b1 thereof, is followed, and a plurality of result data packets c1, c2 and c3 \8230areobtained after the analysis is completed, and b1 timestamps need to be correspondingly stamped on the data packets c1, c2 and c3 \8230.

The T4, T5, and T6 time stamp data is usually in a TCP or UDP format, and may be in other protocols, and the protocol for decoding and outputting by the system is not limited. If the monitoring point is a TCP protocol packet, a mode of TCP reconstruction and service analysis is adopted, and if the monitoring point is a UDP data packet, the monitoring point is directly analyzed. And a result file with a uniform format is generated, so that comparison is convenient, and the result file is provided with a hardware timestamp. In a specific implementation, if the TCP mode is used, the processing is still performed according to the process illustrated in fig. 5 to obtain decoding result data, and then each packet of data result is landed according to the decoding interface format.

And for the data with the time stamps of T4, T5 and T6, if the data is in a UDP mode, analyzing the decoded data packet in the system according to a UDP protocol, and corresponding the data to an analysis result according to the hardware time stamp. In the case illustrated in fig. 6, the data payload extraction module directly extracts payload data, and generates a destage result after performing processing such as packet cutting (cutting a large packet into independent final result packets). In the example case, the final result analysis is performed by printing the drop according to the decoding interface format, and the time stamp is calculated.

In some embodiments, after processing data of multiple monitoring points, result data in a uniform format is obtained, each data packet includes a hardware timestamp, the data packets are analyzed, the timestamps are mainly analyzed, and various calculations are performed on the timestamps to obtain the delay of each network device. An example format is: packet sequence number, hardware timestamp, business timestamp, stock code, price, volume, etc. The same packet data can be found in a plurality of files by key fields such as a business time stamp and a stock code. The data from T1 to T6 generate final tray-dropping results according to the same interface, and each data packet has a corresponding hardware timestamp. And after the data are obtained, starting delay analysis to obtain the delay of each network device on the link. In the exemplary case, the delay of the first decoding device or the second decoding device within the switch can be obtained for each value of | T1-T2| or | T1-T3| of the data packet. For the value of each data packet | T2-T3|, the time delay difference value of the same data packet arriving at the first decoding device and the second decoding device can be obtained. For each data packet | T3-T4| value, the penetration delay of the same data packet processed in the first decoding device or the second decoding device can be obtained, and the penetration delay performances of the two devices can be compared. For each data packet | T4-T6| or | T5-T6| value, the delay inside the switch after the decoding result is obtained. In the example case, the delay of each network device of the market decoding system, especially the performance comparison delay of two or more decoding devices, can be obtained by performing the delay statistical analysis on all the data. Thereby evaluating it. In some embodiments, only the hardware timestamp is analyzed, and the delay of the network device is measured, which is not limited to the specific case.

For clarity of description, the use of certain conventional and specific terms and phrases is intended to be illustrative and not restrictive, but rather to limit the scope of the invention to the particular letter and translation thereof.

Claims

1. The full link delay measuring method based on the FPGA is characterized by comprising the following steps: the method comprises the following steps:

setting an FPGA recording device;

copying output data of a monitoring point into a plurality of parts in a mode of not introducing extra time delay, wherein one part is sent to the FPGA recording device, message data on a link is recorded, and a hardware timestamp is marked according to the internal time of the FPGA recording device;

extracting the effective load of the message data to obtain service data;

analyzing the service data according to an agreed service layer protocol, transmitting a hardware timestamp of the message data to correspond to analysis result data, and generating a result file falling plate;

and analyzing and calculating based on the hardware timestamp to obtain the delay of each network device on the link.

2. The FPGA-based full-link delay measurement method of claim 1, characterized in that: further comprising: selecting a plurality of monitoring points in a network topology; the monitoring points refer to the access nodes of the key equipment, and comprise an exit of the market gateway, an entrance and an exit of the decoding equipment, an entrance of the receiving server and an exit of the switch.

3. The FPGA-based full-link delay measurement method of claim 1, characterized in that: the method comprises the step of arranging an optical splitter at the monitoring point in a mode of not introducing extra time delay.

4. The FPGA-based full-link delay measurement method of claim 1, characterized in that: the accuracy of the hardware timestamp is set to nanosecond level.

5. The FPGA-based full-link delay measurement method of any one of claims 1 to 4, wherein: when the message data is TCP data, reconstructing the TCP data before extracting the payload of the message data, including: reordering and de-duplication.

6. The FPGA-based full-link delay measurement method according to claim 5, wherein: the extracting the payload of the message data comprises: and extracting the effective load in the TCP data according to the TCP protocol.

7. The FPGA-based full-link delay measurement method of claim 6, characterized in that: and analyzing the service data according to an agreed service layer protocol comprises filtering and analyzing the reconstructed TCP data according to an original market protocol.

8. The FPGA-based full-link delay measurement method of claim 5, characterized in that: and when the message data is UDP data, extracting the effective load of the message data and then executing packet cutting.

9. The FPGA-based full-link delay measurement method of claim 1, characterized in that: and the formats of the result files of different monitoring points are consistent.

10. The FPGA-based full-link delay measurement method of claim 1, characterized in that: and the step of generating a result file falling plate is to generate the analysis result data into a result file falling plate according to an interface format of an output result.

11. The FPGA-based full-link delay measurement method according to claim 1, wherein: the obtaining of the delay of each network device on the link includes comparing a difference between hardware timestamps in the analysis results of the two monitoring points, and the obtained delay includes: delay within a network device, sequential delay to reach the same network device.

12. A measurement system, characterized by: the FPGA-based full-link delay measurement method of any one of claims 1 to 11 can be executed, comprising an FPGA recording device and a plurality of network devices; the network equipment is in a network topology structure, and the FPGA recording device is in communication connection with a plurality of nodes of the network topology structure.