CN115765741A

CN115765741A - ADC driving interface circuit

Info

Publication number: CN115765741A
Application number: CN202211566600.5A
Authority: CN
Inventors: 马侠; 唐雨晴; 刘清波; 王梓
Original assignee: HI-TREND TECHNOLOGY (SHANGHAI) CO LTD
Current assignee: HI-TREND TECHNOLOGY (SHANGHAI) CO LTD
Priority date: 2022-12-07
Filing date: 2022-12-07
Publication date: 2023-03-07

Abstract

The application relates to the technical field of integrated circuits, and discloses an ADC driving interface circuit, which comprises: the circuit comprises a programmable gain amplifying circuit, an RC filter circuit and a front end sampling circuit, wherein the amplifying circuit comprises a pressure swing control current controlled by a pressure swing control switch; the RC filter circuit comprises a first resistor, a second resistor and a first capacitor, one end of the first resistor and one end of the second resistor are respectively connected with the pendulum pressing control current, the first capacitor is coupled between the other ends of the first resistor and the second resistor, and two ends of the first resistor and two ends of the second resistor are respectively connected with the pendulum pressing control switch in parallel; the front-end sampling circuit comprises a second capacitor and a third capacitor, wherein one end of the second capacitor is coupled to the other end of the first resistor through the first-stage delay control switch, and one end of the third capacitor is coupled to the other end of the second resistor through the first-stage delay control switch. When the ADC sampling is improved, the slew rate of the ADC optimizes the linearity of a large signal, and compromise between noise and linearity can be well achieved.

Description

ADC driving interface circuit

Technical Field

The present application relates to the field of integrated circuit technologies, and in particular, to an ADC driver interface circuit.

Background

In signal chain communication or measurement system application, high requirements are put on the sensitivity and the linearity of an input signal. Specifically, when a small signal is externally input, the sensitivity of the Reception (RX) channel is high, and when a large signal is externally input, the linearity of the reception channel is good. In order to meet the requirement of high precision, a low-noise Programmable Gain Amplifier (PGA) is integrated in the receiving channel before a high-precision analog-to-digital converter (ADC). The PGA requires not only programmable gain, high dynamic range, and low noise, but also the driving capability required by the ADC when interfacing with the ADC. If the PGA and the ADC are directly connected, high requirements are put on the noise and linearity of the PGA. It is difficult to make good tradeoffs in power consumption, area, noise and linearity in the receive channel design.

Disclosure of Invention

The purpose of the present application is to provide an ADC driving interface circuit, which provides an interface circuit of a PGA and an ADC, and simultaneously considers low-noise design of a small signal and high-linearity design of a large signal, so as to not only meet noise and linearity of the whole RX channel, but also greatly reduce design requirements of the PGA, and save area, power consumption, and design complexity of the whole RX channel, thereby in sensor or signal chain communication applications, well considering compromise between sensitivity and linearity.

The application discloses ADC drives interface circuit includes:

a programmable gain amplification circuit comprising a slew control current controlled by a slew control switch;

the RC filter circuit comprises a first resistor, a second resistor and a first capacitor, one end of the first resistor and one end of the second resistor are respectively connected with the voltage swing control current, the first capacitor is coupled between the other end of the first resistor and the other end of the second resistor, and two ends of the first resistor and the second resistor are respectively connected with a voltage swing control switch in parallel;

a front end sampling circuit comprising a second capacitor and a third capacitor, wherein one end of the second capacitor is coupled to the other end of the first resistor via a first stage delay control switch, the other end of the second capacitor is coupled to a second stage delay control switch, and the two ends of the second capacitor are coupled to a common voltage via a second stage control switch and a first stage control switch, respectively, wherein one end of the third capacitor is coupled to the other end of the second resistor via a first stage delay control switch, the other end of the third capacitor is coupled to a second stage delay control switch, and the two ends of the second capacitor are coupled to the common voltage via a second stage control switch and a first stage control switch, respectively.

In a preferred embodiment, the programmable gain amplifying circuit further includes:

an operational amplifier receiving a differential positive input voltage and a differential negative input voltage, respectively;

a floating bias connected to an output of the operational amplifier and dynamically adjusting the positive and negative input voltages;

first to fourth PMOS transistors, sources of the first to fourth PMOS transistors being connected to a voltage source, gates of the first and third PMOS transistors being connected to the adjusted positive input voltage, gates of the second and fourth PMOS transistors being connected to the adjusted positive input voltage via the slew control switch, drains of the first and second PMOS transistors being connected to the first resistor, drains of the third and fourth PMOS transistors being connected to the second resistor;

first to fourth NMOS transistors, the sources of the first to fourth NMOS transistors all connected to ground, the gates of the first and third NMOS transistors connected to the regulated negative input voltage, the gates of the second and fourth NMOS transistors connected to the regulated negative input voltage via the slew control switch, the drains of the first to fourth NMOS transistors are respectively connected with the drains of the first to fourth PMOS transistors, the drains of the first and second NMOS transistors are both connected with the first resistor, and the drains of the third and fourth NMOS transistors are both connected with the second resistor.

In a preferred embodiment, the opening and closing of the pendulum control switch is controlled by a pendulum control signal, the opening and closing of the first-stage control switch is controlled by a first-stage control signal, and the opening and closing of the second-stage control switch is controlled by a second-stage control signal, the first-stage control signal being enabled prior to the second-stage control signal.

In a preferred example, the slew control signal is enabled at the same time that the first-stage control signal is enabled.

In a preferred example, the time during which the slew control signal is enabled is shorter than the time during which the first-stage control signal is enabled.

In a preferred embodiment, the opening and closing of the first-stage delay control switch is controlled by a first-stage delay control signal that is enabled at the same time as the first-stage control signal and is turned off later than the first-stage control signal.

In a preferred embodiment, the opening and closing of the second-stage delay control switch is controlled by a second-stage delay control signal that is enabled simultaneously with the second-stage control signal and is turned off later than the second-stage control signal.

Compared with the prior art, the application has at least the following beneficial effects:

1) A slew (slew) enhanced switch is added on an RC filter network and an output OPAMP of a PGA, and when ADC sampling is carried out, the slew rate (slew rate) of the ADC is improved, so that the linearity of a large signal is optimized.

2) After a voltage swing (slew) enhanced switch is added into an RC filter network, high linearity can be realized without increasing the power consumption of PGA under a large signal, so that the low power consumption design of the whole channel is ensured.

3) The circuit is simple, the hardware cost is low, and compromise between noise and linearity can be well achieved.

The present specification describes a number of technical features distributed throughout the various technical aspects, and if all possible combinations of technical features (i.e. technical aspects) of the present specification are listed, the description is made excessively long. In order to avoid this problem, the respective technical features disclosed in the above summary of the invention of the present application, the respective technical features disclosed in the following embodiments and examples, and the respective technical features disclosed in the drawings may be freely combined with each other to constitute various new technical solutions (which should be regarded as having been described in the present specification) unless such a combination of the technical features is technically infeasible. For example, in one example, the feature a + B + C is disclosed, in another example, the feature a + B + D + E is disclosed, and the features C and D are equivalent technical means for the same purpose, and technically only one feature is used, but not simultaneously employed, and the feature E can be technically combined with the feature C, then the solution of a + B + C + D should not be considered as being described because the technology is not feasible, and the solution of a + B + C + E should be considered as being described.

Drawings

Fig. 1 is a schematic diagram of an ADC driving interface circuit according to an embodiment of the present application.

Fig. 2 is a more detailed structural schematic diagram of an ADC driving interface circuit according to an embodiment of the present application.

Fig. 3 is a schematic diagram of control timing of an ADC driving interface circuit according to an embodiment of the present application.

Detailed Description

In the following description, numerous technical details are set forth in order to provide a better understanding of the present application. However, it will be understood by those skilled in the art that the technical solutions claimed in the present application may be implemented without these technical details and with various changes and modifications based on the following embodiments.

The following outlines some of the innovative points of the embodiments of the present application:

the invention provides a high-linearity ADC driving interface circuit. In general, in a signal chain path, a programmable gain amplifier is integrated in order to improve the signal sensitivity and resolution of the signal chain path. When the programmable gain amplifier is connected to the ADC, two problems need to be solved, one is low noise and one is linearity of large signal. Many of the solutions seen today are intended to reduce the power consumption and requirements of PGA OPAMPs by adding RC filtering circuits, but at large signal inputs, the settling time is slowed and linearity suffers due to the addition of RC filtering. To compensate, the current has to be increased, which does not serve the purpose of reducing power consumption. The interface circuit provided by the invention is arranged between the PGA and the ADC circuit, not only can reduce the noise of the whole channel, but also can optimize the linearity of a large signal of the channel, and simultaneously can reduce the bandwidth and power consumption requirements of the PGA OPAMP.

To make the objects, technical solutions and advantages of the present application more clear, embodiments of the present application will be described in further detail below with reference to the accompanying drawings.

One embodiment of the present application relates to an ADC driving interface circuit, which is configured as shown in fig. 1, and includes: programmable gain amplifier circuit 100, RC filter circuit 300, front end sampling circuit 200. The programmable gain amplifier circuit 100 includes a slew control current I _ slew controlled by a slew control switch. The RC filter circuit 200 includes a first resistor R1, a second resistor R2 and a first capacitor C1, one end of the first resistor R1 and one end of the second resistor R2 are respectively connected to the slew control current I _ slew, the first capacitor C1 is coupled between the other end of the first resistor R1 and the other end of the second resistor R2, and two ends of the first resistor R1 and the second resistor R2 are respectively connected in parallel to slew control switches. The front-end sampling circuit 200 comprises a second capacitor C2A and a third capacitor C2B, wherein one end of the second capacitor C2A is coupled to the other end of the first resistor R1 via a first-stage delay control switch, the other end of the second capacitor C2A is coupled to a second-stage delay control switch, and the two ends of the second capacitor C2A are coupled to the common voltage VCM via a second-stage delay control switch and a first-stage control switch, respectively, wherein one end of the third capacitor C2B is coupled to the other end of the second resistor R2 via a first-stage delay control switch, the other end of the third capacitor C2B is coupled to a second-stage delay control switch, and the two ends of the second capacitor C2B are coupled to the common voltage VCM via a second-stage control switch and a first-stage control switch, respectively.

In one embodiment, the opening and closing of the slew control switch is controlled by a slew control signal Ph1_ slew, the opening and closing of the first stage control switch is controlled by a first stage control signal Ph1, the opening and closing of the second stage control switch is controlled by a second stage control signal Ph2, the opening and closing of the first stage delay control switch is controlled by a first stage delay control signal Ph1_ d, and the opening and closing of the second stage delay control switch is controlled by a second stage delay control signal Ph2_ d. Wherein the first phase control signal Ph1 is enabled prior to the second phase control signal Ph 2. In one embodiment, the slew control signal Ph1_ slew is enabled at the same time that the first phase control signal Ph1 is enabled. In one embodiment, the slew control signal Ph1_ slew is enabled for a shorter time than the first phase control signal Ph1 is enabled. For example, the slew control signal Ph1_ slew may be a very short pulse signal.

In one embodiment, the first-phase delayed control signal Ph1_ d is enabled at the same time as the first-phase control signal Ph1 and is turned off later than the first-phase control signal Ph 1. In one embodiment, the second phase delay control signal Ph2_ d is enabled at the same time as the second phase control signal Ph2 and is turned off later than the second phase control signal Ph 2.

Referring to FIG. 1, when ph1 and ph1_ d are enabled, capacitor C1 charges capacitors C2A and C2B. When ph2 and ph2_ d are enabled, the voltage across the capacitors C2A and C2B is detected by the subsequent circuit.

In one embodiment, referring to fig. 2, the programmable gain amplifying circuit 100 further comprises: an operational amplifier (OPAMP) 101, a Floating Bias (Floating Bias) 102, a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a fourth PMOS transistor MP4, a first NMOS transistor NP1, a second NMOS transistor NP2, a third NMOS transistor NP3, and a fourth NMOS transistor NP4.

The operational amplifier 101 receives a differential positive input voltage Vinp and a differential negative input voltage Vinn, respectively. The floating bias 102 is connected to the output of the operational amplifier 101 and dynamically adjusts the positive input voltage Vinp and the negative input voltage Vinn, outputting and adjusting the positive input voltage Vfp and the negative input voltage Vfn. Since the op-amp 101 is class AB output, the PMOS and NMOS gates are dynamically adjusted according to the output load, and the floating bias 102 can do this. If the gate is fixed, the output current is fixed, rather than floating.

The sources of the first PMOS transistor MP1, the second PMOS transistor MP2, the third PMOS transistor MP3, and the fourth PMOS transistor MP4 are all connected to a voltage source, the gates of the first PMOS transistor MP1 and the third PMOS transistor MP3 are connected to the adjusted positive input voltage, the gates of the second PMOS transistor MP2 and the fourth PMOS transistor MP4 are connected to the adjusted positive input voltage Vfp through the swing control switch, the drains of the first PMOS transistor MP1 and the second PMOS transistor MP2 are both connected to the first resistor R1, and the drains of the third PMOS transistor MP3 and the fourth PMOS transistor MP4 are both connected to the second resistor R2. The drain of the first PMOS transistor MP1 is connected to the drain of the first NMOS transistor NP1, the drain of the second PMOS transistor MP2 is connected to the drain of the second NMOS transistor NP2, the drain of the third PMOS transistor MP3 is connected to the drain of the third NMOS transistor NP3, and the drain of the fourth PMOS transistor MP4 is connected to the drain of the fourth NMOS transistor NP4.

The sources of the first NMOS transistor NP1, the second NMOS transistor NP2, the third NMOS transistor NP3, and the fourth NMOS transistor NP4 are all connected to ground, the gates of the first NMOS transistor NP1 and the third NMOS transistor NP2 are connected to the adjusted negative input voltage, the gates of the second NMOS transistor NP2 and the fourth NMOS transistor NP4 are connected to the adjusted negative input voltage Vfn through the slew control switch, the drains of the first NMOS transistor NP1 and the second NMOS transistor NP2 are both connected to the first resistor R2, and the drains of the third NMOS transistor NP3 and the fourth NMOS transistor NP4 are both connected to the second resistor R2.

It should be understood that the first PMOS transistor MP1, the second PMOS transistor MP2, the third PMOS transistor MP3, the fourth PMOS transistor MP4, the first NMOS transistor NP1, the second NMOS transistor NP2, the third NMOS transistor NP3, and the fourth NMOS transistor NP4 constitute the slew control current I _ slew shown in fig. 1. When the control signal ph1_ slew is enabled, the second PMOS transistor MP2 and the fourth PMOS transistor MP4, and the second NMOS transistor NP2 and the fourth NMOS transistor NP4 are turned on, so that the voltages of Vop and Von are output, and the current of the output stage of the OPAMP is increased, so that the voltage swing control current I _ slew can be controlled according to ph1_ slew.

According to the method, the slew rate and the current requirement of the PGA OPAMP can be greatly relieved by adding a signal ph1_ slew controlled by a switch. Referring to fig. 2 and 3, ph1_ slew controls both the output stage of OPAMP and the RC network of the PGA. When the ADC enters a sampling mode, the sampling current of the ADC is provided by two parts, one part is provided by the first capacitor C1 to provide charge for the sampling network of the ADC, and the other part is provided by the OPAMP of the PGA to provide current. When the ADC switches from the integration mode to the sampling mode, the voltages at the two ends of the second capacitor C2A and the third capacitor C2B cannot change suddenly, so that the Vxp and the Vxn signals experience a relatively large jump, and the output of the OPAMP of the PGA is correspondingly pulled low. The OPAMP of PGA goes to the slew state, where we set ph1_ slew high and hold it for a short time. In the short ph1_ slew time, the OPAMP in the PGA will increase the current at the output stage to improve the slew rate capability, and at the same time, in the RC filter network, the switches parallel to the resistors R1 and R2 will be closed at the same time, and the output of the PGA will bypass (bypass) the filter resistors R1 and R2, and since the on-resistance of the switch of ph1_ slew is very low, the time constant for charging the current of the PGA OPAMP to the capacitors C1, C2A, and C2B will also become small.

The ph1_ slew of the present application will control the output current of the OPAMP and the time constant of the filter network at the same time, so the output of the PGA will be quickly established and enter the small signal establishment phase as soon as possible. When ph1_ slew is low, the switch is switched off, the PGA enters a normal working mode, and the RC filter network returns to normal. The RC filter network provides a low-pass filter for the signal channel, and because the first capacitor C1 continuously provides charges for the sampling network, the bandwidth requirement of the PGA buffer is also reduced, and the PGA buffer can still work under a small current, so that the power consumption of the whole path is saved.

The pulse width of ph1_ slew needs to be compromised in terms of linearity and noise performance, and ph1_ slew has long switching time, is good for linearity, has sufficient time to build, but has relatively small time for filtering, and the noise performance is poor. And ph1_ slew time is too short, linearity optimization is limited.

It is noted that, in the present patent application, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, the use of the verb "comprise a" to define an element does not exclude the presence of another, same element in a process, method, article, or apparatus that comprises the element. In the present patent application, if it is mentioned that a certain action is executed according to a certain element, it means that the action is executed according to at least the element, and two cases are included: performing the action based only on the element, and performing the action based on the element and other elements. The expression of a plurality of, a plurality of and the like includes 2, 2 and more than 2, more than 2 and more than 2.

The term "coupled to" and its derivatives may be used herein. "coupled" may mean that two or more elements are in direct physical or electrical contact. However, "coupled" may also mean that two or more elements are in indirect contact with each other, but yet still co-operate or interact with each other, and may mean that one or more other elements are coupled or connected between the elements that are said to be coupled to each other.

This specification includes combinations of the various embodiments described herein. Separate references to embodiments (e.g., "one embodiment" or "some embodiments" or "a preferred embodiment") do not necessarily refer to the same embodiment; however, these embodiments are not mutually exclusive, unless indicated as mutually exclusive or as would be apparent to one of ordinary skill in the art. It should be noted that the term "or" is used in this specification in a non-exclusive sense unless the context clearly dictates otherwise or requires otherwise.

All documents mentioned in this specification are to be considered as being incorporated in their entirety into the disclosure of the present application so as to be subject to modification as necessary. It should be understood that the above description is only a preferred embodiment of the present disclosure, and is not intended to limit the scope of the present disclosure. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of one or more embodiments of the present disclosure should be included in the scope of protection of one or more embodiments of the present disclosure.

Claims

1. An ADC drive interface circuit, comprising:

2. The ADC driver interface circuit of claim 1, wherein the programmable gain amplification circuit further comprises:

3. The ADC drive interface circuit of claim 1 wherein the opening and closing of the slew control switch is controlled by a slew control signal, the opening and closing of the first stage control switch is controlled by a first stage control signal, and the opening and closing of the second stage control switch is controlled by a second stage control signal, the first stage control signal being enabled prior to the second stage control signal.

4. The ADC drive interface circuit of claim 3 wherein said slew control signal is enabled at the same time that said first stage control signal is enabled.

5. The ADC drive interface circuit of claim 4 wherein said slew control signal is enabled for a time shorter than a time said first stage control signal is enabled.

6. The ADC drive interface circuit of claim 3 wherein opening and closing of the first stage delay control switch is controlled by a first stage delay control signal that is enabled at the same time as the first stage control signal and is turned off later than the first stage control signal.

7. The ADC drive interface circuit of claim 3 wherein opening and closing of the second stage delay control switch is controlled by a second stage delay control signal that is enabled simultaneously with the second stage control signal and is turned off later than the second stage control signal.