CN115765732A - Apparatus and method for adjusting frequency divider, chip and storage medium - Google Patents
Apparatus and method for adjusting frequency divider, chip and storage medium Download PDFInfo
- Publication number
- CN115765732A CN115765732A CN202211578401.6A CN202211578401A CN115765732A CN 115765732 A CN115765732 A CN 115765732A CN 202211578401 A CN202211578401 A CN 202211578401A CN 115765732 A CN115765732 A CN 115765732A
- Authority
- CN
- China
- Prior art keywords
- frequency
- module
- target
- frequency divider
- divider
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
Landscapes
- Power Sources (AREA)
Abstract
The present disclosure provides an apparatus and method, a chip, and a storage medium for adjusting a frequency divider. The device comprises a dormancy module, a monitoring module, an up-conversion module and a down-conversion module; the status module is configured to generate status information of a target module; the listening module is configured to listen for the status information; the frequency boosting module is configured to increase the frequency of the frequency divider of the target module to a first target frequency when the state information is a switch from a low load to a high load; the frequency down module is configured to reduce the frequency of the frequency divider of the target module to a second target frequency when the status information is idle or switched from high load to low load. In the technical scheme, the frequency divider frequency is automatically adjusted based on the real-time state of the system, so that the stability of system operation is improved, and the power consumption of the system is saved.
Description
Technical Field
The present disclosure relates to the field of frequency dividers, and in particular, to an apparatus and method for adjusting a frequency divider, a chip, and a storage medium.
Background
In many electronic devices such as electronic clocks, frequency synthesizers, etc., signals of different frequencies are required to work cooperatively, and a common method is to use a crystal oscillator with high stability as a main oscillation source and obtain various required frequency components through conversion. Among them, the frequency divider is a main frequency conversion means.
In the prior art, when functional modules such as a CPU, a GPU, an NPU, a coder-decoder and the like of a circuit system are switched from a low load to a high load, current abrupt change can be generated in a short time. The voltage collapse is caused by the delay of the circuit response, so that the system works abnormally, and the normal operation of the circuit can be ensured by increasing the power supply voltage.
In addition, under the condition of low load or low data throughput of the functional module, the frequency on the data bus is still consistent with the frequency in the working state, so that the waste of power consumption is caused.
Disclosure of Invention
Embodiments of the present disclosure provide an apparatus and method for adjusting a frequency divider, a chip, and a storage medium, which perform automatic adjustment of a frequency of the frequency divider based on a real-time state of a system, thereby improving stability of system operation and saving system power consumption.
In a first aspect, the present disclosure provides an apparatus for adjusting a frequency divider. The device includes: a sleep module configured to generate state information of a target module; an intercept module configured to intercept the state information; a frequency raising module configured to raise a frequency of a frequency divider of the target module to a first target frequency when the state information is a switch from a low load to a high load; and a frequency reduction module configured to reduce the frequency of the frequency divider of the target module to a second target frequency when the status information is idle or switched from high load to low load.
In one implementation form of the first aspect, the frequency boosting module is configured to: receiving an up-conversion instruction sent by the interception module based on the state information; increasing the voltage of the frequency divider, and increasing the frequency of the frequency divider by a first preset value at intervals of a first preset duration until the voltage and the frequency of the frequency divider are a first target voltage and a first target frequency; and sending the frequency raising feedback information to the interception module.
In one implementation of the first aspect, the frequency boost module is configured to: receiving an up-conversion instruction sent by the interception module based on the state information; sending a voltage increasing signal to an external power supply management module, increasing the frequency of the frequency divider after the external power supply management module finishes boosting, and then increasing the frequency of the frequency divider to the first target frequency by the target module; and sending the frequency boosting feedback information to the interception module.
In one implementation of the first aspect, the frequency reduction module is configured to: receiving a frequency reduction instruction sent by the interception module based on the state information; reducing the frequency of the frequency divider by a second preset value every second preset time interval until the frequency of the frequency divider is the second target frequency, and reducing the voltage of the frequency divider to be a second target voltage; and sending the frequency reduction feedback information to the interception module.
In one implementation of the first aspect, the frequency reduction module is configured to: receiving a frequency reduction instruction sent by the interception module based on the state information; enabling the target module to reduce the frequency of the frequency divider to the second target frequency, then sending a voltage reduction signal to an external power management module, and waiting for the external power management module to reduce the voltage to a second target voltage; and sending the frequency reduction feedback information to the interception module.
In an implementation manner of the first aspect, the apparatus further includes a clearing module, where the clearing module is configured to clear data in the listening module when the status information is that the automatic frequency modulation function is turned off.
In a second aspect, the present disclosure provides a method for adjusting a frequency divider. The method comprises the following steps: generating state information of the target module; monitoring the state information when the automatic frequency modulation function is started; when the state information is switching from low load to high load, increasing the frequency of a frequency divider of the target module to a first target frequency; and when the state information is idle or switching from high load to low load, reducing the frequency of the frequency divider of the target module to a second target frequency.
In one implementation of the second aspect, increasing the frequency of the frequency divider of the target module to a first target frequency comprises: receiving an up-conversion instruction generated based on the state information; responding to the frequency increasing instruction, and increasing the frequency of the frequency divider by a first preset value at intervals of a first preset time length until the frequency of the frequency divider is the first target frequency; and sending the frequency raising feedback information to the interception module.
In one implementation of the second aspect, increasing the frequency of the frequency divider of the target module to a first target frequency comprises: receiving an up-conversion instruction generated based on the state information; responding to the frequency increasing instruction, sending a voltage increasing signal to an external power supply management module, waiting for the external power supply management module to increase the frequency of the frequency divider after the external power supply management module finishes voltage increasing, and then increasing the frequency of the frequency divider to the first target frequency by the target module; and sending the frequency boosting feedback information to the interception module.
In one implementation of the second aspect, reducing the frequency of the frequency divider of the target module to a second target frequency comprises: receiving a frequency reduction instruction generated based on the state information; in response to the frequency reduction instruction, reducing the frequency of the frequency divider by a second preset value at intervals of a second preset time length until the frequency of the frequency divider is the second target frequency; and sending the frequency reduction feedback information to the interception module.
In one implementation of the second aspect, reducing the frequency of the frequency divider of the target module to a second target frequency comprises: receiving a frequency reduction instruction generated based on the state information; responding to the frequency reduction instruction, enabling the target module to reduce the frequency of the frequency divider to the second target frequency, then sending a voltage reduction signal to an external power supply management module, and waiting for the external power supply management module to reduce the voltage to the second target voltage; sending down-conversion feedback information to the interception module
In one implementation form of the second aspect, the method further comprises: and when the state information is that the automatic frequency modulation function is closed, clearing the sensed data.
In a third aspect, the present disclosure provides a chip. The chip includes: a frequency divider; and the above-mentioned device.
In a fourth aspect, the present disclosure provides a computer-readable storage medium having stored thereon a computer program for execution by a processor to implement the above-described method.
According to the embodiment of the disclosure, the device and method for adjusting the frequency divider, the chip and the storage medium of the disclosure automatically adjust the frequency of the frequency divider when the system is switched from a low load to a high load through real-time monitoring of the system state, thereby avoiding instantaneous current when the functional module is switched from the low load to the high load and reducing the possibility of voltage collapse; and when the system is idle, the frequency on the data bus is reduced, and the running power consumption of the system is saved.
Drawings
Fig. 1 is a schematic diagram illustrating an embodiment of an apparatus for adjusting a frequency divider according to the present disclosure;
FIG. 2 is a flow chart of an apparatus for adjusting a frequency divider according to an embodiment of the present disclosure;
FIG. 3 is a block diagram of a method for adjusting a frequency divider according to an embodiment of the present disclosure;
fig. 4 is a schematic structural diagram of a chip according to an embodiment of the disclosure.
Detailed Description
The embodiments of the present disclosure are described below with specific examples, and other advantages and effects of the present disclosure will be readily apparent to those skilled in the art from the disclosure in the specification. The disclosure may be carried into practice or applied to various other specific embodiments, and various modifications and changes may be made in the details within the description and the drawings without departing from the spirit of the disclosure.
It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present disclosure, and the components related to the present disclosure are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complex.
The scheme for adjusting the frequency divider is applied to a System On Chip (SOC), which belongs to a functional module for frequency divider automatic frequency modulation on the SOC. The frequency divider frequency is automatically adjusted based on the real-time state of the system, so that the stability of system operation is improved, and the power consumption of the system is saved.
Hereinafter, embodiments according to the present disclosure are described by way of detailed description with reference to the accompanying drawings.
Fig. 1 shows a schematic structural diagram of an apparatus for adjusting a frequency divider according to an embodiment of the present disclosure. Fig. 2 shows a block schematic of an apparatus for adjusting a frequency divider according to an embodiment of the present disclosure. As shown in fig. 1, the system includes a sleep module 1, a listening module 2, an up-conversion module 3, and a down-conversion module 4.
The hibernation module 1 is configured to generate status information of the target module. The state information includes the auto-tune enable information dvfs _ en and the system IDLE information IDLE. In some embodiments, when the chirp enable information dvfs _ en is a low level signal, it indicates that the chirp function of the frequency divider is turned off, and when the chirp enable information dvfs _ en is a high level signal, it indicates that the chirp function of the frequency divider is turned on. Further, the exit of the system IDLE information IDLE or the level pull-down indicates a transition from a low load to a high load, and the entry of the system IDLE information IDLE or the level pull-up indicates a transition from a high load to a low load.
The interception module 2 is connected to the dormant module 1, and the interception module 2 is configured to intercept the status information.
The frequency boosting module 3 is connected to the listening module 2, and the frequency boosting module 3 is configured to increase the frequency of the frequency divider of the target module to a first target frequency when the state information is a switch from a low load to a high load. To reduce the possibility of voltage collapse when the target module switches from low load to high load, the up-conversion module 3 will gently increase the frequency of the frequency divider.
In an embodiment, as shown in fig. 2, when the state information is switched from low load to high load, 31) the frequency boost module 3 receives a frequency boost command fup _ trig signal sent by the listening module based on the state information. And then 32) increasing the voltage of the frequency divider, and increasing the frequency of the frequency divider by a first preset value at intervals of a first preset duration until the voltage and the frequency of the frequency divider are a first target voltage and a first target frequency. And according to a first preset time length t1, subtracting a first preset value step1 from the value of the current frequency division register until the frequency division value of the first target frequency is reached. The values of step1 and t1 can be custom set by the user. Subsequently, 33) sending an up-conversion feedback information fup _ cached signal to the listening module.
In another embodiment, when the status information is switched from low load to high load, 31'), the frequency boosting module 3 receives a frequency boosting command sent by the listening module based on the status information. Then, 32') sending a voltage raising signal to an external power management module, waiting for the external power management module to raise the frequency of the frequency divider after the external power management module finishes boosting, and then raising the frequency of the frequency divider to the first target frequency by the target module. Setting, by the target module, the frequency of the frequency divider directly to the first target frequency. Then 33') sends an up-conversion feedback message to the listening module.
The down-conversion module 4 is connected to the listening module 2, and the down-conversion module 4 is configured to reduce the frequency of the frequency divider of the target module to a second target frequency when the status information is idle or is switched from a high load to a low load. When the target module is switched from low load to high load, the frequency-reducing module 4 will gradually reduce the frequency of the frequency divider, thereby saving system power consumption.
In an embodiment, as shown in fig. 2, when the state information is switched from high load to low load, 41) the down-conversion module 4 receives a down-conversion command fdwn _ trig signal sent by the interception module based on the state information. And then 42) reducing the frequency of the frequency divider by a second preset value every second preset time interval until the frequency of the frequency divider is the second target frequency, and reducing the voltage of the frequency divider to be a second target voltage. And adding a second preset value step2 to the value of the current frequency division register according to a second preset time length t2 until the frequency division value of the second target frequency is reached. The values of step2 and t2 can be custom set by the user. Subsequently, 43) send the down-conversion feedback information fdwn _ cached to the listening module.
In another embodiment, when the status information is switched from high load to low load, 41'), the down-conversion module 4 receives a down-conversion instruction sent by the listening module based on the status information. Then 42') causing the target module to reduce the frequency of the frequency divider to the second target frequency, and then sending a voltage reduction signal to an external power management module, waiting for the external power management module to reduce the voltage to the second target voltage. Setting, by the target module, the frequency of the frequency divider directly to the second target frequency. Then 43') sends down feedback information to the listening module.
In addition, the apparatus for adjusting a frequency divider of the embodiments of the present disclosure may further include a clearing module 5. The clearing module 5 is connected with the monitoring module 2, and the clearing module 5 is configured to clear the data in the dormant module when the state information is that the automatic frequency modulation function is turned off. And when the state information dvfs _ en signal of the sleep module 1 is at a low level, indicating that the automatic frequency conversion function is closed. When receiving the dvfs _ en signal, the interception module 2 notifies the clearing module 5 of closing the automatic frequency conversion function through the dvfs _ disable signal. At this time, the clearing module clears the data generated by the interception module so as to facilitate subsequent state interception.
The protection scope of the method for adjusting the frequency divider according to the embodiment of the present disclosure is not limited to the execution sequence of the steps listed in this embodiment, and all the schemes of adding, subtracting, and replacing steps in the prior art according to the principles of the present disclosure are included in the protection scope of the present disclosure.
The embodiments of the present disclosure also provide a device for adjusting a frequency divider, which can implement the method for adjusting a frequency divider described in the present disclosure, but the implementation device of the device for adjusting a frequency divider described in the present disclosure includes, but is not limited to, the structure of the device for adjusting a frequency divider listed in this embodiment, and all the structural modifications and substitutions of the prior art made according to the principles of the present disclosure are included in the scope of the present disclosure.
Fig. 3 shows a flow diagram of a method for adjusting a frequency divider according to an embodiment of the disclosure. As shown in fig. 3, the method for adjusting a frequency divider of the present disclosure includes the following steps S1 to S4.
In step S1, state information of the target module is generated based on the hibernation module. The state information includes the auto-tune enable information dvfs _ en and the system IDLE information IDLE. And when the automatic frequency modulation enabling information dvfs _ en is a low-level signal, the automatic frequency modulation function of the frequency divider is turned off. And when the automatic frequency modulation enabling information dvfs _ en is a high-level signal, the automatic frequency modulation function of the frequency divider is started. When the system IDLE information IDLE exits or the level is pulled low, it indicates a transition from low load to high load. The system IDLE information IDLE enters or the level is pulled high, indicating a transition from high load to low load.
And S2, monitoring the state information based on the monitoring module when the automatic frequency modulation function is started.
In step S3, when the state information is switched from low load to high load based on the frequency increasing module, the frequency of the frequency divider of the target module is increased to a first target frequency. To reduce the likelihood of voltage collapse when the target module switches from low load to high load, the up-conversion module will gently increase the frequency of the frequency divider.
In one embodiment, as shown in fig. 2, increasing the frequency of the frequency divider of the target module based on the frequency increasing module when the state information is switched from low load to high load includes the following steps.
31 Receive an up-conversion instruction fup _ trig signal generated based on the state information.
32 In response to the frequency increasing instruction, increasing the frequency of the frequency divider by a first preset value every a first preset time interval until the frequency of the frequency divider is the first target frequency. And according to a first preset time length t1, subtracting a first preset value step1 from the value of the current frequency division register until the frequency division value of the first target frequency is reached. The values of step1 and t1 can be set by user customization.
33 Send an up-conversion feedback information fup _ cached signal to the listening module.
In another embodiment, increasing the frequency of the frequency divider of the target module based on the frequency increasing module when the state information is a switch from a low load to a high load comprises the following steps.
31') receives an up-conversion instruction generated based on the state information.
32') in response to the frequency-increasing instruction, sending a voltage-increasing signal to an external power management module, waiting for the external power management module to increase the frequency of the frequency divider after the external power management module finishes boosting, and then increasing the frequency of the frequency divider to the first target frequency by the target module. Setting, by the target module, the frequency of the divider directly to the first target frequency.
33') sending an up-conversion feedback message to the listening module.
In step S4, based on the frequency-reducing module, when the state information is idle or switching from high load to low load, the frequency of the frequency divider of the target module is reduced to a second target frequency. When the target module is switched from low load to high load, the frequency-reducing module 4 will gradually reduce the frequency of the frequency divider, thereby saving system power consumption.
In one embodiment, as shown in fig. 2, the step of reducing the frequency of the frequency divider of the target module to a second target frequency based on the down-conversion module when the status information is switched from high load to low load comprises the following steps.
41 Receive a down command fdwn _ trig signal generated based on the state information.
42 In response to the down-conversion instruction, reducing the frequency of the frequency divider by a second preset value every second preset time interval until the frequency of the frequency divider is the second target frequency. And adding a second preset value step2 to the value of the current frequency division register according to a second preset time length t2 until the frequency division value of the second target frequency is reached. The values of step2 and t2 can be custom set by the user.
43 Send down feedback information fdwn _ cached to the listening module.
In another embodiment, the step of reducing the frequency of the frequency divider of the target module to a second target frequency based on the down-conversion module when the status information is switching from high load to low load comprises the following steps.
41') receive a down-conversion instruction generated based on the status information.
42') in response to the down-conversion instruction, the target module is caused to reduce the frequency of the frequency divider to the second target frequency, and then a voltage reduction signal is sent to the external power management module to wait for the external power management module to reduce the voltage to the second target voltage. Wherein the frequency of the frequency divider is directly set to the second target frequency by the target module.
43') sending a down-conversion feedback message to the listening module.
In addition, the method for adjusting the frequency divider of the embodiment of the present disclosure further includes clearing data in the sleep module based on a clearing module when the state information is that the automatic frequency modulation function is turned off. And when the state information dvfs _ en signal of the sleep module is in a low level, indicating that the automatic frequency conversion function is closed. And when the interception module receives the dvfs _ en signal, informing the clearing module of closing the automatic frequency conversion function through the dvfs _ disable signal. At this time, the clearing module clears the data generated by the interception module so as to facilitate subsequent state interception.
In the several embodiments provided in the present disclosure, it should be understood that the disclosed system, apparatus, or method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, a module/unit may be divided into only one logical functional division, and an actual implementation may have another division, for example, a plurality of modules or units may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or modules or units, and may be in an electrical, mechanical or other form.
Modules/units described as separate parts may or may not be physically separate, and parts displayed as modules/units may or may not be physical modules, may be located in one place, or may be distributed on a plurality of network units. Some or all of the modules/units can be selected according to actual needs to achieve the purposes of the embodiments of the present disclosure. For example, each functional module/unit in the embodiments of the present disclosure may be integrated into one processing module, or each module/unit may exist alone physically, or two or more modules/units may be integrated into one module/unit.
It will be further appreciated by those of ordinary skill in the art that the elements and algorithm steps of the examples described in connection with the embodiments disclosed herein may be embodied in electronic hardware, computer software, or combinations of both, and that the components and steps of the examples have been described in a functional general in the foregoing description for the purpose of illustrating clearly the interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.
The embodiment of the disclosure also provides a computer readable storage medium. It will be understood by those of ordinary skill in the art that all or part of the steps in the method for adjusting a frequency divider implementing the above embodiments may be implemented by a program that is stored in a computer-readable storage medium, where the storage medium is a non-transitory (non-transitory) medium, such as a random access memory, a read-only memory, a flash memory, a hard disk, a solid state disk, a magnetic tape (magnetic tape), a floppy disk (floppy disk), an optical disk (optical disk), and any combination thereof. The storage medium may be any available medium that can be accessed by a computer or a data storage device including one or more available media integrated servers, data centers, and the like. The usable medium may be a magnetic medium (e.g., a floppy disk, a hard disk, a magnetic tape), an optical medium (e.g., a Digital Video Disk (DVD)), or a semiconductor medium (e.g., a Solid State Disk (SSD)), among others.
As shown in fig. 4, an embodiment of the present disclosure further provides a chip, which includes a frequency divider 401 and the foregoing apparatus 402 for adjusting the frequency divider.
The foregoing embodiments are merely illustrative of the principles of the present disclosure and their efficacy, and are not to be construed as limiting the disclosure. Any person skilled in the art can modify or change the above-described embodiments without departing from the spirit and scope of the present disclosure. Accordingly, it is intended that all equivalent modifications or changes be made by those skilled in the art without departing from the spirit and technical spirit of the present disclosure and be covered by the claims of the present disclosure.
Claims (14)
1. An apparatus for adjusting a frequency divider, comprising:
a sleep module configured to generate state information of a target module;
an intercept module configured to intercept the state information;
a frequency boosting module configured to increase a frequency of a frequency divider of the target module to a first target frequency when the state information is a switch from a low load to a high load; and
a down-conversion module configured to reduce the frequency of the frequency divider of the target module to a second target frequency when the status information is idle or switched from high load to low load.
2. The apparatus of claim 1, wherein the frequency boosting module is configured to:
receiving an up-conversion instruction sent by the interception module based on the state information;
increasing the voltage of the frequency divider, and increasing the frequency of the frequency divider by a first preset value at intervals of a first preset duration until the voltage and the frequency of the frequency divider are a first target voltage and a first target frequency;
and sending the frequency raising feedback information to the interception module.
3. The apparatus of claim 1, wherein the frequency boosting module is configured to:
receiving an up-conversion instruction sent by the interception module based on the state information;
sending a voltage increasing signal to an external power supply management module, increasing the frequency of the frequency divider after the external power supply management module finishes boosting, and then increasing the frequency of the frequency divider to the first target frequency by the target module;
and sending the frequency raising feedback information to the interception module.
4. The apparatus of claim 1, wherein the frequency reduction module is configured to:
receiving a frequency reduction instruction sent by the interception module based on the state information;
reducing the frequency of the frequency divider by a second preset value every second preset time interval until the frequency of the frequency divider is the second target frequency, and reducing the voltage of the frequency divider to be a second target voltage;
and sending the frequency reduction feedback information to the interception module.
5. The apparatus of claim 1, wherein the frequency reduction module is configured to:
receiving a frequency reduction instruction sent by the interception module based on the state information;
enabling the target module to reduce the frequency of the frequency divider to the second target frequency, then sending a voltage reduction signal to an external power management module, and waiting for the external power management module to reduce the voltage to a second target voltage;
and sending the frequency reduction feedback information to the interception module.
6. The apparatus of claim 1, further comprising a clearing module configured to clear data in the listening module when the status information is that the auto-tune function is off.
7. A method for adjusting a frequency divider, comprising:
generating state information of the target module;
monitoring the state information when the automatic frequency modulation function is started;
when the state information is switching from low load to high load, increasing the frequency of a frequency divider of the target module to a first target frequency;
and when the state information is idle or switching from high load to low load, reducing the frequency of the frequency divider of the target module to a second target frequency.
8. The method of claim 7, wherein increasing the frequency of the frequency divider of the target module to a first target frequency comprises:
receiving an up-conversion instruction generated based on the state information;
responding to the frequency increasing instruction, and increasing the frequency of the frequency divider by a first preset value at intervals of a first preset time length until the frequency of the frequency divider is the first target frequency;
and sending the frequency raising feedback information to the interception module.
9. The method of claim 7, wherein increasing the frequency of the frequency divider of the target module to a first target frequency comprises:
receiving an up-conversion instruction generated based on the state information;
responding to the frequency increasing instruction, sending a voltage increasing signal to an external power supply management module, waiting for the external power supply management module to increase the frequency of the frequency divider after the external power supply management module finishes voltage increasing, and then increasing the frequency of the frequency divider to the first target frequency by the target module;
and sending the frequency boosting feedback information to the interception module.
10. The method of claim 7, wherein reducing the frequency of the frequency divider of the target module to a second target frequency comprises:
receiving a frequency reduction instruction generated based on the state information;
in response to the frequency reduction instruction, reducing the frequency of the frequency divider by a second preset value at intervals of a second preset time length until the frequency of the frequency divider is the second target frequency;
and sending the frequency reduction feedback information to the interception module.
11. The method of claim 7, wherein reducing the frequency of the frequency divider of the target module to a second target frequency comprises:
receiving a frequency reduction instruction generated based on the state information;
responding to the frequency reduction instruction, enabling the target module to reduce the frequency of the frequency divider to the second target frequency, then sending a voltage reduction signal to an external power supply management module, and waiting for the external power supply management module to reduce the voltage to the second target voltage;
and sending the frequency reduction feedback information to the interception module.
12. The method of claim 7, further comprising: and when the state information is that the automatic frequency modulation function is closed, clearing the sensed data.
13. A chip, comprising:
a frequency divider; and
the device of any one of claims 1 to 6.
14. A computer-readable storage medium, on which a computer program is stored, the computer program being executable by a processor for implementing the method according to any one of claims 7 to 12.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211578401.6A CN115765732A (en) | 2022-12-09 | 2022-12-09 | Apparatus and method for adjusting frequency divider, chip and storage medium |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211578401.6A CN115765732A (en) | 2022-12-09 | 2022-12-09 | Apparatus and method for adjusting frequency divider, chip and storage medium |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN115765732A true CN115765732A (en) | 2023-03-07 |
Family
ID=85345075
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202211578401.6A Pending CN115765732A (en) | 2022-12-09 | 2022-12-09 | Apparatus and method for adjusting frequency divider, chip and storage medium |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115765732A (en) |
-
2022
- 2022-12-09 CN CN202211578401.6A patent/CN115765732A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP1325402B1 (en) | Processor power mode transition | |
| JP5707321B2 (en) | Sleep processor | |
| US8095818B2 (en) | Method and apparatus for on-demand power management | |
| CN1202457C (en) | Method and apparatus to provide deterministic power-on voltage in system having processor-controlled voltage level | |
| CN108885486B (en) | Enhanced Dynamic Clock and Voltage Scaling (DCVS) scheme | |
| US11644884B2 (en) | Controlling a processor clock | |
| KR20040060727A (en) | Dynamic Voltage Transitions | |
| US10147464B1 (en) | Managing power state in one power domain based on power states in another power domain | |
| US20220244772A1 (en) | Power management method and device | |
| CN111142644A (en) | Hard disk operation control method and device and related components | |
| WO2019005281A1 (en) | Bandwidth-monitored frequency hopping within a selected dram operating point | |
| US10732697B2 (en) | Voltage rail coupling sequencing based on upstream voltage rail coupling status | |
| CN112041779A (en) | PDN resonance aware wake-up control | |
| US7181634B2 (en) | Apparatus for switching between a combination of operating modes such that the power consumed is reduced relative to the time of switching | |
| US9223384B2 (en) | Synthesizing intermediate performance levels in integrated circuits, and related processor systems, methods, and computer-readable media | |
| CN102929381B (en) | Electronic system and method for managing power supply thereof | |
| CN104204988A (en) | Active display processor sleep state | |
| US20130297953A1 (en) | Control system | |
| US7167992B2 (en) | Method for controlling the switching of operating modes of an information processor according to the time of switching of the operating modes | |
| US9841804B2 (en) | Clocking a processor | |
| CN111406254A (en) | Configurable data refresh from volatile memory to non-volatile memory | |
| CN115765732A (en) | Apparatus and method for adjusting frequency divider, chip and storage medium | |
| US8452993B2 (en) | Circuits, systems, and methods for dynamically controlling a power supply configuration in response to load requirements from a digital circuit | |
| US7098726B2 (en) | Method and apparatus for operating a voltage regulator based on operation of a timer | |
| CN113504826B (en) | Dynamic voltage frequency adjusting circuit and dynamic voltage frequency adjusting method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |