CN115765459A

CN115765459A - Control circuit and method for DC/DC converter, DC/DC converter circuit and electronic equipment

Info

Publication number: CN115765459A
Application number: CN202310011229.4A
Authority: CN
Inventors: 陈登政; 苏咨云
Original assignee: Agco Microelectronics Shenzhen Co ltd
Current assignee: Agco Microelectronics Shenzhen Co ltd
Priority date: 2023-01-05
Filing date: 2023-01-05
Publication date: 2023-03-07
Anticipated expiration: 2043-01-05
Also published as: CN115765459B

Abstract

The present disclosure provides a control circuit and a method for a DC/DC converter, a DC/DC conversion circuit and an electronic device, and relates to the field of electronic technology, wherein the control circuit comprises: a timer, comprising: a comparator configured to generate a pulse at a timing at which a voltage value of the ramp voltage signal changes to a voltage value of the reference voltage signal each time; a controller configured to control the first switch to switch from on to off in response to a pulse; controlling the second switch to be switched off during the on period of the first switch; the control circuit satisfies a first condition or a second condition, the first condition including that a change speed of a voltage value of the ramp voltage signal during a change according to a first trend changes between a first speed and a second speed; the second condition includes a voltage value of the reference voltage signal varying between a first value and a second value. The control circuit can allow the DC/DC converter to provide a fast transient response and reduce electromagnetic interference generated by switches in the DC/DC converter.

Description

Control circuit and method for DC/DC converter, DC/DC converter circuit and electronic equipment

Technical Field

The present disclosure relates to the field of electronic technologies, and in particular, to a control circuit and method for a DC/DC converter, a DC/DC converter circuit, and an electronic device.

Background

A DC/DC converter is a voltage converter that converts a DC input voltage into a DC output voltage. DC/DC converters are divided into three categories: a step-up DC/DC converter, a step-down DC/DC converter, and a step-up/step-down DC/DC converter.

The inventors are aware of a DC/DC converter comprising two switches connected in series between an input terminal and a ground terminal of the DC/DC converter. At times other than the dead time set to avoid simultaneous conduction of the two switches, the two switches are controlled to operate in opposition, i.e. when one switch is conducting, the other is off.

Disclosure of Invention

According to an aspect of the embodiments of the present disclosure, there is provided a control circuit of a DC/DC converter including a first switch and a second switch connected in series between an input terminal and a ground terminal, the first switch being connected between the input terminal and the second switch, the control circuit including: a timer, comprising: a comparator configured to generate a pulse at a first time when a voltage value of a ramp voltage signal changes to a voltage value of a reference voltage signal according to a first trend each time, wherein the voltage value of the ramp voltage signal changes according to a second trend from the first time, and the second trend is opposite to the first trend; and a controller configured to control the first switch to switch from on to off in response to each pulse; controlling the second switch to be turned off during the first switch is turned on; wherein the control circuit satisfies one of a first condition and a second condition, wherein: the first condition includes: the voltage value of the ramp voltage signal changes between a first speed and a second speed according to the change speed of the first change trend change period; the second condition includes: the voltage value of the reference voltage signal varies between a first value and a second value.

In some embodiments, the reference voltage signal in the second condition includes at least an interval in which a voltage value increases continuously and an interval in which a voltage value decreases continuously.

In some embodiments, the voltage value of the reference voltage signal in the second condition is unique at any time.

In some embodiments, the first condition further comprises: the voltage value of the reference voltage signal is constant; the second condition further comprises: the voltage value of the ramp voltage signal has the same change speed in any two change periods according to the first change trend.

In some embodiments, the timer further comprises: a first signal generation circuit configured to generate a first signal having an intensity value that varies between a third value and a fourth value; and a second signal generation circuit configured to generate the ramp voltage signal in the first condition based on the first signal.

In some embodiments, the first signal is a current signal, and a change speed of the voltage value of the ramp voltage signal in the first condition during each change according to the first change trend is positively correlated with a current value of the first signal during the change.

In some embodiments, the timer further comprises: a first signal generation circuit configured to generate a first signal having an intensity value that varies between a third value and a fourth value, wherein the first signal is the reference voltage signal in the second condition.

In some embodiments, the first signal comprises at least an interval of successively increasing intensity values and an interval of successively decreasing intensity values.

In some embodiments, the intensity value of the first signal is unique at any time.

In some embodiments, the intensity value of the first signal varies periodically between the third value and the fourth value.

In some embodiments, the first signal generating circuit comprises: a charge pump circuit configured to generate a second signal, the second signal being a voltage signal, a voltage value of the second signal periodically varying between a fifth value and a sixth value, according to a clock signal and a control signal, wherein the clock signal is used for controlling the second signal to periodically vary, and the control signal is used for controlling the voltage value of the second signal to vary between the fifth value and the sixth value; an edge limiter circuit configured to compare a voltage value of the second signal with the fifth value and the sixth value, respectively, to generate the control signal; and a signal processing circuit configured to process the second signal to output the first signal.

In some embodiments, the charge pump circuit comprises: a capacitor; a switch array connected to the capacitor, the switch array having a plurality of modes including a first mode and a second mode, a voltage value of the second signal increasing if the switch array is in the first mode and decreasing if the switch array is in the second mode; and a logic operation circuit configured to control the switch array to switch from a current mode to another mode at a time when the voltage value of the second signal changes to the fifth value or the sixth value according to the control signal.

In some embodiments, the plurality of modes further includes a third mode, and the voltage value of the second signal is constant if the switch array is in the third mode.

In some embodiments, the first mode comprises a plurality of first sub-modes, the second mode comprises a plurality of second sub-modes, the voltage value of the second signal has a different increasing speed if the switch array is in a different first sub-mode and a different decreasing speed if the switch array is in a different second sub-mode, wherein: the edge limiter circuit is further configured to compare a voltage value of the second signal with a seventh value between the fifth value and the sixth value to generate the control signal; the logic operation circuit is also configured to control the switch array to be switched from one first sub-mode to another first sub-mode at the current time according to the control signal; and controlling the switch array to be switched from the current second sub-mode to another second sub-mode at the second moment according to the control signal, wherein the second moment is the moment when the voltage value of the second signal changes to the seventh value.

In some embodiments, the first signal generating circuit comprises a state control circuit configured to be in a first state or a second state, the first signal generating circuit configured to generate the first signal if the state control circuit is in the first state and to generate a third signal if the state control circuit is in the second state, wherein an intensity value of the third signal is constant at an eighth value equal to one-half of a sum of the third value and the fourth value.

In some embodiments, the waveform of the first signal is triangular or trapezoidal in shape.

According to another aspect of the embodiments of the present disclosure, there is provided a DC/DC conversion circuit including: the control circuit of the DC/DC converter according to any of the above embodiments; and the DC/DC converter.

According to still another aspect of an embodiment of the present disclosure, there is provided an electronic device including: the DC/DC conversion circuit according to any of the above embodiments.

According to a further aspect of the embodiments of the present disclosure, there is provided a control method for a control circuit of a DC/DC converter according to any one of the embodiments, including: the comparator generates a pulse at the moment when the voltage value of the ramp voltage signal changes to the voltage value of the reference voltage signal according to the first change trend each time; the controller controls the second switch to be turned off during the first switch is turned on; and the controller controls the first switch to switch from on to off in response to each pulse.

In the control circuit of the DC/DC converter of the embodiment of the present disclosure, the comparator compares the ramp voltage signal and the reference voltage signal to generate one pulse at a first timing at which the voltage value of the ramp voltage signal changes to the voltage value of the reference voltage signal in accordance with a first trend of change each time, and the controller controls the first switch to be switched from on to off in response to each pulse. Further, the voltage value of the ramp voltage signal compared by the comparator changes between the first speed and the second speed at a change speed during the change according to the first change trend, or the voltage value of the reference voltage signal compared by the comparator changes between the first value and the second value. In this way, the control circuit can generate a broadband signal which enables the duration of each time the first switch is turned on to be changed between the first duration and the second duration under the condition that the load of the DC/DC converter is not changed. In this way, the control circuit can reduce electromagnetic interference generated by the alternating on and off of the switches in the DC/DC converter while allowing the DC/DC converter to provide a fast transient response.

The technical solution of the present disclosure is further described in detail by the accompanying drawings and examples.

Drawings

In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art without creative efforts. In the drawings:

fig. 1 is a schematic diagram of a control circuit of a DC/DC converter according to some embodiments of the present disclosure;

FIGS. 2A and 2B are schematic diagrams of control circuits of DC/DC converters according to further embodiments of the present disclosure;

FIGS. 3A and 3B are schematic diagrams of control circuits of DC/DC converters according to still further embodiments of the present disclosure;

FIG. 4 is a schematic diagram of a first signal generating circuit according to some embodiments of the present disclosure;

FIG. 5 is a schematic diagram of a first signal generating circuit according to further embodiments of the present disclosure;

FIGS. 6A and 6B are schematic diagrams of a first signal generating circuit according to further embodiments of the present disclosure;

figures 7A through 7D are waveform diagrams of signals according to some embodiments of the present disclosure; and

fig. 8 is a flow chart schematic of a control method of a control circuit of a DC/DC converter according to some embodiments of the present disclosure.

Detailed Description

The technical solutions in the embodiments of the present disclosure will be described clearly and completely with reference to the drawings in the embodiments of the present disclosure, and it is obvious that the embodiments described are only some embodiments of the present disclosure, rather than all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments disclosed herein without making any creative effort, shall fall within the protection scope of the present disclosure.

The relative arrangement of the components and steps, the numerical expressions, and numerical values set forth in these embodiments do not limit the scope of the present disclosure unless specifically stated otherwise.

In all examples shown and discussed herein, any particular value should be construed as merely illustrative, and not limiting. Thus, other examples of the exemplary embodiments may have different values.

The use of "first," "second," and similar words in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element preceding the word covers the element listed after the word, and does not exclude the possibility that other elements are also covered. "upper", "lower", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.

In the present disclosure, when a specific component is described as being positioned between a first component and a second component, there may or may not be an intervening component between the specific component and the first component or the second component. When it is described that a specific component is connected to other components, the specific component may be directly connected to the other components without having an intervening component, or may be directly connected to the other components without having an intervening component.

Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate.

One way of controlling a DC/DC converter known to the inventors is: the high-side switch of the two switches (i.e., the switch connected between the input and the other switch) is turned on for a constant duration (commonly referred to as constant on-time, COT) and turned off for a duration after the end of the turn-on, the duration of the turn-off being related to the real-time load of the DC/DC converter.

In the related art, this control manner may be implemented based on a feedback comparator and a timer (i.e., an on timer). In particular, the feedback comparator controls when the high-side switch starts to conduct according to a feedback signal reflecting the real-time load of the DC/DC converter. When the high-side switch starts to be conducted, the timer starts to time, and when the time length counted by the timer reaches a constant time length, the high-side switch is disconnected.

It can be seen that the DC/DC converter can provide fast transient response in this control mode, since it does not need to be implemented based on a compensation circuit such as an error amplifier.

However, since the on-duration of the high-side switch is constant and the off-duration is load-dependent, that is, the switching frequency of the DC/DC converter is not changed under the condition of a constant load, the control signal of the DC/DC converter is a periodic narrow-band signal. Such a narrow-band signal may cause the switches in the DC/DC converter to turn on and off alternately, which may cause serious Electromagnetic Interference (EMI), for example, electromagnetic Interference to electronic components disposed beside the DC/DC converter.

In order to solve the above problems, the present disclosure provides a control circuit of a DC/DC converter, which is capable of reducing electromagnetic interference generated by alternately turning on and off switches in the DC/DC converter by spreading a periodic narrow-band signal while allowing the DC/DC converter to provide a fast transient response.

Fig. 1 is a schematic diagram of a control circuit of a DC/DC converter according to some embodiments of the present disclosure. For ease of understanding, both the power output stage 200 of the DC/DC converter and the control circuit 100 of the DC/DC converter are shown in fig. 1.

Referring to fig. 1, the power output stage 200 includes a first switch 210 and a second switch 220 connected in series between an input terminal VIN and a ground terminal GND, and the first switch 210 is connected between the input terminal VIN and the second switch 220. That is, the first switch 210 is a high-side switch and the second switch 220 is a low-side switch. The first switch 210 and the second switch 220 may be, for example, metal-Oxide-Semiconductor Field-Effect transistors (MOSFETs).

The power output stage 200 also includes an output terminal VOUT. In some embodiments, the output terminal VOUT is configured to be connected to an inductor not shown in the DC/DC converter.

With continued reference to fig. 1, the control circuit 100 of the DC/DC converter includes a timer 110 and a controller 120. The timer 110 and the controller 120 are described separately below.

The timer 110 includes a comparator 1110. The comparator 1110 is configured to generate a pulse Sp at a first time when the voltage value of the ramp voltage signal Vramp changes to the voltage value of the reference voltage signal Vref according to a first trend of change.

Here, the voltage value of the ramp voltage signal Vramp changes in a second trend opposite to the first trend from the first time.

For example, the voltage value of the ramp voltage signal Vramp changes according to a first trend from the time when the first switch 210 starts to be turned on, and changes according to a second trend from the first time when the voltage value of the reference voltage signal Vref changes. The moment at which the first switch 210 starts to conduct may be controlled by the control circuit 100, e.g. by a feedback comparator not shown in the control circuit 100.

In some embodiments, the first trend of change is an upward trend, and the second trend of change is a downward trend. In this case, the voltage value of the reference voltage signal Vref remains substantially equal to or greater than the voltage value of the ramp voltage signal Vramp.

In other embodiments, the first trend is a downward trend and the second trend is a upward trend. In this case, the voltage value of the reference voltage signal Vref remains substantially smaller than or equal to the voltage value of the ramp voltage signal Vramp.

The controller 120 may be, for example, a Pulse Width Modulation (PWM) controller.

The controller 120 is configured to control the first switch 210 to switch from on to off in response to each pulse Sp generated by the comparator 1110. That is, the controller 120 is configured to control the first switch 210 to switch from on to off at each first time, so that the time length of each time the first switch 210 is turned on is equal to the time length of the voltage value of the ramp voltage signal Vramp that changes according to the first trend of change at a certain time.

Further, the controller 120 is also configured to control the second switch 220 to be turned off during the time when the first switch 210 is turned on.

In some embodiments, the controller 120 may be further configured to control both the first switch 210 and the second switch 220 to be turned off at a dead time set to avoid simultaneous conduction of the first switch 210 and the second switch 220. The controller 120 is further configured to control the first switch 210 and the second switch 220 to be in opposite operating states, i.e., one is on and the other is off, at times other than the dead time.

In summary, the controller 120 is configured to generate a control signal for controlling the power output stage 200 in accordance with each pulse Sp generated by the timer 110, such that the first switch 210 and the second switch 220 operate in the manner described above.

The control circuit 100 of the DC/DC converter of the embodiments of the present disclosure satisfies one of the first condition and the second condition.

The first condition includes that the change speed of the voltage value of the ramp voltage signal Vramp during the change according to the first change trend changes between the first speed and the second speed. That is, the voltage value of the ramp voltage signal Vramp differs in the change speed during at least two changes in the first trend, and the change speed during each change in the first trend is between the first speed and the second speed.

It can be understood that the change speed of the voltage value of the ramp voltage signal Vramp during the change according to the first change trend is the slope of the ramp voltage signal Vramp during the change of the voltage value according to the first change trend.

In the case where the control circuit 100 satisfies the first condition, even though the load of the DC/DC converter is not changed, the time period during which the voltage value of the ramp voltage signal Vramp changes according to the first trend of change each time changes between the first time period and the second time period due to the change in the slope of the ramp voltage signal Vramp, so that the time period during which the first switch 210 is turned on each time also changes between the first time period and the second time period.

The second condition includes a voltage value of the reference voltage signal Vref varying between a first value and a second value. That is, the voltage value of the reference voltage signal Vref varies rather than being constant.

In the case where the control circuit 100 satisfies the second condition, even though the load of the DC/DC converter is not changed, the time period during which the voltage value of the ramp voltage signal Vramp changes according to the first change trend each time changes between the first time period and the second time period due to the voltage value change of the reference voltage signal Vref, so that the time period during which the first switch 210 is turned on each time also changes between the first time period and the second time period.

It can be seen that, in the case where the first condition or the second condition is satisfied, the time period of each turn-on of the first switch 210 is not constant but varies between the first time period and the second time period even though the load of the DC/DC converter is constant. That is, the control signal of the power output stage 200 generated by the controller 120 is not a periodic narrow-band signal that makes the duration of each turn-on of the first switch 210 constant, but a wide-band signal obtained by spreading, so that the electromagnetic interference generated by the alternate turn-on and turn-off of the switches in the power output stage 200 can be reduced.

In the control circuit 100 of the DC/DC converter of the embodiment of the present disclosure, the comparator 1110 compares the ramp voltage signal Vramp with the reference voltage signal Vref to generate one pulse Sp at a first time when the voltage value of the ramp voltage signal Vramp changes to the voltage value of the reference voltage signal Vref according to a first trend of change each time, and the controller 120 controls the first switch 210 to switch from on to off in response to each pulse Sp. Further, the voltage value of the ramp voltage signal Vramp compared by the comparator 1110 changes between the first speed and the second speed at a change speed during the change according to the first change trend, or the voltage value of the reference voltage signal Vref compared by the comparator 1110 changes between the first value and the second value. In this way, the control circuit 100 can generate a broadband signal that changes the time duration of each turn-on of the first switch 210 between the first time duration and the second time duration under the condition that the load of the DC/DC converter is not changed. In this manner, the control circuit 100 can reduce electromagnetic interference generated by the alternate on and off of the switches in the power output stage 200 while allowing the DC/DC converter to provide a fast transient response.

In addition, it should be understood that, due to the generation of the broadband signal, the electromagnetic interference generated by the control circuit 100 itself to the outside is also reduced.

Next, the timer 110 in the control circuit 100 will be described with reference to various embodiments.

First, the timer 110 in the control circuit 100 satisfying the first condition will be described with reference to fig. 2A. Fig. 2A is a schematic diagram of a control circuit of a DC/DC converter according to other embodiments of the present disclosure.

As shown in fig. 2A, the timer 110 includes a first signal generating circuit 1120 and a second signal generating circuit 1130 in addition to the comparator 1110.

The first signal generation circuit 1120 is configured to generate a first signal S1, the intensity value of the first signal S1 varying between a third value and a fourth value. The second signal generation circuit 1130 is configured to generate the ramp voltage signal Vramp in the first condition based on the first signal S1.

In some embodiments, the first signal S1 is a current signal, and the speed of change of the voltage value of the ramp voltage signal Vramp during each change according to the first change trend in the first condition is positively correlated with the current value of the first signal S1 during the change.

For example, the first speed at which the voltage value of the ramp voltage signal Vramp changes is greater than the second speed, and the third value of the first signal S1 is greater than the fourth value. In this case, when the current value of the first signal S1 is the third value, the speed at which the voltage value of the ramp voltage signal Vramp changes in the first trend is the first speed; when the current value of the first signal S1 is the fourth value, the speed at which the voltage value of the ramp voltage signal Vramp changes in the first trend is the second speed.

In the above embodiment, the first signal generating circuit 1120 in the timer 110 generates the first signal S1 whose intensity value is changed between the third value and the fourth value, so that the second signal generating circuit 1130 generates the ramp voltage signal Vramp according to the first signal S1, and the voltage value of the ramp voltage signal Vramp is changed between the first speed and the second speed at the changing speed during the change according to the first changing tendency. In this manner, the comparator 1110 generates the pulse Sp based on the ramp voltage signal Vramp in the first condition, and the control circuit 100 satisfies the first condition.

In some embodiments, in the first condition, the voltage value of the reference voltage signal Vref is constant. That is, the first condition includes, in addition to the change speed of the voltage value of the ramp voltage signal Vramp during the change according to the first change trend changing between the first speed and the second speed: the voltage value of the reference voltage signal Vref is constant.

In some embodiments, the control circuit 100 may further include a reference signal generator, not shown, configured to generate a reference voltage signal Vref having a constant voltage value.

Some implementations of the second signal generating circuit 1130 are described below in conjunction with FIG. 2B.

As shown in fig. 2B, the second signal generation circuit 1130 includes a subcircuit 1131 and a capacitor C1, as some implementations. The sub-circuit 1131 is configured to generate a constant current I for charging the capacitor C1.

For example, referring to fig. 2B, the sub-circuit 1131 includes a voltage dividing circuit 11311, a current source circuit 11312, and a current mirror circuit 11313.

The voltage divider circuit 11311 includes a resistor R1 and a resistor R2 connected in series between the input terminal VIN and the ground terminal.

The current source circuit 11312 includes a differential amplifier D, a transistor Q1, and a resistor R3. One input terminal of the differential amplifier D is connected to the intermediate node between the resistors R1 and R2. The output terminal of the differential amplifier D1 is connected to the gate of the transistor Q1. The transistor Q1 further includes a first electrode and a second electrode outside the gate. For example, the first electrode is a source and the second electrode is a drain. For another example, the first electrode is a drain and the second electrode is a source. The electrodes of other transistors may be similar hereafter. A first electrode of the transistor Q1 is connected to the resistor R3, and an intermediate node between the resistor R3 and the first electrode of the transistor Q1 is connected to the other input terminal of the differential amplifier D.

The current mirror circuit 11313 includes a transistor Q2 and a transistor Q3. Transistors Q2 and Q3 each include a first electrode, a second electrode, and a gate. Specifically, the gates of transistors Q2 and Q3, and the first electrode of transistor Q2 are connected to the second electrode of transistor Q1 in current source circuit 11312. Second electrodes of the transistors Q2 and Q3 are both connected to the power supply terminal VDD of the current mirror circuit 11313. A constant current I flows from the first electrode of the transistor Q3.

If only a constant current I is charged into the capacitor C1, the voltage value of the ramp voltage signal Vramp generated by the second signal generating circuit 1130 may be constant at a varying speed during the variation according to the first variation trend.

In fig. 2B, the second signal generating circuit 1130 receives the first signal S1 (i.e., the current signal) from the first signal generating circuit 1120 and generates the ramp voltage signal Vramp according to the first signal S1. In this case, the constant current I and the first signal S1 charge the capacitor C1 in common.

Since the current value of the first signal S1 generated by the first signal generating circuit 1120 varies between the third value and the fourth value, the speed at which the capacitor C1 is charged varies with the variation of the current value of the first signal S1. In this case, the second signal generation circuit 1130 generates the ramp voltage signal Vramp in the first condition.

The control circuit 100 satisfying the first condition has been explained so far.

Next, the timer 110 in the control circuit 100 satisfying the second condition will be described with reference to fig. 3A. Fig. 3A is a schematic diagram of a control circuit of a DC/DC converter according to still further embodiments of the present disclosure.

As shown in fig. 3A, the timer 110 includes a first signal generating circuit 1120 in addition to the comparator 1110.

The first signal generation circuit 1120 is configured to generate a first signal S1, the intensity value of the first signal S1 varying between a third value and a fourth value.

Specifically, the first signal S1 generated by the first signal generation circuit 1120 is the reference voltage signal Vref in the second condition compared by the comparator 1110. In other words, in these embodiments, the third value is equal to the first value, and the fourth value is equal to the second value.

In the above embodiment, the first signal generating circuit 1120 in the timer 110 generates the first signal S1 having the intensity value varying between the third value and the fourth value, and the first signal S1 is the reference voltage signal Vref having the voltage value varying between the first value and the second value. In this manner, the comparator 1110 generates the pulse Sp based on the reference voltage signal Vref in the second condition, and the control circuit 100 satisfies the second condition.

In some embodiments, in the second condition, the change speed of the voltage value of the ramp voltage signal Vramp is the same during any two changes according to the first change trend. In other words, the change speed of the voltage value of the ramp voltage signal Vramp during the change according to the first trend of change is constant.

In this case, the second condition includes, in addition to the voltage value of the reference voltage signal Vref varying between the first value and the second value: the voltage value of the ramp voltage signal Vramp changes at the same speed during any two changes according to the first change trend.

In these embodiments, as shown in fig. 3A, the control circuit 100 may further include a third signal generation circuit 1140. The third signal generation circuit 1140 is configured to generate a ramp voltage signal Vramp whose voltage value changes at a constant rate during a period in which the voltage value changes according to the first trend of change.

Fig. 3B illustrates some implementations of the third signal generating circuit 1140. As shown in fig. 3B, the third signal generating circuit 1140 includes a sub-circuit 1141 and a capacitor C2. The sub-circuit 1141 is configured to generate a constant current I for charging the capacitor C2.

For example, similar to the sub-circuit 1131, the sub-circuit 1141 includes a voltage dividing circuit 11411, a current source circuit 11412, and a current mirror circuit 11413. For the related description of the voltage divider circuit 11411, the current source circuit 11412, and the current mirror circuit 11413, reference is made to the above description of the voltage divider circuit 11311, the current source circuit 11312, and the current mirror circuit 11313, and no further description is given here.

Since only the constant current I charges the capacitor C2, the voltage value of the ramp voltage signal Vramp generated by the third signal generating circuit 1140 is constant at a varying speed during the variation according to the first variation trend.

The control circuit 100 satisfying the second condition has been explained so far.

As can be seen from the above-mentioned some implementations of the control circuit 100 satisfying the first condition and some implementations of the control circuit 100 satisfying the second condition, in both conditions, the timer 110 includes the first signal generating circuit 1120 configured to generate the first signal S1. The first signal generating circuit 1120 will be described in connection with some embodiments.

In some embodiments, the first signal S1 includes at least an interval in which the intensity value continuously increases and an interval in which the intensity value continuously decreases.

Taking the first signal S1 as an example of the reference voltage signal Vref in the second condition, in some embodiments, the reference voltage signal Vref at least includes a section in which the voltage value increases continuously and a section in which the voltage value decreases continuously.

The voltage value of the reference voltage signal Vref continuously increases in an interval, which indicates that the slope of the reference voltage signal Vref at any point in the interval is positive. The voltage value of the reference voltage signal Vref decreases continuously in an interval, which indicates that the slope of the reference voltage signal Vref at any point in the interval is negative.

Assume that a time period during which the voltage value of the ramp voltage signal Vramp changes to the voltage value of the reference voltage signal Vref in the first trend of change is a when the voltage value of the reference voltage signal Vref is a, and a time period during which the voltage value of the ramp voltage signal Vramp changes to the voltage value of the reference voltage signal Vref in the first trend of change is 2A when the voltage value of the reference voltage signal Vref is 2A.

In this case, if the voltage value of the reference voltage signal Vref is continuously increased from a to 2A in a certain interval, the period in which the voltage value of the ramp voltage signal Vramp changes to the voltage value of the reference voltage signal Vref in the first trend of change may be any one period from a to 2A, for example, 1.3A, 1.4A, 1.9A, and the like.

Accordingly, the switching frequency of the power output stage 200 may be any one of a to 2A. In other words, in this manner, the switching frequency of the power output stage 200 can be smoothly changed at least in an interval in which the voltage value of the reference voltage signal Vref continuously increases and an interval in which the voltage value continuously decreases.

Similarly, in the case where the first signal S1 is a current signal on which the ramp voltage signal Vramp in the first condition is generated, the first signal S1 includes at least an interval in which the current value increases continuously and an interval in which the current value decreases continuously. In this manner, the switching frequency of the power output stage 200 can be smoothly changed at least in an interval in which the current value of the first signal S1 continuously increases and an interval in which the current value continuously decreases.

In the above embodiment, the first signal S1 at least includes an interval in which the intensity value continuously increases and an interval in which the intensity value continuously decreases. In this way, the control circuit 100 can control the switching frequency of the power output stage 200 to smoothly vary at least in an interval in which the intensity value of the first signal S1 continuously increases and an interval in which the intensity value continuously decreases. That is, at least in these intervals, the switching frequency of the power output stage 200 may be controlled to a certain frequency within a continuous frequency range, rather than to a certain frequency among several frequencies at intervals. For example, the original switching frequency of the on/off of the switch in the power output stage 200 before spreading is 2GHz, and the switching frequency of the on/off of the switch after spreading can be controlled and modulated to a certain frequency within a continuous frequency range of 1.9GHz to 2.1ghz. In this way, the electromagnetic interference generated by the alternate on and off of the switches in the power output stage 200 can be further reduced.

Further, in some embodiments, the intensity value of the first signal S1 is unique at any time. In this case, the intensity value of the first signal S1 changes in a continuously increasing or continuously decreasing manner during the change period without a sudden change. That is, any point on the first signal S1 has a slope.

For example, the first signal S1 includes only an interval in which the intensity value continuously increases and an interval in which the intensity value continuously decreases. For another example, the first signal S1 includes only an interval in which the intensity value continuously increases, an interval in which the intensity value continuously decreases, and an interval in which the intensity value is constant.

Taking the example that the first signal S1 is the reference voltage signal Vref in the second condition as an example, in some embodiments, the voltage value of the reference voltage signal Vref is unique at any time.

In the above embodiment, the intensity value of the first signal S1 is unique at any time. In this way, the control circuit 100 can control the switching frequency of the power output stage 200 to smoothly vary in any interval of the variation of the intensity value of the first signal S1. That is, in any interval in which the intensity value of the first signal S1 varies, the switching frequency of the power output stage 200 may be controlled to a certain frequency in a continuous frequency range, rather than to a certain frequency among several frequencies at intervals. Thus, the electromagnetic interference generated by the alternate on/off of the switches in the power output stage 200 can be further reduced.

In some embodiments, the intensity value of the first signal S1 varies periodically between the third value and the fourth value. Some implementations of the first signal generating circuit 1120 for generating such a first signal S1 are described below with reference to fig. 4.

Fig. 4 is a schematic diagram of a first signal generating circuit, according to some embodiments of the present disclosure.

As shown in fig. 4, the first signal generation circuit 1120 includes a charge pump circuit 1121, an edge limiter circuit 1122, and a signal processing circuit 1123.

The charge pump circuit 1121 is configured to generate the second signal S2 according to the clock signal CLK and the control signal SC.

Here, the clock signal CLK is used to control the second signal S2 to vary periodically, and the control signal SC is used to control the voltage value of the second signal S2 to vary between a fifth value and a sixth value. That is, the second signal S2 is a voltage signal whose voltage value periodically changes between the fifth value and the sixth value.

The edge limiter circuit 1122 is configured to compare the voltage value of the second signal S2 with a fifth value and a sixth value, respectively, to generate the control signal SC.

The signal processing circuit 1123 is configured to process the second signal S2 to output the first signal S1.

As some implementations, the signal processing circuit 1123 performs a voltage-to-current conversion process on the second signal S2 to output the first signal S1 as a current signal. In this case, for example, the frequency of the first signal S1 is the same as the frequency of the second signal S2, and the shape of the waveform of the first signal S1 is also the same as the shape of the waveform of the second signal S2.

As other implementations, the signal processing circuit 1123 performs voltage isolation processing on the second signal S2 to output the first signal S1 as the reference voltage signal Vref. In this case, for example, the frequency of the first signal S1 is the same as the frequency of the second signal S2, and the shape of the waveform of the first signal S1 is also the same as the shape of the waveform of the second signal S2. In some examples, the first signal S1 is identical to the second signal S2, in which case the fifth value is equal to the third value and the sixth value is equal to the fourth value. In other examples, the first signal S1 is different in amplitude from the second signal S2.

In the above embodiment, the edge limiter circuit 1122 compares the voltage value of the second signal S2 generated by the charge pump circuit 1121 with the fifth value and the sixth value, respectively, to generate the control signal SC for controlling the voltage value of the second signal S2 to vary between the fifth value and the sixth value. The charge pump circuit 1121 may generate the second signal S2 having a voltage value periodically changing between a fifth value and a sixth value according to the clock signal CLK and the control signal SC generated by the edge limiter circuit 1122. Then, the signal processing circuit 1123 processes the second signal S2, so that the first signal S1 whose intensity value periodically changes between the third value and the fourth value can be generated. In this manner, the first signal generation circuit 1120 can generate the first signal S1 whose intensity value periodically changes between the third value and the fourth value.

Some implementations of the charge pump circuit 1121 are further described below in conjunction with fig. 5. FIG. 5 is a schematic diagram of a first signal generating circuit according to other embodiments of the present disclosure.

As shown in fig. 5, the charge pump circuit 1121 includes a capacitor 1121a, a switch array 1121b, and a logic operation circuit 1121c.

The switch array 1121b is connected to the capacitor 1121 a. The switch array 1121b has a plurality of modes. For example, the switch array 1121b includes a plurality of switches, wherein at least one of the switches is in opposite operating states in different ones of a plurality of modes.

The plurality of modes includes a first mode and a second mode. In the case where the switch array 1121b is in the first mode, the voltage value of the second signal S2 increases, that is, the intensity value of the first signal S1 increases. In the case where the switch array 1121b is in the second mode, the voltage value of the second signal S2 decreases, that is, the intensity value of the first signal S1 decreases.

The logic operation circuit 1121c is configured to control the switch array 1121b to switch from the currently-located mode to another mode at a time point when the voltage value of the second signal S2 changes to a fifth value or a sixth value according to the control signal SC.

It should be understood that the logic operation circuit 1121c may be configured to control the switch array 1121b to perform periodic mode switching according to the control signal SC and the clock signal CLK. For example, the switch array 1121b may be controlled to be in the first mode and then in the second mode in one control period.

In the above-described embodiment, the voltage value of the second signal S2 is increased when the switch array 1121b is in the first mode, and the voltage value of the second signal S2 is decreased when the switch array 1121b is in the second mode. In this way, by controlling the switch array 1121b to be in the first mode for a period of time and to be in the second mode for another period of time, the second signal S2 can at least include a section in which the voltage value continuously increases and a section in which the voltage value continuously decreases. In this manner, the signal processing circuit 1123 can output the first signal S1 including at least a section in which the intensity value continuously increases and a section in which the intensity value continuously decreases from the second signal S2.

In some embodiments, the plurality of modes of the switch array 1121b also includes a third mode. In the case where the switch array 1121b is in the third mode, the voltage value of the second signal S2 is constant, that is, the intensity value of the first signal S1 is constant.

In this case, for example, the switch array 1121b may be controlled to be in the first mode, the third mode, the second mode, and the third mode in sequence in one control cycle. In practice, various other examples are possible and will not be described here.

By adjusting the order and the number of times the switch array 1121b is in a mode within one control period, the shape of the waveform of the second signal S2 generated by the charge pump circuit 1121, and thus the shape of the waveform of the first signal S1, can be changed.

In the above embodiment, the switch array 1121b further includes a third mode, and the switch array 1121b is controlled to be in the third mode within a period of time, so that the second signal S2 further includes an interval with a constant voltage value, and further the first signal S1 further includes an interval with a constant intensity value. As such, the first signal generation circuit 1120 may generate the first signal S1 of a waveform of more various shapes.

As some implementations, the plurality of modes of the switch array 1121b include only a first mode, a second mode, and a third mode.

In this manner, the second signal S2 includes only an interval in which the voltage value increases continuously, an interval in which the voltage value decreases continuously, and an interval in which the voltage value is constant. That is, the voltage value of the second signal S2 at any time is unique. In this way, the signal processing circuit 1123 can output the first signal S1 having a unique intensity value at any time, based on the second signal S2.

In some embodiments, the first mode includes a plurality of first sub-modes and the second mode includes a plurality of second sub-modes. For example, the plurality of first sub-patterns correspond to the plurality of second sub-patterns one to one.

In some embodiments, the voltage value of the second signal S2 has different increasing speeds with the switch array 1121b in different first sub-modes. Similarly, in some embodiments, the voltage value of the second signal S2 has a different reduction speed with the switch array 1121b in a different second sub-mode.

In other words, the slope of the second signal S2 is different when the switch array 1121b is in a different first sub-mode, and the slope of the second signal S2 is also different when the switch array 1121b is in a different second sub-mode.

As some implementations, the speed at which the voltage value of the second signal S2 increases during the switch array 1121b being in the first sub-mode is equal to the speed at which the voltage value of the second signal S2 decreases during the switch array 1121b being in the second sub-mode corresponding to the first sub-mode. That is, the slope of the second signal S2 during the switch array 1121b being in the first sub-mode is equal to the absolute value of the slope of the second signal S2 during the switch array 1121b being in the second sub-mode corresponding to the first sub-mode. For example, when the switch array 1121b is in the first sub-mode, the voltage value of the second signal S2 increases at a rate of 0.5 (V/μ S), and when the switch array 1121b is in the second sub-mode corresponding to the first sub-mode, the voltage value of the second signal S2 decreases at a rate of 0.5 (V/μ S).

In these embodiments, the edge limiter circuit 1122 is further configured to compare the voltage value of the second signal S2 with a seventh value between the fifth value and the sixth value to generate the control signal SC. It should be understood that the seventh value is neither equal to the fifth value nor equal to the sixth value. That is, the edge limiter circuit 1122 is configured to compare the voltage value of the second signal S2 with the fifth value, the sixth value, and the seventh value to generate the control signal SC.

It is to be appreciated that the edge limiter circuit 1122 may be configured to compare the voltage value of the second signal S2 with one or more seventh values.

Further, the logic operation circuit 1121c is further configured to control the switch array 1121b to switch from the currently located one first sub-mode to another first sub-mode at a second time according to the control signal SC. Similarly, the logic operation circuit 1121c is further configured to control the switch array 1121b to switch from one second sub-mode to another second sub-mode at the present time according to the control signal SC.

Here, the second timing is a timing at which the voltage value of the second signal S2 changes to the seventh value. For example, when the edge limiter circuit 1122 compares the voltage value of the second signal S2 with a plurality of seventh values, the logic operation circuit 1121c controls the switch array 1121b to switch from the currently located first (second) sub-mode to another first (second) sub-mode when the voltage value of the second signal S2 changes to any one of the seventh values.

In the above embodiment, the edge limiter circuit 1122 compares the voltage value of the second signal S2 with the fifth value, the sixth value and the seventh value between the fifth value and the sixth value to generate the control signal SC. In this way, the logic operation circuit 1121c may further control the switch array 1121b to switch from the currently located first (second) sub-mode to another first (second) sub-mode at the second time according to the control signal SC. As such, the first signal generation circuit 1120 may generate the first signal S1 of a waveform of more various shapes.

Some specific implementations of the first signal generating circuit 1120 are described below in conjunction with fig. 6A and 6B. In fig. 6A and 6B, the inverted signal of the signal is represented by adding a letter B to the character representing the signal. For example, the clock signal CLKb represents an inverted signal of the clock signal CLK.

As shown in fig. 6A and 6B, the edge limiting circuit 1122 includes

comparators

11221 and 11222.

The comparator 11221 is configured to compare the second signal S2 with the voltage signal VtoneH to output a control sub-signal SC1. The voltage value of VtoneH is a fifth value, i.e., the comparator 11221 is configured to compare the voltage value of the second signal S2 with the fifth value.

The comparator 11222 is configured to compare the second signal S2 with the voltage signal VtoneL to output a control sub-signal SC2. The voltage value of VtoneL is a sixth value, that is, the comparator 11221 is configured to compare the voltage value of the second signal S2 with the sixth value.

The voltage signals VtoneH and VtoneL may be generated by the voltage regulating circuit 11223. The voltage regulation circuit 11223 may be configured to generate voltage signals VtoneH and VtoneL according to the initial reference voltage signal Vref'. The voltage value of the initial reference voltage signal Vref' may be equal to one-half of the sum of the voltage values of the voltage signals VtoneH and VtoneL.

As some implementations, the voltage value of the voltage signal VtoneH is greater than the voltage value of the initial reference voltage signal Vref 'and less than or equal to 1.1 times the voltage value of the initial reference voltage signal Vref'. Accordingly, the voltage value of the voltage signal VtoneL is less than the voltage value of the initial reference voltage signal Vref 'and greater than or equal to 0.9 times the voltage value of the initial reference voltage signal Vref'.

With continued reference to fig. 6A and 6B, switch array 1121B includes switch 11211 and switch 11212 connected in series. An intermediate node of the switch 11211 and the switch 11212 is connected to one end of the capacitor 1121 a.

In some embodiments, referring to fig. 6A and 6B, the other end of the capacitor 1121a is connected to one end of the capacitor C4, and the other end of the capacitor C4 is grounded. In this case, the charge pump circuit 1121 may further include a differential amplifier 1121d, and an output terminal and an input terminal of the differential amplifier 1121d are connected to intermediate nodes of the capacitor 1121a and the capacitor C4, respectively. The other input terminal of the differential amplifier 1121d receives an initial reference voltage signal Vref'.

With continued reference to fig. 6A and 6B, the logic operation circuit 1121c includes a latch 11213 and a latch 11214. The latch 11213 is configured to control an operation state of the switch 11211, for example, on or off, according to the clock signal CLK and the control sub-signal SC1. The latch 11214 is configured to control an operation state of the switch 11212, for example, on or off, according to the clock signal CLKb and the control sub-signal SC2b.

For example, referring to fig. 6A and 6B, latches 11213 and 11214 are both SR latches.

In this case, the set (S) terminal of the latch 11213 is connected to the output terminal of the and circuit A1, and the reset (R) terminal is connected to the output terminal of the nand circuit AN 1. The and circuit A1 and the nand circuit AN1 each receive the clock signal CLK and the control sub-signal SC1. The latch 11213 outputs a signal SW1 for controlling the operating state of the switch 11211 via the Q terminal, based on the S terminal signal generated by the and circuit A1 and the R terminal signal generated by the not circuit AN 1.

Similarly, the S terminal of the latch 11214 is connected to the output terminal of the and gate circuit A2, and the R terminal is connected to the output terminal of the nand gate circuit AN 2. The and gate circuit A2 and the nand gate circuit AN2 each receive the clock signal CLKb and the control sub-signal SC2b. The latch 11214 outputs a signal SW2 for controlling the operating state of the switch 11212 via the Q terminal, based on the S terminal signal generated by the and circuit A2 and the R terminal signal generated by the nand circuit AN 2.

In the case where the switch 11211 is turned on and the switch 11212 is turned off, the switch array 1121b is in the first mode, and the voltage value of the second signal S2 is increased. In the case where the switch 11211 is turned off and the switch 11212 is turned on, the switch array 1121b is in the second mode, and the voltage value of the second signal S2 decreases. In the case where both the switches 11211 and 11212 are turned off, the switch array 1121b is in the third mode, and the voltage value of the second signal S2 is constant.

If the time when the voltage value of the second signal S2 changes to the fifth value and the sixth value each time coincides with the time when the level of the clock signal CLK changes each time, the logic operation circuit 1121c controls the switch array 1121b to switch between the first mode and the second mode. In this case, the first signal S1 generated by the first signal generating circuit 1120 includes an interval in which the intensity value continuously increases and an interval in which the intensity value continuously decreases.

In contrast, if there is a case where the time at which the voltage value of the second signal S2 changes to the fifth value and the sixth value does not overlap the time at which the level of the clock signal CLK changes, the logic operation circuit 1121c controls the switch array 1121b to switch from three modes, i.e., the first mode, the second mode, and the third mode. In this case, the first signal S1 generated by the first signal generation circuit 1120 includes an interval in which the intensity value is constant, in addition to an interval in which the intensity value continuously increases and an interval in which the intensity value continuously decreases.

As some implementations, the signal processing circuit 1123 is a voltage-to-current conversion circuit configured to perform a voltage-to-current conversion process on the second signal S2. In this case, the first signal S1 is a current signal. The second signal generation circuit 1130 generates the ramp voltage signal Vramp in the first condition based on the first signal S1.

For example, referring to fig. 6A, the voltage-current conversion circuit includes a current source circuit 11231 and a current mirror circuit 11232. For the description of the current source circuit 11231 and the current mirror circuit 11232, reference may be made to the description of the current source circuit 11312 and the current mirror circuit 11313, which are not described herein again.

As other implementations, the signal processing circuit 1123 is a voltage isolation circuit configured to voltage isolate the second signal S2. In this case, the first signal S1 is a voltage signal. That is, the first signal S1 is the reference voltage signal Vref in the second condition.

For example, referring to fig. 6B, the voltage isolation circuit includes a differential amplifier D' and a capacitor C3. One input terminal of the differential amplifier D' is connected to the output terminal of the charge pump circuit 1121. One end of the capacitor C3 is connected to the output end of the differential amplifier D', and the other end is grounded. An intermediate node between the capacitor C3 and the output terminal of the differential amplifier D 'is connected to the other input terminal of the differential amplifier D'.

In connection with the example shown in fig. 6A and 6B, how the logic operation circuit 1121c controls the switch array 1121B to be in the first mode, the second mode or the third mode according to the clock signal CLK and the control signal SC (i.e., the control sub-signals SC1 and SC 2), so as to enable the first signal generation circuit 1120 to generate the first signal S1 has been described.

It should be understood that fig. 6A and 6B are just some implementations of the first signal generating circuit 1120. In practice, the first signal generating circuit 1120 may have various modifications.

For example, in order for the first mode and the second mode of the switch array 1121b to include a plurality of first sub-modes and a plurality of second sub-modes, respectively, the switch array 1121b may include not only two switches 11211 and 11212 but more switches so that the capacitor 1121a has different charging speeds in different first sub-modes and different discharging speeds in different second sub-modes. Accordingly, the logical operation circuit 1121c may include not only two

latches

11213 and 11214 but also more latches in order to control the operation states of the respective switches among more switches. Similarly, the edge limiting circuit 1122 may include not only two

comparators

11221 and 11222, but also more comparators to further compare the voltage value of the second signal S2 with one or more seventh values to generate the control signal SC.

In some embodiments, the first signal generation circuit 1120 includes a state control circuit. The state control circuit is configured to be in a first state or a second state.

The first signal generation circuit 1120 is configured to generate the first signal S1 if the state control circuit is in the first state, and to generate the third signal if the state control circuit is in the second state. Here, the intensity value of the third signal is constant at an eighth value, and the eighth value is equal to one-half of the sum of the third value and the fourth value.

In other words, when the state control circuit is in the first state, the first signal generation circuit 1120 generates the first signal S1 whose intensity value changes, and when the state control circuit is in the second state, the first signal generation circuit 1120 generates the third signal whose intensity value is always constant. It is understood that the third signal may be a current signal or a voltage signal.

In the case where the first signal generating circuit 1120 generates the third signal, the control circuit 100 no longer satisfies the first condition and the second condition. In other words, in this case, if the load of the DC/DC converter is not changed, the duration of each change of the ramp voltage signal Vramp according to the first trend of change is also not changed.

That is, in the case where the first signal generating circuit 1120 generates the third signal, the control circuit 100 generates a periodic narrow-band signal for controlling the power output stage 200.

For example, in the case that the first signal generating circuit 1120 generates the first signal S1, the control signal generated by the control circuit 100 can control the duration of each turn-on of the first switch to be [ T ] ₁ ，T ₂ ]To change between. In the case that the first signal generating circuit 1120 generates the third signal, the control signal generated by the control circuit 100 controls the first switch to be turned on each time for a period of time constant at T ₃ . In this case, T ₁ 、T ₂ And T ₃ The following relationship can be satisfied: t is ₁ +T ₂ =2T ₃ . In some examples, T ₁ 、T ₂ And T ₃ The following relationship may also be satisfied: 0.9T ₃ ≤T ₁ ＜T ₃ And, T ₃ ＜T ₂ ≤1.1T ₃ 。

In the above embodiment, by adjusting the state control circuit 1124 to be in the first state or the second state, the control circuit 100 can generate a wideband signal or a periodic narrowband signal for controlling the power output stage 200. Thus, the control mode of the power output stage 200 can be flexibly adjusted according to actual requirements.

In addition, since the eighth value of the third signal generated by the first signal generating circuit 1120 is equal to one-half of the sum of the third value and the fourth value of the first signal S1 it generates. In this way, it is ensured that the center frequencies of the broadband signal and the narrowband signal generated by the control circuit 100 for controlling the power output stage 200 coincide.

As some implementations, referring to fig. 6A and 6B, the state control circuit includes a switch 1124 connected to a charge pump circuit 1121.

With the switch 1124 open, the state control circuit is in the first state, and the charge pump circuit 1121 normally generates the second signal S2. Thus, the first signal generating circuit 1120 generates the first signal S1.

Conversely, with switch 1124 conductive, the state control circuit is in the second state. In this case, the charge pump circuit 1121 is shorted by a line formed by the conduction of the switch 1124, thereby generating the initial reference voltage signal Vref' having a voltage value constant at the eighth value instead of the second signal S2. Thus, the first signal generating circuit 1120 generates the third signal.

In some embodiments, referring to fig. 6A and 6B, the operating state of switch 1124 is controlled by signal sENb. For example, in the case where the signal sENb has a first level, the switch 1124 is turned on; and in the case where the signal sENb has the second level, the switch 1124 is turned off.

In this case, the logic operation circuit 1121c is further configured to control each of the switches (e.g., the switches 11211 and 11212) in the switch array 1121b to be turned off according to an inverted signal sEN of the signal sENb.

For example, referring to fig. 6A and 6B, the logic operation circuit 1121c further includes an and gate circuit A3 and an and gate circuit A4. The and circuit A3 is configured to output a control signal of the switch 11211 according to the signal SW1 and the signal sEN. The and circuit A4 is configured to output a control signal of the switch 11212 according to the signal SW2 and the signal sEN.

The first signal generating circuit 1120 of the embodiment of the present disclosure has been explained so far. To facilitate understanding, examples of some of the main signals of the embodiments of the present disclosure are given below.

Fig. 7A-7D are waveform diagrams of signals according to some embodiments of the present disclosure. Specifically, fig. 7A to 7C show some signals in the case where the control circuit 100 satisfies the second condition, and fig. 7D shows some signals in the case where the control circuit 100 satisfies the first condition.

As shown in fig. 7A, the reference voltage signal Vref (e.g., the first signal S1) periodically varies between a first value (third value) and a second value (fourth value), and the shape of the waveform of the reference voltage signal Vref is a triangle. In other words, the reference voltage signal Vref includes only an interval in which the voltage value continuously increases and an interval in which the voltage value continuously decreases.

Further, fig. 7A also shows the initial reference voltage signal Vref'. It can be seen that in order to ensure that the broadband signal and the narrowband signal generated by the control circuit 100 for controlling the power output stage 200 have substantially the same duration for turning on the first switch 210, the portions of the reference voltage signal Vref on both sides of the initial reference voltage signal Vref' are completely symmetrical.

That is, in one period, the area of the region formed by the portion of the reference voltage signal Vref larger than the initial reference voltage signal Vref 'and the initial reference voltage signal Vref' is equal to the area of the region formed by the portion of the reference voltage signal Vref smaller than the initial reference voltage signal Vref 'and the initial reference voltage signal Vref'.

Fig. 7A also shows a ramp voltage signal Vramp. The ramp voltage signal Vramp changes (i.e., rises) in accordance with a first trend from the time when the first switch 210 starts to be turned on. At a first time t1 rising to the reference voltage signal Vref, the ramp voltage signal Vramp starts to change (i.e., fall) according to a second trend of change.

Here, the change speed of the voltage value of the ramp voltage signal Vramp during any two changes according to the first change tendency is the same. That is, the ramp voltage signal Vramp has the same slope during each rise of the voltage value.

At each first time t1, the comparator 1110 generates a pulse Sp, and the controller 120 controls the first switch 210 to switch from on to off. Specifically, the controller 120 may generate the PWM signal Spwm as shown in fig. 7A to control the first switch 210 to be turned on during a period in which the PWM signal Spwm has a high level and to be turned off during a period in which the PWM signal Spwm has a low level.

Referring to fig. 7A, since the reference voltage signal Vref varies and the slope of the ramp voltage signal Vramp does not vary during each rise in voltage value, this results in a variation in the duration of each rise in the ramp voltage signal Vramp. That is, the PWM signal Spwm has a duration change of a high level in each period.

Fig. 7B and 7C are substantially similar to the case of fig. 7A, except that the shape of the waveform of the reference voltage signal Vref is different. As described previously, the shape of the waveform of the reference voltage signal Vref in fig. 7A is a triangle, while the shape of the waveform of the reference voltage signal Vref in fig. 7B is a trapezoid, and the shape of the waveform of the reference voltage signal Vref in fig. 7C is a more complex polygon. Therefore, the details of fig. 7B and 7C will not be described here, and the relevant points can be referred to the description of fig. 7A.

As can be seen in connection with the examples shown in fig. 7A to 7C, in the case where the second condition is satisfied, the control signal Spwm generated by the control circuit 100 for controlling the power output stage 200 is a broadband signal, and causing the switches in the power output stage 200 to be alternately turned on and off generates less electromagnetic interference.

Next, an example shown in fig. 7D will be explained.

As shown in fig. 7D, since the first signal S1 changes between the third value and the fourth value, the change speed of the voltage value of the ramp voltage signal Vramp during the change (i.e., rise) according to the first change tendency changes between the first speed and the second speed. Further, the slope of the ramp voltage signal Vramp during each rise of the voltage value is positively correlated with the intensity value of the first signal S1 during this period.

Fig. 7D also shows the reference voltage signal Vref with a constant voltage value.

In fig. 7D, since the current value of the first signal S1 changes between the third value and the fourth value, this causes the slope of the ramp voltage signal Vramp to change during each rise of the voltage value, which in turn causes the duration of each rise of the ramp voltage signal Vramp to change. That is, the PWM signal Spwm has a duration change of a high level in each period.

As can be seen in connection with the example shown in fig. 7D, in the case that the first condition is satisfied, the control signal Spwm generated by the control circuit 100 for controlling the power output stage 200 is also a broadband signal, so that the switches in the power output stage 200 are turned on and off alternately to generate less electromagnetic interference.

It should be understood that fig. 7D illustrates only one case where the shape of the waveform of the first signal S1 is a triangle, but the disclosed embodiments are not limited thereto. For example, the shape of the waveform of the first signal S1 may also be a trapezoid or other more complex polygon.

The control circuit 100 of the various embodiments of the present disclosure has been fully described so far. It is understood that the control circuit 100 of the present disclosure can be obtained by simply modifying the timer in the control circuit of the COT DC/DC converter of the related art (for example, by additionally adding the first signal generating circuit 1120 to the timer), and is low in manufacturing cost and convenient to manufacture.

The present disclosure also provides a control method of the control circuit 100 of the DC/DC converter based on any one of the above embodiments. As shown in FIG. 8, the control method includes steps 802 to 806.

In step 802, the comparator 1110 generates a pulse Sp each time the voltage value of the ramp voltage signal Vramp changes to the voltage value of the reference voltage signal Vref according to a first trend.

At step 804, the controller 120 controls the second switch 220 to be turned off during the time when the first switch 210 is turned on.

At step 806, the controller 120 controls the first switch 210 to switch from on to off in response to each pulse Sp.

In this manner, a broadband signal for controlling the power output stage 200 in the DC/DC converter can be generated, so that electromagnetic interference can be reduced.

It should be understood that the control method may also include other steps to implement the operations performed by the control circuit 100 of any of the above embodiments. And will not be described in detail herein.

The present disclosure also provides a DC/DC converter circuit comprising the control circuit 100 of the DC/DC converter of any one of the above embodiments and the power output stage 200 in the DC/DC converter of any one of the above embodiments.

An embodiment of the present disclosure further provides an electronic device including the DC/DC conversion circuit of any one of the above embodiments. The electronic device may be, for example, a power supply, a mobile phone, a computer, etc.

Thus, various embodiments of the present disclosure have been described in detail. Some details that are well known in the art have not been described in order to avoid obscuring the concepts of the present disclosure. It will be fully apparent to those skilled in the art from the foregoing description how to practice the presently disclosed embodiments.

In the present specification, the embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same or similar parts in the embodiments are referred to each other. As for the embodiments of the method, the DC/DC converter circuit and the electronic device, since they correspond substantially to the embodiments of the control circuit of the DC/DC converter, the description is relatively simple, and for the relevant points, reference may be made to the partial description of the embodiments of the control circuit.

Although some specific embodiments of the present disclosure have been described in detail by way of example, it should be understood by those skilled in the art that the foregoing examples are for purposes of illustration only and are not intended to limit the scope of the present disclosure. It will be understood by those skilled in the art that various changes may be made in the above embodiments or equivalents may be substituted for elements thereof without departing from the scope and spirit of the present disclosure. The scope of the present disclosure is defined by the appended claims.

Claims

1. A control circuit of a DC/DC converter comprising a first switch (210) and a second switch (220) connected in series between an input terminal and a ground terminal, the first switch (210) being connected between the input terminal and the second switch (220), the control circuit (100) comprising:

a timer (110) comprising:

a comparator (1110) configured to generate a pulse (Sp) at a first time (t 1) at which the voltage value of a ramp voltage signal (Vramp) changes to the voltage value of a reference voltage signal (Vref) according to a first trend of change each time, wherein the voltage value of the ramp voltage signal (Vramp) changes from the first time (t 1) according to a second trend of change opposite to the first trend of change; and

a controller (120) configured to control the first switch (210) to switch from on to off in response to each pulse (Sp); -controlling the second switch (220) to be open during the first switch (210) being on;

wherein the control circuit (100) satisfies one of a first condition and a second condition, wherein:

the first condition includes: the voltage value of the ramp voltage signal (Vramp) changes between a first speed and a second speed at a changing speed during the change according to the first trend;

the second condition includes: the voltage value of the reference voltage signal (Vref) varies between a first value and a second value.

2. Control circuit according to claim 1, wherein said reference voltage signal (Vref) in said second condition comprises at least an interval of successively increasing voltage values and an interval of successively decreasing voltage values.

3. A control circuit according to claim 2, wherein the voltage value of the reference voltage signal (Vref) in the second condition is unique at any time.

4. The control circuit of claim 1,

the first condition further comprises: the voltage value of the reference voltage signal (Vref) is constant;

the second condition further comprises: the voltage value of the ramp voltage signal (Vramp) has the same change speed in any two change periods according to the first change trend.

5. The control circuit of claim 1, wherein the timer (110) further comprises:

a first signal generation circuit (1120) configured to generate a first signal (S1), the intensity value of the first signal (S1) varying between a third value and a fourth value; and

a second signal generation circuit (1130) configured to generate the ramp voltage signal (Vramp) in the first condition based on the first signal (S1).

6. The control circuit according to claim 5, wherein the first signal (S1) is a current signal, and a speed of change of the voltage value of the ramp voltage signal (Vramp) in the first condition during each change according to the first trend of change is positively correlated with a current value of the first signal (S1) during the change.

7. The control circuit of claim 1, wherein the timer (110) further comprises:

a first signal generation circuit (1120) configured to generate a first signal (S1), the intensity value of the first signal (S1) varying between a third value and a fourth value,

wherein the first signal (S1) is the reference voltage signal (Vref) in the second condition.

8. The control circuit according to any of claims 5-7, wherein the first signal (S1) comprises at least an interval of continuously increasing intensity values and an interval of continuously decreasing intensity values.

9. The control circuit according to claim 8, wherein the intensity value of the first signal (S1) is unique at any time.

10. The control circuit according to any of claims 5-7, wherein the intensity value of the first signal (S1) varies periodically between the third value and the fourth value.

11. The control circuit of claim 10, wherein the first signal generating circuit (1120) comprises:

a charge pump circuit (1121) configured to generate a second signal (S2), the second signal (S2) being a voltage signal, a voltage value of the second signal (S2) periodically varying between a fifth value and a sixth value, according to a clock signal (CLK) for controlling the second signal (S2) to periodically vary, and a control Signal (SC) for controlling the voltage value of the second signal (S2) to vary between the fifth value and the sixth value;

an edge limiter circuit (1122) configured to compare a voltage value of the second signal (S2) with the fifth and sixth values, respectively, to generate the control Signal (SC); and

a signal processing circuit (1123) configured to process the second signal (S2) to output the first signal (S1).

12. The control circuit of claim 11, wherein the charge pump circuit (1121) comprises:

a capacitor (1121 a);

a switch array (1121 b) connected to the capacitor (1121 a), the switch array (1121 b) having a plurality of modes including a first mode and a second mode, a voltage value of the second signal (S2) being increased if the switch array (1121 b) is in the first mode and being decreased if the switch array (1121 b) is in the second mode; and

a logic operation circuit (1121 c) configured to control the switch array (1121 b) to switch from a current mode to another mode at a time point when the voltage value of the second signal (S2) changes to the fifth value or the sixth value according to the control Signal (SC).

13. The control circuit of claim 12, wherein the plurality of modes further includes a third mode, the voltage value of the second signal (S2) being constant if the switch array (1121 b) is in the third mode.

14. The control circuit of claim 12, wherein the first mode comprises a plurality of first sub-modes, the second mode comprises a plurality of second sub-modes, the voltage value of the second signal (S2) has a different increasing speed if the switch array (1121 b) is in a different first sub-mode, and a different decreasing speed if the switch array (1121 b) is in a different second sub-mode, wherein:

the edge limiter circuit (1122) is further configured to compare a voltage value of the second signal (S2) with a seventh value between the fifth value and the sixth value to generate the control Signal (SC); and

the logic operation circuit (1121 c) is also configured to control the switch array (1121 b) to switch from a first sub-mode to another first sub-mode at the present time according to the control Signal (SC); controlling the switch array (1121 b) to switch from a second sub-mode currently being in to another second sub-mode at the second time in accordance with the control Signal (SC),

wherein the second time is a time when the voltage value of the second signal (S2) changes to the seventh value.

15. The control circuit according to any of claims 5-7, wherein the first signal generation circuit (1120) comprises a state control circuit configured to be in a first state or a second state,

the first signal generation circuit (1120) is configured to generate the first signal (S1) if the state control circuit is in the first state and to generate a third signal if the state control circuit is in the second state,

wherein the intensity value of the third signal is constant at an eighth value equal to one-half of the sum of the third value and the fourth value.

16. The control circuit according to any of claims 5-7, wherein the shape of the waveform of the first signal (S1) is triangular or trapezoidal.

17. A DC/DC conversion circuit comprising:

a control circuit of the DC/DC converter of any one of claims 1 to 16; and

the DC/DC converter.

18. An electronic device, comprising:

the DC/DC conversion circuit of claim 17.

19. A control method based on the control circuit of the DC/DC converter of any one of claims 1 to 16, comprising:

the comparator generates a pulse at the moment when the voltage value of the ramp voltage signal changes to the voltage value of the reference voltage signal according to the first change trend each time;

the controller controls the second switch to be turned off during the first switch is turned on; and

the controller controls the first switch to switch from on to off in response to each pulse.