CN115764961B

CN115764961B - Energy storage system and midpoint potential balance control method and device

Info

Publication number: CN115764961B
Application number: CN202310031593.7A
Authority: CN
Inventors: 李俊芝; 董航飞; 陆伟; 冯中魁; 李宗宝; 石九林; 徐小飞
Original assignee: Jiangsu Zhongtian Technology Co Ltd
Current assignee: Zhongtian Group Shanghai Superconducting Technology Co ltd
Priority date: 2023-01-10
Filing date: 2023-01-10
Publication date: 2023-05-05
Anticipated expiration: 2043-01-10
Also published as: CN115764961A

Abstract

The specification provides an energy storage system and a midpoint potential balance control method and device. The method comprises the following steps: detecting whether the first relay and the second relay are both in an off state under the condition that the inverter module is determined to exit the standby state; under the condition that the first relay and the second relay are not in the disconnection state, determining a first target relay meeting the requirements from the first relay and the second relay; the first target relay is controlled to be in a closed state, so that the first capacitor and the second capacitor are charged and discharged through the target lead by utilizing the power supply module; detecting whether the time delay of the first target relay is larger than or equal to a first time preset value; and under the condition that the time delay is larger than or equal to a first time preset value, controlling the inverter module to generate different state levels based on a pulse width modulation technology. Based on the method, the problem of high system complexity in the existing method can be solved, and the neutral point potential balance of the energy storage system is realized so as to prolong the service life of equipment.

Description

Energy storage system and midpoint potential balance control method and device

Technical Field

The specification belongs to the technical field of power electronics, and particularly relates to an energy storage system and a midpoint potential balance control method and device.

Background

With the increasing environmental awareness, higher requirements are put on the voltage class and the power class of the inverter. The inverter mostly adopts a three-level topological structure, which comprises a Neutral Point Clamped (NPC) three-level inverter and an Active Neutral Point Clamped (ANPC) three-level inverter. The neutral-point clamped three-level inverter has the advantages of low harmonic content of an output waveform and high output power, so that the neutral-point clamped three-level inverter is widely applied to the technical field of power electronics.

Because of the inherent characteristics of the three-level topological structure, each phase of voltage can be in a zero-level switching state, namely, a current path exists at the midpoint of the direct current bus, and when two capacitors adjacent to the midpoint are respectively in a charging state and a discharging state, the voltage difference of the two capacitors is caused to be different from zero, so that the service life of the capacitor at the direct current side is reduced; meanwhile, the direction and the magnitude of the output voltage vector in each direction can be changed, so that the Total Harmonic Distortion (THD) value of the current at the output side is increased, the content of low-order harmonic is increased, and the output efficiency is reduced. Therefore, a certain method is needed to realize the balance of the midpoint potential.

In the prior art, the neutral point potential balance control method can be generally divided into a hardware scheme and a software scheme. The hardware scheme needs to add a balance bridge and other hardware devices, so that the complexity and the use cost of the system are improved. Software schemes can be divided into two methods, carrier modulation and space vector modulation. The carrier modulation causes problems such as reduced dc voltage utilization, increased current distortion, and increased system loss. The space vector modulation algorithm is complex, has higher requirement on the computing capacity of the digital processing chip, and is not beneficial to popularization and application.

In view of the above technical problems, no effective solution has been proposed at present.

Disclosure of Invention

The specification provides an energy storage system and a midpoint potential balance control method and device, which can solve the problems of high system complexity and high application cost in the existing method and realize the balance control of midpoint potential in the operation process of the energy storage system.

An objective of the embodiments of the present disclosure is to provide an energy storage system, and a method and an apparatus for controlling midpoint potential balance. The energy storage system at least comprises a power supply module and an inverter module;

the power supply module comprises a plurality of parallel battery clusters; the topological structure of the inverter module comprises a plurality of bridge arm structures;

Intermediate nodes in the battery cluster are connected through target wires; the target wires are respectively connected with intermediate nodes of a plurality of bridge arm structures in the topological structure of the inverter module;

the topological structure of the inverter module comprises a plurality of bridge arm structures which are respectively connected with the alternating current filter circuit; the alternating current filter circuit is connected with a power grid.

Further, the inverter module comprises a clamp type three-level inverter; correspondingly, the topological structure of the inverter module comprises three bridge arm structures.

Further, the topological structure of the inverter module also comprises a first relay and a second relay; the first relay and the second relay are connected between the direct current positive bus and the direct current negative bus in series; the first relay is used for controlling the first resistor access circuit; the second relay is used for controlling a second resistor access circuit; an intermediate junction between the second relay and the first resistor is connected to a target conductor.

Further, the topological structure of the inverter module further comprises a first capacitor and a second capacitor; the first capacitor and the second capacitor are connected between the direct current positive bus and the direct current negative bus in series; an intermediate junction between the first capacitor and the second capacitor is connected to a target conductor.

The embodiment of the specification also provides a midpoint potential balance control method, wherein the midpoint potential balance control method is applied to an energy storage system and comprises the following steps:

controlling the inverter module to generate different-state levels based on a pulse width modulation technology under the condition that the first relay and the second relay in the inverter module of the energy storage system are determined to be in a closed state;

detecting whether the clamping voltage difference is smaller than or equal to a first voltage preset value; and controlling the first relay and the second relay to be in a disconnected state under the condition that the clamping voltage difference is less than or equal to a first voltage preset value;

detecting whether the inverter module enters a standby state; stopping the inverter module from generating the level of the different states under the condition that the inverter module is determined to enter the standby state;

detecting whether the inverter module exits the standby state; detecting whether the first relay and the second relay are both in an off state under the condition that the inverter module is determined to exit the standby state;

under the condition that the first relay and the second relay are not in the disconnection state, determining a first target relay meeting the requirements from the first relay and the second relay; the first target relay is controlled to be in a closed state, so that the first capacitor and the second capacitor are charged and discharged through the target lead by utilizing the power supply module; the first target relay is a relay in an off state in the first relay and the second relay;

Detecting whether the time delay generated from closing to actual working of the first target relay is greater than or equal to a first time preset value or not; and under the condition that the time delay generated from closing to actual working of the first target relay is larger than or equal to a first time preset value, controlling the inverter module to generate different state levels based on a pulse width modulation technology.

Further, in another embodiment of the method, in the event that it is determined that both the first relay and the second relay are in an off state, the inverter module is controlled to generate different state levels based on a pulse width modulation technique.

Further, in another embodiment of the method, the detecting whether the inverter module enters a standby state includes:

detecting whether a power instruction issued by an upper computer is smaller than a first power preset value or not;

detecting whether the real-time power of the inverter module is smaller than a second power preset value or not and whether the duration of the real-time power smaller than the second power preset value is larger than a third time preset value or not under the condition that the power instruction issued by the upper computer is smaller than the first power preset value;

and determining that the inverter module enters a standby state under the condition that the real-time power of the inverter module is smaller than the second power preset value and the duration time of the real-time power smaller than the second power preset value is larger than the third time preset value.

Further, in another embodiment of the method, in a case where it is determined that the inverter module does not exit the standby state, detecting whether the standby state duration is greater than or equal to a second time preset value;

under the condition that the duration time of the standby state is larger than or equal to a second time preset value, determining a second target relay meeting the requirements from the first relay and the second relay; and controlling the second target relay to be in an off state; the second target relay is a relay with smaller clamping voltage corresponding to the first relay and the second relay;

detecting whether the clamping voltage difference is smaller than or equal to a second voltage preset value;

and controlling the relays except for the second target relay in the first relay and the second relay to be in an off state under the condition that the clamping voltage difference is less than or equal to a second voltage preset value.

In another aspect, the present application provides a neutral point potential balance control device, including:

the starting module is used for controlling the inverter module to generate different-state levels based on a pulse width modulation technology under the condition that the first relay and the second relay in the inverter module of the energy storage system are determined to be in a closed state;

The first control module is used for detecting whether the clamping voltage difference is smaller than or equal to a first voltage preset value; and controlling the first relay and the second relay to be in a disconnected state under the condition that the clamping voltage difference is less than or equal to a first voltage preset value;

the second control module is used for detecting whether the inverter module enters a standby state; stopping the inverter module from generating the level of the different states under the condition that the inverter module is determined to enter the standby state;

the third control module is used for detecting whether the inverter module exits from the standby state; detecting whether the first relay and the second relay are both in an off state under the condition that the inverter module is determined to exit the standby state;

the fourth control module is used for determining a first target relay meeting the requirements from the first relay and the second relay under the condition that the first relay and the second relay are not in the disconnection state; the first target relay is controlled to be in a closed state, so that the first capacitor and the second capacitor are charged and discharged through the target lead by utilizing the power supply module; the first target relay is a relay in an off state in the first relay and the second relay;

The fifth control module is used for detecting whether the time delay generated from closing to actual working of the first target relay is greater than or equal to a first time preset value; and under the condition that the time delay generated from closing to actual working of the first target relay is larger than or equal to a first time preset value, controlling the inverter module to generate different state levels based on a pulse width modulation technology.

In yet another aspect, the present application further provides a computer readable storage medium having stored thereon computer instructions that when executed implement the above-described midpoint potential balance control method.

The energy storage system at least comprises a power supply module and an inverter module; the power supply module comprises a plurality of parallel battery clusters; the topological structure of the inverter module comprises a plurality of bridge arm structures; intermediate nodes in the battery cluster are connected through target wires; the target wires are respectively connected with intermediate nodes of a plurality of bridge arm structures in the topological structure of the inverter module; the topological structure of the inverter module comprises a plurality of bridge arm structures which are respectively connected with the alternating current filter circuit; the alternating current filter circuit is connected with a power grid.

The specification also provides a midpoint potential balancing method, wherein the midpoint potential balancing control method is applied to an energy storage system, and under the condition that a first relay and a second relay in an inverter module of the energy storage system are determined to be in a closed state, the inverter module is controlled to generate levels in different states based on a pulse width modulation technology; detecting whether the clamping voltage difference is smaller than or equal to a first voltage preset value; and controlling the first relay and the second relay to be in a disconnected state under the condition that the clamping voltage difference is less than or equal to a first voltage preset value; detecting whether the inverter module enters a standby state; stopping the inverter module from generating the level of the different states under the condition that the inverter module is determined to enter the standby state; detecting whether the inverter module exits the standby state; detecting whether the first relay and the second relay are both in an off state under the condition that the inverter module is determined to exit the standby state; under the condition that the first relay and the second relay are not in the disconnection state, determining a first target relay meeting the requirements from the first relay and the second relay; the first target relay is controlled to be in a closed state, so that the first capacitor and the second capacitor are charged and discharged through the target lead by utilizing the power supply module; the first target relay is a relay in an off state in the first relay and the second relay; detecting whether the time delay generated from closing to actual working of the first target relay is greater than or equal to a first time preset value or not; and under the condition that the time delay generated from closing to actual working of the first target relay is larger than or equal to a first time preset value, controlling the inverter module to generate different state levels based on a pulse width modulation technology.

And controlling the inverter module to generate different state levels based on the pulse width modulation technique in the case that it is determined that both the first relay and the second relay are in the off state.

Further, when detecting whether the inverter module enters a standby state, detecting whether a power instruction issued by the upper computer is smaller than a first power preset value; detecting whether the real-time power of the inverter module is smaller than a second power preset value or not and whether the duration of the real-time power smaller than the second power preset value is larger than a third time preset value or not under the condition that the power instruction issued by the upper computer is smaller than the first power preset value; and determining that the inverter module enters a standby state under the condition that the real-time power of the inverter module is smaller than the second power preset value and the duration time of the real-time power smaller than the second power preset value is larger than the third time preset value.

In addition, under the condition that the inverter module is not out of the standby state, detecting whether the duration of the standby state is larger than or equal to a second time preset value; under the condition that the duration time of the standby state is larger than or equal to a second time preset value, determining a second target relay meeting the requirements from the first relay and the second relay; and controlling the second target relay to be in an off state; the second target relay is a relay with smaller clamping voltage corresponding to the first relay and the second relay; detecting whether the clamping voltage difference is smaller than or equal to a second voltage preset value; and under the condition that the clamping voltage difference is less than or equal to a second voltage preset value, controlling the relays except for the second target relay in the first relay and the second relay to be in an off state so as to avoid power loss caused by long-time access of the first resistor and the second resistor to the circuit.

Drawings

In order to more clearly illustrate the embodiments of the present disclosure, the drawings that are required for the embodiments will be briefly described below, and the drawings described below are only some embodiments described in the present disclosure, and other drawings may be obtained according to these drawings without inventive effort for a person of ordinary skill in the art.

FIG. 1 is a schematic flow chart of one embodiment of a neutral point potential balance control method provided in the present specification;

FIG. 2 is a schematic diagram of an embodiment of an energy storage system provided herein;

FIG. 3 is a schematic flow chart of another embodiment of a neutral-point potential balance control method provided in the present disclosure;

FIG. 4 is a schematic diagram of another embodiment of an energy storage system provided herein;

FIG. 5 is a schematic block diagram of an embodiment of a neutral-point potential balance control device provided in the present disclosure;

fig. 6 is a schematic structural diagram of a server provided in the present specification.

Detailed Description

In order to make the technical solutions in the present specification better understood by those skilled in the art, the technical solutions in the embodiments of the present specification will be clearly and completely described below with reference to the drawings in the embodiments of the present specification, and it is obvious that the described embodiments are only some embodiments of the present specification, not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are intended to be within the scope of the present disclosure.

In consideration of a midpoint potential balance control method based on a hardware scheme, an additional hardware facility is added into an original circuit structure to keep midpoint potential balance, so that the complexity of system design and the application cost are increased, and in the actual application process, coordination control parameters among various closed loops are difficult to determine, so that the difficulty of actual popularization and application is increased.

Further, a midpoint potential balance control method based on a software scheme is considered, and the method can be generally divided into two methods of carrier modulation and space vector modulation; the carrier modulation generally adopts a closed-loop control mode of injecting special fixed zero sequence components or increasing midpoint potential of a direct current side bus to inhibit midpoint potential fluctuation, and the mode can cause the problems of reduced direct current voltage utilization rate, increased current distortion rate, increased system loss and the like; the space vector modulation can adjust the selection, the action sequence and the time of the redundant voltage vector from the time scale of the switching period, but the algorithm is complex, has higher requirement on the computing capacity of a digital processing chip, and is not beneficial to popularization and application.

Aiming at the problems and the specific reasons for generating the problems in the prior art, the application considers to introduce a midpoint potential balance control method suitable for an energy storage system so as to realize the technical effect of eliminating midpoint voltage difference.

Based on the above-mentioned idea, referring to fig. 2, the present disclosure proposes an energy storage system, where the energy storage system at least includes a power supply module and an inverter module; the power supply module comprises a plurality of parallel battery clusters; the topological structure of the inverter module comprises a plurality of bridge arm structures; intermediate nodes in the battery cluster are connected through target wires; the target wires are respectively connected with intermediate nodes of a plurality of bridge arm structures in the topological structure of the inverter module; the topological structure of the inverter module comprises a plurality of bridge arm structures which are respectively connected with the alternating current filter circuit; the alternating current filter circuit is connected with a power grid.

In particular implementations, the energy storage system may include the following topologies.

The power supply module comprises a plurality of battery packs, wherein each battery pack is connected with one inverter module; each battery pack comprises a plurality of parallel battery clusters; each battery cluster comprises a plurality of battery modules connected in series; each battery module includes a plurality of battery cells. For example, in some implementations, the battery pack includes 5 parallel battery clusters, each including 20 battery modules connected in series. The embodiment of the present disclosure is exemplified by the above battery pack, and is similar in other scenarios, and will not be described in detail.

The inverter module comprises a clamping type three-level inverter; correspondingly, the topological structure of the inverter module comprises three bridge arm structures; wherein the first bridge arm comprises six switching tubes T with clamping diodes _A1 ~T _A6 ，T _A1 ~T _A6 Respectively with clamping diode D _A1 ~D _A6 Parallel T _A1 Output end T of (C) _A2 、T _A5 T is the input terminal of (1) _A4 Is connected with the input end T of _A3 、T _A6 T is the output terminal of (1) _A5 Output end T of (C) _A6 T is the input terminal of (1) _A1 Is connected with a direct current positive bus, T _A4 The output end of (1) is connected with a direct current negative bus, T _A5 Output terminal T of (2) _A6 Is connected with the middle point of the DC bus, T _A2 Output terminal T of (2) _A3 The input end of the power supply is connected with an alternating current filter circuit; wherein the method comprises the steps ofThe direct current bus comprises a direct current positive bus and a direct current negative bus; the second bridge arm comprises six switching tubes T with clamping diodes _B1 ~ T _B6 ，T _B1 ~T _B6 Respectively with clamping diode D _B1 ~D _B6 Parallel T _B1 Output end T of (C) _B2 、T _B5 T is the input terminal of (1) _B4 Is connected with the input end T of _B3 、T _B6 T is the output terminal of (1) _B5 Output end T of (C) _B6 T is the input terminal of (1) _B1 Is connected with a direct current positive bus, T _B4 The output end of (1) is connected with a direct current negative bus, T _B5 Output terminal T of (2) _B6 Is connected with the middle point of the DC bus, T _B2 Output terminal T of (2) _B3 The input end of the power supply is connected with an alternating current filter circuit; the third bridge arm comprises six switching tubes T with clamping diodes _C1 ~ T _C6 ，T _C1 ~T _C6 Respectively with clamping diode D _C1 ~D _C6 Parallel T _C1 Output end T of (C) _C2 、T _C5 T is the input terminal of (1) _C4 Is connected with the input end T of _C3 、T _C6 T is the output terminal of (1) _C5 Output end T of (C) _C6 T is the input terminal of (1) _C1 Is connected with a direct current positive bus, T _C4 The output end of (1) is connected with a direct current negative bus, T _C5 Output terminal T of (2) _C6 Is connected with the middle point of the DC bus, T _C2 Output terminal T of (2) _C3 Is connected with the alternating current filter circuit. It should be noted that, the topology of the inverter module may be adjusted according to the actual situation, which is not limited in this specification.

The topological structure of the inverter module also comprises a first relay and a second relay; the first relay and the second relay are connected between the direct current positive bus and the direct current negative bus in series; the first relay is used for controlling the first resistor access circuit; the second relay is used for controlling a second resistor access circuit; an intermediate junction between the second relay and the first resistor is connected to a target conductor.

The topological structure of the inverter module also comprises a first capacitor and a second capacitor; the first capacitor and the second capacitor are connected between the direct current positive bus and the direct current negative bus in series; an intermediate junction between the first capacitor and the second capacitor is connected to a target conductor.

The target lead can charge and discharge the battery pack by utilizing the physical characteristics of the battery pack, when the voltage difference between the first capacitor and the second capacitor exceeds a voltage threshold value, so as to realize balance control of the midpoint potential.

In one embodiment, the energy storage system can be specifically applied to the situations of power generation side energy storage, power grid side energy storage, user side energy storage, micro power grid energy storage and the like.

The specification provides a midpoint potential balance control method, which is applied to the energy storage system. Firstly, under the condition that a first relay and a second relay in an inverter module of an energy storage system are determined to be in a closed state, controlling the inverter module, and generating levels in different states based on a pulse width modulation technology; detecting whether the clamping voltage difference is smaller than or equal to a first voltage preset value; and controlling the first relay and the second relay to be in a disconnected state under the condition that the clamping voltage difference is less than or equal to a first voltage preset value; then, detecting whether the inverter module enters a standby state; stopping the inverter module from generating the level of the different states under the condition that the inverter module is determined to enter the standby state; detecting whether the inverter module exits the standby state; detecting whether the first relay and the second relay are both in an off state under the condition that the inverter module is determined to exit the standby state; under the condition that the first relay and the second relay are not in the disconnection state, determining a first target relay meeting the requirements from the first relay and the second relay; the first target relay is controlled to be in a closed state, so that the first capacitor and the second capacitor are charged and discharged through the target lead by utilizing the power supply module; the first target relay is a relay in an off state in the first relay and the second relay; finally, detecting whether the time delay generated from closing to actual working of the first target relay is greater than or equal to a first time preset value; and under the condition that the time delay generated from closing to actual working of the first target relay is larger than or equal to a first time preset value, controlling the inverter module to generate different state levels based on a pulse width modulation technology. In particular, and with reference to FIG. 1, the method may include the following.

S101: in the event that the first relay and the second relay in the inverter module of the energy storage system are determined to be in a closed state, the inverter module is controlled to generate different state levels based on a pulse width modulation technique.

In some embodiments, the first relay is configured to control an on state of the first resistor; under the condition that the first relay is closed, the first resistor is connected into the circuit to charge and discharge the first capacitor; under the condition that the first relay is disconnected, the first resistor is disconnected from the circuit, so that the circuit loss is reduced; the second relay is used for controlling the access state of the second resistor; under the condition that the second relay is closed, the second resistor is connected into the circuit to charge and discharge the second capacitor; in the case where the second relay is open, the second resistor is disconnected from the circuit to reduce circuit loss.

In some embodiments, the method further comprises, prior to controlling the inverter module to generate the different state levels based on the pulse width modulation technique, in the event that the first relay and the second relay in the inverter module of the energy storage system are determined to be in the closed state:

s1: collecting the positive bus voltage and the negative bus voltage of a battery cluster in a power supply module; the positive bus voltage of the battery cluster comprises a positive bus voltage of the battery cluster 1, a positive bus voltage of the battery cluster 2, a positive bus voltage of the battery cluster 3, a positive bus voltage of the battery cluster 4 and a positive bus voltage of the battery cluster 5; the negative bus voltage of the battery cluster comprises a negative bus voltage of the battery cluster 1, a negative bus voltage of the battery cluster 2, a negative bus voltage of the battery cluster 3, a negative bus voltage of the battery cluster 4 and a negative bus voltage of the battery cluster 5;

S2: the voltage difference between the positive bus voltage of the battery cluster and the negative bus voltage of the battery cluster is obtained, and the battery cluster with the smallest voltage difference is taken as a target battery cluster; wherein the target battery cluster may be one or more;

s3: detecting whether the voltage difference between the positive bus voltage of the battery cluster and the negative bus voltage of the battery cluster of the target battery cluster is larger than a third voltage preset value or not;

s4: and controlling the target battery cluster to be in an off state under the condition that the voltage difference between the battery cluster positive bus voltage and the battery cluster negative bus voltage of the target battery cluster is determined to be larger than a third voltage preset value.

In a specific implementation scenario, referring to fig. 4, each battery cluster in the power supply module may be connected to a topological midpoint of the inverter module through a disconnecting switch, where the disconnecting switch is used to control the target battery cluster to be in an off state.

S102: detecting whether the clamping voltage difference is smaller than or equal to a first voltage preset value; and controlling the first relay and the second relay to be in an off state under the condition that the clamping voltage difference is less than or equal to the first voltage preset value.

In some embodiments, the clamping voltage difference may specifically be a voltage difference between the first capacitor and the second capacitor.

In some embodiments, in the case where the clamping voltage difference is determined to be greater than the first voltage preset value, the method further comprises, when embodied: it is detected whether the inverter module enters a standby state.

S103: detecting whether the inverter module enters a standby state; in the case where it is determined that the inverter module enters the standby state, the inverter module is stopped from generating the level of the different state.

In some embodiments, the detecting whether the inverter module enters the standby state may include:

s1: detecting whether a power instruction issued by an upper computer is smaller than a first power preset value or not;

s2: detecting whether the real-time power of the inverter module is smaller than a second power preset value or not and whether the duration of the real-time power smaller than the second power preset value is larger than a third time preset value or not under the condition that the power instruction issued by the upper computer is smaller than the first power preset value;

s3: and determining that the inverter module enters a standby state under the condition that the real-time power of the inverter module is smaller than the second power preset value and the duration time of the real-time power smaller than the second power preset value is larger than the first time preset value.

In some embodiments, the inverter module needs to adjust its working state at any time according to the power instruction issued by the upper computer, and after determining that the inverter module enters the standby state, the inverter module stops generating the levels of different states, so as to reduce the power generated by the energy storage system.

S104: detecting whether the inverter module exits the standby state; in the event that it is determined that the inverter module exits the standby state, it is detected whether both the first relay and the second relay are in an open state.

In some embodiments, detecting whether the inverter module exits the standby state may include, in particular: detecting whether a power instruction issued by the upper computer is larger than or equal to a first power preset value, and determining that the inverter module exits from a standby state under the condition that the power instruction issued by the upper computer is larger than or equal to the first power preset value.

In some embodiments, referring to fig. 3, in a case where it is determined that the inverter module does not exit the standby state, the method further includes, when implemented:

s1: detecting whether the duration of the standby state is greater than or equal to a second time preset value under the condition that the inverter module is not out of the standby state;

s2: under the condition that the duration time of the standby state is larger than or equal to a second time preset value, determining a second target relay meeting the requirements from the first relay and the second relay; and controlling the second target relay to be in an off state; the second target relay is a relay with smaller clamping voltage corresponding to the first relay and the second relay;

S3: detecting whether the clamping voltage difference is smaller than or equal to a second voltage preset value;

s4: and controlling the relays except for the second target relay in the first relay and the second relay to be in an off state under the condition that the clamping voltage difference is less than or equal to a second voltage preset value.

In some embodiments, the second time preset value may be determined according to actual requirements and battery characteristics in the field. For example, in some implementations, the second time preset value may be set to 1 minute.

In some embodiments, the second voltage preset value may be determined in the following manner when in implementation:

s1: under the condition of obtaining a unit power factor, generating first positive and negative bus voltage difference data in the process of running at full power, and recording the maximum value of the first positive and negative bus voltage difference data as a first intermediate value;

s2: acquiring second positive and negative bus voltage difference data generated in the process of running with maximum apparent power under the condition that a neutral point connecting passage of a direct current bus is cut off and voltage difference control of a positive and negative bus is not increased within a direct current voltage allowable range, and recording the maximum value of the second positive and negative bus voltage difference data as a second intermediate value;

S3: determining a second voltage preset value according to the first intermediate value and the second intermediate value; the second voltage preset value is larger than or equal to the first intermediate value and smaller than or equal to the second intermediate value.

For example, in some implementation scenarios, the voltage corresponding to the first capacitor is 450V, and the voltage corresponding to the second capacitor is 550V, then the second target relay is determined to be the first relay corresponding to the first capacitor, and the first relay is controlled to be in an off state, the second capacitor is discharged through the second resistor connected with the second relay, and the voltage of the second capacitor is reduced, so that balance of midpoint potential is achieved.

Based on the embodiment, under the condition that the energy storage system is in a standby state for a long time, the first resistor and the second resistor can be disconnected from the circuit in time, so that the circuit loss caused by excessive consumption of electric energy by the first resistor and the second resistor is avoided.

S105: under the condition that the first relay and the second relay are not in the disconnection state, determining a first target relay meeting the requirements from the first relay and the second relay; the first target relay is controlled to be in a closed state, so that the first capacitor and the second capacitor are charged and discharged through the target lead by utilizing the power supply module; the first target relay is a relay in an off state in the first relay and the second relay.

In some embodiments, in the event that it is determined that both the first relay and the second relay are in an open state, the method further comprises: the inverter module is controlled to generate different state levels based on a pulse width modulation technique.

In some embodiments, where it is determined that both the first relay and the second relay are in an off state, it may be determined that the clamping voltage difference is less than a first voltage preset value, at which time the inverter module may be controlled to generate different state levels based on a pulse width modulation technique.

S106: detecting whether the time delay generated from closing to actual working of the first target relay is greater than or equal to a first time preset value or not; and under the condition that the time delay generated from closing to actual working of the first target relay is larger than or equal to a first time preset value, controlling the inverter module to generate different state levels based on a pulse width modulation technology.

In some embodiments, the first time preset value may be determined in the following manner when in implementation:

s1: acquiring action time by inquiring a relay specification;

s2: determining action time allowance according to background information;

s3: and determining a first time preset value according to the action time and the action time allowance.

For example, in some implementation scenarios, the relay may be an EVQ150 type relay, and accordingly, the action time is 30ms, the action time margin is determined to be 10ms according to background data, and accordingly, the first time preset value may be determined to be 40ms. The embodiment of the present disclosure is exemplified by an EVQ150 relay, and is similar in other scenarios, which will not be described in detail.

Based on the above embodiment, when the first resistor and the second resistor are determined to be connected to the circuit, the inverter module is controlled to generate different levels based on the pulse width modulation technology, so that the balance control of the midpoint potential is realized by using the target conductor.

Preferably, when the midpoint potential balance control method is implemented, the method can further comprise the steps of controlling the three-phase modulation wave based on the zero-sequence component, and adding a zero-sequence component on the basis of the three-phase modulation wave so as to improve the voltage utilization rate of the direct current bus; the three-phase modulation wave specifically includes an a phase, a b phase, and a c phase. In some embodiments, the modulated wave corresponding to the first leg is a-phase, the modulated wave corresponding to the second leg is b-phase, and the modulated wave corresponding to the third leg is c-phase.

In some embodiments, the controlling the three-phase modulated wave based on the zero sequence component may include:

s1: obtaining an initial three-phase modulation wave;

s2: constructing a zero sequence component according to the initial three-phase modulation wave;

s3: the target three-phase modulated wave is calculated based on the initial three-phase modulated wave and the zero sequence component.

In some embodiments, the obtaining the initial three-phase modulation wave may include:

the initial three-phase modulated wave is calculated according to the following equation:

（1）

wherein,,V _ma 、V _mb 、V _mc respectively represents an initial a-phase modulation wave, an initial b-phase modulation wave and an initial c-phase modulation wave,V _a 、V _b 、V _c the amplitude of the initial a-phase modulation wave, the amplitude of the initial b-phase modulation wave and the amplitude of the initial c-phase modulation wave are respectively represented, w represents the fundamental frequency of the power grid voltage, and t represents time.

In some embodiments, the constructing the zero sequence component according to the initial three-phase modulation wave may include:

the zero sequence component is constructed according to the following formula:

（2）

wherein,,V _m0 representing the zero sequence component,V _max representing the maximum value in the initial three-phase modulated wave,V _min representing the minimum value in the initial three-phase modulated wave.

In some embodiments, the calculating the target three-phase modulated wave based on the initial three-phase modulated wave and the zero sequence component may include:

The target three-phase modulated wave is calculated according to the following formula:

（3）

wherein,,

the target modulated waves of the a phase, the b phase and the c phase are respectively represented.

Based on the above-mentioned neutral point potential balance control method, the present disclosure further provides an embodiment of a neutral point potential balance control device, and referring to fig. 5, the neutral point potential balance control device specifically includes the following modules:

a starting module 501, configured to control an inverter module of the energy storage system to generate levels in different states based on a pulse width modulation technique when it is determined that a first relay and a second relay in the inverter module are in a closed state;

the first control module 502 is configured to detect whether the clamping voltage difference is less than or equal to a first voltage preset value; and controlling the first relay and the second relay to be in a disconnected state under the condition that the clamping voltage difference is less than or equal to a first voltage preset value;

a second control module 503, configured to detect whether the inverter module enters a standby state; stopping the inverter module from generating the level of the different states under the condition that the inverter module is determined to enter the standby state;

a third control module 504, configured to detect whether the inverter module exits the standby state; detecting whether the first relay and the second relay are both in an off state under the condition that the inverter module is determined to exit the standby state;

A fourth control module 505, configured to determine a first target relay that meets a requirement from the first relay and the second relay when it is determined that the first relay and the second relay are not both in an off state; the first target relay is controlled to be in a closed state, so that the first capacitor and the second capacitor are charged and discharged through the target lead by utilizing the power supply module; the first target relay is a relay in an off state in the first relay and the second relay;

a fifth control module 506, configured to detect whether a time delay generated from closing to actual operation of the first target relay is greater than or equal to a first time preset value; and under the condition that the time delay generated from closing to actual working of the first target relay is larger than or equal to a first time preset value, controlling the inverter module to generate different state levels based on a pulse width modulation technology.

In some embodiments, the starting module 501 may be further configured to, in a case where it is determined that the first relay and the second relay in the inverter module of the energy storage system are in a closed state, control the inverter module, and collect the positive bus voltage and the negative bus voltage of the battery cluster in the power supply module before generating the levels of different states based on the pulse width modulation technique; the voltage difference between the positive bus voltage of the battery cluster and the negative bus voltage of the battery cluster is obtained, and the battery cluster with the smallest voltage difference is taken as a target battery cluster; detecting whether the voltage difference between the positive bus voltage of the battery cluster and the negative bus voltage of the battery cluster of the target battery cluster is larger than a third voltage preset value or not; and controlling the target battery cluster to be in an off state under the condition that the voltage difference between the battery cluster positive bus voltage and the battery cluster negative bus voltage of the target battery cluster is determined to be larger than a third voltage preset value.

In some embodiments, the first control module 502 may be further configured to detect whether the inverter module enters the standby state if the clamping voltage difference is greater than the first voltage preset value.

In some embodiments, the second control module 503 may be specifically configured to detect whether the power command issued by the host computer is smaller than a first power preset value; detecting whether the real-time power of the inverter module is smaller than a second power preset value or not and whether the duration of the real-time power smaller than the second power preset value is larger than a third time preset value or not under the condition that the power instruction issued by the upper computer is smaller than the first power preset value; determining that the inverter module enters a standby state when the real-time power of the inverter module is smaller than the second power preset value and the duration time of the real-time power smaller than the second power preset value is larger than the first time preset value; in the case where it is determined that the inverter module enters the standby state, the inverter module is stopped from generating the level of the different state.

In some embodiments, the third control module 504 may be further configured to detect whether the duration of the standby state is greater than or equal to the second time preset value if it is determined that the inverter module does not exit the standby state; under the condition that the duration time of the standby state is larger than or equal to a second time preset value, determining a second target relay meeting the requirements from the first relay and the second relay; and controlling the second target relay to be in an off state; the second target relay is a relay with smaller clamping voltage corresponding to the first relay and the second relay; detecting whether the clamping voltage difference is smaller than or equal to a second voltage preset value; and controlling the relays except for the second target relay in the first relay and the second relay to be in an off state under the condition that the clamping voltage difference is less than or equal to a second voltage preset value.

In some embodiments, the fourth control module 505 may also be configured to control the inverter module to generate different states of the electrical level based on a pulse width modulation technique if it is determined that the first relay and the second relay are both in an open state.

In some embodiments, the fifth control module 506 may be further configured to determine the first time preset value by: acquiring action time by inquiring a relay specification; determining action time allowance according to background information; and determining a first time preset value according to the action time and the action time allowance.

It should be noted that, the units, devices, or modules described in the above embodiments may be implemented by a computer chip or entity, or may be implemented by a product having a certain function. For convenience of description, the above devices are described as being functionally divided into various modules, respectively. Of course, when the present description is implemented, the functions of each module may be implemented in the same piece or pieces of software and/or hardware, or a module that implements the same function may be implemented by a plurality of sub-modules or a combination of sub-units, or the like. The above-described apparatus embodiments are merely illustrative, for example, the division of the units is merely a logical function division, and there may be additional divisions when actually implemented, for example, multiple units or components may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form.

The embodiments of the present specification also provide a computer storage medium storing computer program instructions for a midpoint potential balance control method, the computer program instructions realizing when executed: controlling the inverter module to generate different-state levels based on a pulse width modulation technology under the condition that the first relay and the second relay in the inverter module of the energy storage system are determined to be in a closed state; detecting whether the clamping voltage difference is smaller than or equal to a first voltage preset value; and controlling the first relay and the second relay to be in a disconnected state under the condition that the clamping voltage difference is less than or equal to a first voltage preset value; detecting whether the inverter module enters a standby state; stopping the inverter module from generating the level of the different states under the condition that the inverter module is determined to enter the standby state; detecting whether the inverter module exits the standby state; detecting whether the first relay and the second relay are both in an off state under the condition that the inverter module is determined to exit the standby state; under the condition that the first relay and the second relay are not in the disconnection state, determining a first target relay meeting the requirements from the first relay and the second relay; the first target relay is controlled to be in a closed state, so that the first capacitor and the second capacitor are charged and discharged through the target lead by utilizing the power supply module; the first target relay is a relay in an off state in the first relay and the second relay; detecting whether the time delay generated from closing to actual working of the first target relay is greater than or equal to a first time preset value or not; and under the condition that the time delay generated from closing to actual working of the first target relay is larger than or equal to a first time preset value, controlling the inverter module to generate different state levels based on a pulse width modulation technology.

In the present embodiment, the storage medium includes, but is not limited to, a random access Memory (Random Access Memory, RAM), a Read-Only Memory (ROM), a Cache (Cache), a Hard Disk (HDD), or a Memory Card (Memory Card). The memory may be used to store computer program instructions. The network communication unit may be an interface for performing network connection communication, which is set in accordance with a standard prescribed by a communication protocol.

In this embodiment, the functions and effects of the program instructions stored in the computer storage medium may be explained in comparison with other embodiments, and are not described herein.

The present disclosure also provides a server comprising a processor and a memory for storing processor-executable instructions, the processor, when embodied, being operable to perform the following steps according to the instructions: controlling the inverter module to generate different-state levels based on a pulse width modulation technology under the condition that the first relay and the second relay in the inverter module of the energy storage system are determined to be in a closed state; detecting whether the clamping voltage difference is smaller than or equal to a first voltage preset value; and controlling the first relay and the second relay to be in a disconnected state under the condition that the clamping voltage difference is less than or equal to a first voltage preset value; detecting whether the inverter module enters a standby state; stopping the inverter module from generating the level of the different states under the condition that the inverter module is determined to enter the standby state; detecting whether the inverter module exits the standby state; detecting whether the first relay and the second relay are both in an off state under the condition that the inverter module is determined to exit the standby state; under the condition that the first relay and the second relay are not in the disconnection state, determining a first target relay meeting the requirements from the first relay and the second relay; the first target relay is controlled to be in a closed state, so that the first capacitor and the second capacitor are charged and discharged through the target lead by utilizing the power supply module; the first target relay is a relay in an off state in the first relay and the second relay; detecting whether the time delay generated from closing to actual working of the first target relay is greater than or equal to a first time preset value or not; and under the condition that the time delay generated from closing to actual working of the first target relay is larger than or equal to a first time preset value, controlling the inverter module to generate different state levels based on a pulse width modulation technology.

In order to more accurately complete the above instructions, referring to fig. 6, another specific server is provided in this embodiment of the present disclosure, where the server includes a network communication port 601, a processor 602, and a memory 603, and the above structures are connected by an internal cable, so that each structure may perform specific data interaction.

The network communication port 601 may be specifically configured to obtain states of a first relay and a second relay in an inverter module of the energy storage system.

The processor 602 may be specifically configured to, when determining that the first relay and the second relay in the inverter module of the energy storage system are in a closed state, control the inverter module to generate levels in different states based on a pulse width modulation technique; detecting whether the clamping voltage difference is smaller than or equal to a first voltage preset value; and controlling the first relay and the second relay to be in a disconnected state under the condition that the clamping voltage difference is less than or equal to a first voltage preset value; detecting whether the inverter module enters a standby state; stopping the inverter module from generating the level of the different states under the condition that the inverter module is determined to enter the standby state; detecting whether the inverter module exits the standby state; detecting whether the first relay and the second relay are both in an off state under the condition that the inverter module is determined to exit the standby state; under the condition that the first relay and the second relay are not in the disconnection state, determining a first target relay meeting the requirements from the first relay and the second relay; the first target relay is controlled to be in a closed state, so that the first capacitor and the second capacitor are charged and discharged through the target lead by utilizing the power supply module; the first target relay is a relay in an off state in the first relay and the second relay; detecting whether the time delay generated from closing to actual working of the first target relay is greater than or equal to a first time preset value or not; and under the condition that the time delay generated from closing to actual working of the first target relay is larger than or equal to a first time preset value, controlling the inverter module to generate different state levels based on a pulse width modulation technology.

The memory 603 may be used for storing a corresponding program of instructions.

In this embodiment, the network communication port 601 may be a virtual port that binds with different communication protocols, so that different data may be sent or received. For example, the network communication port may be a port responsible for performing web data communication, a port responsible for performing FTP data communication, or a port responsible for performing mail data communication. The network communication port may also be an entity's communication interface or a communication chip. For example, it may be a wireless mobile network communication chip, such as GSM, CDMA, etc.; it may also be a Wifi chip; it may also be a bluetooth chip.

In this embodiment, the processor 602 may be implemented in any suitable manner. For example, the processor may take the form of, for example, a microprocessor or processor, and a computer-readable medium storing computer-readable program code (e.g., software or firmware) executable by the (micro) processor, logic gates, switches, an application specific integrated circuit (Application Specific Integrated Circuit, ASIC), a programmable logic controller, and an embedded microcontroller, among others. The description is not intended to be limiting.

In this embodiment, the memory 603 may include multiple levels, and in a digital system, the memory may be any memory as long as it can hold binary data; in an integrated circuit, a circuit with a memory function without a physical form is also called a memory, such as a RAM, a FIFO, etc.; in the system, the storage device in physical form is also called a memory, such as a memory bank, a TF card, and the like.

Although the present description provides method operational steps as described in the examples or flowcharts, more or fewer operational steps may be included based on conventional or non-inventive means. The order of steps recited in the embodiments is merely one way of performing the order of steps and does not represent a unique order of execution. When implemented by an apparatus or client product in practice, the methods illustrated in the embodiments or figures may be performed sequentially or in parallel (e.g., in a parallel processor or multi-threaded processing environment, or even in a distributed data processing environment). The terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, it is not excluded that additional identical or equivalent elements may be present in a process, method, article, or apparatus that comprises a described element. The terms first, second, etc. are used to denote a name, but not any particular order.

Those skilled in the art will also appreciate that, in addition to implementing the controller in a pure computer readable program code, it is well possible to implement the same functionality by logically programming the method steps such that the controller is in the form of logic gates, switches, application specific integrated circuits, programmable logic controllers, embedded microcontrollers, etc. Such a controller can be regarded as a hardware component, and means for implementing various functions included therein can also be regarded as a structure within the hardware component. Or even means for achieving the various functions may be regarded as either software modules implementing the methods or structures within hardware components.

The description may be described in the general context of computer-executable instructions, such as program modules, being executed by a computer. Generally, program modules include routines, programs, objects, components, data structures, classes, etc. that perform particular tasks or implement particular abstract data types. The specification may also be practiced in distributed computing environments where tasks are performed by remote processing devices that are linked through a communications network. In a distributed computing environment, program modules may be located in both local and remote computer storage media including memory storage devices.

From the above description of embodiments, it will be apparent to those skilled in the art that the present description may be implemented in software plus a necessary general hardware platform. Based on such understanding, the technical solutions of the present specification may be embodied essentially in the form of a software product, which may be stored in a storage medium, such as a ROM/RAM, a magnetic disk, an optical disk, etc., and include several instructions to cause a computer device (which may be a personal computer, a mobile terminal, a server, or a network device, etc.) to perform the methods described in the various embodiments or portions of the embodiments of the present specification.

Various embodiments in this specification are described in a progressive manner, and identical or similar parts are all provided for each embodiment, each embodiment focusing on differences from other embodiments. The specification is operational with numerous general purpose or special purpose computer system environments or configurations. For example: personal computers, server computers, hand-held or portable devices, tablet devices, multiprocessor systems, microprocessor-based systems, set top boxes, programmable electronic devices, network PCs, minicomputers, mainframe computers, distributed computing environments that include any of the above systems or devices, and the like.

Although the present specification has been described by way of example, it will be appreciated by those skilled in the art that there are many variations and modifications to the specification without departing from the spirit of the specification, and it is intended that the appended claims encompass such variations and modifications as do not depart from the spirit of the specification.

Claims

1. An energy storage system is characterized by at least comprising a power supply module and an inverter module;

the topological structure of the inverter module comprises a plurality of bridge arm structures which are respectively connected with the alternating current filter circuit; the alternating current filter circuit is connected with a power grid;

the topological structure of the inverter module also comprises a first relay and a second relay; the first relay and the second relay are connected between the direct current positive bus and the direct current negative bus in series; the first relay is used for controlling the first resistor access circuit; the second relay is used for controlling a second resistor access circuit; an intermediate node between the second relay and the first resistor is connected with a target wire;

The energy storage system is used for: detecting whether the inverter module exits the standby state; detecting whether the first relay and the second relay are both in an off state under the condition that the inverter module is determined to exit the standby state; under the condition that the first relay and the second relay are not in the disconnection state, determining a first target relay meeting the requirements from the first relay and the second relay; the first target relay is controlled to be in a closed state, so that the first capacitor and the second capacitor are charged and discharged through the target lead by utilizing the power supply module; the first target relay is a relay in an off state in the first relay and the second relay; detecting whether the time delay generated from closing to actual working of the first target relay is greater than or equal to a first time preset value or not; and under the condition that the time delay generated from closing to actual working of the first target relay is larger than or equal to a first time preset value, controlling the inverter module to generate different state levels based on a pulse width modulation technology.

2. The energy storage system of claim 1, wherein the inverter module comprises a clamp three-level inverter; correspondingly, the topological structure of the inverter module comprises three bridge arm structures.

3. The energy storage system of claim 1, wherein the topology of the inverter module further comprises a first capacitor and a second capacitor; the first capacitor and the second capacitor are connected between the direct current positive bus and the direct current negative bus in series; an intermediate junction between the first capacitor and the second capacitor is connected to a target conductor.

4. The neutral point potential balance control method is characterized by being applied to an energy storage system and comprising the following steps of:

detecting whether the time delay generated from closing to actual working of the first target relay is greater than or equal to a first time preset value or not; under the condition that the time delay generated from closing to actual working of the first target relay is larger than or equal to a first time preset value, controlling the inverter module to generate different-state levels based on a pulse width modulation technology;

the energy storage system at least comprises a power supply module and an inverter module; the power supply module comprises a plurality of parallel battery clusters; the topological structure of the inverter module comprises a plurality of bridge arm structures; intermediate nodes in the battery cluster are connected through target wires; the target wires are respectively connected with intermediate nodes of a plurality of bridge arm structures in the topological structure of the inverter module; the topological structure of the inverter module comprises a plurality of bridge arm structures which are respectively connected with the alternating current filter circuit; the alternating current filter circuit is connected with a power grid; the topological structure of the inverter module also comprises a first relay and a second relay; the first relay and the second relay are connected between the direct current positive bus and the direct current negative bus in series; the first relay is used for controlling the first resistor access circuit; the second relay is used for controlling a second resistor access circuit; an intermediate junction between the second relay and the first resistor is connected to a target conductor.

5. The method according to claim 4, wherein the method further comprises:

in the event that it is determined that both the first relay and the second relay are in an off state, the inverter module is controlled to generate different state levels based on a pulse width modulation technique.

6. The method of claim 4, wherein detecting whether the inverter module enters a standby state comprises:

7. The method according to claim 4, wherein the method further comprises:

detecting whether the duration of the standby state is greater than or equal to a second time preset value under the condition that the inverter module is not out of the standby state;

8. A neutral point potential balance control device, comprising:

the fifth control module is used for detecting whether the time delay generated from closing to actual working of the first target relay is greater than or equal to a first time preset value; under the condition that the time delay generated from closing to actual working of the first target relay is larger than or equal to a first time preset value, controlling the inverter module to generate different-state levels based on a pulse width modulation technology;

9. A computer storage medium having stored thereon computer instructions which, when executed, implement the steps of the method of any of claims 4 to 7.