CN115763380A - Manufacturing method of semiconductor device and semiconductor device - Google Patents

Abstract

The invention provides a manufacturing method of a semiconductor device and the semiconductor device. The manufacturing method comprises the steps of processing a fin structure on a substrate layer, processing an oxide layer surrounding the fin structure outside the fin structure to enable the fin structure to extend out of the surface of the oxide layer, processing pseudo polysilicon gates between the surface of the oxide layer and the fin structure, and forming an interlayer dielectric layer on the surface of the oxide layer between the adjacent pseudo polysilicon gates; removing the pseudo polysilicon gate until the oxide layer is exposed; implanting ion dopant into the oxide layer to etch the oxide layer down to a certain depth; and depositing the surface of the oxide layer after etching to form the metal gate. The manufacturing method processes the fin structure after removing the pseudo polysilicon gate, and can be used for manufacturing semiconductor devices, especially fin field effect transistors.

Description

Manufacturing method of semiconductor device and semiconductor device

Technical Field

The invention relates to the technical field of semiconductors, in particular to a manufacturing method of a semiconductor device and the semiconductor device.

Background

In an actual chip, there is a case where a plurality of semiconductor elements are densely arranged, for example: transistors, diodes, resistors, capacitors, etc., as the size of semiconductor devices continues to decrease, the integration of electronic components continues to increase, making it possible for more semiconductor devices to be integrated in a given area.

As the size of semiconductor devices decreases, more leakage current is caused, which affects the normal use of the components, and thus, it is required to reduce the leakage current.

The fin-shaped structure of the fin field effect transistor increases the control area of the gate to the channel, so that the gate control capability is greatly enhanced, the short channel effect can be effectively inhibited, and the sub-threshold leakage current is reduced. Due to the suppression of the short channel effect and the enhancement of the grid control capability, the fin field effect transistor can use thicker grid oxide than the traditional fin field effect transistor, so that the grid leakage current of the fin field effect transistor is reduced.

In addition, for the fin field effect transistor, fin heights of different types of transistor devices are distinguished, so that a process window of leakage current can be increased, and the leakage current is further reduced.

The patent TWI584478B, semiconductor and method of manufacturing the same, discloses a semiconductor device. The semiconductor device is a fin field effect transistor including a first fin and a second fin. The first fin is surrounded by the first isolation region and has a first height relative to the upper surface of the first isolation region, the second fin is surrounded by the second isolation region and has a second height relative to the upper surface of the second isolation region, and the upper surfaces of the first isolation region and the second isolation region are different levels.

The above patent discloses a method for manufacturing a semiconductor device, which comprises implanting ions into a first isolation region, etching a first fin, implanting ions into a second isolation region, etching a second fin, and forming the first fin and the second fin having different heights by changing the etching rate according to the difference of the ion dopants implanted into the isolation region. After the fin etching is finished, the dummy gate dielectric layer is processed and the dummy gate is etched.

The above patent processes the fin layer prior to the dummy polysilicon gate deposition of the semiconductor device and has the following disadvantages:

the fin layer processing step is before the chemical mechanical polishing step of the interlayer dielectric layer, so that the chemical mechanical polishing process window is enlarged, and the stability and controllability of the chemical mechanical polishing process are influenced;

the fin layer processing step precedes the transistor epitaxy (source and drain epitaxy) processing, resulting in a difficult to control epitaxial layer processing uniformity.

Disclosure of Invention

The present invention is directed to a method for fabricating a semiconductor device and a semiconductor device, and more particularly to a method for fabricating different fin heights in a fin field effect transistor, and a semiconductor device using the fin height field effect transistor.

In order to achieve the above object, some embodiments of the present invention provide the following technical solutions:

the manufacturing method of the semiconductor device comprises the following steps:

processing a first fin type field effect transistor structure, wherein the first fin type field effect transistor structure comprises a plurality of first fin structures on a substrate layer, a first oxide layer surrounding the first fin structures is processed outside the first fin structures, the first fin structures extend out of the surface of the first oxide layer, pseudo polycrystalline silicon gates are processed between the surface of the first oxide layer and the surface of the first fin structures, and a first interlayer dielectric layer is formed on the surface of the first oxide layer and between the adjacent pseudo polycrystalline silicon gates;

removing the pseudo polysilicon gate until the first oxide layer is exposed;

implanting a first ion dopant into the first oxide layer;

etching the first oxide layer down to a first depth;

and depositing and forming a first metal gate on the surface of the first oxide layer corresponding to the first depth.

In some embodiments of the invention, the synchronizing further comprises the steps of:

processing a second fin field effect transistor structure on the same substrate layer of the first fin field effect transistor structure, wherein the second fin field effect transistor structure is a semiconductor element different from the first fin field effect transistor structure and comprises a plurality of second fin structures on the substrate layer, a second oxide layer surrounding the second fin structures is processed outside the second fin structures, the second fin structures extend out of the surface of the second oxide layer, pseudo polycrystalline silicon gates are processed between the surface of the second oxide layer and the second fin structures, and a second interlayer dielectric layer is formed on the surface of the second oxide layer between the adjacent pseudo polycrystalline silicon gates;

removing the pseudo polysilicon gate until the second oxide layer is exposed;

implanting a second ion dopant into the second oxide layer, the second ion dopant being different from the first ion dopant;

etching the second oxide layer down to a second depth;

and depositing and forming a second metal gate on the surface of the second oxide layer corresponding to the second depth.

In some embodiments of the present invention, the etching of the first oxide layer and the etching of the second oxide layer are performed simultaneously.

In some embodiments of the present invention, the method further comprises the steps of:

when a first ion dopant is injected into the first oxide layer, the exposed area of the second oxide layer is shielded by the photoresist layer;

after the first ion dopant injection is finished, removing the light resistance layer;

shielding an exposed area of the first oxide layer with a photoresist layer while implanting a second ion dopant into the second oxide layer;

and removing the photoresist layer after the second ion dopant injection is finished.

In some embodiments of the invention, the first depth and the second depth are at least 2nm.

In some embodiments of the invention, the difference in height between the first depth and the second depth is at least 2nm.

In some embodiments of the present invention, the method further comprises the steps of:

the epitaxial regions of the first and second fin structures are processed before the first and second oxide layer etches are performed.

In some embodiments of the present invention, the method further comprises the steps of:

before removing the pseudo polysilicon gate, carrying out chemical mechanical grinding treatment on the surfaces of the first interlayer dielectric layer and the second interlayer dielectric layer and the surface of the pseudo polysilicon gate, so that the top surface of the first interlayer dielectric layer is flush with the top surface of the pseudo polysilicon gate, and the top surface of the second interlayer dielectric layer is flush with the top surface of the pseudo polysilicon gate.

In some embodiments of the present invention, the method further comprises the steps of:

and carrying out chemical mechanical polishing treatment on the first interlayer dielectric layer, the first metal grid electrode, the second interlayer dielectric layer and the second metal grid electrode to enable the top surface of the first metal grid electrode to be flush with the top surface of the first interlayer dielectric layer and the top surface of the second metal grid electrode to be flush with the top surface of the second interlayer dielectric layer.

Some embodiments of the invention further provide a fin field effect transistor manufactured by the above method.

Compared with the prior art, the technical scheme of the invention has the beneficial effects that:

1. after the pseudo-polysilicon gate is removed (pseudo-polysilicon gate chemical mechanical polishing), the fin structure is etched, so that a chemical mechanical polishing process window can be controlled, and the stability and controllability of a chemical mechanical polishing process are ensured.

2. The fin layer processing step is that after the transistor epitaxy (source epitaxy and drain epitaxy) is processed, the fin height is the same before the epitaxy is formed, the problem that the epitaxy is difficult to control due to different fin heights can be solved, and the controllability of the processing uniformity of the epitaxy layer is improved.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise.

FIG. 1a is a first view structural diagram of a FinFET;

FIG. 1b is a second view structural diagram of a FinFET;

FIG. 1c is a third view structural diagram of a FinFET;

FIG. 2a is a flow chart of a manufacturing method according to a first embodiment;

FIG. 2b is a schematic diagram of a first FinFET structure with a dummy polysilicon gate;

FIG. 2c is a schematic view of the first FinFET structure with the dummy polysilicon gate removed;

FIG. 2d is a schematic view of a structure of implanting a first ion dopant into a first oxide layer;

FIG. 2e is a schematic diagram of etching a first depth structure;

FIG. 2f is a schematic diagram of the first FinFET structure after processing the first metal gate;

FIG. 3a is a flowchart of a manufacturing method according to a second embodiment;

FIG. 3b is a schematic diagram of a first FinFET structure and a second FinFET structure with dummy polysilicon gates fabricated on the same substrate;

FIG. 3c is a schematic diagram of removing a dummy polysilicon gate structure of the first FinFET structure and the second FinFET structure;

FIG. 3d is a schematic view of a structure for implanting a first ion dopant into a first oxide layer;

FIG. 3e is a schematic view illustrating a structure of implanting a second ion dopant into a second oxide layer;

FIG. 3f is a schematic view of the semiconductor structure after etching to the first depth and the second depth;

fig. 3g is a schematic structural diagram of the semiconductor device after the first metal gate and the second metal gate are processed.

In the above figures:

1-a substrate layer;

2-a metal gate;

3-pseudo polysilicon gate;

4-an interlayer dielectric layer;

5-an oxide layer;

601-a first fin structure, 602-a second fin structure;

701-a first oxide layer, 702-a second oxide layer;

801-a first interlayer dielectric layer, 802-a second interlayer dielectric layer;

901-a first metal gate, 902-a second metal gate;

1001-first depth, 1002-second depth;

11-a photoresist layer;

12-fin structure;

1301-a first ion dopant, 1302-a second ion dopant.

Detailed Description

In order to make the technical problems, technical solutions and advantageous effects to be solved by the present invention more clearly apparent, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

Referring to fig. 1a, 1b and 1c, a structure of a finfet in the prior art is shown.

The finfet comprises a substrate layer 1, which may be a silicon substrate, or other elemental semiconductor such as germanium, or a compound semiconductor such as silicon carbide or gallium arsenide, for example, for the substrate layer 1.

The fin field effect transistor further comprises a plurality of fin structures 12 which are arranged above the substrate layer 1 at intervals and are formed by photoetching or etching to be used as a source electrode and a drain electrode of the transistor. Wherein, the etching process can adopt dry etching or wet etching.

An oxide layer 5 is provided around the fin structure, as an insulating structure, the height of the fin structure extending above the upper surface of the oxide layer 5, i.e. the height of the top of the fin structure is higher than the height of the surface of the oxide layer 5.

The fin field effect transistor further includes a gate structure disposed over a middle portion of the fin structure. There will be a metal gate 2 and a dummy polysilicon gate 3, depending on the process steps. Before the metal gate 2 is processed, a gate structure is usually constructed by using a dummy polysilicon gate 3 as an auxiliary structure, an interlayer dielectric layer 4 is filled between the dummy polysilicon gates 3, and after the dummy polysilicon gates 3 are removed, gate replacement is performed to process the metal gate 2. The metal gate 2 connects the two fin structures of the same transistor and is deposited using a high-k dielectric, for example, the metal gate may be made of TiN, taN, niSi, coSi, mo, cu, W, al, co, and/or other suitable conductive materials. After removing the dummy polysilicon gate 3, an interlayer dielectric layer 4 is filled between the metal gates 2.

The first embodiment of the invention provides a manufacturing method of a semiconductor device, in particular to a manufacturing method of fin height of a fin field effect transistor.

A first embodiment of the present invention first provides a processing method for a single semiconductor device, and the method is implemented with reference to fig. 2a as a flowchart of the manufacturing method of the first embodiment, and fig. 2b to 2f as schematic diagrams of steps of the manufacturing method of the semiconductor device provided by the first embodiment.

First, the present invention will be described by taking the structure of an NMOS transistor as an example.

Referring first to fig. 2b, before the fin structure height is processed, a first fin field effect transistor structure (illustrated as an NMOS transistor in the drawing) is first processed, including a plurality of first fin structures 601 on the substrate layer 1, and two first fin structures 601 are shown, corresponding to a source region and a drain region of the NMOS transistor, respectively.

The first oxide layer 701 surrounding the first fin structure 601 is processed outside the first fin structure such that the first fin structure 601 protrudes out of the surface of the first oxide layer 701, i.e. the height of the first fin structure 601 is higher than the height of the surface of the first oxide layer 701. The first oxide layer 701 may be made of a dielectric material such as silicon oxide, high Density Plasma (HDP) oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass, a low-k dielectric material, and/or other suitable insulating materials.

Processing a dummy polysilicon gate 3 on the surface of the first oxide layer 701 and between the adjacent first fin structures 601; a first interlayer dielectric layer 801 is formed on the surface of the first oxide layer 701 between the adjacent dummy polysilicon gates 3. The first interlayer dielectric layer 801 may be made of silicon nitride and/or silicon oxynitride, and may be formed by a chemical vapor deposition process.

With further reference to fig. 2c, the dummy polysilicon gate 3 is removed until the upper surface of the first oxide layer 701 is exposed.

Referring to fig. 2d, a first ion dopant 1301 is implanted into the first oxide layer 701, and the ion dopant may be selected according to the type of the semiconductor device. Taking an NMOS transistor as an example, a P-type implant is performed to implant P-type dopants in the first oxide layer 701, wherein the P-type dopants include boron, aluminum, gallium, and indium, and the implant dose is less than or equal to 1013cm "2.

Referring to fig. 2e, after the first ion dopant implantation is completed, the first oxide layer 701 is etched down to a first depth 1001 at an etch rate of 35A/min to 53A/min.

The range indicated by the arrow in fig. 2e refers to the height of the first fin structure 601 formed after the first etch depth 1001. Specifically, a mask plate corresponding to a pattern of a region to be etched of the first fin field effect transistor structure is designed, the surface of the first oxide layer 701 is etched downwards through exposure imaging, and the etching depth can be controlled by controlling the etching rate and the etching time by adopting a dry etching or wet etching technology.

The first depth 1001 is formed by etching from the surface of the first oxide layer 701 to a direction close to the substrate layer 1, and is a height difference between the surface of the first oxide layer 701 after etching at the periphery of the first fin structure 601 after etching and the surface of the first oxide layer 701 before non-etching. As shown in the drawing, the first depth 1001 also represents the distance between the surface of the first oxide layer 701 and the bottom surface of the first interlayer dielectric layer 801 after the etching. In some embodiments of the present invention, the first depth 1001 is at least 2nm, and the process size of the first depth 1001 is selected according to the requirements for the performance of the semiconductor device.

Referring to fig. 2f, a first metal gate 901 is deposited on the surface of the first oxide layer 801 corresponding to the first depth 1001. Still further, a gate high dielectric constant dielectric may be fabricated between the first fin structure 601 and the first metal gate 901, using, for example, laO, alO, zrO, tiO, ta2O5, Y2O3, srTiO3, baTiO3, baZrO, hfZrO, hfLaO, hfTaO, hfSiO, hfSiON, hfTiO, laSiO, alSiO, (Ba, sr) TiO3, al2O3, or other suitable high-k dielectric material, combinations thereof, or other suitable materials.

At this point, the processing of the first fin field effect transistor (NMOS transistor) is completed.

The second embodiment of the present invention further provides a method for processing multiple semiconductor devices on the substrate layer, and more particularly, a method for processing fin structures with different heights corresponding to each semiconductor device.

Referring to fig. 3a, which is a flowchart of the manufacturing method of the present embodiment, and referring to fig. 3b to fig. 3g, which are schematic diagrams of implementation of steps of the manufacturing method of the semiconductor device provided in the present embodiment.

Referring to fig. 3b, a second finfet structure is fabricated on the same substrate layer 1 as the first finfet structure, with the two finfet structures spaced apart.

The second finfet structure is a semiconductor device (illustrated as a PMOS transistor in the figures) that is different from the first finfet structure, and includes a plurality of second fin structures 602 on the substrate layer 1, and two second fin structures 602 are shown, corresponding to the source and drain regions of the PMOS transistor.

Before the first oxide layer 701 and the second oxide layer 702 are etched, the epitaxial regions of the first fin structure 601 and the second fin structure 602 are processed. The epitaxial region may be made of the same material as the substrate 1, or the epitaxial region in the source and drain regions of the NMOS transistor may comprise epitaxial silicon or epitaxial silicon carbide, and the source and drain regions of the PMOS transistor may comprise epitaxial silicon germanium or epitaxial germanium.

A second oxide layer 702 surrounding the second fin structure 602 is processed outside the second fin structure 602, so that the second fin structure 602 protrudes out of the surface of the second oxide layer 702, and dummy polysilicon gates 3 are processed between the second fin structure 602 and the surface of the second oxide layer 702, and a second interlayer dielectric layer 802 is formed on the surface of the second oxide layer 702 between adjacent dummy polysilicon gates 3.

In the second finfet structure, the second oxide layer 702 and the second interlayer dielectric layer 802 may be respectively formed with the same or different compositions as the first oxide layer 701 and the first interlayer dielectric layer 801.

Referring to fig. 3c, the dummy polysilicon gates 2 of the first and second finfet structures are etched away until the upper surfaces of the first and second oxide layers 701 and 702 are exposed.

A first ion dopant 1301 is implanted into the first oxide layer 701, for example, an NMOS transistor is P-type implanted, and a P-type dopant is implanted into the first oxide layer 701, wherein the P-type dopant includes boron, aluminum, gallium, and indium, and the implantation dose is less than or equal to 1013cm < -2 >.

A second ion dopant 1302 is implanted into the second oxide layer 702, such as a PMOS transistor, for example, by an N-type implant, wherein the second oxide layer 702 is implanted with an N-type dopant comprising nitrogen, phosphorus, arsenic, and antimony at a dose less than or equal to 1013cm "2.

A mask plate corresponding to the patterns of the to-be-etched areas of the first FinFET structure and the second FinFET structure is designed, and is exposed and imaged, the surface of the first oxide layer 701 is etched downwards to a first depth 1001, and the surface of the second oxide layer 702 is etched downwards to a second depth 1002. The etching rate is 35A/min-53A/min.

The second depth 1002 is formed by etching from the surface of the second oxide layer 702 to a direction close to the substrate layer 1, and is a height difference between the surface of the second oxide layer 702 after etching and the surface of the second oxide layer 702 before non-etching at the periphery of the second fin structure 602 after etching. As shown in the figure, the second depth 1002 also represents the distance between the surface of the unetched second oxide layer 702 and the bottom surface of the first interlayer dielectric layer 801. In some embodiments of the present invention, the second depth 1002 is at least 2nm, and the process size of the second depth 1002 is selected based on the performance requirements of the semiconductor device.

The etching of the first oxide layer 701 and the second oxide layer 702 can be performed simultaneously, and the etching depth can be controlled by controlling the etching rate and the etching time. Since different types of ion dopants are implanted, the first depth 1001 and the second depth 1002 of the etching are different in the same etching speed and etching time, and different fin heights are formed.

Fig. 3d and 3e, in some embodiments of the invention, in order to avoid mis-implanting the first ion dopant 1301 into the second oxide layer 702, the photoresist layer 11 is used to block the exposed region of the second oxide layer 802 during ion implantation of the first oxide layer 701; after the implantation of the first ion dopant 1301 is finished, the photoresist layer 11 is removed.

Similarly, the second ion dopant 1302 is prevented from being implanted into the first oxide layer 701 by mistake, and when the second oxide layer 702 is subjected to ion implantation, the exposed area of the first oxide layer 701 is shielded by using the photoresist layer 11; after the implantation of the second ion dopant 1302 is completed, the photoresist layer 11 is removed.

Further, the second depth 1002 may be the same as the first depth 1001, or different from the first depth 1001. In a preferred embodiment, the second depth 1002 is different from the first depth 1001 by a height difference of at least 2nm. Referring to fig. 3f, the height of the first fin structure 601 and the second fin structure 602, respectively, formed after etching is shown by arrows, and it can be seen that fin structures of different heights are formed.

Referring to fig. 3g, after the fin structure height processing is finished, a first metal gate 901 is deposited on the surface of the first oxide layer 701 corresponding to the first depth 1001, and a second metal gate 902 is deposited on the surface of the second oxide layer 702 corresponding to the second depth 1002. Further, a gate dielectric layer may be processed between the first fin structure 601 and the first metal gate 901, and between the second fin structure 602 and the second metal gate 902, which is the same as the foregoing embodiments and is not described again.

At this point, the processing of the first fin field effect transistor (NMOS transistor) and the second fin field effect transistor (PMOS transistor) having different fin heights is completed.

In some embodiments of the present invention, in the manufacturing method according to the first and second embodiments, before removing the dummy polysilicon gate 3, the dummy polysilicon gate 3 may be planarized by one or more cmp steps. Therefore, the following steps are further included.

For the first finfet structure, the first interlayer dielectric layer 801 and the dummy polysilicon gate 3 are subjected to a chemical mechanical polishing process to planarize the first interlayer dielectric layer 801, thereby improving the planarity of the top surface, and making the top surface of the first interlayer dielectric layer 801 flush with the top surface of the dummy polysilicon gate 3.

For the second finfet structure, the surface of the second interlayer dielectric layer 802 and the surface of the dummy polysilicon gate 3 are subjected to chemical mechanical polishing, so that the second interlayer dielectric layer 802 is planarized, and the top surface planarity is improved. The top surface of the second interlayer dielectric layer 802 is made flush with the top surface of the dummy polysilicon gate 3.

In some embodiments of the present invention, in the manufacturing method according to the first and second embodiments, after the metal gate is processed, the metal gate may be planarized by one or more chemical mechanical polishing steps. The processing method further comprises the following steps:

for the first finfet structure, the surfaces of the first interlayer dielectric layer 801 and the first metal gate 701 are subjected to a chemical mechanical polishing process, so that the top surface of the first interlayer dielectric layer 801 is flush with the top surface of the first metal gate 701.

For the first finfet structure, the second interlayer dielectric 802 and the second metal gate 702 are polished by chemical mechanical polishing, so that the top surface of the second interlayer dielectric 802 is flush with the top surface of the second metal gate 702.

A third embodiment of the present invention provides a semiconductor device that can be manufactured by the semiconductor manufacturing method of the first embodiment. The semiconductor device may be a memory device, an input-output device, or the like. The semiconductor device integrates a multi-fin field effect transistor structure, wherein the fin field effect transistors comprise transistors, diodes, resistors, capacitors and the like, and the fin structures of different fin field effect transistors are different in height.

The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the present invention, it should be noted that any modifications, equivalents and improvements made by those skilled in the art within the spirit and principle of the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present patent application shall be subject to the protection scope of the appended claims.

Claims (10)

1. The manufacturing method of the semiconductor device is characterized by comprising the following steps:

processing a first fin type field effect transistor structure, wherein the first fin type field effect transistor structure comprises a plurality of first fin structures on a substrate layer, a first oxide layer surrounding the first fin structures is processed outside the first fin structures, the first fin structures extend out of the surface of the first oxide layer, pseudo polycrystalline silicon gates are processed between the surface of the first oxide layer and the surface of the first fin structures, and a first interlayer dielectric layer is formed on the surface of the first oxide layer and between the adjacent pseudo polycrystalline silicon gates;

removing the pseudo polysilicon gate until the first oxide layer is exposed;

implanting a first ion dopant into the first oxide layer;

etching the first oxide layer down to a first depth;

and depositing and forming a first metal gate on the surface of the first oxide layer corresponding to the first depth.

2. The method of manufacturing a semiconductor device according to claim 1, further comprising the steps of:

processing a second fin field effect transistor structure on the same substrate layer of the first fin field effect transistor structure, wherein the second fin field effect transistor structure is a semiconductor element different from the first fin field effect transistor structure and comprises a plurality of second fin structures on the substrate layer, a second oxide layer surrounding the second fin structures is processed outside the second fin structures, the second fin structures extend out of the surface of the second oxide layer, pseudo polycrystalline silicon gates are processed between the surface of the second oxide layer and the second fin structures, and a second interlayer dielectric layer is formed on the surface of the second oxide layer between the adjacent pseudo polycrystalline silicon gates;

removing the pseudo polysilicon gate until the second oxide layer is exposed;

implanting a second ion dopant into the second oxide layer, the second ion dopant being different from the first ion dopant;

etching the second oxide layer down to a second depth;

and depositing and forming a second metal gate on the surface of the second oxide layer corresponding to the second depth.

3. The method for manufacturing a semiconductor device according to claim 2, wherein the etching of the first oxide layer and the etching of the second oxide layer are performed simultaneously.

4. The method of manufacturing a semiconductor device according to claim 2, further comprising the steps of:

shielding an exposed area of the second oxide layer by using a photoresist layer when a first ion dopant is injected into the first oxide layer;

after the first ion dopant injection is finished, removing the light resistance layer;

shielding an exposed area of the first oxide layer with a photoresist layer while implanting a second ion dopant into the second oxide layer;

and removing the photoresist layer after the second ion dopant injection is finished.

5. The method of manufacturing a semiconductor device according to claim 2, wherein the first depth and the second depth are at least 2nm.

6. The method for manufacturing a semiconductor device according to claim 5, wherein a difference in height between the first depth and the second depth is at least 2nm.

7. The method of manufacturing a semiconductor device according to claim 2, further comprising the steps of:

the epitaxial regions of the first and second fin structures are processed before the first and second oxide layer etches are performed.

8. The method of manufacturing a semiconductor device according to claim 2, further comprising the steps of:

before removing the pseudo polysilicon gate, carrying out chemical mechanical grinding treatment on the surfaces of the first interlayer dielectric layer and the second interlayer dielectric layer and the surface of the pseudo polysilicon gate, so that the top surface of the first interlayer dielectric layer is flush with the top surface of the pseudo polysilicon gate, and the top surface of the second interlayer dielectric layer is flush with the top surface of the pseudo polysilicon gate.

9. The method of manufacturing a semiconductor device according to claim 2, further comprising the steps of:

and carrying out chemical mechanical polishing treatment on the first interlayer dielectric layer, the first metal grid electrode, the second interlayer dielectric layer and the second metal grid electrode to enable the top surface of the first metal grid electrode to be flush with the top surface of the first interlayer dielectric layer and the top surface of the second metal grid electrode to be flush with the top surface of the second interlayer dielectric layer.

10. A semiconductor device characterized by being manufactured by the method for manufacturing a semiconductor device according to any one of claims 1 to 9.

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