CN115763368A - Tungsten filling method, semiconductor manufacturing method and semiconductor device - Google Patents
Tungsten filling method, semiconductor manufacturing method and semiconductor device Download PDFInfo
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- CN115763368A CN115763368A CN202211547965.3A CN202211547965A CN115763368A CN 115763368 A CN115763368 A CN 115763368A CN 202211547965 A CN202211547965 A CN 202211547965A CN 115763368 A CN115763368 A CN 115763368A
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Abstract
The invention relates to a tungsten filling method, a semiconductor manufacturing method and a semiconductor device. The tungsten filling method comprises the following steps: growing a silicon layer on the inner wall of the hole; introducing WF into the hole 6 Gas, make it and silicon layer produce the replacement reaction, replace the silicon layer with the tungsten layer; growing a silicon layer on the surface of the generated tungsten layer and introducing WF 6 Gas is used for replacing the next tungsten layer; repeating the steps until the tungsten generated by replacement is filled in the holes. The tungsten filling method can fill metal tungsten in the hole without generating gaps.
Description
Technical Field
The invention belongs to the technical field of semiconductors, and particularly relates to a tungsten filling method, a semiconductor manufacturing method and a semiconductor device.
Background
Three-dimensional (3D) wafer-to-wafer, die-to-wafer, or die-to-die vertical stacking techniques seek to achieve the long-felt goal of vertically stacking multiple layers of active IC devices, such as processors, programmable devices, and memory devices, to shorten average wire lengths, thereby reducing interconnect RC delays and improving system performance.
In the chip packaging process, vertical conduction is made between chips and between wafers through Contact windows (Contact Via), so that the chips are interconnected. The contact window is filled with a conductive material, and usually tungsten is deposited by chemical vapor deposition. For example, an adhesion layer (Ti/TiN) is grown in the contact window, and then tungsten is filled in the adhesion layer.
However, although the deposition coverage of tungsten is good when filling the contact via according to the above prior art, the contact via has a high aspect ratio, and is usually accompanied by a gap (Seam) during the filling process, which causes a series of problems in the manufacturing of electronic devices; furthermore, as the device size is reduced, the formation of gaps is one of the main problems affecting the electrical characteristics of the contact.
Disclosure of Invention
Aiming at least one defect existing in the related art, the invention provides a tungsten filling method, a semiconductor manufacturing method and a semiconductor device.
A first aspect of an embodiment of the present invention provides a method for filling tungsten in a hole, including the following steps:
growing a silicon layer on the inner wall of the hole;
introducing WF into the hole 6 Gas, make WF 6 The gas and the silicon layer generate a replacement reaction to replace the silicon layer with a tungsten layer;
growing a silicon layer on the surface of the generated tungsten layer and introducing WF 6 Gas is used for replacing the next tungsten layer;
repeating the steps until the tungsten generated by replacement is filled in the holes.
In some embodiments of the present invention, after each round of displacement reaction is completed, the surface of the tungsten layer resulting from the displacement is subjected to a plasma treatment.
In some embodiments of the present invention, no adhesion layer is disposed on the inner wall of the hole before the silicon layer is grown.
In some embodiments of the present invention, after the tungsten fills the hole, a process of planarizing the surface of the hole is further included.
A second aspect of embodiments of the present invention provides a method of manufacturing a semiconductor device, including the steps of:
forming one or more semiconductor chip assemblies on a semiconductor substrate;
forming an interlayer dielectric over the semiconductor substrate and the semiconductor chip assembly;
forming a contact window extending into the semiconductor substrate in the interlayer dielectric;
filling the contact window according to the tungsten filling method of any one of the above;
and performing a back thinning process on the semiconductor substrate to expose the contact window on the back of the semiconductor substrate.
In some embodiments of the present invention, in the step of forming the contact window, a patterned hard mask is disposed over the interlayer dielectric, and the contact window is formed by a wet etching or dry etching process.
In some embodiments of the present invention, after the contact filling is completed, the method further comprises the following steps: an inter-metal dielectric is formed over the contact opening and the inter-metal dielectric, and a first conductive element is formed in the inter-metal dielectric, the first conductive element being electrically connected to the semiconductor chip assembly and the contact opening.
In some embodiments of the present invention, after performing the back side thinning process, the method further comprises the following steps: a back dielectric layer is formed on the back surface of the semiconductor substrate, and a second conductive element is formed in the back dielectric layer and electrically connected with the contact window.
A third aspect of embodiments of the present invention provides a semiconductor device manufactured by the method of manufacturing a semiconductor according to any one of the above.
In some embodiments of the present invention, the contact window is filled with tungsten, no gap exists inside the tungsten, and no adhesion layer exists between the tungsten and the inner wall of the contact window.
Compared with the prior art, the invention has the advantages and positive effects that:
(1) In the tungsten filling method provided by at least one embodiment of the present invention, the silicon layer is used as a base, and the tungsten layer is sequentially grown through multiple replacement reactions, so that the hole can be filled with metal tungsten without generating a gap.
(2) According to the tungsten filling method provided by at least one embodiment of the invention, after each round of tungsten layer replacement is completed, plasma treatment is carried out, so that surface impurities can be effectively removed, the purity of a tungsten layer film is improved, the condition that a contact window is sealed is avoided, and the formed tungsten layer is more compact.
(3) According to the semiconductor device provided by at least one embodiment of the invention, the metal tungsten filled in the contact window does not have a gap, so that the electrical property of the semiconductor device can be improved; in addition, the contact window is filled by replacing the stack of silicon layers, thereby eliminating the adhesion layer (Ti/TiN) in the prior art.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the invention without limiting the invention. In the drawings:
FIG. 1 is a flow chart illustrating a semiconductor manufacturing method according to an embodiment of the present invention;
fig. 2 is a schematic flow chart illustrating a tungsten filling method according to an embodiment of the present invention;
FIGS. 3 a-3 f are schematic diagrams of contact holes at various stages during the filling process according to an embodiment of the present invention;
fig. 4 is a schematic cross-sectional view of a semiconductor device after step S2 is completed in accordance with an embodiment of the present invention;
fig. 5 is a schematic cross-sectional view of a semiconductor device after step S3 is completed in accordance with an embodiment of the present invention;
FIG. 6 is a schematic cross-sectional view of a semiconductor device after completing step S4 in accordance with a semiconductor manufacturing method provided by an embodiment of the present invention;
fig. 7 is a schematic cross-sectional view of the semiconductor device after step S7 is completed in the semiconductor manufacturing method according to the embodiment of the present invention.
In the figure:
100. a semiconductor substrate; 101. an interlayer dielectric; 102. a contact window; 103. an inter-metal dielectric; 104. a conductive pad; 105. a back dielectric layer; 200. a semiconductor chip assembly.
Detailed Description
The technical solutions in the embodiments will be clearly and completely described below with reference to the drawings in the embodiments of the present invention. It is to be understood that the described embodiments are merely some embodiments of the invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present invention without making any creative effort, shall fall within the protection scope of the present invention.
It is obvious that the drawings in the following description are only examples or embodiments of the present application, and that it is also possible for a person skilled in the art to apply the present application to other similar contexts on the basis of these drawings without inventive effort. Moreover, it should be appreciated that in the development of any such actual implementation, as in any engineering or design project, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which may vary from one implementation to another.
Reference in the specification to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the specification. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is to be expressly and implicitly understood by one of ordinary skill in the art that the embodiments described herein may be combined with other embodiments without conflict.
It is appreciated that although the figures may show a specific order of method steps, the order of the steps may differ from the order depicted. Further, two or more steps may be performed simultaneously or partially simultaneously. Such variations will depend on the software and hardware chosen and on designer choice. All such variations are within the scope of the present disclosure.
Unless otherwise defined, technical or scientific terms referred to herein should have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The use of the terms "a" and "an" and "the" and similar referents in the context of describing the invention (including a single reference) are to be construed in a non-limiting sense as indicating either the singular or the plural. The present application is directed to the use of the terms "including," "comprising," "having," and any variations thereof, which are intended to cover non-exclusive inclusions; for example, a process, method, system, article, or apparatus that comprises a list of steps or modules (elements) is not limited to only those steps or elements but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus. Reference to "connected," "coupled," and the like in this application is not intended to be limited to physical or mechanical connections, but rather can include electrical connections, whether direct or indirect. The term "plurality" as referred to herein means two or more. "and/or" describes an association relationship of associated objects, meaning that three relationships may exist, for example, "A and/or B" may mean: a exists alone, A and B exist simultaneously, and B exists alone. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship. Reference herein to the terms "first," "second," etc. merely distinguish similar objects and do not denote a particular order or importance to the objects.
The term "aspect ratio" as used herein refers to the ratio of the height to the width of a contact. The term "contact" refers to an opening in a semiconductor device for filling with a conductive material, the opening passing through at least a portion of a semiconductor substrate. Elements not specifically shown or described in this application may take many forms known to those skilled in the art. Also, when a layer is referred to as being "on" another layer or on a substrate, it can be directly on the other layer or on the substrate, or intervening layers may also be present.
Embodiments of the present application provide a method for manufacturing a semiconductor, which includes a method for filling tungsten, which is provided in the embodiments of the present application. The semiconductor manufacturing method provided by the present application will be described in detail with reference to the following embodiments, wherein the tungsten filling method will be described in detail in the corresponding method steps by taking the semiconductor contact as an example.
As shown in fig. 1, a method for manufacturing a semiconductor according to an embodiment of the present application includes the following steps:
s1: forming one or more semiconductor chip assemblies on a semiconductor substrate;
s2: forming an interlayer dielectric over the semiconductor substrate and the semiconductor chip assembly;
s3: forming a contact window extending into the semiconductor substrate in the interlayer dielectric;
s4: filling metal tungsten in the contact window;
s6: and performing a back thinning process on the semiconductor substrate to expose the contact window on the back of the semiconductor substrate.
Each step in the above manufacturing method will be described in detail below with reference to the drawings.
In the embodiment of the present application, the semiconductor structure is formed by a wafer. Specifically, step S1 forms a semiconductor substrate 100 in a wafer, and forms one or more semiconductor chip assemblies 200 in and/or on the semiconductor substrate 100.
In some embodiments, the semiconductor substrate 100 is a bulk silicon substrate (bulk substrate), and alternatively, may also be a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. The semiconductor substrate has a front surface and a back surface, and the chip assembly 200 is formed on the front surface side of the semiconductor substrate 100.
In some embodiments, the semiconductor chip assembly 200 may include a plurality of individual circuit elements, such as transistors (e.g., MOS), diodes, resistors, capacitors, and/or other active or passive semiconductor devices formed by a variety of integrated circuit fabrication processes. As to a specific method of forming the semiconductor chip assembly 200, which is not described in detail in the present application, reference may be made to any prior art method capable of forming the semiconductor chip assembly 200.
Step S2 forms an interlayer dielectric 101 over the semiconductor substrate 100 and the semiconductor chip assembly 200. For example, the interlayer dielectric 101 is formed by deposition. A cross-sectional view of the semiconductor device formed after step S2 is shown in fig. 4. In some embodiments, the interlayer dielectric (ILD) 101 may be an oxygen-containing dielectric material, which may be, for example, tetraethylorthosilicate (TEOS) oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), or the like. In some embodiments, the interlayer dielectric 101 may be formed by, for example, FCVD, spin-coating, CVD, or another deposition method.
Next, in step S3, a contact window 102 extending into the semiconductor substrate 100 is formed in the interlayer dielectric 101. A cross-sectional view of the semiconductor device formed after step S3 is shown in fig. 5. The contact 102 has a high aspect ratio, for example, an aspect ratio of 5 to 10. In some embodiments, a patterned hard mask is disposed over the interlayer dielectric 101, and a contact window extending from the interlayer dielectric 101 into the semiconductor substrate 100 is formed by a wet etching or dry etching process. The dry etching method utilizes plasma gas to bombard the surface of a material to achieve an etching effect, and has the characteristics of high etching rate, good directionality, capability of manufacturing holes with large depth-width ratio, strong etching rate controllability and the like, so that the dry etching method is the most commonly used method at present. The contact window 102 extends from the surface of the interlayer dielectric 101 to at least a portion of the semiconductor substrate 100. In some embodiments, the etching process includes a deep reactive ion etching process to etch a portion of the semiconductor substrate 100.
In step S4, the contact 102 is filled with a conductive material, typically a metal material, and therefore this step is also referred to as metallization of the contact 102. In the embodiments provided in the present application, the contact window 102 is mainly filled with metal tungsten, and the contact window 102 is filled with the tungsten filling method provided in the present application. In the following description, the contact window 102 will be used as a specific form of the hole in the tungsten filling method, and the tungsten filling method will be described in detail with the aid of the contact window 102. The method for filling tungsten provided in the embodiment of the present application (in the present embodiment, i.e., the method for filling the contact window) includes, as shown in fig. 2, the following steps:
s401: growing a silicon layer on the inner wall of the contact window 102;
s402: introducing WF into the contact window 102 6 Gas, make WF 6 The gas and the silicon layer on the inner wall of the contact window 102 generate a replacement reaction to replace the silicon layer with a tungsten layer;
s403: growing a silicon layer on the surface of the generated tungsten layer and introducing WF 6 Gas is used for replacing the next tungsten layer;
s404: the above step S403 is repeated until the contact 102 is filled with the tungsten generated by the replacement.
Hereinafter, the filling method of tungsten provided in the above embodiment will be described in detail with reference to fig. 3a to 3 f. The schematic diagram of the initial stage of the filling process is shown in fig. 3 a.
In step S401, the silicon layer may be grown by any suitable method, for example, in some embodiments, an ultra high vacuum chemical vapor deposition (UHV-CVD) method, an MEB method, or the like is used as a growth method. For example, silane (SiH) 4 ) Or Tetraethoxysilane (TEOS) to form a silicon layer. As shown in fig. 3b, after step S401, a silicon layer is grown on the inner wall of the contact 102.
In step S402, WF is applied to the contact window 102 6 Gas, WF 6 The gas enters the contact hole 102 and performs a displacement reaction with the silicon layer grown on the inner wall of the contact hole 102, the chemical formula of the displacement reaction is 2W 6 +3Si→2W+3SiF 4 . After the replacement reaction, the tungsten layer replaces the original silicon layer, and the generated SiF is replaced 4 The colorless gas escapes through the opening at the top of the contact 102. Thus, the contact hole 102 is filled with a thin film of metal tungsten layer, as shown in FIG. 3 c.
In step S403, a silicon layer is grown on the surface of the generated tungsten layer and WF is introduced 6 Gas is used for replacing the next tungsten layer; after the replacement of the round is finishedAnd growing a second tungsten layer on the surface of the first tungsten layer.
In step S404, the above step S403 is repeated until the tungsten generated by the replacement fills the contact 102, as shown in fig. 3 e.
In some embodiments, after step S402 and step S403, that is, as shown in fig. 3d, after each round of replacement reaction is completed, step S405 of performing plasma treatment on the surface of the tungsten layer generated by replacement is further included. In the plasma treatment process, the tungsten layer generated after the replacement is impacted by the high-energy ion flow, so that surface impurities can be effectively removed, the purity of the tungsten layer is improved, and the condition that the contact window 102 is sealed in the metallization process can be avoided. In addition, the tungsten layer after plasma treatment is more compact and compact. In some embodiments, the plasma gas employed during plasma processing is H 2 Or N 2 And the like.
In the above example, after the first displacement reaction is completed, plasma treatment (optional) is performed, and then a silicon layer is grown on the first tungsten layer, followed by introducing WF 6 And (3) performing a displacement reaction on the tungsten layer and the silicon layer by using gas to generate a second tungsten layer, performing plasma treatment (optional) on the second tungsten layer, and then circularly performing the third layer and the fourth layer 8230, 8230and the growth of the tungsten layer until the contact window 102 is filled with tungsten.
The filling method of the contact window 102 provided in the above embodiment adopts a displacement reaction to sequentially perform the growth of the tungsten layer thin film, and adopts a plasma treatment to perform a post-treatment on the newly grown thin film after the thin film growth, so that the tungsten layer can be sequentially grown without a gap, the problem of a void generated by the conventional process is avoided, and the grown tungsten layer has high purity and good compactness.
In addition, compared with the conventional process, the contact 102 is filled by silicon layer growth, so that no gap is generated, and no adhesion problem occurs by stacking tungsten layers in the subsequent process flow, therefore, no adhesion layer (Ti/TiN) is required in the filling method provided by the present application.
It is understood that the filling method provided above in the present application can be applied to any scenario requiring filling metal tungsten, and is not limited to contact windows.
In some embodiments, after the tungsten fills the contact window, step S406 is further included to perform a planarization process on the surface of the contact window 102, so that the silicon layer deposited at the opening of the contact window 102 is removed, so that the metalized contact window 102 has a surface that is flush with the periphery of the opening, and the contact window after the planarization process is shown in fig. 3 f. In some embodiments, the planarization process may be performed by conventional methods such as etching, chemical Mechanical Polishing (CMP), and the like.
Through the above steps, the metallization of the contact window 102 in the semiconductor device is completed. Next, a back end of line (BEOL) process is performed on the semiconductor device for interconnection.
Step S5, forming an inter-metal dielectric 103 (see fig. 7) over the metallized contact windows 102 and the inter-metal dielectric 101, and forming a first conductive element in the inter-metal dielectric 103, the first conductive element being electrically connected to the semiconductor chip assembly 200 and the contact windows 102. The first conductive element may be provided in more than two. In some embodiments, the inter-metal dielectric 103 may be a dielectric layer comprising multiple layers of dielectric materials, one or more of which may be made of a low dielectric constant material, such as SiO 2 And so on. In some embodiments, the conductive elements include conductive lines (not shown) and conductive pads 104, and the conductive pads 104 in the inter-metal dielectric 103 are connected to the semiconductor chip assembly 200 and the contact windows 102 by the conductive lines. The conductive pads 104 may be made of, for example, copper or a copper alloy.
In step S6, a back thinning process is performed on the semiconductor substrate 100 to expose the metal tungsten in the contact window 102 on the back surface of the semiconductor substrate 100. In the thinning process, the surface of the wafer is bonded to a carrier because the wafer is thinner, the back surface of the wafer is thinned, and the tungsten metal in the contact window 102 is exposed on the back surface of the wafer after thinning. The thinning process may employ existing techniques such as grinding.
In step S7, after the thinning process is performed, a back dielectric layer 105 (see fig. 7) is formed on the back surface of the semiconductor substrate 100, and a second conductive element is formed in the back dielectric layer 105. The second conductive element may include a conductive line and a conductive pad 104, and the conductive pad 104 in the backside dielectric layer 105 is electrically connected to the contact window 102 through the conductive line (not shown).
The two or more semiconductor devices formed by the above method are bonded together at the positions of the conductive pads to form a three-dimensional chip structure. Bonding methods include oxide-oxide bonding, oxide-silicon bonding, copper-copper bonding, copper-solder bonding, adhesive bonding, or combinations thereof.
Another aspect of the embodiments of the present application provides a semiconductor device manufactured by the above semiconductor manufacturing method. In the structure of the semiconductor device, the contact 102 is filled with tungsten metal, and there is no adhesion layer between the tungsten and the inner wall of the contact 102, which is usually a Ti or TiN layer in the prior art. That is, in some embodiments, there is no Ti layer or TiN layer between the tungsten and the inner wall of the contact 102.
Finally, it should be noted that: the embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.
The above examples are only intended to illustrate the technical solution of the present invention and not to limit it; although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art will understand that: modifications of the embodiments of the invention or equivalent substitutions for parts of the technical features are possible; without departing from the spirit of the present invention, it is intended to cover all aspects of the invention as defined by the appended claims.
Claims (10)
1. A tungsten filling method is used for filling tungsten in a hole, and is characterized by comprising the following steps:
growing a silicon layer on the inner wall of the hole;
introducing WF into the hole 6 Gas, make WF 6 The gas and the silicon layer generate a replacement reaction to replace the silicon layer with a tungsten layer;
growing a silicon layer on the surface of the generated tungsten layer and introducing WF 6 Gas is used for replacing the next tungsten layer;
and repeating the steps until the holes are filled with the tungsten generated by replacement.
2. The tungsten filling method according to claim 1, wherein after completion of each round of the replacement reaction, a surface of the tungsten layer produced by the replacement is subjected to plasma treatment.
3. The method of claim 1, wherein no adhesion layer is disposed on the inner wall of the hole before the silicon layer is grown.
4. The method as claimed in claim 1, further comprising a process of planarizing a surface of the hole after the hole is filled with tungsten.
5. A method of manufacturing a semiconductor device, comprising the steps of:
forming one or more semiconductor chip assemblies on a semiconductor substrate;
forming an interlayer dielectric over the semiconductor substrate and the semiconductor chip assembly;
forming a contact window extending into the semiconductor substrate in the interlayer dielectric;
the method for filling tungsten according to any one of claims 1 to 4, wherein the contact window is filled;
and performing a back thinning process on the semiconductor substrate to expose the contact window on the back of the semiconductor substrate.
6. The method for manufacturing a semiconductor according to claim 5, wherein in the step of forming the contact window, a patterned hard mask is provided over the interlayer dielectric, and the contact window is formed by a wet etching or dry etching process.
7. The method for manufacturing a semiconductor according to claim 5, further comprising the step of, after the filling of the contact hole is completed: forming an inter-metal dielectric over the contact window and the inter-metal dielectric, and forming a first conductive element in the inter-metal dielectric, the first conductive element being electrically connected to the semiconductor chip assembly and the contact window.
8. The method for manufacturing a semiconductor according to claim 5, further comprising, after performing the back surface thinning process, the steps of: and forming a back dielectric layer on the back surface of the semiconductor substrate, and forming a second conductive element in the back dielectric layer, wherein the second conductive element is electrically connected with the contact window.
9. A semiconductor device manufactured by the method for manufacturing a semiconductor according to any one of claims 5 to 8.
10. The semiconductor device according to claim 9, wherein the contact window is filled with tungsten, no gap exists inside the tungsten, and no adhesion layer exists between the tungsten and an inner wall of the contact window.
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