CN115762597A - Read-write mechanism design method for continuous multi-bit error correcting code memory - Google Patents
Read-write mechanism design method for continuous multi-bit error correcting code memory Download PDFInfo
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Abstract
The application relates to a read-write mechanism design method for a continuous multi-bit error correcting code memory. The method comprises the following steps: when the multi-bit error correcting code memory is read, the read data is decoded by the decoder to judge whether an error occurs, if no error occurs, the data is directly output, if an error occurs, the data in the multi-bit error correcting code memory is re-read to carry out error positioning and error correction, in the process of writing, the encoder is designed into a data interleaving arrangement calculation mode to carry out encoding operation on the data to be written, then the data is written into the multi-bit error correcting code memory to be stored, meanwhile, the vertical check code is updated, the read data and the write data before the writing operation are converted into one beat to carry out operation, the reading operation of the data is completed when the clock rises, and the data is written into the storage unit of the multi-bit error correcting code memory at the clock falls after calculation. By adopting the method, the read-write accuracy of the multi-bit error correcting code memory can be improved.
Description
Technical Field
The present application relates to the field of static random access memory technologies, and in particular, to a method, a computer device, and a computer medium for designing a read-write mechanism for a continuous multi-bit error correction code memory.
Background
Static Random-Access Memory (SRAM), which has the advantages of high read/write speed and low power consumption, is widely used as a cache Memory, and occupies an important position in a multi-core microprocessor. Under the process of 40nm or more, the capacity of the on-chip SRAM can reach dozens of megabits, however, the large-capacity SRAM is a weak link sensitive to irradiation, when high-energy particles bombard a storage circuit, charges deposited on a track of the storage circuit are collected by a sensitive node, so that the logic state of the circuit is turned over, and therefore, the reinforcement of the storage is the problem which must be solved firstly to ensure the soft error rate index of a chip.
However, the existing error correcting code memory mainly aims at correcting one bit error, the read-write mechanism of the existing error correcting code memory needs one beat of clock period for reading and writing respectively, if the existing error correcting code memory corrects multiple bit errors, BCH codes are usually adopted, the time sequence and area overhead required in the process is huge, and a method capable of improving the read-write efficiency of the memory needs to be provided
Disclosure of Invention
In view of the foregoing, it is desirable to provide a method, a computer device, and a computer medium for designing a read/write mechanism for a continuous multi-bit error correction code memory, which can improve the read/write efficiency of the memory.
A method for designing a read-write mechanism facing a continuous multi-bit error correcting code memory, the method comprising:
constructing a multi-bit error correcting code memory; the multi-bit error correcting code memory comprises a storage array, a horizontal error correcting code array, a vertical error correcting code array, an encoder and a decoder;
when the multi-bit error correcting code memory is read, the read data is decoded by a decoder to judge whether an error occurs, if no error occurs, the data is directly output, and if an error occurs, the data in the multi-bit error correcting code memory is read again to carry out error positioning and error correction;
in the process of writing operation of the multi-bit error correcting code memory, the encoder is designed in a data interleaving arrangement calculation mode to perform encoding operation on data to be written, write the data into the multi-bit error correcting code memory for storage, and update the vertical check code at the same time;
the read data and the write data before the write operation are converted into one beat for operation, the read operation of the data is completed when the clock rises, and the data is written into the memory cells of the multi-bit error correcting code memory on the falling edge of the clock after calculation.
In one embodiment, when the multi-bit ecc memory performs a read operation, the read data is decoded by a decoder to determine whether an error occurs, if no error occurs, the data is directly output, and if an error occurs, the data in the multi-bit ecc memory is re-read to perform error location and error correction, including:
the address signal is decoded and sends a read request to the multi-bit error correcting code memory when reaching the multi-bit error correcting code memory;
and reading the data of the address corresponding to the address signal by using the multi-bit error correction code memory, reading the horizontal parity check code, and performing error detection on the data stored in the multi-bit error correction code memory according to the horizontal parity check code and the calculation unit of the error correction code.
In one embodiment, whether the read data has errors is judged according to the parity check result, and if the read data has no errors, the data is directly output; if an error occurs, starting error correction operation;
after detecting the occurrence of errors, reading all data and vertical parity check codes in the storage array from the multi-bit error correction code storage;
calculating the stored data one by one with the vertical parity check code to obtain error bits;
and calculating the error distance according to the error bit, and performing the read operation of the multi-bit error correcting code memory according to the calculation result.
In one embodiment, the method for calculating the error distance according to the error bit and performing the reading operation of the multi-bit error correction code memory according to the calculation result comprises the following steps:
calculating the error distance according to the error bit, if the error distance is larger than the interleaving number of the multi-bit error correcting code memory during the write operation, exceeding the error correcting capability range, and retransmitting the stored data;
if the error distance is less than the interleaving number of the multi-bit error correcting code memory during the writing operation, the error is positioned and the error data is overturned to obtain the correct data and output the correct data, thereby completing the reading operation of the multi-bit error correcting code memory.
In one embodiment, during a write operation of the multi-bit ecc memory, the encoder is designed to perform an encoding operation on data to be written in a data interleaving calculation manner, write the encoded data into the multi-bit ecc memory for storage, and update the vertical check code at the same time, including:
in the process of writing operation of the multi-bit error correction code memory, the encoder arranges data, encodes the data in an interleaving mode, and writes the encoded data into the multi-bit error correction code memory for storage, wherein if n bits are corrected, the interleaving number is n.
In one embodiment, the address signal is decoded and a write request is sent to the multi-bit ECC memory at the same time when the address signal reaches the multi-bit ECC memory;
reading original data of an address corresponding to the address signal by using a multi-bit error correcting code memory, and reading a vertical parity check code;
comparing and calculating the vertical parity check code and the data to be written, if the data to be written is consistent with the original data, not returning the vertical parity check code, and if the data to be written is inconsistent with the original data, modifying the vertical parity check code; meanwhile, the data to be written is subjected to the encoding operation of a horizontal error correcting code;
and updating and writing back the vertical parity check code, and writing the encoded data into a storage array of the multi-bit error correction code memory to finish the write operation of the multi-bit error correction code memory once.
A computer device comprising a memory and a processor, the memory storing a computer program, the processor implementing the following steps when executing the computer program:
constructing a multi-bit error correcting code memory; the multi-bit error correction code memory comprises a storage array, a horizontal error correction code array, a vertical error correction code array, an encoder and a decoder;
when the multi-bit error correcting code memory is used for reading, the read data is decoded by a decoder to judge whether an error occurs, if no error occurs, the data is directly output, and if an error occurs, the data in the multi-bit error correcting code memory is read again to carry out error positioning and error correction;
in the process of writing operation of the multi-bit error correcting code memory, the encoder is designed in a data interleaving arrangement calculation mode to perform encoding operation on data to be written, write the data into the multi-bit error correcting code memory for storage, and update the vertical check code at the same time;
the read data and the write data before the write operation are converted into one beat for operation, the read operation of the data is completed when the clock rises, and the data is written into the memory cells of the multi-bit error correcting code memory on the falling edge of the clock after calculation.
A computer-readable storage medium, on which a computer program is stored which, when executed by a processor, carries out the steps of:
constructing a multi-bit error correcting code memory; the multi-bit error correcting code memory comprises a storage array, a horizontal error correcting code array, a vertical error correcting code array, an encoder and a decoder;
when the multi-bit error correcting code memory is used for reading, the read data is decoded by a decoder to judge whether an error occurs, if no error occurs, the data is directly output, and if an error occurs, the data in the multi-bit error correcting code memory is read again to carry out error positioning and error correction;
in the process of writing operation of the multi-bit error correcting code memory, the encoder is designed in a data interleaving arrangement calculation mode to perform encoding operation on data to be written, write the data into the multi-bit error correcting code memory for storage, and update the vertical check code at the same time;
and converting the read data and the write data before the write operation into one beat for operation, finishing the read operation of the data when the clock rises, and writing the data into the memory cells of the multi-bit error correction code memory on the falling edge of the clock after calculation.
According to the read-write mechanism design method, the computer equipment and the storage medium for the continuous multi-bit error correcting code memory, firstly, the multi-bit error correcting code memory is constructed; the multi-bit error correction code memory comprises a storage array, a horizontal error correction code array, a vertical error correction code array, an encoder and a decoder; when the multi-bit error correcting code memory is used for reading, whether errors occur or not is judged after the read data are decoded by the decoder, if no errors occur, the data are directly output, if errors occur, the data in the multi-bit error correcting code memory are read again for error positioning and error correction, and the multi-bit error correction of the two-dimensional error correcting code can avoid the time of reading without errors, so that the time overhead and the area overhead are greatly reduced during reading, and the reading efficiency is improved. In the process of writing the multi-bit error correcting code memory, an encoder is designed to encode data to be written in a data interleaving arrangement calculation mode and then write the data into the multi-bit error correcting code memory for storage, and a vertical check code is updated at the same time.
Drawings
FIG. 1 is a flow chart illustrating a method for designing a read/write mechanism for a serial multi-bit ECC memory according to an embodiment;
FIG. 2 is a diagram illustrating an embodiment of encoding data using a two-dimensional error correction code algorithm;
FIG. 3 is a diagram of an architecture of a multi-bit ECC memory in one embodiment;
FIG. 4 is a flow diagram illustrating a read operation performed by the multi-bit ECC memory in one embodiment;
FIG. 5 is a flow diagram illustrating a write operation performed by the multi-bit ECC memory in one embodiment;
FIG. 6 is a timing diagram illustrating the write operation of the SRAM in one embodiment;
FIG. 7 is a diagram of the internal structure of a computer device in one embodiment.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
In one embodiment, as shown in fig. 1, a method for designing a read-write mechanism for a continuous multi-bit error correcting code memory is provided, which includes the following steps:
step 102, constructing a multi-bit error correction code memory; the multi-bit error correction code memory includes a memory array, a horizontal error correction code array, a vertical error correction code array, an encoder, and a decoder.
As shown in fig. 3, the whole structure of the multi-bit error correction code memory SRAM is shown. The main function of the SRAM is data storage, wherein the main part includes a storage array, a horizontal error correction code array, a vertical error correction code array, an encoder, a decoder, and the like. The storage array is the most main component of the SRAM, and a horizontal error correction code array is added, so that the data in the storage array is subjected to error detection to achieve a protection function. And data is transmitted with the outside through Column I/O.
And step 104, when the multi-bit error correcting code memory is read, the read data is decoded by a decoder to judge whether errors occur, if no errors occur, the data is directly output, and if errors occur, the data in the multi-bit error correcting code memory is read again to carry out error positioning and error correction.
In the conventional BCH code, a large number of clock cycles are required to complete the decoding operation during the reading operation, i.e., a large amount of time is required. According to the two-dimensional error correction code algorithm adopted during error correction, parity check coding is the simplest coding scheme with the least hardware overhead, but the two-dimensional error correction code algorithm can only be used for error detection and cannot be used for error correction. Then, the data bits are reorganized, and multiple parity checks are adopted, wherein the possible error positions determined by the parity checks are different and mutually overlapped. The error is localized by reducing the overlap area to an error bit. The error correction of the two-dimensional error correction code can avoid the time for reading operation without error. The decoder of the two-dimensional error correcting code is much simpler than the BCH code, so that the time overhead and the area overhead are greatly reduced during the reading operation, and the efficiency of the reading operation is improved. According to the method, two-dimensional parity check coding is adopted, data bits in the SRAM are in a two-dimensional matrix form, parity check is adopted in the vertical direction and the horizontal direction, and errors are located through cross. Because only parity check coding is used, the hardware overhead is small and the SRAM has higher cost-effectiveness ratio under the same error correction capability.
And 106, in the process of writing the multi-bit error correcting code memory, the encoder is designed to perform encoding operation on the data to be written in a data interleaving arrangement calculation mode, then writes the data into the multi-bit error correcting code memory for storage, and simultaneously updates the vertical check code.
As shown in fig. 2, an n-way alternation scheme is adopted in the horizontal and vertical directions, and the encoder is designed to perform encoding operation on data to be written in a data interleaving arrangement calculation mode so as to achieve the purpose of correcting n bit errors. Compared with the traditional write operation, the vertical check code is added firstly, then the write operation is changed into 'reading before writing', the vertical parity updating logic can be pipelined and is separated from the key access way of SRAM access, and therefore, the performance is not directly influenced. Since the data addresses of the write operation and the read operation are identical, there is no need to re-extract the address information. The vertical parity update does not affect the access time or cycle time of the SRAM sub-array as long as the vertical parity update rate matches the data access rate of the SRAM. Updating vertical parity rows like registers is faster than accessing the main array, so the rate can be easily matched in practice. According to the method and the device, the data can be read when the clock rises, and the data is written into the storage unit of the SRAM on the falling edge of the clock after calculation, so that the whole writing process is finished in one beat, and the reading and writing efficiency can be obviously improved.
And step 108, converting the read data and the write data before the write operation into one beat for operation, finishing the read operation of the data when the clock rises, and writing the data into the memory cells of the multi-bit error correction code memory on the falling edge of the clock after calculation.
When the SRAM performs a write operation, a read operation needs to be performed first. The conventional read operation and write operation respectively need one beat, if the read operation is performed before the write operation, the time of two beats is needed, and the write efficiency of the SRAM is low. According to the method, in the SRAM framework, reading data and writing before writing operation are converted into one beat for operation, address information does not need to be extracted again because data addresses of the writing operation and the reading operation are consistent, the reading operation of the data is completed when a clock rises, the data is written into a storage unit of the SRAM on the falling edge of the clock after calculation, the whole writing process is completed in one beat, and the data writing efficiency of the memory is greatly improved.
The read-write mechanism design method for the continuous multi-bit error correcting code memory comprises the following steps of firstly constructing the multi-bit error correcting code memory; the multi-bit error correcting code memory comprises a storage array, a horizontal error correcting code array, a vertical error correcting code array, an encoder and a decoder; when the multi-bit error correcting code memory is used for reading, whether errors occur or not is judged after the read data are decoded by the decoder, if no errors occur, the data are directly output, if errors occur, the data in the multi-bit error correcting code memory are read again for error positioning and error correction, and the multi-bit error correction of the two-dimensional error correcting code can avoid the time of reading without errors, so that the time overhead and the area overhead are greatly reduced during reading, and the reading efficiency is improved. In the process of writing the multi-bit error correcting code memory, the encoder is designed to perform encoding operation on data to be written in a data interleaving arrangement calculation mode, then the data to be written in the multi-bit error correcting code memory is written in the multi-bit error correcting code memory for storage, and the vertical check code is updated simultaneously.
In one embodiment, when the multi-bit error correction code memory performs a read operation, the read data is decoded by a decoder to determine whether an error occurs, if no error occurs, the data is directly output, and if an error occurs, the data in the multi-bit error correction code memory is re-read to perform error positioning and error correction, including:
the address signal is decoded and sends out a read request to the multi-bit error correcting code memory at the same time of reaching the multi-bit error correcting code memory;
and reading the data of the address corresponding to the address signal by using the multi-bit error correction code memory, reading the horizontal parity check code, and performing error detection on the data stored in the multi-bit error correction code memory according to the horizontal parity check code and the calculation unit of the error correction code.
In one embodiment, whether the read data has errors is judged according to the parity check result, and if the read data has no errors, the read data is directly output; if an error occurs, starting error correction operation;
after detecting the occurrence of errors, reading all data and vertical parity check codes in the storage array from the multi-bit error correction code storage;
calculating the stored data one by one with the vertical parity check code to obtain error bits;
and calculating the error distance according to the error bits, and reading the multi-bit error correction code memory according to the calculation result.
In a specific embodiment, as shown in FIG. 4, (1) the address signal is decoded and a read request is issued to the SRAM at the same time as the address signal reaches the SRAM; (2) at the moment, the SRAM reads the data of the address, reads out the horizontal parity check code, and performs error detection operation on the data stored in the SRAM through a calculation unit of an error correction code; (3) judging whether the read data has errors or not according to the parity check result; (4) if no error occurs, directly outputting the data; if an error occurs, starting error correction operation; (5) after detecting the occurrence of errors, reading all data and vertical parity check codes in the storage array from the SRAM; (6) calculating the stored data and the vertical parity check code one by one so as to locate the wrong position, and turning the wrong position so as to obtain correct data; (7) and outputting correct data after error correction is finished, and finishing one-time reading operation by the SRAM. And refreshing the background of the SRAM after the read operation is finished so as to eliminate the influence of accumulated errors.
In one embodiment, the method for calculating the error distance according to the error bit and performing the reading operation of the multi-bit error correction code memory according to the calculation result comprises the following steps:
calculating the error distance according to the error bit, if the error distance is larger than the interleaving number of the multi-bit error correcting code memory during the write operation, exceeding the error correcting capability range, and retransmitting the stored data;
if the error distance is less than the interleaving number of the multi-bit error correcting code memory during the writing operation, the error is positioned and the error data is overturned to obtain the correct data and output the correct data, thereby completing the reading operation of the multi-bit error correcting code memory.
In a specific embodiment, when performing a read operation, a decoding operation needs to be performed on data, which includes determining whether there is error data, and after an error occurs, it needs to read the entire stored data of the SRAM, and after calculation, it first determines the distance at which the error occurs, for example, in a device for correcting four bits, if the distance at which the error occurs is greater than 4, the error exceeds the error correction capability range, and at this time, a reset operation is performed on the entire system. If the error distance is less than 4, the error is positioned and the error data is turned over, and after the reading and writing process is finished, the correct data is updated and reset in the background.
In one embodiment, during a write operation of the multi-bit ecc memory, the encoder is designed to perform an encoding operation on data to be written in a data interleaving calculation manner, write the encoded data into the multi-bit ecc memory for storage, and update the vertical check code at the same time, including:
in the process of writing the multi-bit error correcting code memory, the encoder arranges data, encodes the data in an interleaving mode, and writes the data into the multi-bit error correcting code memory for storage, wherein if n bits are corrected, the interleaving number is n.
In a specific embodiment, as shown in fig. 6, which is a timing waveform diagram of a write operation process of an SRAM, during the write operation, an encoder is designed to perform an encoding operation on data to be written in a manner of data interleaving calculation, for example, an encoding manner of a bit-error-correcting two-dimensional error correction code is an exclusive or operation on all data of each row, such as h 1 ＝W 00 ^W 01 ^W 02 ^W 03 ^W 04 ^W 05 ^W 06 ^W 07 And so on. The encoder for correcting multiple bit errors arranges the data in an interleaving mode, if two bit errors are corrected, the interleaving number is 2, and the error correcting code is h 1 ＝W 00 ^W 02 ^W 04 ^W 06 ，h 2 ＝W 01 ^W 03 ^W 05 ^W 07 (ii) a If the four-bit error is corrected, the interleaving number is 4, and the error correcting codes are h respectively 1 ＝W 00 ^W 04 ，h 2 ＝W 01 ^W 05 ，h3＝W 02 ^W 06 ，h 4 ＝W 03 ^W 07 And so on. And writing the coded data into an SRAM for storage by the coder. And performing operation on the written data and the read storage data to update the vertical error correction code array.
In one embodiment, the address signal is decoded and a write request is sent to the multi-bit ECC memory at the same time when the address signal reaches the multi-bit ECC memory;
reading original data of an address corresponding to the address signal by using a multi-bit error correcting code memory, and reading a vertical parity check code;
comparing and calculating the vertical parity check code and the data to be written, if the data to be written is consistent with the original data, not returning the vertical parity check code, and if the data to be written is inconsistent with the original data, modifying the vertical parity check code; meanwhile, the data to be written is subjected to encoding operation of a horizontal error correcting code;
and updating and writing back the vertical parity check code, and writing the encoded data into a storage array of the multi-bit error correction code memory to finish the write operation of the multi-bit error correction code memory once.
In a specific embodiment, a write flow in the SRAM architecture of the present application is different from a conventional SRAM write flow in that a mechanism for updating a vertical check code is added, and a specific flow is shown in fig. 5, (1) an address signal is decoded and a write request is sent to the SRAM while reaching the SRAM; (2) at the moment, the SRAM reads the original data of the address, reads out the vertical parity check code, compares the vertical parity check code with the incoming data to be written, does not return the vertical parity check code if the data to be written is consistent with the original data, and modifies the vertical parity check code if the data to be written is inconsistent with the original data; meanwhile, the data to be written is subjected to encoding operation of a horizontal error correcting code; (3) and updating and writing back the vertical parity check code, and simultaneously writing the encoded data into a storage array of the SRAM to finish the write operation of the SRAM once.
It should be understood that, although the steps in the flowchart of fig. 1 are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not limited to being performed in the exact order illustrated and, unless explicitly stated herein, may be performed in other orders. Moreover, at least a portion of the steps in fig. 1 may include multiple sub-steps or multiple stages that are not necessarily performed at the same time, but may be performed at different times, and the order of performance of the sub-steps or stages is not necessarily sequential, but may be performed in turn or alternately with other steps or at least a portion of the sub-steps or stages of other steps.
In one embodiment, a computer device is provided, which may be a terminal, and its internal structure diagram may be as shown in fig. 7. The computer device includes a processor, a memory, a network interface, a display screen, and an input device connected by a system bus. Wherein the processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device comprises a nonvolatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of an operating system and computer programs in the non-volatile storage medium. The network interface of the computer device is used for communicating with an external terminal through a network connection. The computer program is executed by a processor to realize a read-write mechanism design method facing a continuous multi-bit error correcting code memory. The display screen of the computer equipment can be a liquid crystal display screen or an electronic ink display screen, and the input device of the computer equipment can be a touch layer covered on the display screen, a key, a track ball or a touch pad arranged on a shell of the computer equipment, an external keyboard, a touch pad or a mouse and the like.
Those skilled in the art will appreciate that the architecture shown in fig. 7 is merely a block diagram of some of the structures associated with the disclosed aspects and is not intended to limit the computing devices to which the disclosed aspects apply, as particular computing devices may include more or less components than those shown, or may combine certain components, or have a different arrangement of components.
In an embodiment, a computer device is provided, comprising a memory storing a computer program and a processor implementing the steps of the method in the above embodiments when the processor executes the computer program.
In an embodiment, a computer storage medium is provided, on which a computer program is stored, which, when being executed by a processor, carries out the steps of the method in the above-mentioned embodiments.
It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above may be implemented by hardware instructions of a computer program, which may be stored in a non-volatile computer-readable storage medium, and when executed, may include the processes of the embodiments of the methods described above. Any reference to memory, storage, database or other medium used in the embodiments provided herein can include non-volatile and/or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically Programmable ROM (EPROM), electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms such as Static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double Data Rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous Link DRAM (SLDRAM), rambus (Rambus) direct RAM (RDRAM), direct Rambus Dynamic RAM (DRDRAM), and Rambus Dynamic RAM (RDRAM), among others.
The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is specific and detailed, but not to be understood as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, and these are all within the scope of protection of the present application. Therefore, the protection scope of the present patent application shall be subject to the appended claims.
Claims (8)
1. A method for designing a read-write mechanism facing a continuous multi-bit error correcting code memory is characterized by comprising the following steps:
constructing a multi-bit error correcting code memory; the multi-bit error correction code memory comprises a storage array, a horizontal error correction code array, a vertical error correction code array, an encoder and a decoder;
when the multi-bit error correcting code memory is used for reading, the read data is decoded by a decoder to judge whether an error occurs, if no error occurs, the data is directly output, and if an error occurs, the data in the multi-bit error correcting code memory is read again to carry out error positioning and error correction;
in the process of writing the multi-bit error correcting code memory, the encoder is designed in a data interleaving arrangement calculation mode to perform encoding operation on data to be written, write the data into the multi-bit error correcting code memory for storage, and update the vertical check code at the same time;
the read data and the write data before the write operation are converted into one beat for operation, the read operation of the data is completed when the clock rises, and the data is written into the memory cells of the multi-bit error correcting code memory on the falling edge of the clock after calculation.
2. The method of claim 1, wherein when the multi-bit ECC memory is performing a read operation, the read data is decoded by the decoder to determine whether there is an error, if there is no error, the data is directly output, and if there is an error, the data in the multi-bit ECC memory is re-read to perform error location and error correction, including:
the address signal is decoded and sends out a read request to the multi-bit error correcting code memory at the same time of reaching the multi-bit error correcting code memory;
and reading the data of the address corresponding to the address signal by using a multi-bit error correction code memory, reading out the horizontal parity check code, and performing error detection on the data stored in the multi-bit error correction code memory according to the horizontal parity check code and the calculation unit of the error correction code.
3. The method of claim 2, further comprising:
judging whether the read data has errors according to the parity check result, and if not, directly outputting the data; if an error occurs, starting error correction operation;
after detecting the error, reading all data and vertical parity check codes in the storage array from the multi-bit error correcting code storage;
calculating the stored data one by one with the vertical parity check code to obtain error bits;
and calculating the error distance according to the error bit, and reading the multi-bit error correction code memory according to the calculation result.
4. The method of claim 3, wherein calculating the error distance according to the error bits, and performing a read operation of the multi-bit ECC memory according to the calculation result comprises:
calculating the error distance according to the error bit, if the error distance is larger than the interleaving number of the multi-bit error correcting code memory during the write operation, exceeding the error correcting capability range, and retransmitting the stored data;
if the error distance is less than the interleaving number of the multi-bit error correcting code memory during the write operation, the error is positioned and the error data is inverted to obtain the correct data and output the correct data, thereby completing the read operation of the multi-bit error correcting code memory.
5. The method of claim 4, wherein during the writing operation of the multi-bit ECC memory, the encoder is designed to perform the encoding operation on the data to be written in a manner of data interleaving calculation, write the data to the multi-bit ECC memory for storage, and update the updated vertical parity check code simultaneously, including:
in the process of writing operation of the multi-bit error correction code memory, the encoder arranges data, encodes the data in an interleaving mode, and writes the encoded data into the multi-bit error correction code memory for storage, wherein if n bits are corrected, the interleaving number is n.
6. The method of claim 5, further comprising:
the address signal is decoded and sends a write request to the multi-bit error correcting code memory when reaching the multi-bit error correcting code memory;
reading original data of an address corresponding to the address signal by using a multi-bit error correcting code memory, and reading a vertical parity check code;
comparing and calculating the vertical parity check code and the data to be written, if the data to be written is consistent with the original data, not returning the vertical parity check code, and if the data to be written is inconsistent with the original data, modifying the vertical parity check code; meanwhile, the data to be written is subjected to encoding operation of a horizontal error correcting code;
and updating and writing back the vertical parity check code, and writing the encoded data into a storage array of the multi-bit error correction code memory to finish the write operation of the multi-bit error correction code memory once.
7. A computer device comprising a memory and a processor, the memory storing a computer program, wherein the processor implements the steps of the method of any one of claims 1 to 6 when executing the computer program.
8. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the steps of the method of any one of claims 1 to 6.
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| CN115985380A (en) * | 2023-03-17 | 2023-04-18 | 之江实验室 | FeFET array data verification method based on digital circuit control |
| CN117234792A (en) * | 2023-11-09 | 2023-12-15 | 北京火山引擎科技有限公司 | Data verification method, device, equipment and medium for DPU |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN115985380A (en) * | 2023-03-17 | 2023-04-18 | 之江实验室 | FeFET array data verification method based on digital circuit control |
| CN115985380B (en) * | 2023-03-17 | 2023-06-20 | 之江实验室 | FeFET array data verification method based on digital circuit control |
| CN117234792A (en) * | 2023-11-09 | 2023-12-15 | 北京火山引擎科技有限公司 | Data verification method, device, equipment and medium for DPU |
| CN117234792B (en) * | 2023-11-09 | 2024-02-09 | 北京火山引擎科技有限公司 | Data verification method, device, equipment and medium for DPU |
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