CN115756936A - Kernel instruction adapting method and device, computer equipment and storage medium - Google Patents
Kernel instruction adapting method and device, computer equipment and storage medium Download PDFInfo
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Abstract
The application relates to a kernel instruction adaptation method, a kernel instruction adaptation device, computer equipment and a storage medium, which are applied to the field of power grids, wherein the method comprises the following steps: receiving an operation instruction to be executed sent by a terminal; performing exception identification on the operation instruction to obtain an identification result; if the identification result of the operation instruction is an error instruction, correcting the operation instruction to obtain a corrected operation instruction; and executing the corrected operation instruction. The method realizes the matching between the operation instruction and the server architecture by screening and correcting the error instruction, is suitable for the matching of the core instruction of the ARM architecture, and can avoid time waste caused by the error operation instruction.
Description
Technical Field
The present application relates to the field of power grid technologies, and in particular, to a kernel instruction adaptation method, apparatus, computer device, storage medium, and computer program product.
Background
The ARM architecture (advanced RISC CMache) is a 32-bit Reduced Instruction Set (RISC) processor architecture, and due to the characteristics of low power consumption and suitability for the field of mobile communication, the ARM server is adopted to replace a server of an X86 architecture (a computer language instruction set executed by a microprocessor) to become a development trend of various industries, and the power grid industry is no exception. In order to adapt the existing operating system of the power grid to the ARM architecture, an adaptation method for the core instruction of the ARM architecture needs to be developed.
Disclosure of Invention
In view of the above, it is necessary to provide a kernel instruction adapting method, apparatus, computer device, computer readable storage medium and computer program product for solving the technical problem of the incompatibility between the kernel instruction and the ARM architecture.
In a first aspect, the present application provides a kernel instruction adaptation method. The method comprises the following steps:
receiving an operation instruction to be executed sent by a terminal;
performing exception identification on the operation instruction to obtain an identification result;
if the identification result of the operation instruction is an error instruction, correcting the operation instruction to obtain a corrected operation instruction;
and executing the corrected operation instruction.
In one embodiment, the method further comprises:
acquiring the instruction type of the operation instruction;
and if the instruction type of the operation instruction is not matched with the target instruction type, determining that the operation instruction is an error instruction.
In one embodiment, the modifying the operation instruction to obtain a modified operation instruction includes:
and recompiling the operation instruction based on a compiler of the target instruction type to obtain the corrected operation instruction.
In one embodiment, before executing the modified operation instruction, the method further includes:
debugging the corrected operation instruction to obtain a debugging result;
the executing the corrected operation instruction includes:
and if the debugging result is normal, executing the corrected operation instruction.
In one embodiment, before the executing the modified operation instruction, the method further includes:
displaying an operation confirmation key and an operation cancellation key;
and executing the corrected operation instruction based on the trigger instruction aiming at the operation confirmation key.
In one embodiment, the method further comprises:
detecting the abnormal condition of each stage in the execution process of the operation instruction;
and when the abnormality of any stage is detected, stopping the operation of the operation instruction, and setting the operation instruction to be in an unavailable state.
In a second aspect, the application further provides a kernel instruction adapting device. The device comprises:
the core module is used for receiving an operation instruction to be executed sent by the terminal and sending the operation instruction to the detection module;
the detection module is used for carrying out exception identification on the operation instruction to obtain an identification result and sending the operation instruction to the safety frame module under the condition that the identification result is an error instruction;
the safety frame module is used for correcting the operation instruction to obtain a corrected operation instruction;
and the execution module is used for executing the corrected operation instruction.
In one embodiment, the detection module is further configured to obtain an instruction type of the operation instruction; if the instruction type of the operation instruction is not matched with the target instruction type, determining that the operation instruction is an error instruction;
in one embodiment, the safety framework module is further configured to recompile the operation instruction based on a compiler of a target instruction type to obtain the modified operation instruction.
In one embodiment, the apparatus further includes a debugging module, configured to perform debugging processing on the modified operation instruction to obtain a debugging result;
and the execution module is further used for executing the corrected operation instruction when the debugging result is normal debugging.
In one embodiment, the device further comprises a confirmation module for displaying an operation confirmation key and an operation cancel key;
the execution module is further configured to execute the corrected operation instruction based on the trigger instruction for the operation confirmation key.
In one embodiment, the safety framework module is used for detecting abnormal conditions of the operation instructions from detection of various stages in the execution process; and when the abnormality of any stage is detected, stopping the operation of the operation instruction, and setting the operation instruction to be in an unavailable state.
In a third aspect, the present application also provides a computer device. The computer device comprises a memory storing a computer program and a processor implementing the following steps when executing the computer program:
receiving an operation instruction to be executed sent by a terminal;
performing exception identification on the operation instruction to obtain an identification result;
if the identification result of the operation instruction is an error instruction, correcting the operation instruction to obtain a corrected operation instruction;
and executing the corrected operation instruction.
In a fourth aspect, the present application further provides a computer-readable storage medium. The computer-readable storage medium, on which a computer program is stored which, when executed by a processor, carries out the steps of:
receiving an operation instruction to be executed sent by a terminal;
performing exception identification on the operation instruction to obtain an identification result;
if the identification result of the operation instruction is an error instruction, correcting the operation instruction to obtain a corrected operation instruction;
and executing the corrected operation instruction.
In a fifth aspect, the present application further provides a computer program product. The computer program product comprising a computer program which when executed by a processor performs the steps of:
receiving an operation instruction to be executed sent by a terminal;
performing exception identification on the operation instruction to obtain an identification result;
if the identification result of the operation instruction is an error instruction, correcting the operation instruction to obtain a corrected operation instruction;
and executing the corrected operation instruction.
According to the kernel instruction adapting method, the kernel instruction adapting device, the computer equipment, the storage medium and the computer program product, the operation instruction to be executed sent by the terminal is subjected to exception identification, and the operation instruction is corrected under the condition that the identification result is that the operation instruction belongs to an error instruction, so that the corrected operation instruction meeting the requirement is obtained, and the corrected operation instruction can be executed. The method realizes the matching between the operation instruction and the server architecture by screening and correcting the error instruction, is suitable for the matching of the kernel instruction of the ARM architecture, and can avoid time waste caused by the error operation instruction.
Drawings
FIG. 1 is a diagram of an application environment of a kernel instruction adaptation method in one embodiment;
FIG. 2 is a flowchart illustrating a method for adapting kernel instructions according to an embodiment;
FIG. 3 is a flowchart illustrating a kernel instruction adaptation method according to another embodiment;
FIG. 4 is a block diagram showing the structure of a core instruction adaptation apparatus according to an embodiment;
FIG. 5 is a schematic structural diagram of a core instruction adaptation apparatus in another embodiment;
FIG. 6 is a flowchart illustrating the use of the kernel instruction adaptation apparatus in one embodiment;
FIG. 7 is a diagram illustrating an internal structure of a computer device according to an embodiment.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of and not restrictive on the broad application.
The kernel instruction adaptation method provided by the embodiment of the application can be applied to an application environment shown in fig. 1. Wherein the terminal 102 communicates with the server 104 via a network. The data storage system may store data that the server 104 needs to process. The data storage system may be integrated on the server 104 or may be placed on the cloud or other network server. In an application scenario of the present disclosure, the terminal 102 sends an operation instruction to be executed to the server 104, and after receiving the operation instruction, the server 104 performs exception identification on the operation instruction to obtain an identification result; if the identification result of the operation instruction is an error instruction, correcting the operation instruction to obtain a corrected operation instruction; and executing the corrected operation instruction.
The terminal 102 may be, but not limited to, various personal computers, notebook computers, smart phones, tablet computers, internet of things devices and portable wearable devices, and the internet of things devices may be smart speakers, smart televisions, smart air conditioners, smart car-mounted devices, and the like. The portable wearable device can be a smart watch, a smart bracelet, a head-mounted device, and the like. The server 104 may be implemented as a stand-alone server or a server cluster comprised of multiple servers.
In an embodiment, as shown in fig. 2, a kernel instruction adaptation method is provided, which is described by taking the method as an example applied to the server 104 in fig. 1, and includes the following steps:
and step S210, receiving an operation instruction to be executed sent by the terminal.
The operation instruction to be executed may be an X86 instruction, and the X86 instruction is an instruction based on an X86 architecture.
And step S220, performing exception identification on the operation instruction to obtain an identification result.
In specific implementation, considering that the operation instruction sent by the terminal may not be adapted to the architecture of the server, after receiving the operation instruction sent by the terminal, the server may perform exception identification on the operation instruction, and identify whether the operation instruction matches the architecture of the server, so as to take different processing measures according to an identification result.
More specifically, the instruction type of the operation instruction may be acquired, and the operation instruction is subjected to exception identification based on the instruction type, so as to obtain an identification result.
In step S230, if the identification result of the operation command is an error command, the operation command is modified to obtain a modified operation command.
Wherein the fault instruction may represent an operation instruction that is not adapted to the architecture of the server.
In the concrete implementation, if it is recognized that the operation instruction sent by the terminal is not adapted to the framework of the server, the operation instruction is determined to be an error instruction, and a preset correction method is further adopted to correct the operation instruction, so that the corrected operation instruction is matched with the framework of the server.
In step S240, the corrected operation command is executed.
In specific implementation, after the server corrects the erroneous operation instruction, the server can execute the corrected operation instruction because the obtained corrected operation instruction matches with the architecture of the server.
In the kernel instruction adaptation method, the operation instruction to be executed sent by the terminal is subjected to exception identification, and the operation instruction is corrected under the condition that the identification result is that the operation instruction belongs to an error instruction, so that a corrected operation instruction meeting the requirement is obtained, and the corrected operation instruction can be executed. The method realizes the matching between the operation instruction and the server architecture by screening and correcting the error instruction, is suitable for the matching of the core instruction of the ARM architecture, and can avoid time waste caused by the error operation instruction.
In an exemplary embodiment, the method further includes: acquiring an instruction type of an operation instruction; and if the instruction type of the operation instruction is not matched with the target instruction type, determining that the operation instruction is an error instruction.
The target instruction type is an instruction corresponding to an architecture adopted by the server, and the server can adopt an ARM architecture, so that the target instruction type can be an ARM instruction.
In specific implementation, after receiving an operation instruction to be executed sent by a terminal, a server can also detect the instruction type of the operation instruction, match the instruction type of the operation instruction with a target instruction type, and if the instruction type of the operation instruction is matched with the target instruction type, determine that the operation instruction is a correct instruction and execute the operation instruction. If the two are not matched, the operation instruction is determined to be an error instruction, correction processing needs to be carried out on the error instruction, and the error instruction is corrected to be the operation instruction with the same type as the target instruction.
In this embodiment, by obtaining the instruction type of the operation instruction, the exception identification result of the operation instruction can be determined according to the matching result of the instruction type and the target instruction type, so that an error instruction which is not matched with the target instruction can be screened out, and the error instruction can be processed in time.
In an exemplary embodiment, in the step S230, performing a correction process on the operation instruction to obtain a corrected operation instruction includes: and recompiling the operation instruction based on the compiler of the target instruction type to obtain the corrected operation instruction.
In the specific implementation, the purpose of correcting the operation instruction is to enable the operation instruction to be matched with the architecture adopted by the server, and the target instruction type is the instruction type corresponding to the architecture adopted by the server, so that the operation instruction can be modified into the operation instruction of the target instruction type, and the adaptation of the operation instruction and the server architecture is realized.
More specifically, a compiler of the target instruction type may be obtained, and the compiler may recompile the operation instruction to obtain a modified operation instruction matching the target instruction type.
In this embodiment, the operation instruction modified by the compiler of the target instruction type is matched with the target instruction type, so as to be matched with the server architecture, and the server can execute the modified operation instruction.
In an exemplary embodiment, before the step S240 executing the corrected operation instruction, the method further includes: debugging the corrected operation instruction to obtain a debugging result;
executing the corrected operation instruction, including: and if the debugging result is normal, executing the corrected operation instruction.
In specific implementation, in order to ensure normal execution of the corrected operation instruction, after the corrected operation instruction is obtained, debugging processing may be performed on the corrected operation instruction, that is, whether an error still exists in the corrected operation instruction is detected, and whether normal execution is possible, and if an error does not exist, the normal execution is performed, and it is determined that a debugging result is normal, so that the corrected operation instruction may be executed. Otherwise, if an error exists or the normal execution cannot be carried out, determining that the debugging result is abnormal, and outputting error prompt information.
In this embodiment, through the debugging processing on the corrected operation instruction, the corrected operation instruction is executed under the condition that the debugging result is normal, so that secondary error screening of the operation instruction is realized, and normal execution of the operation instruction to be executed by the server is further ensured.
In an exemplary embodiment, before the step S240 executes the corrected operation instruction, the method further includes: displaying an operation confirmation key and an operation cancellation key; and executing the corrected operation instruction based on the trigger instruction aiming at the operation confirmation key.
In the specific implementation, an operation confirmation key and an operation cancel key can be further arranged for a user to select before executing the corrected operation instruction, and when a trigger instruction for the operation confirmation key is received, the corrected operation instruction can be executed; and when a trigger instruction for the operation canceling key is received, the execution operation of the corrected operation instruction is canceled.
For example, a rectangular "operation confirmation" key and a circular "operation cancellation" key are provided for the user to decide the last step of the operation instruction.
In an exemplary embodiment, the method further comprises a data source for acquiring the operation instruction, detecting the operation instruction again based on the data source, and displaying the operation confirmation key and the operation cancel key when the detection result is normal.
In the embodiment, the final choice is made by the user by displaying the operation confirmation key and the operation cancellation key, so that the device damage caused by operation instruction errors can be reduced, and the safety guarantee is further enhanced.
In an exemplary embodiment, the method further comprises: detecting abnormal conditions of each stage in the execution process of the operation instruction; when the abnormality of any stage is detected, the operation of the operation instruction is stopped, and the operation instruction is set to be in an unavailable state.
In specific implementation, the TrustZone technology (a system-wide security method) is also adopted for securely starting the operating system, specifically, by TrustZone, a digital signature check is added at each stage of system starting, so that the security of a loaded image is ensured, unauthorized or intentional modification during starting is prevented, and the security of the operating system is ensured. When the startup fails, the measures mainly taken include stopping the startup and protecting data (such as an operation instruction), and the data can be set to an unavailable state.
In this embodiment, when an abnormal condition of the operation instruction from detection of each stage in the execution process is detected, and when an abnormality is detected in any stage, the operation on the operation instruction is stopped, and the operation instruction is set to the unavailable state, so that the security of the operating system can be ensured.
Referring to fig. 3, a flowchart of a kernel instruction adaptation method according to another embodiment is shown, where in this embodiment, the method includes the following steps:
step S310, receiving an operation instruction to be executed sent by a terminal, and acquiring an instruction type of the operation instruction;
step S320, if the instruction type of the operation instruction is not matched with the target instruction type, determining that the operation instruction is an error instruction;
step S330, recompiling the operation instruction based on the compiler of the target instruction type to obtain a corrected operation instruction;
step S340, debugging the corrected operation instruction to obtain a debugging result;
step S350, if the debugging result is normal, displaying an operation confirmation key and an operation cancellation key;
step S360, executing the corrected operation instruction based on the trigger instruction for the operation confirmation key.
In the kernel instruction adaptation method provided by this embodiment, the exception identification is performed on the to-be-executed operation instruction sent by the terminal, and when the identification result is that the operation instruction belongs to an incorrect instruction, the operation instruction is modified to obtain a modified operation instruction meeting the requirement, so that the modified operation instruction can be executed. The method realizes the matching between the operation instruction and the server architecture by screening and correcting the error instruction, is suitable for the matching of the core instruction of the ARM architecture, and can avoid time waste caused by the error operation instruction.
Based on the same inventive concept, the embodiment of the present application further provides a kernel instruction adaptation device for implementing the kernel instruction adaptation method. The implementation scheme for solving the problem provided by the apparatus is similar to the implementation scheme described in the above method, so specific limitations in one or more embodiments of the kernel instruction adaptation apparatus provided below may refer to the limitations on the kernel instruction adaptation method in the foregoing, and details are not described here again.
In one embodiment, as shown in fig. 4, there is provided a kernel instruction adapting apparatus, comprising a core module 410, a detection module 420, a security framework module 430 and an execution module 440, wherein,
the core module 410 is configured to receive an operation instruction to be executed and sent by the terminal, and send the operation instruction to the detection module;
the detection module 420 is configured to perform exception identification on the operation instruction to obtain an identification result, and send the operation instruction to the safety framework module when the identification result is an error instruction;
the safety framework module 430 is configured to modify the operation instruction to obtain a modified operation instruction;
and the execution module 440 is configured to execute the corrected operation instruction.
In an exemplary embodiment, the detection module 410 is further configured to obtain an instruction type of the operation instruction; if the instruction type of the operation instruction is not matched with the target instruction type, determining that the operation instruction is an error instruction;
in an exemplary embodiment, the security framework module 430 is further configured to recompile the operation instruction based on the compiler of the target instruction type, so as to obtain a modified operation instruction.
In an exemplary embodiment, the apparatus further includes a debugging module, configured to perform debugging processing on the modified operation instruction to obtain a debugging result; the execution module 440 is further configured to execute the corrected operation instruction when the debugging result is that the debugging is normal.
In an exemplary embodiment, the apparatus further comprises a confirmation module for presenting an operation confirmation key and an operation cancel key; the execution module 440 is further configured to execute the corrected operation instruction based on the trigger instruction for the operation confirmation key.
In an exemplary embodiment, the security framework module 430 is further configured to detect an abnormal condition of the operation instruction from detection of each stage in the execution process; and when the abnormality of any stage is detected, stopping the operation of the operation instruction, and setting the operation instruction to be in an unavailable state.
In an exemplary embodiment, the execution module 440 is further configured to execute the operation instruction if the identification result of the operation instruction is a correct instruction.
Referring to fig. 5, a schematic structural diagram of a kernel instruction adaptation apparatus according to another embodiment is shown, including: the system comprises a core module, a detection module, a safety frame module, a starting module, a debugging module, a connecting module, a confirmation module and an execution module, wherein as shown in fig. 5, the core module is connected with the detection module, and the detection module is respectively connected with the starting module and the safety frame module; the safety frame module is connected with the debugging module, the debugging module is connected with the starting module, the starting module is respectively connected with the connecting module and the confirming module, the connecting module is connected with the confirming module, and the executing module is connected with the confirming module.
More specifically, the detection module is connected to the core module by a wire, and is adapted to a library and a software stack integrated in an OS (Operating System) user layer, where the main source of the detection module is various open source codes, and the main work is recompilation by an ARM-based compiler, and adjustment of part of the codes or the type of compilation for the ARM architecture.
In an exemplary embodiment, the debugging module and the starting module are connected by using an optical fiber data connection line.
In an exemplary embodiment, the connection module is capable of observing data, analyzing data, graphical data, and statistical data, and the connection module uses a 5G network for information collection.
In an exemplary embodiment, the core module adopts a brand-new ARM64 micro-architecture, and a compiler and a CPU are adopted for vertical optimization in the operating device for supporting the ARM64 micro-architecture; the adaptation method carries out the separation processing of the multi-level page tables of the kernel and the task according to the memory management, the interrupt management and the task of the equipment management of the operating device and the multi-level page tables in the ARM64 micro-architecture. And the specific processing steps are processed in a manner of running an arm cpu driver, thereby solving the problem of specific adaptation.
The modules in the kernel instruction adaptation device can be wholly or partially implemented by software, hardware and a combination thereof. The modules can be embedded in a hardware form or independent from a processor in the computer device, and can also be stored in a memory in the computer device in a software form, so that the processor can call and execute operations corresponding to the modules.
Referring to fig. 6, a schematic usage flow diagram of a kernel instruction adaptation apparatus in an exemplary embodiment includes the following steps:
the core module is used for analyzing data triggered by a user, converting the data into an operation instruction and sending the operation instruction to the detection module;
the detection module is used for identifying the operation instruction sent by the core module, screening the error instruction, and directly sending the correct operation instruction to the starting module if the operation instruction is correct; if the operation instruction is wrong, transmitting the wrong instruction to the safety framework module;
the safety frame module is used for correcting the error instruction and transmitting the corrected operation instruction to the debugging module;
the debugging module is used for debugging the corrected operation instruction, and if the debugging result is normal, the corrected operation instruction which is normally debugged is sent to the starting module;
and the starting module is used for executing the starting instruction on the operation instruction sent by the detection module or the corrected operation instruction sent by the debugging module.
The connection module is used for carrying out information acquisition by using a 5G network and transmitting an acquired instruction data source to the confirmation module;
the confirmation module is provided with two buttons on the surface, wherein the two buttons are respectively a rectangular 'confirmation' button and a circular 'cancellation' button, the transmitted information is further analyzed, the result is displayed, and the operator decides the instruction finally through the rectangular 'confirmation' button and the circular 'cancellation' button, so that the device damage caused by instruction errors can be reduced, and the safety guarantee is further enhanced.
It should be understood that, although the steps in the flowcharts related to the embodiments as described above are sequentially displayed as indicated by arrows, the steps are not necessarily performed sequentially as indicated by the arrows. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. Moreover, at least a part of the steps in the flowcharts related to the embodiments described above may include multiple steps or multiple stages, which are not necessarily performed at the same time, but may be performed at different times, and the execution order of the steps or stages is not necessarily sequential, but may be rotated or alternated with other steps or at least a part of the steps or stages in other steps.
In one embodiment, a computer device is provided, which may be a server, and the internal structure thereof may be as shown in fig. 7. The computer device includes a processor, a memory, and a network interface connected by a system bus. Wherein the processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program, and a database. The internal memory provides an environment for the operating system and the computer program to run on the non-volatile storage medium. The database of the computer device is used for storing data in the kernel instruction adapting process. The network interface of the computer device is used for communicating with an external terminal through a network connection. The computer program is executed by a processor to implement a method of kernel instruction adaptation.
It will be appreciated by those skilled in the art that the configuration shown in fig. 7 is a block diagram of only a portion of the configuration associated with the present application, and is not intended to limit the computing device to which the present application may be applied, and that a particular computing device may include more or fewer components than shown, or may combine certain components, or have a different arrangement of components.
In an embodiment, a computer device is further provided, which includes a memory and a processor, the memory stores a computer program, and the processor implements the steps of the above method embodiments when executing the computer program.
In an embodiment, a computer-readable storage medium is provided, on which a computer program is stored which, when being executed by a processor, carries out the steps of the above-mentioned method embodiments.
In an embodiment, a computer program product is provided, comprising a computer program which, when being executed by a processor, carries out the steps of the above-mentioned method embodiments.
It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by hardware instructions of a computer program, which can be stored in a non-volatile computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. Any reference to memory, database, or other medium used in the embodiments provided herein may include at least one of non-volatile and volatile memory. The nonvolatile Memory may include Read-Only Memory (ROM), magnetic tape, floppy disk, flash Memory, optical Memory, high-density embedded nonvolatile Memory, resistive Random Access Memory (ReRAM), magnetic Random Access Memory (MRAM), ferroelectric Random Access Memory (FRAM), phase Change Memory (PCM), graphene Memory, and the like. Volatile Memory can include Random Access Memory (RAM), external cache Memory, and the like. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM), for example. The databases referred to in various embodiments provided herein may include at least one of relational and non-relational databases. The non-relational database may include, but is not limited to, a block chain based distributed database, and the like. The processors referred to in the embodiments provided herein may be general purpose processors, central processing units, graphics processors, digital signal processors, programmable logic devices, quantum computing based data processing logic devices, etc., without limitation.
All possible combinations of the technical features in the above embodiments may not be described for the sake of brevity, but should be considered as being within the scope of the present disclosure as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the present application. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, and these are all within the scope of protection of the present application. Therefore, the protection scope of the present application shall be subject to the appended claims.
Claims (10)
1. A method for kernel instruction adaptation, the method comprising:
receiving an operation instruction to be executed sent by a terminal;
performing exception identification on the operation instruction to obtain an identification result;
if the identification result of the operation instruction is an error instruction, correcting the operation instruction to obtain a corrected operation instruction;
and executing the corrected operation instruction.
2. The method of claim 1, further comprising:
acquiring the instruction type of the operation instruction;
and if the instruction type of the operation instruction is not matched with the target instruction type, determining that the operation instruction is an error instruction.
3. The method according to claim 2, wherein the modifying the operation instruction to obtain a modified operation instruction comprises:
and recompiling the operation instruction based on a compiler of the target instruction type to obtain the corrected operation instruction.
4. The method of claim 1, wherein prior to executing the revised operation instruction, further comprising:
debugging the corrected operation instruction to obtain a debugging result;
the executing the corrected operation instruction includes:
and if the debugging result is normal, executing the corrected operation instruction.
5. The method of claim 4, wherein prior to executing the revised operating instructions, further comprising:
displaying an operation confirmation key and an operation cancel key;
and executing the corrected operation instruction based on the trigger instruction aiming at the operation confirmation key.
6. The method of claim 1, further comprising:
detecting abnormal conditions of each stage in the execution process of the operation instruction;
and when the abnormality of any stage is detected, stopping the operation of the operation instruction, and setting the operation instruction to be in an unavailable state.
7. An apparatus for adapting kernel instructions, the apparatus comprising:
the core module is used for receiving an operation instruction to be executed sent by the terminal and sending the operation instruction to the detection module;
the detection module is used for carrying out exception identification on the operation instruction to obtain an identification result and sending the operation instruction to the safety frame module under the condition that the identification result is an error instruction;
the safety frame module is used for correcting the operation instruction to obtain a corrected operation instruction;
and the execution module is used for executing the corrected operation instruction.
8. A computer device comprising a memory and a processor, the memory storing a computer program, characterized in that the processor, when executing the computer program, implements the steps of the kernel instruction adaptation method of any one of claims 1 to 6.
9. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the steps of the kernel instruction adaptation method of any one of claims 1 to 6.
10. A computer program product comprising a computer program, characterized in that the computer program, when being executed by a processor, carries out the steps of the kernel instruction adaptation method of any one of claims 1 to 6.
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| CN202211565517.6A CN115756936A (en) | 2022-12-07 | 2022-12-07 | Kernel instruction adapting method and device, computer equipment and storage medium |
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| CN202211565517.6A CN115756936A (en) | 2022-12-07 | 2022-12-07 | Kernel instruction adapting method and device, computer equipment and storage medium |
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