CN115756562A

CN115756562A - Online configuration method, system, device and medium for clock jitter eliminator in switch

Info

Publication number: CN115756562A
Application number: CN202211392745.8A
Authority: CN
Inventors: 郭雷; 张广乐
Original assignee: Suzhou Inspur Intelligent Technology Co Ltd
Current assignee: Suzhou Inspur Intelligent Technology Co Ltd
Priority date: 2022-11-08
Filing date: 2022-11-08
Publication date: 2023-03-07

Abstract

The invention provides a method, a system, a device and a medium for online configuration of a clock jitter eliminator in a switch, wherein the method comprises the following steps: when the switch is powered on and started for the first time, the BMC sends a starting signal to the CPU; reading the model of the clock jitter eliminator through the BMC; judging whether the jitter eliminator needs to be reconfigured according to the model of the clock jitter eliminator; if yes, reconfiguring the clock jitter eliminator through the BMC, and releasing and resetting the PHY chip through the CPU; if not, directly resetting the PHY chip through the CPU; when the switch runs, detecting the preset signal state of the CPU through the BMC, and judging whether hot restart or cold restart operation occurs; when a cold restart operation occurs, the clock jitter eliminator is again configured. The invention can reconfigure the firmware of the clock jitter eliminator chip according to the requirement in the process of the initial power-on and restarting of the switch through the BMC chip.

Description

Online configuration method, system, device and medium for clock jitter eliminator in switch

Technical Field

The invention relates to the technical field of computers, in particular to an online configuration method, system, device and medium of a clock jitter eliminator in a switch.

Background

In a switch with high-density ports, the number of MAC chip servers is limited, so that ports cannot be generated, and PHY/GearBox chips are generally adopted for port expansion. The MAC chip and the PHY chip both require reference clocks of the same frequency, and in some scenarios with higher requirements, the clocks of the MAC chip and the PHY chip are also required to be homologous. In the current switch design, one MAC chip is connected with a plurality of PHY chips, a clock expander for expanding a path generated by a clock generator is used for PHY, the clock line is usually long in routing and can pass through a connector, jitter is inevitably introduced into a signal reaching the clock expander, and the introduced jitter can influence the working state of the PHY chip to cause packet loss.

Clock jitter removers are commonly used in the industry to remove jitter from clocks generated by clock generators, and clock generator chips are also commonly used to spread one clock input to multiple outputs and remove jitter from each output clock. Chips such as clock jitter eliminators are usually customized chips, and need to be matched with corresponding firmware, the firmware needs to be configured by a chip manufacturer according to corresponding requirements, and the firmware is burned into the chip through OTP when the chip leaves a factory and never lost, and the firmware configuration of the chips is often more. In recent years, due to insufficient chip capacity, a chip manufacturer preferentially supplies a customer with a large order quantity, some customers with a small order quantity cannot be met generally, and configuration firmware of different customers is different and cannot be used directly.

Disclosure of Invention

In view of the foregoing problems, an object of the present invention is to provide an online configuration method, system, device and medium for a clock jitter eliminator in a switch, which can reconfigure a firmware of the clock jitter eliminator chip according to requirements during the initial power-on and reboot of the switch through a BMC chip.

In order to achieve the purpose, the invention is realized by the following technical scheme: an online configuration method for a clock jitter eliminator in a switch comprises the following steps:

when the switch is powered on and started for the first time, the BMC sends a starting signal to the CPU;

reading the model of the clock jitter eliminator through the BMC;

judging whether the jitter eliminator needs to be reconfigured according to the model of the clock jitter eliminator;

if yes, reconfiguring the clock jitter eliminator through the BMC, and releasing and resetting the PHY chip through the CPU;

if not, directly resetting the PHY chip through the CPU;

when the switch runs, detecting the preset signal state of the CPU through the BMC, and judging whether hot restart or cold restart operation occurs;

when a cold restart operation occurs, the clock jitter eliminator is again configured.

Further, the reading, by the BMC, the type of the clock jitter eliminator includes:

the BMC reads configuration firmware of the clock jitter eliminator through an I2C interface;

the model number of the clock jitter eliminator is identified from the configuration firmware.

Further, the determining whether the jitter canceller needs to be reconfigured according to the clock jitter canceller model includes:

if the clock jitter eliminator is a customized clock jitter eliminator of the switch, the jitter eliminator does not need to be reconfigured;

if the clock jitter eliminator is a switch-adapted clock jitter eliminator of the same family, the jitter eliminator needs to be reconfigured.

Further, reconfiguring the clock jitter eliminator by the BMC includes:

the control BMC writes the required configuration firmware into the clock jitter eliminator via the I2C interface.

Further, the configuration duration of the BMC for reconfiguring the clock jitter eliminator is less than or equal to 5 seconds.

Further, the detecting of the preset signal state of the CPU by the BMC and the judging of whether the hot restart or cold restart operation occurs include:

detecting the states of a PLT _ RST signal and an S4 signal of the CPU through the BMC;

when the PLT _ RST signal has a falling edge and the S4 signal has a rising edge, the cold restart operation of the switch occurs; when the PLT _ RST signal falls and the S4 signal is unchanged, the switch has a hot restart operation.

Further, the reconfiguring the clock jitter eliminator when the cold restart operation occurs comprises:

reading the model of the clock jitter eliminator through the BMC;

judging whether the clock jitter eliminator is a clock jitter eliminator of the same series adapted to the switch or not;

if yes, reconfiguring the clock jitter eliminator through the BMC;

if not, the process is ended directly.

Correspondingly, the invention also discloses an online configuration system of the clock jitter eliminator in the switch, which comprises the following steps: the BMC sends a starting signal to the CPU when the switch is started up by being powered on for the first time;

the reading unit is used for reading the model of the clock jitter eliminator through the BMC;

the judging unit judges whether the jitter eliminator needs to be reconfigured according to the model of the clock jitter eliminator;

the configuration unit is used for reconfiguring the clock jitter eliminator through the BMC and resetting the PHY chip through the CPU;

and the signal identification unit is used for detecting the preset signal state of the CPU through the BMC when the switch runs and judging whether hot restart or cold restart operation occurs.

Correspondingly, the invention discloses an online configuration device of a clock jitter eliminator in a switch, which comprises the following steps:

the memorizer, is used for storing the online configuration procedure of the clock jitter eliminator in the exchanger;

a processor, configured to implement the steps of the method for configuring a clock jitter eliminator in a switch in-line when executing the program for configuring the clock jitter eliminator in the switch in-line.

Accordingly, the present invention discloses a readable storage medium, on which a clock jitter eliminator online configuration program in a switch is stored, wherein the clock jitter eliminator online configuration program in the switch, when executed by a processor, implements the steps of the clock jitter eliminator online configuration method in the switch as described in any one of the above.

Compared with the prior art, the invention has the beneficial effects that: the invention discloses an online configuration method, a system, a device and a medium of a clock jitter eliminator in a switch, which can select other custom chips in the same series when the supply voltage of a custom chip of the clock jitter eliminator in the switch is insufficient, and reconfigure a firmware for the clock jitter eliminator chip through a BMC (baseboard management controller) chip in the process of initial power-on and restart of the switch without increasing any material cost, thereby ensuring the production of switch products. The invention utilizes the BMC system in the switch to control the power-on time sequence of the switch system through the BMC, shortens the online burning time of the BMC configuration clock jitter eliminator and ensures that the switch can work normally.

Therefore, compared with the prior art, the invention has prominent substantive features and remarkable progress, and the beneficial effects of the implementation are also obvious.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.

FIG. 1 is a process flow diagram of an embodiment of the present invention.

Fig. 2 is a flow chart of the reconfiguration of the firmware for the clock jitter eliminator during a switch reboot in accordance with an embodiment of the present invention.

Fig. 3 is a system block diagram of an embodiment of the present invention.

In the figure, 1, a power-on unit; 2. a reading unit; 3. a judgment unit; 4. a configuration unit; 5. and a signal identification unit.

Detailed Description

The core of the invention is to provide an online configuration method of a clock jitter eliminator in a switch, in the prior art, because the capacity of a chip is insufficient, the clock jitter eliminator is a customized chip, a supplier needs to generate configuration firmware according to the requirements of customers, and the chips with different requirements of the customers cannot be directly used.

Firstly, when the switch is powered on and started for the first time, the BMC sends a starting signal to the CPU, and reads the type of the clock jitter eliminator through the BMC. At the moment, judging whether the jitter eliminator needs to be reconfigured according to the model of the clock jitter eliminator; if yes, reconfiguring the clock jitter eliminator through the BMC, and releasing and resetting the PHY chip through the CPU; if not, the PHY chip is directly reset through the CPU. When the switch runs, detecting the preset signal state of the CPU through the BMC, and judging whether hot restart or cold restart operation occurs; when a cold restart operation occurs, the clock jitter eliminator is again configured. Therefore, the invention can select other custom chips in the same series when the supply voltage of the custom chip of the clock jitter eliminator in the switch is insufficient, and the firmware of the clock jitter eliminator chip is reconfigured by the BMC chip in the process of the initial power-on and restart of the switch, so that the material cost is not increased, and the production of switch products is ensured.

In order to make the technical personnel in the technical field understand the scheme of the invention better, the use scene related to the invention is specifically explained as follows:

one or more clock jitter eliminators are arranged in the existing switch board, a clock generator generates a clock of 156.25MHz, jitter is introduced into a clock signal after the clock signal passes through a long path and a connector, the clock jitter eliminator eliminates the jitter, then a plurality of paths of clocks are generated and output to a PHY chip, and therefore the homology of reference clocks of the MAC chip and the PHY chip is guaranteed. The configuration firmware of the clock jitter eliminator can be programmed by OTP before leaving factory, and can also be loaded by an external EEPROM, but the method additionally increases the cost of an EEPROM chip, and the EEPROM is required to be programmed off line during PCBA production, so that the manufacturing cost is increased, and therefore the OTP clock jitter eliminator is commonly used in the industry. The clock jitter eliminator is a customized chip, a supplier also generates configuration firmware according to customer requirements, and chips with different customer requirements cannot be directly used. In recent years, the chip supply is in short supply, a supplier usually ensures customers with large shipment quantity, and chips with smaller consumption face the problem of chip shortage and influence product delivery; the supplier prints different silk screens for different customers' chips, which are identical in hardware and only different from configuration firmware.

The clock jitter eliminator chip is usually provided with an I2C or SPI interface for loading firmware or modifying various configurations of the chip, and the modified clock jitter eliminator chip takes effect in real time, so that the clock jitter eliminator chip in the same series (a custom chip with large shipment volume) can be modified on line through the I2C interface to ensure supply. The switch system is complex and mainly comprises a CPU system, a switching chip system and a PHY chip switching system, the three systems have very strong coupling, the timing sequence of the PHY chip has a requirement on the time when the clock is stable, and if the reference clock of the PHY chip is unstable, the complete machine function of the switch is finally failed. Meanwhile, the working mode of the switch is complex, including initial power-on startup, cold restart and hot restart, and the clock jitter eliminator chip needs to be configured in all three scenes, and the time sequence requirement of hardware needs to be met.

In addition, a BMC system is also usually provided in the switch system, and this completely independent CPU system monitors the hardware status of the switch. After the clock is stable, the CPU performs reset on the PHY chip, and then the CPU can configure the working mode of the PHY chip, if the clock has a problem and the PHY chip fails to initialize, the function of the whole exchange plane will be invalid. In the boot sequence, the CPU system is always allowed to boot after the BMC system boots, and the time from the stabilization of the PHY chip clock to the resetting of the PHY chip is very short in the design of the boot sequence of the switch. Therefore, as long as the BMC is reasonably designed to configure the software logic of the clock jitter eliminator, the possibility of realizing online update of the configuration firmware of the clock jitter eliminator through the BMC exists.

The present invention will be described in further detail with reference to the accompanying drawings and specific embodiments. It should be apparent that the described embodiments are only some embodiments of the present invention, and not all embodiments. All other embodiments, which can be obtained by a person skilled in the art without making any creative effort based on the embodiments in the present invention, belong to the protection scope of the present invention.

The first embodiment is as follows:

as shown in fig. 1, this embodiment provides an online configuration method for a clock jitter eliminator in a switch, including the following steps:

s1: when the switch is powered on and started for the first time, the BMC sends a starting signal to the CPU.

S2: the model of the clock jitter eliminator is read by the BMC.

Firstly, the BMC reads configuration firmware of a clock jitter eliminator through an I2C interface; the model number of the clock jitter eliminator is identified from the configuration firmware.

S3: and judging whether the jitter eliminator needs to be reconfigured according to the model of the clock jitter eliminator. If yes, executing step S4; if not, step S5 is executed.

Specifically, if the clock jitter eliminator is determined to be a switch customized clock jitter eliminator according to the clock jitter eliminator model, the clock jitter eliminator does not need to be reconfigured; if the clock jitter eliminator is determined to be the same series of clock jitter eliminators adapted to the switch based on the clock jitter eliminator model, the jitter eliminator needs to be reconfigured.

S4: the clock jitter killer is reconfigured by the BMC.

Specifically, the control BMC writes the required configuration firmware into the clock jitter reducer via the I2C interface.

It should be noted that, the time for the BMC to reconfigure the clock jitter eliminator cannot be too long, and must be controlled within 5 seconds, if the configuration time exceeds 5 seconds, the switch plane is powered on and the PHY chip is reset, and if the clock jitter eliminator does not stably output the 156.26MHz clock at this time, the PHY chip cannot normally operate, and the CPU software cannot initialize the PHY chip.

S5: the PHY chip is reset by the CPU.

S6: when the switch runs, the CPU is detected to be in a preset signal state through the BMC, and whether hot restart or cold restart operation occurs is judged.

The preset signals of the CPU comprise a PLT _ RST signal and an S4 signal. When the PLT _ RST is in a falling edge, the system has a shutdown action, if the S4 signal is not changed, the system is a hot restart, the hot restart switching plane is not powered off, and the BMC does not need to repeatedly configure a clock jitter eliminator. After the falling edge of PLT _ RST occurs, the switch plane will be powered off and on during the cold restart, so the clock jitter eliminator needs to be configured again during the cold restart.

And S7. When a cold restart operation occurs, the clock jitter eliminator is again configured.

By way of example, steps S6 and S7 described above implement reconfiguring the clock jitter counter firmware during a switch restart. As shown in fig. 2, the specific process is as follows:

1. and judging whether the PLT _ RST signal has a falling edge or not, if so, executing the next step, and if not, directly ending.

2. And judging whether the signal of S4 has a rising edge, if so, executing the next step, and if not, directly ending.

3. The read clock de-jittering signal.

4. Judging whether the clock jitter eliminator is a clock jitter eliminator of the same series adapted to the switch or not, if so, reconfiguring the clock jitter eliminator through the BMC; if not, the process is ended directly.

The embodiment provides an online configuration method of a clock jitter eliminator in a switch, which can select other custom chips in the same series when the supply voltage of a custom chip of the clock jitter eliminator in the switch is insufficient, and reconfigure firmware for the clock jitter eliminator chip through a BMC (baseboard management controller) chip in the process of initial power-on and restart of the switch without increasing any material cost, thereby ensuring the production of switch products. The method utilizes the BMC system in the switch to control the power-on time sequence of the switch system through the BMC, shortens the online burning time of the BMC configuration clock jitter eliminator, and ensures that the switch can work normally.

Example two:

based on the first embodiment, as shown in fig. 3, the present invention further discloses an online configuration system for a clock jitter eliminator in a switch, including: the device comprises a power-on unit 1, a reading unit 2, a judging unit 3, a configuration unit 4 and a signal identification unit 5.

And the power-on unit 1 is used for sending a power-on signal to the CPU by the BMC when the switch is powered on and started for the first time.

And the reading unit 2 is used for reading the model of the clock jitter eliminator through the BMC.

The reading unit 2 is specifically configured to: reading configuration firmware of the clock jitter eliminator through an I2C interface by using a BMC (baseboard management controller); the model number of the clock jitter eliminator is identified from the configuration firmware.

And a judging unit 3 for judging whether the jitter eliminator needs to be reconfigured according to the model of the clock jitter eliminator. The determining unit 3 is specifically configured to: if the clock jitter eliminator is determined to be a customized clock jitter eliminator of the switch according to the model of the clock jitter eliminator, the clock jitter eliminator does not need to be reconfigured; if the clock jitter eliminator is determined to be a switch-adapted clock jitter eliminator of the same family based on the clock jitter eliminator model, then the jitter eliminator needs to be reconfigured.

And the configuration unit 4 is used for reconfiguring the clock jitter eliminator through the BMC and resetting the PHY chip through the CPU.

And the signal identification unit 5 is used for detecting the preset signal state of the CPU through the BMC when the switch runs and judging whether hot restart or cold restart operation occurs.

The signal identification unit 5 is specifically configured to: detecting the states of a PLT _ RST signal and an S4 signal of the CPU through the BMC; when the PLT _ RST signal has a falling edge and the S4 signal has a rising edge, the cold restart operation of the switch occurs; when the PLT _ RST signal occurs a falling edge and the S4 signal is unchanged, the switch has a warm restart operation.

The embodiment provides an online configuration system of a clock jitter eliminator in a switch, which can select other custom chips in the same series when the supply voltage of a custom chip of the clock jitter eliminator in the switch is insufficient, and reconfigure firmware for the clock jitter eliminator chip through a BMC (baseboard management controller) chip in the process of initial power-on and restart of the switch without increasing any material cost, thereby ensuring the production of switch products.

Example three:

the embodiment discloses an online configuration device of a clock jitter eliminator in a switch, which comprises a processor and a memory; wherein, the processor implements the following steps when executing the online configuration program of the clock jitter eliminator in the switch saved in the memory:

1. when the switch is powered on and started for the first time, the BMC sends a starting signal to the CPU.

2. The model of the clock jitter eliminator is read by the BMC.

3. And judging whether the jitter eliminator needs to be reconfigured according to the model of the clock jitter eliminator. If yes, executing step 4; if not, executing step 5.

4. The clock de-jitterer is reconfigured by the BMC.

5. The PHY chip is reset by the CPU.

6. When the switch runs, the CPU preset signal state is detected through the BMC, and whether hot restart or cold restart operation occurs is judged.

7. When a cold restart operation occurs, the clock de-jitterer is again configured.

Further, the online configuration apparatus of the clock jitter eliminator in the switch in this embodiment may further include:

the input interface is used for acquiring an externally-introduced online configuration program of the clock jitter eliminator in the switch, storing the acquired online configuration program of the clock jitter eliminator in the switch into the memory, and also used for acquiring various instructions and parameters transmitted by external terminal equipment and transmitting the instructions and parameters into the processor, so that the processor performs corresponding processing by using the instructions and the parameters. In this embodiment, the input interface may specifically include, but is not limited to, a USB interface, a serial interface, a voice input interface, a fingerprint input interface, a hard disk reading interface, and the like.

And the output interface is used for outputting various data generated by the processor to the terminal equipment connected with the output interface so that other terminal equipment connected with the output interface can acquire various data generated by the processor. In this embodiment, the output interface may specifically include, but is not limited to, a USB interface, a serial interface, and the like.

And the communication unit is used for establishing a remote communication connection between the online configuration device of the clock jitter eliminator in the switch and the external server so that the online configuration device of the clock jitter eliminator in the switch can mount the image file into the external server. In this embodiment, the communication unit may specifically include, but is not limited to, a remote communication unit based on a wireless communication technology or a wired communication technology.

And the keyboard is used for acquiring various parameter data or instructions input by a user through real-time key cap knocking.

And the display is used for displaying relevant information in the short circuit positioning process of the power supply line of the running server in real time.

The mouse can be used for assisting a user to input data and simplifying the operation of the user.

Example four:

the present embodiments also disclose a readable storage medium, which may include Random Access Memory (RAM), memory, read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, a hard disk, a removable hard disk, a CD-ROM, or any other form of storage medium known in the art. The readable storage medium stores a clock jitter eliminator online configuration program in the switch, and when the clock jitter eliminator online configuration program in the switch is executed by the processor, the method comprises the following steps:

2. The model of the clock jitter eliminator is read by the BMC.

4. The clock jitter killer is reconfigured by the BMC.

5. The PHY chip is reset by the CPU.

7. When a cold restart operation occurs, the clock jitter eliminator is again configured.

In summary, the invention can reconfigure the firmware of the clock jitter eliminator chip according to the requirement in the process of the initial power-on and the restarting of the switch through the BMC chip.

The embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same or similar parts among the embodiments are referred to each other. The method disclosed by the embodiment corresponds to the system disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the description of the method part.

Those of skill would further appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative components and steps have been described above generally in terms of their functionality in order to clearly illustrate this interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.

In the embodiments provided by the present invention, it should be understood that the disclosed system, system and method can be implemented in other ways. For example, the above-described system embodiments are merely illustrative, and for example, the division of the units is only one type of logical functional division, and other divisions may be realized in practice, for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, systems or units, and may be in an electrical, mechanical or other form.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one position, or may be distributed on multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, functional modules in the embodiments of the present invention may be integrated into one processing unit, or each module may exist alone physically, or two or more modules are integrated into one unit.

Similarly, each processing unit in the embodiments of the present invention may be integrated into one functional module, or each processing unit may exist physically, or two or more processing units are integrated into one functional module.

The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in Random Access Memory (RAM), memory, read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

Finally, it should also be noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrases "comprising one of 8230; \8230;" 8230; "does not exclude the presence of additional like elements in a process, method, article, or apparatus that comprises the element.

The method, system, apparatus and readable storage medium for configuring the clock jitter eliminator in the switch in-line provided by the present invention are described in detail above. The principles and embodiments of the present invention are explained herein using specific examples, which are presented only to assist in understanding the method and its core concepts. It should be noted that, for those skilled in the art, without departing from the principle of the present invention, it is possible to make various improvements and modifications to the present invention, and those improvements and modifications also fall within the scope of the claims of the present invention.

Claims

1. An online configuration method for a clock jitter eliminator in a switch is characterized by comprising the following steps:

reading the model of the clock jitter eliminator through the BMC;

if not, directly resetting the PHY chip through the CPU;

when a cold restart operation occurs, the clock de-jitterer is again configured.

2. The method of claim 1, wherein the reading, by the BMC, the model of the clock jitter canceller comprises:

the model of the clock debouncing is identified from the configuration firmware.

3. The method of claim 1, wherein the determining whether the de-jittering device needs to be reconfigured according to the model of the de-jittering device comprises:

4. The method of in-line configuration of a clock jitter reducer in a switch of claim 1, wherein the reconfiguring the clock jitter reducer by the BMC comprises:

and the control BMC writes the required configuration firmware into the clock de-jittering device through an I2C interface.

5. The method of claim 4, wherein the BMC reconfigures the clock jitter handler for a configuration time period of 5 seconds or less.

6. The method of claim 1, wherein the detecting, by the BMC, the preset signal state of the CPU and determining whether a hot restart or a cold restart operation occurs comprises:

7. The method of on-line configuration of a clock jitter eliminator in a switch of claim 6, wherein said reconfiguring the clock jitter eliminator when a cold restart operation occurs comprises:

reading the model of the clock jitter eliminator through the BMC;

if yes, reconfiguring the clock jitter eliminator through the BMC;

if not, the process is ended directly.

8. An in-line configuration system for a clock jitter eliminator in a switch, comprising:

the BMC sends a starting signal to the CPU when the switch is started up by being powered on for the first time;

9. An apparatus for configuring a clock jitter eliminator in a switch online, comprising:

a processor for implementing the steps of the method for configuring a clock jitter eliminator in a switch in-line according to any one of claims 1 to 7 when executing the program for configuring the clock jitter eliminator in the switch in-line.

10. A readable storage medium, characterized by: the readable storage medium has stored thereon an in-switch clock jitter injector in-line configuration program, which when executed by a processor implements the steps of the in-switch clock jitter injector in-line configuration method as claimed in any one of claims 1 to 7.