CN115752814A - Method for producing a capacitive pressure sensor and capacitive pressure sensor - Google Patents

Abstract

The present disclosure relates to a method for manufacturing a microelectromechanical device. The method comprises the following steps: forming a first protective layer of crystalline alumina impermeable to HF on the substrate; forming a sacrificial layer of silicon oxide removable by HF on the first protective layer; forming a second protective layer of crystalline alumina on the sacrificial layer; exposing a sacrificial portion of the sacrificial layer; forming a first membrane layer of porous material permeable to HF on the sacrificial portion; removing the sacrificial part through the first film layer to form a cavity; and sealing the pores of the first membrane layer by forming a second membrane layer on the first membrane layer.

Description

Method for producing a capacitive pressure sensor and capacitive pressure sensor

Technical Field

The present disclosure relates to a method for manufacturing a microelectromechanical (MEMS) device and a microelectromechanical device.

Background

Different techniques are used to form the membrane based on gluing/bonding of the two substrates or based on removal of the sacrificial layer.

For example, US 6,521,965 provides for the fabrication of bottom electrodes; forming a sacrificial region on the bottom electrode; epitaxially growing a film layer; forming an etching hole in the film layer; removing the sacrificial region through the etch hole; and the hole is closed by filling the oxide. US 6,527,961 also describes a similar process for manufacturing a pressure sensor. US 6,012,336 uses metal or silicon nitride to fill the etch holes.

In the process shown, the filling of the etch holes is a critical step. In fact, it is not possible to use conformal materials that would otherwise penetrate into the cavity just formed and cause the cavity to be at least partially filled, resulting in erroneous capacitive coupling. On the other hand, also considering the geometry of narrow and deep holes for applications requiring thick films, the use of non-conformal materials may not allow it to close completely. In fact, typically, the same hole is closed near the top opening before the fill material completely fills the etched hole in the bottom.

Even if two different materials are used (the first non-conformal material narrows the top opening and prevents the second conformal material from penetrating into the cavity), the problem cannot be solved.

Disclosure of Invention

Various embodiments of the present disclosure are directed to processes and devices that overcome the deficiencies of the prior art.

According to the present disclosure, a method for manufacturing a MEMS device and a MEMS device obtained thereby are provided. In particular, the present disclosure relates to the manufacture of capacitive pressure sensors and capacitive pressure sensors obtained thereby. Capacitive pressure sensors are provided with a suspended area or membrane that is movable relative to the rest of the structure. In particular, the membrane represents a variable electrode facing a fixed part forming a fixed electrode and separated from the fixed part by a partially or completely buried cavity.

Drawings

For a better understanding of the present disclosure, embodiments thereof will now be described, by way of non-limiting example only, with reference to the accompanying drawings, in which:

1-14 illustrate in lateral cross-sectional views the manufacturing steps of a microelectromechanical device, in particular a capacitive pressure sensor, according to an embodiment of the present disclosure;

figure 15A illustrates a differential capacitive pressure sensor in a transverse cross-sectional view according to another embodiment of the present disclosure;

FIG. 15B shows a package in which the pressure sensor of FIG. 15A is housed or receivable;

FIG. 16 shows a capacitive pressure sensor according to another embodiment of the present disclosure; and

fig. 17 illustrates a capacitive pressure sensor according to another embodiment of the present disclosure.

Detailed Description

Fig. 1-14 illustrate subsequent fabrication steps of a microelectromechanical (MEMS) device or system 30, according to embodiments of the present disclosure. In particular, the MEMS device 30 integrates a micro-electromechanical structure for converting one or more ambient pressure signals into corresponding electrical signals. In particular, the conversion is performed based on a change in capacitance. Therefore, hereinafter, the MEMS device 30 is also referred to as a pressure sensor or a capacitive pressure sensor.

Fig. 1-14 show the wafer in a transverse cross-sectional view in a three-axis reference system with axes X, Y, Z that are orthogonal to each other.

FIG. 1 showsA wafer 1 is shown, the wafer 1 having a front face 1a and a rear face 1b opposite to each other along an axis Z, the wafer 1 comprising a substrate 2 of semiconductor material, typically silicon. At the front side 1a, the substrate 2 is covered with an insulating layer 3, for example silicon oxide (SiO) having a thickness between 0.2 and 2 μm (typically 0.5 μm) ₂ ). The insulating layer 3 is formed by, for example, thermal oxidation.

In fig. 2, a structural layer 4 of a conductive material, such as N-doped polysilicon (e.g., with a doping density of 1 · 10), is formed on an insulating layer 3 ¹⁹ To 2.10 ²⁰ Ion/cm ³ In between). In one embodiment, structural layer 4 is formed by depositing polysilicon using an LPCVD technique.

Referring to the capacitive pressure sensor, the structural layer 4 forms the bottom electrode of the pressure sensor (i.e., the bottom plate of the capacitor).

Subsequently, fig. 3, the structural layer 4 is patterned (e.g. photolithographically) to define the desired and/or intended shape during the design step of the bottom electrode of the pressure sensor.

The method then continues with fig. 4, forming an etch stop layer 5 over the structural layer 4 (and over the exposed portions of the insulating layer 3). According to an embodiment of the present disclosure, the etch stop layer 5 is aluminum oxide (Al) ₂ O ₃ ) Also known as aluminum oxide (aluminum). The thickness of the etch stop layer 5 is for example a few tens of nanometers, for example between 20 and 60nm, in particular 40nm.

The etch stop layer 5 is formed by an Atomic Layer Deposition (ALD) technique. Deposition of Al by ALD technique ₂ O ₃ Usually, trimethylaluminum (TMA, al (CH) is used ₃ ) ₃ ) And water (H) ₂ O) vapor is performed as a reactant. As H ₂ As an alternative to O vapor, ozone (O) may be used ₃ ). For example, TMA is used as the aluminum source and H ₂ O acts as an oxidizing agent and deposition can occur. Documents by Steven m. George, chem. (rev. 2010,110, p.111-131), or purunen, r.l., j. (appl. Phys.2005,97, p.121-301) describe possible methods for forming the etch stop layer 5.

Patent document WO 2013/061313 also describes a method for forming a sheetAl for the context of the present disclosure ₂ O ₃ A method for etching a stop layer. In particular, the etch stop layer 5 is provided with two Al layers, as described in WO 2013/061313 ₂ O ₃ A process of ALD deposition of an intermediate layer, both of which crystallize. The following sequences: i) First intermediate layer Al ₂ O ₃ Ii) crystallization of the first intermediate layer, iii) second intermediate layer Al ₂ O ₃ And iv) crystallization of the second intermediate layer, allowing the formation of Al ₂ O ₃ An etch stop layer 5, the etch stop layer 5 having the property of being resistant to an etching solution comprising hydrofluoric acid (HF), in particular the property of the etch stop layer 5 of being impermeable to such HF-based solutions.

Furthermore, in addition to being resistant to HF etching and to HF impermeability, the etch stop layer 5 exhibits optimal stiction characteristics for the underlying silicon oxide layer 3 and for the polysilicon layer 4, exhibits optimal dielectric characteristics (which do not change with any subsequent thermal treatments), exhibits a small (negligible) variation of the warp radius of the wafer 1, and exhibits a high degree of compatibility with thermal treatments at high temperatures (above 1000 ℃).

Then, in fig. 5, a sacrificial layer 8 of, for example, silicon oxide is formed. The thickness of this sacrificial layer 8 at the structural layer 4 and above the structural layer 4 is between 0.4 and 2 μm (or in any case chosen according to the capacitance value). In order to compensate for the presence of the "step" between the insulating layer 3 and the structural layer 4, and in order to form the sacrificial layer 8 with a flat top surface, after the sacrificial layer 8 is formed, a planarization step (for example, via CMP) is performed.

Alternatively, the sacrificial layer 8 may be formed in two sub-steps, which, after each other, comprise:

forming a first sacrificial sublayer 8a, here a silicon oxide deposited with a Plasma Enhanced Chemical Vapor Deposition (PECVD) technique (TEOS or silane-based oxide), until the etch stop layer 5 in the region of the etch stop layer 5 extending above the structural layer 4 is completely covered; the thickness tox1 of the first sacrificial sublayer 8a, measured transversely to the structural layer 4 along the Z-axis, is greater than the sum of the thicknesses of the structural layer 4 and the etch stop layer 5 (for example, between 700nm and 1.5 μm);

planarizing the first sacrificial sublayer 8a, for example using CMP techniques, to obtain the same planar top surface, but without exposing portions of the underlying etch stop layer 5;

forming a second sacrificial sublayer 8b over the first sacrificial sublayer 8a, the second sacrificial sublayer 8b here being silicon oxide deposited with PECVD techniques (TEOS or silane-based oxide); the thickness tox-c of the second sacrificial sublayer 8b, measured along the Z-axis from the top surface of the first sacrificial sublayer 8a, is between 300nm and 2 μm.

The first sacrificial sublayer 8a and the second sacrificial sublayer 8b together form the sacrificial layer 8. The thickness of the sacrificial layer 8 is chosen according to the desired capacitance value (e.g. between 500nm and 2.3 μm).

Then, fig. 6, etching is performed on the sacrificial layer 8 to form a trench 10, the trench 10 surrounding or internally defining a region 8' of the sacrificial layer 8. The trench 10 extends along the axis Z over the entire thickness of the sacrificial layer 8. In this way, the region 8' is separated from the rest of the sacrificial layer 8 by the trench 10. The shape of the area 8' defined by the trench 10 corresponds to the desired shape of the cavity with the two conductive plates of the capacitor, which form the sensitive element of the pressure sensor and face each other through the cavity, as can be seen more clearly from the following description.

Then, with reference to fig. 7, the method continues by forming a further etch stop layer 15 over the sacrificial layer 8 (including the region 8') and in the trench 10. According to one embodiment of the present disclosure, the etch stop layer 15 is aluminum oxide (Al) ₂ O ₃ ) With a thickness of a few tens of nanometers, for example between 20 and 60nm, in particular 40nm.

The etch stop layer 15 is formed according to the same method discussed previously for the etch stop layer 5.

Then, fig. 8, the etch stop layer 15 is patterned by removing selective portions above the region 8 'to form a cavity 15a through the etch stop layer 15 until the surface of the region 8' is reached. At least a portion of the surface of region 8' is thus exposed through cavity 15 a. The area of the region 8' exposed in this process step (i.e. the cavity 15 a) defines the shape and spatial extent of the top plate of the capacitor forming the active element of the pressure sensor, as will be more clearly seen from the following description.

Then, fig. 9, a step of depositing a structural layer 16 above the etch stop layer 15 and in the cavity 15a is carried out to cover the surface of the region 8'. In one embodiment, structural layer 16 is a conductive material, such as doped polysilicon (e.g., doped at 1 · 10) ¹⁸ To 2.10 ²⁰ Ion/cm ³ In between). Alternatively, structural layer 16 may be undoped polysilicon.

Structural layer 16 is deposited, for example, using LPCVD techniques. The thickness of the structural layer 16 is for example between 0.2 μm and 1 μm.

Subsequently, fig. 10, structural layer 16 is defined, for example lithographically, to selectively remove structural layer 16 at cavity 15 a. In particular, in one embodiment, structural layer 16 is not completely removed at cavity 15a, so as to leave region 16 'which region 16' serves as an anchor for a subsequent layer (layer 20, shown in fig. 11) to be deposited later. Obviously, in other embodiments, if the anchor does not have to structurally support layer 20 of fig. 11, region 16' is not formed and structural layer 16 is completely removed at cavity 15 a.

Next, FIG. 11, as described above, permeable layer 20 is formed over structural layer 16, anchor regions 16' (if any), and regions 8' exposed between anchor regions 16 '.

In one embodiment of the present disclosure, the permeable layer 20 is polysilicon permeable to the chemical solution used to subsequently remove the region 8'. For example, in the depicted embodiment, where region 8 'is silicon oxide, hydrofluoric acid (HF) or HF-containing solutions may be used to selectively remove region 8'. In this case, the permeable layer 20 is provided with pores or openings to allow hydrofluoric acid to flow through the permeable layer 20 to reach and remove the region 8' and form a buried cavity or chamber 22.

Permeable layer 20 is in particular polysilicon, which has pores (or pores) with a diameter in the range of 1 to 50 nm. The thickness of permeable layer 20 is in the range of 50 to 150nm, for example 100nm. Permeable layer 20 is deposited, for example, by LPCVD techniques. According to an exemplary, non-limiting embodiment, the deposition conditions are such that the silane source gas has a process window of about 600 ℃ in a deposition environment having a pressure of about 550 mtorr in the pull-compression transition region. The size of the pores of permeable layer 20 is typically selected such that the chemical etching solution (liquid or gas) used to remove region 8' can penetrate the pores until permeable layer 20 is reached.

In general, the permeable layer 20 may be porous polysilicon, or polysilicon with pores (openings) that are actively formed by selectively removing material by mechanical or physicochemical action after its deposition.

Referring to fig. 12, the etching step (identified by arrow 21) of the region 8' is performed by a vapor etching technique using HF or a buffered HF mixture or using HF in vapor form. The material of region 8' is completely removed and a buried cavity 22 is formed. As described above, the chemical used for etching penetrates the openings or pores of permeable layer 20.

Next, fig. 13, a sealing layer 24 is formed on the permeable layer 20 (e.g., by performing epitaxial growth of amorphous silicon) to form a second electrode operatively coupled to the first electrode (i.e., layer 4 formed in fig. 3) through the cavity 22. The thickness of the sealing layer 24 is for example between 0.2 μm and 2 μm. SiH can be used as amorphous silicon of sealing layer 24 ₄ /H ₂ Or SiH ₄ the/He is deposited as a precursor by PECVD techniques at a deposition temperature between 200 and 400 ℃. Depending on the application, sealing layer 24 may use Phosphine (PH) ₃ ) Or boranes (B) ₂ H ₆ ) And (4) in-situ doping. In the context of the present disclosure, the sealing layer is electrically conductive (due to doping).

One or more further layers 25 may be deposited or formed on the sealing layer 24, for example one or more layers of corresponding materials with a passivating or enhancing function selected from: polycrystalline silicon, al ₂ O ₃ 、HfO ₂ 、SiN(PE)。

The sealing of the permeable layer 20 (and hence the buried cavity 22) may be performed in a controlled pressure environment (reaction chamber) in order to set a desired pressure value in the buried cavity 22. For example, the pressure value may vary between 0.09mbar and 205 mbar.

However, it is alternatively noted that forming the sealing layer 24 by depositing amorphous silicon using PECVD techniques allows to generate a desired pressure in the buried cavity 22. In fact, the product between the deposition temperature of the layer 24 (about 350 ℃) and the working pressure in the reaction chamber (about 1.5 torr) allows to have a low pressure inside the cavity 22 once the layer 24 has cooled down.

Then, referring to fig. 14, conductive pads 28, 29 are formed to allow external biasing from the sensing electrodes of the pressure sensor thus fabricated. A conductive pad 28 is electrically coupled to the sealing layer 24, while another conductive pad 29 is electrically coupled to the structural layer 4, at the side of the buried cavity 22. The pads 28, 29 are formed by depositing a conductive material (e.g., a metal such as aluminum) and patterning it to achieve the desired expansion of the pads.

In one embodiment, in order to bring the conductive pad 29 into contact with the structural layer 4, a step is performed of selectively removing the layers 25, 24, 20, 16, 15 and possibly the layer 8 (if present in the area where the pad 29 is desired to be formed).

To protect the layers exposed through the openings thus formed, one or more of the layers 25 previously described may be formed after such openings are formed (and thus one or more layers 25 are also deposited within the openings) and before the pads 29 are formed.

Alternatively, the conductive pads 29 may be in electrical contact with the structural layer 4 by conductive paths extending between the structural layer 4 and the conductive pads 29.

A MEMS device 30 is thus formed, in particular a capacitive pressure sensor, even more particularly an absolute pressure sensor, which is configured to sense a pressure variation outside the sensor with respect to a pressure value (fixed value, set during the manufacturing step, as described above) present inside the buried cavity 22.

The pressure sensor 30 is provided with a support (substrate 2 plus layer 3) on which extends a first electrode (layer 4) of a capacitor for capacitive sensing. The first electrode faces the buried cavity 22 (in particular, with the insertion layer 5). A second electrode (layer 20 plus layer 24) extends over the buried cavity 22, opposite the first electrode 4. The first and second electrodes face each other through the buried cavity 22. The second electrode is a membrane configured to deflect along the Z-axis. Pressure changes in the environment outside the pressure sensor 30 result in deflection of the second electrode and consequent changes in the capacitance of the capacitor formed thereby, which are sensed by the conductive pads 28, 29 and processed by the circuitry.

According to a different further embodiment (fig. 15A), the MEMS device is a differential capacitive pressure sensor 30', the differential capacitive pressure sensor 30' being configured to provide a signal identifying a difference between two ambient pressures experienced by the same sensor. The pressure sensor 30 'is manufactured according to the same steps previously described for the pressure sensor 30 (fig. 1-14), with the difference that the cavity 22 has to be connected to the outside in order to be able to operate the sensor 30' as a differential sensor. To this end, the cavity 22 is fluidly connected to the exterior of the pressure sensor 30', for example by means of a suitably arranged passage that allows air (or other gaseous fluid) to flow towards the cavity 22. The resulting deformation of the membrane (second electrode) is indicative of the difference between the first ambient pressure P1 (outside the cavity 22) and the second ambient pressure P2 (inside the cavity 22), and the signal converted by the differential pressure sensor 30' is a differential pressure signal.

Referring to fig. 15B, a differential pressure sensor 30 'is provided with a package 32 (common elements of the pressure sensor 30' and the pressure sensor 30 are identified with the same reference numerals). The package 32 includes an inner housing 33, with the differential pressure sensor 30' housed or disposed in the inner housing 33. The package 32 has a first through opening 32a, the first through opening 32a being configured to put the membrane (second electrode) of the differential pressure sensor 30' in fluid communication with the environment outside the package 32 and forming an access channel for the pressure P1 to the membrane (and not to the cavity 22). The package 32 also has a second through opening 32b, the second through opening 32b being configured to place the cavity 22 in fluid communication with the environment outside the package 32 and forming an access passage for the pressure P2 to the cavity 22 (and not to the membrane). The first and second through openings 32a, 32b are thus formed and connected to the pressure sensor 30' so that inside the package 32 the pressures P1 and P2 remain separated in order to allow correct operation of the pressure sensor in differential mode. In other words, the pressure sensor 30' is mounted in the enclosure 32 such that the access passage to the cavity 22 is connected to the second through opening 32b by a suitable fluid-tight (watertight) arrangement or system to prevent fluid connection of the second through opening 32b with other areas of the internal cavity of the enclosure 32.

Thus, the differential pressure sensor 30' is adapted to be installed in a system/assembly, wherein the first through opening 32a is in communication with a first environment at an ambient pressure P1 and the second through opening 32b is in communication with a second environment having an ambient pressure P2. The first through opening 32a thus forms a passage for a pressure P1, which pressure P1 acts on a first side of the membrane (for example, outside the cavity 22) to deform it. The second through opening 32b forms a respective passage for a pressure P2, which pressure P2 acts on a second side of the membrane opposite the first side (for example, inside the cavity 22) to generate a force that deforms the membrane, which force is opposite to the force generated by the pressure P1. The resulting membrane deformation represents the difference between pressure P1 and pressure P2, and the signal converted by differential pressure sensor 30' is a differential pressure signal.

The patent documents US7,763,487 and US8,008,738 describe packages that may be used in the context of the present disclosure to package a differential-type pressure sensor 30'.

Fig. 16 illustrates another embodiment of a MEMS device according to the present disclosure, which is suitable for use with both pressure sensor 30 and pressure sensor 30'. The MEMS device shown in fig. 16 includes all of the elements and features previously described in the respective embodiments.

The MEMS device of fig. 16 further comprises a further buried cavity or cavity 42 extending into the substrate 2 below the first electrode (i.e. below the layer 4). For example, the buried cavity 42 extends from the bottom of the cavity 22 to a distance d ₁ (measured along the axis Z), the distance d ₁ Between 20 μm and 60 μm. In this way, the portion of wafer 1 above buried cavity 42 forms a further membrane that can be deflected to relieve any residual stresses generated during fabrication, or any residual stresses that may occur during use of MEMS device 30, 30Force, thereby preventing any structural problems such as breakage, cracks, deformation.

For example, the buried cavity 42 may be formed according to the formation process of buried cavities described in US7,763,487 and US8,008,738.

According to another embodiment of the present disclosure, as shown in fig. 17, both the MEMS device 30 and the MEMS device 30' include respective anti-stiction layers 50 inside the buried cavity 22 and/or the buried cavity 42 (if any). For simplicity of description and illustration, the buried cavity 42 is not shown in fig. 17, however, as mentioned above, what has been described also applies to the case where this buried cavity 42 is present.

The anti-stiction layer 50 can completely or partially cover the inner walls of the cavity 22 (and/or the cavity 42).

The material of the anti-stiction layer 50 is selected to limit or prevent partial occlusion of the cavity 22 (and/or cavity 42) due to potential mutual adhesion of the walls bounding the cavity 22 (and/or cavity 42) up and down. This undesirable effect will result in the second electrode not moving properly and in failure of the MEMS device 30/30'.

To this end, the anti-stiction layer 50 can be introduced into the cavity 22 through a suitable opening that communicates the cavity 22 with the environment in which deposition of the anti-stiction layer 50 occurs. This opening may be closed later in the case of an absolute pressure sensor 30, or in the case of a differential pressure sensor 30', an opening for bringing the cavity 22 into fluid communication with the external environment, thus remaining fluid accessible.

The deposition of the anti-adhesion layer 50 may be performed by a vapor phase process.

Materials that may be used for the anti-blocking layer 50 include, but are not limited to, chlorosilanes, trichlorosilane, dichlorosilane, siloxanes, or combinations thereof, and the like, such as:

DDMS- (dimethyldichlorosilane);

FOTS- "perfluoro octyl trichlorosilane";

PF10 TAS- "Perfluorodecyl tris (dimethylamino) silane";

PFDA- "perfluorodecanoic acid"; or

Combinations thereof.

Useful materials and their deposition processes can be found, for example, in the following documents: "Vapor phase anti-stimulation coatings for MEMS" (Device and Materials Reliability, IEEE Transactions on.3.173-178.10.1109/TDMR.2003.821540) by Ashurst, W. & Carraro, C. & Maboudian, roya. (2004).

The above-described fabrication methods and devices have many advantages according to various embodiments.

Due to the monolithic structure of the membrane, which is substantially free of empty regions, the membrane is robust and therefore particularly suitable for providing different types of MEMS structures, thereby reducing the risk of breakage, deformation or damage that undermines its function.

This process is easy to perform, since it does not have any specific critical or execution difficulties, ensuring high yields and reducing the final costs. It should also be noted that this manufacturing method uses a single wafer of semiconductor material, and therefore is economically advantageous and less critical, since there is no gluing or bonding step between the wafers.

Furthermore, the manufacturing method is particularly flexible, as it allows to provide in a simple manner a buried cavity and/or membrane having the desired shape and dimensions in terms of area and thickness. In particular, for applications as pressure sensors, a high thickness of the membrane can be obtained to improve the accuracy of the same sensor.

The use of porous silicon ensures the obtainment of membranes with regular shape and prevents the undesired formation which could damage or in any case reduce the electrical/mechanical characteristics of the finished MEMS device.

The simultaneous presence of two crystalline aluminum oxide layers prevents shorting between the top and bottom electrodes of the capacitor and allows the definition of film diameters that are independent of etch time during the fabrication steps.

Furthermore, since two crystalline alumina layers are used, the dimensions of the film can be precisely defined without using time etching. In fact, the crystallized aluminum oxide acts as a hard mask for the subsequent HF etching with the aim of removing the oxide layer underneath the film.

The use of a layer of polysilicon that is permeable to HF enables the formation of a porous grid that allows HF to penetrate and etch the oxide. The permeable polysilicon also serves as a support for the top layer.

The use of an amorphous silicon layer 24 (deposited by PECVD), thanks to its rapid closure of the porous polysilicon layer, also allows to define the desired pressure in the buried cavity 22. In fact, the product between the deposition temperature (about 350 ℃) and the working pressure in the reaction chamber (about 1.5 torr) allows a high vacuum inside the cavity 22 once the amorphous silicon layer 24 has cooled down. In addition, by using amorphous silicon and performing PECVD deposition, the volume of the cavity 22 is not reduced by unnecessary or waste products (unnecessary or waste products).

Finally, it is apparent that modifications and variations may be made to the methods and apparatus described and illustrated herein without thereby departing from the scope of the present disclosure.

The teachings of the present disclosure may be used to provide different types of MEMS devices relative to those described, such as accelerometers, gyroscopes, resonators, valves, jet printheads, etc., in which case the structure below and/or above the membrane is adjusted according to the intended application. In any case, the size, shape and number of channels are optimized according to the application, and the MEMS device is finished with structures and elements for its operability.

This can be performed using the substrate 2 or a further epitaxial layer formed above the sealing layer 24 if it is desired to integrate electronic components in the same wafer 1.

A method for manufacturing a microelectromechanical device (30: forming a first protective layer (5) impermeable to the etching chemical solution on the substrate (2); forming a sacrificial layer (8, 8') of a material that can be removed by the above-mentioned etching chemical solution on the first protective layer (5); forming a second protective layer (15) impermeable to said etching chemical solution on the sacrificial layer (8, 8'); selectively removing a portion of the second protective layer (15) to expose a respective sacrificial portion (8 ') of the sacrificial layer (8, 8'); forming a first membrane layer (20) of porous material on said sacrificial portion (8'), the first membrane layer (20) being permeable to said etching chemical solution; removing the sacrificial portion (8') through the first membrane layer (20) using the etching chemistry solution to form a cavity (22); and sealing the pores of the first membrane layer (20) by forming a second membrane layer (24) on the first membrane layer (20).

The etching chemical solution may include hydrofluoric acid HF, and the first protective layer (5) and the second protective layer (15) may include crystalline alumina.

The first membrane layer (20) may be porous silicon or silicon having a plurality of through holes or pores.

Forming the second film layer (24) may include depositing doped amorphous silicon by PECVD techniques.

The method may further comprise the steps of: forming a conductive layer (4) on a substrate (2), wherein the step of forming a first protective layer (5) may comprise forming the first protective layer (5) over the conductive layer (4), the conductive layer (4) and the second film layer (24) being capacitively coupled to each other through a cavity (22).

The conductive layer (4) may be doped polysilicon.

The method may further include the step of forming a buried cavity (42) in the substrate (2), the buried cavity (42) being below the cavity (22) and at least partially aligned with the cavity (22).

The method may further comprise the step of fluidly connecting the cavity (22) with an environment outside the microelectromechanical device (30.

The method may further comprise the step of covering the cavity (22) internally by an anti-adhesion layer, and allowing chemical substances including chlorosilane, trichlorosilane, dichlorosilane and siloxane to flow through the through opening.

The method may further comprise the steps of: -arranging said micro-electromechanical device (30; and coupling the one of the first and second inlet channels (32a, 32b) to the through opening by a fluid sealing arrangement or system configured to prevent fluid connection between the inner housing of the package (32) and the cavity (22).

The microelectromechanical device (30.

A micro-electromechanical device (30: a substrate (2); a first protective layer (5) extending over the substrate (2) and impermeable to etching chemical solutions; -a sacrificial layer (8, 8') of material extending over the first protective layer (5) and removable by means of the above-mentioned etching chemical solution; a second protective layer (15) extending over the sacrificial layer (8, 8') and impermeable to said etching chemical solution; a first membrane layer (20) of porous material permeable to said etching chemical solution; a cavity (22) extending between the first film layer (20) and the first protective layer (5); and a second film layer (24) on the first film layer (20) configured to seal pores of the first film layer (20).

The etching chemistry may include hydrofluoric acid (HF), and the first and second protective layers (5, 15) may include crystalline alumina.

The first membrane layer (20) may be porous silicon or silicon having a plurality of through holes or pores.

The second film layer (24) may be doped amorphous silicon.

The device may further comprise a conductive layer (4) on the substrate (2), wherein the first protective layer (5) extends over the conductive layer (4), and wherein the conductive layer (4) and the second film layer (24) may be capacitively coupled to each other through the cavity (22).

The conductive layer (4) may be doped polysilicon.

The device may further include a buried cavity (42) in the substrate (2) below the cavity (22) and at least partially aligned with the cavity (22).

The device may further comprise a through opening fluidly connected between the cavity (22) and an environment outside the microelectromechanical device (30.

The device may further include an anti-stiction layer internally covering the cavity (22), the anti-stiction layer comprising a material selected from the group consisting of chlorosilane, trichlorosilane, dichlorosilane, siloxane.

The device may further comprise a package (32) having an inner housing and provided with a first access channel (32a 32b) and a second access channel (32b 32a) facing said inner housing, wherein one of the first and second access channels (32a 32b) may be coupled to the through opening by a fluid sealing arrangement or system configured to prevent a fluid connection between said inner housing of the package (32) and said cavity (22).

The microelectromechanical device (30.

The various embodiments described above can be combined to provide further embodiments. These and other changes can be made to the embodiments in light of the above detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.

Claims (26)

1. A method for manufacturing a microelectromechanical device, the method comprising:

forming a first protective layer impermeable to an etching chemical solution on a substrate;

forming a sacrificial layer of a material configured to be removed by the etching chemical solution on the first protective layer;

forming a second protective layer impermeable to the etching chemical solution on the sacrificial layer;

exposing a sacrificial portion of the sacrificial layer by selectively removing a portion of the second protective layer;

forming a first membrane layer of porous material on the sacrificial portion, the first membrane layer being permeable to the etching chemistry solution;

removing the sacrificial portion through the first membrane layer using the etch chemistry solution to form a cavity; and

the pores of the first film layer are sealed by forming a second film layer on the first film layer.

2. The method of claim 1, wherein the etching chemistry solution comprises hydrofluoric acid (HF) and the first and second protective layers comprise crystalline alumina.

3. The method of claim 1, wherein the first membrane layer comprises porous silicon or silicon with a plurality of through holes.

4. The method of claim 1, wherein forming the second film layer comprises depositing doped amorphous silicon by a Plasma Enhanced Chemical Vapor Deposition (PECVD) technique.

5. The method of claim 1, further comprising:

forming a conductive layer on the substrate,

wherein forming the first protective layer comprises forming the first protective layer on the conductive layer, an

The conductive layer and the second film layer are capacitively coupled to each other.

6. The method of claim 5, wherein the conductive layer comprises doped polysilicon.

7. The method of claim 1, further comprising:

forming a buried cavity in the substrate, the buried cavity being below and at least partially aligned with the cavity.

8. The method of claim 1, further comprising:

a step of fluidly connecting the cavity with an environment external to the microelectromechanical device through a through opening.

9. The method of claim 8, further comprising:

the cavity is internally covered with an anti-blocking layer by flowing a chemical substance including chlorosilane, trichlorosilane, dichlorosilane, siloxane, or a combination thereof through the through opening.

10. The method of claim 8, further comprising:

disposing the microelectromechanical device within a package, the package including an inner housing, a first access channel, and a second access channel; and

fluidly coupling one of the first access channel or the second access channel to the through opening without a fluid connection between the inner housing of the package and the cavity.

11. The method of claim 1, wherein the microelectromechanical device is a capacitive pressure sensor.

12. A microelectromechanical device comprising:

a substrate;

a first protective layer on the substrate, impermeable to an etching chemical solution;

a sacrificial layer of a material on the first protective layer that can be removed by the etch chemistry solution;

a second protective layer on the sacrificial layer that is impermeable to the etch chemistry solution;

a first membrane layer of porous material permeable to the etching chemical solution;

a cavity between the first film layer and the first protective layer; and

a second film layer on the first film layer configured to seal pores of the first film layer.

13. The device of claim 12, wherein the etching chemistry comprises hydrofluoric acid (HF), and the first and second protective layers comprise crystalline alumina.

14. The device of claim 12, wherein the first membrane layer comprises porous silicon or silicon with a plurality of through-holes.

15. The device of claim 12, wherein the second film layer comprises doped amorphous silicon.

16. The device of claim 12, further comprising:

a conductive layer on the substrate and having a first conductive layer,

wherein the first protective layer is located on the conductive layer, an

The conductive layer and the second film layer are capacitively coupled to each other.

17. The device of claim 16, wherein the conductive layer comprises doped polysilicon.

18. The device of claim 12, further comprising:

a buried cavity in the substrate below and at least partially aligned with the cavity.

19. The device of claim 12, further comprising:

a through opening fluidly connected between the cavity and an environment external to the microelectromechanical device.

20. The device of claim 19, further comprising:

an anti-stiction layer internally covering the cavity, the anti-stiction layer comprising a material selected from the group consisting of chlorosilane, trichlorosilane, dichlorosilane, and siloxane.

21. The device of claim 19, further comprising:

a package comprising an inner housing, a first access passage and a second access passage,

wherein one of the first access channel or the second access channel is fluidly coupled to the through opening without a fluid connection between the inner housing of the package and the cavity.

22. The device of claim 12, wherein the microelectromechanical device is a capacitive pressure sensor.

23. A method, comprising:

forming an insulating layer on a substrate;

forming a first structural layer on the insulating layer;

forming a first etch stop layer on the first structural layer;

forming a sacrificial layer on the first etch stop layer, the sacrificial layer comprising a trench defining a portion of the sacrificial layer;

forming a second etch stop layer on the sacrificial layer and in the trench, the second etch stop layer including an opening aligned with the portion of the sacrificial layer;

forming a second structural layer on the second etch stop layer and in the opening, the second structural layer comprising a plurality of openings aligned with the portion of the sacrificial layer;

forming a permeable layer on the second structural layer; and

forming a cavity by removing the portion of the sacrificial layer.

24. The method of claim 23, further comprising:

a sealing layer is formed on the permeable layer.

25. The method of claim 23, further comprising:

fluidly coupling the chamber to an ambient environment by forming a channel extending through the second etch stop layer, the second structural layer, and the permeable layer.

26. The method of claim 23, further comprising:

an anti-adhesion layer is formed on the walls of the chamber.

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