CN115752524A - Decoding circuit of photoelectric encoder and electronic device - Google Patents
Decoding circuit of photoelectric encoder and electronic device Download PDFInfo
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Abstract
The application provides a decoding circuit of a photoelectric encoder and electronic equipment, wherein the decoding circuit of the photoelectric encoder comprises differential filtering equipment, signal conversion equipment and computing equipment; the differential filtering device is used for sequentially carrying out differential amplification and filtering processing on the two paths of original signals output by the output end of the photoelectric encoder to obtain two paths of processed original signals; the signal conversion equipment is used for converting the first processed original signal into a square wave signal and converting the second processed original signal into a digital signal; the computing equipment is used for respectively converting the square wave signals and the digital signals into angle coarse codes of the photoelectric encoder and angle fine codes of the photoelectric encoder, and determining position values of the photoelectric encoder according to the angle coarse codes and the angle fine codes. Therefore, the control precision of the subsequent photoelectric encoder is greatly improved, and the problem of how to improve the precision of angle measurement of the photoelectric encoder in the existing scheme is solved.
Description
Technical Field
The application relates to the technical field of decoding of encoders, in particular to a decoding circuit of a photoelectric encoder and electronic equipment.
Background
The measurement of the position of the motor rotor is a very important part, and is one of the keys for determining whether a servo system has good stability, high precision, high response speed and the like. At present, there are three main components for measuring the rotation angle of a motor: photoelectric encoder, magnetoelectric encoder and resolver.
The rotary transformer can output the absolute position of the rotor, is high-temperature resistant, corrosion resistant, shockproof and impact resistant, and is particularly suitable for being used in severe environments. However, the resolver needs an excitation signal to work normally, and the processing process and the communication interface of the output signal of the resolver are complicated, so that the application of the resolver is inconvenient.
The magnetoelectric encoder cannot obtain high-quality original voltage signals due to the special structure and principle of the magnetoelectric encoder, and the circuit structure in the subsequent signal processing process is complex, the anti-interference capability is poor, the stability is poor, and the precision and the higher resolution ratio are difficult to ensure.
The photoelectric encoder is a sensor which converts mechanical geometric displacement on an output shaft into pulse or digital quantity through photoelectric conversion, and is widely applied to angle measurement of a servo system at present, and plays a key role in controlling the servo system. With the increasing requirement of the servo system on the precision, how to improve the precision of the angle measurement becomes an urgent problem to be solved.
Disclosure of Invention
The present application provides a decoding circuit of a photoelectric encoder and an electronic device, so as to solve the problem of how to improve the accuracy of the angle measurement of the photoelectric encoder in the existing scheme.
According to an aspect of an embodiment of the present invention, there is provided a decoding circuit of a photoelectric encoder, the decoding circuit of the photoelectric encoder including a differential filtering device, a signal conversion device, and a calculation device; the differential filter device is provided with a first input end, a second input end, a first output end and a second output end, the first input end of the differential filter device and the second input end of the differential filter device are respectively used for being electrically connected with the output end of the photoelectric encoder, and the differential filter device is used for carrying out differential amplification and filtering processing on two paths of original signals output by the output end of the photoelectric encoder in sequence to obtain two paths of processed original signals which are respectively a first processed original signal and a second processed original signal; the signal conversion equipment is provided with a first input end, a second input end, a first output end and a second output end, the first input end of the signal conversion equipment is electrically connected with the first output end of the differential filter equipment, the second input end of the signal conversion equipment is electrically connected with the second output end of the differential filter equipment, and the signal conversion equipment is used for converting the first processed original signal into a square wave signal and converting the second processed original signal into a digital signal; the computing equipment is respectively electrically connected with the first output end of the signal conversion equipment and the second output end of the signal conversion equipment, and is used for respectively converting the square wave signal and the digital signal into the angle coarse code of the photoelectric encoder and the angle fine code of the photoelectric encoder, and determining the position value of the photoelectric encoder according to the angle coarse code and the angle fine code.
Optionally, the signal conversion device includes a shaping circuit and an analog-to-digital converter, the shaping circuit has an input end and an output end, the input end of the shaping circuit is electrically connected to the first output end of the differential filter device, the output end of the shaping circuit is electrically connected to the computing device, and the shaping circuit is configured to convert the first processed original signal into the square wave signal; the analog-to-digital converter is provided with an input end and an output end, the analog-to-digital converter is electrically connected with the second output end of the differential filtering device, the output end of the analog-to-digital converter is electrically connected with the computing device, and the analog-to-digital converter is used for converting the second processed original signal into a digital signal.
Optionally, the shaping circuit includes a first resistor module, a second resistor module, a third resistor module, a fourth resistor module, a first capacitor module, a second capacitor module, and a first comparator, a first end of the first resistor module and a first end of the second resistor module are respectively electrically connected to the first output end of the differential filter device, a second end of the first resistor module is respectively electrically connected to the first end of the third resistor module, the first end of the first capacitor module, and the first input end of the first comparator, a first end of the second resistor module is respectively electrically connected to the first end of the second capacitor module and the second input end of the first comparator, an output end of the first comparator is respectively electrically connected to the second end of the third resistor module, the second end of the first capacitor module, and the first end of the fourth resistor module, a second end of the fourth resistor module is respectively electrically connected to the computing device and the voltage source, and a second end of the second capacitor module is grounded.
Optionally, the two original signals are a first original signal and a second original signal respectively, the differential filtering device includes a first differential amplifying circuit, a first filtering circuit, a second differential amplifying circuit and a second filtering circuit, the first differential amplifying circuit has an input end and an output end, the input end of the first differential amplifying circuit is used for receiving the first original signal, and the first differential amplifying circuit is used for performing differential amplification processing on the first original signal to obtain a first original signal after differential amplification; the first filter circuit is provided with an input end and an output end, the input end of the first filter circuit is electrically connected with the output end of the first differential amplification circuit, the output end of the first filter circuit is electrically connected with the first input end of the signal conversion equipment, and the first filter circuit is used for filtering the first original signal after differential amplification to obtain the first processed original signal; the second differential amplification circuit is provided with an input end and an output end, the input end of the second differential amplification circuit is used for receiving the second original signal, and the second differential amplification circuit is used for carrying out differential amplification processing on the second original signal to obtain a differentially amplified second original signal; the second filter circuit is provided with an input end and an output end, the input end of the second filter circuit is electrically connected with the output end of the second differential amplification circuit, the output end of the second filter circuit is electrically connected with the second input end of the signal conversion equipment, and the second filter circuit is used for filtering the second original signal after differential amplification to obtain the original signal after the second processing.
Optionally, the first differential amplifier circuit includes a fifth resistor module, a sixth resistor module, a seventh resistor module, an eighth resistor module, a ninth resistor module, a tenth resistor module, an eleventh resistor module, a second comparator and a third comparator, a first end of the fifth resistor module is configured to receive a first signal of the first original signal, a first end of the sixth resistor module is configured to receive a second signal of the first original signal, the first signal of the first original signal and the second signal of the first original signal are signals with opposite phases, a second end of the fifth resistor module is electrically connected to the first end of the seventh resistor module and the first input end of the second comparator, a second end of the sixth resistor module is electrically connected to the first end of the eighth resistor module and the second input end of the second comparator, an output end of the second comparator is electrically connected to the second end of the seventh resistor module and the first end of the ninth resistor module, the second end of the ninth resistor module is electrically connected to the third end of the ninth resistor module and the second input end of the eleventh resistor module, and the eleventh resistor module are electrically connected to the second input end of the eleventh resistor module, and the second resistor module are electrically connected to the ground, and the second resistor module, respectively, and the eleventh resistor module are electrically connected to the filter module, and the second resistor module.
Optionally, the first filter circuit includes a twelfth resistor module, a thirteenth resistor module, a fourteenth resistor module, a fifteenth resistor module, a third capacitor module, a fourth capacitor module, and a fourth comparator, a first end of the twelfth resistor module is electrically connected to an output end of the first differential amplifier circuit, a second end of the twelfth resistor module is electrically connected to a first end of the thirteenth resistor module and a first end of the third capacitor module, a second end of the thirteenth resistor module is electrically connected to a first end of the fourth capacitor module and a first input end of the fourth comparator, a second input end of the fourth comparator is electrically connected to a first end of the fourteenth resistor module and a first end of the fifteenth resistor module, an output end of the fourth comparator is electrically connected to a second end of the fifteenth resistor module, a second end of the third capacitor module, and a first input end of the signal conversion device, and a second end of the fourteenth resistor module and a second end of the fourth capacitor module are grounded, respectively.
Optionally, the computing device includes an FPGA chip, the FPGA chip has a first input end, a second input end and an output end, the first input end of the FPGA chip is electrically connected with the first output end of the signal conversion device, the second input end of the FPGA chip is electrically connected with the second output end of the signal conversion device, the FPGA chip is used for converting the square wave signal and the digital signal into the angle coarse code of the photoelectric encoder and the angle fine code of the photoelectric encoder respectively, and determining the position value of the photoelectric encoder according to the angle coarse code and the angle fine code.
Optionally, the decoding circuit of the photoelectric encoder further includes a controller, the controller is electrically connected to the output end of the FPGA chip, and the controller is configured to control the photoelectric encoder by using the position value of the photoelectric encoder.
Optionally, the controller is a digital signal processing chip.
According to another aspect of the embodiments of the present invention, there is further provided an electronic device, where the electronic device includes any one of the decoding circuits of the photoelectric encoder.
In the embodiment of the invention, the angle coarse code of the photoelectric encoder and the angle fine code of the photoelectric encoder are respectively converted by computing equipment according to the square wave signal and the digital signal output by the signal conversion equipment, and the position value of the photoelectric encoder is determined according to the angle coarse code and the angle fine code, so that the control precision of the subsequent photoelectric encoder is greatly improved, and the problem of how to improve the precision of the angle measurement of the photoelectric encoder in the existing scheme is solved.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this application, illustrate embodiments of the application and, together with the description, serve to explain the application and are not intended to limit the application. In the drawings:
FIG. 1 shows a schematic diagram of a decoding circuit of an optoelectronic encoder according to an embodiment of the present application;
FIG. 2 shows a schematic diagram of a shaping circuit according to an embodiment of the present application;
fig. 3 shows a schematic diagram of a first differential amplifying circuit according to an embodiment of the present application;
fig. 4 shows a schematic diagram of a first filter circuit according to an embodiment of the application.
Wherein the figures include the following reference numerals:
100. a differential filtering device; 200. a signal conversion device; 300. a computing device.
Detailed Description
It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict. The present application will be described in detail below with reference to the embodiments with reference to the attached drawings.
In order to make the technical solutions better understood by those skilled in the art, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only partial embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that the terms "first," "second," and the like in the description and claims of this application and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It should be understood that the data so used may be interchanged under appropriate circumstances such that embodiments of the application described herein may be used. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. Also, in the specification and claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element or "connected" to the other element through a third element.
As mentioned in the background art, the photoelectric encoder is a sensor that converts the mechanical geometric displacement on the output shaft into a pulse or digital quantity through photoelectric conversion, and is widely used in the angular measurement of the servo system, and plays a key role in the control of the servo system. With the increasing requirement of the servo system on the precision, how to improve the precision of the angle measurement becomes a problem to be solved urgently, and in order to solve the problem of how to improve the precision of the angle measurement of the photoelectric encoder in the existing scheme, in a typical embodiment of the present application, a decoding circuit and an electronic device of the photoelectric encoder are provided.
According to an embodiment of the present application, there is provided a decoding circuit of a photoelectric encoder, as shown in fig. 1, including a differential filtering device 100, a signal conversion device 200, and a computing device 300; the differential filter device 100 has a first input end, a second input end, a first output end and a second output end, the first input end of the differential filter device 100 and the second input end of the differential filter device 100 are respectively used for being electrically connected with the output end of the photoelectric encoder, the differential filter device 100 is used for sequentially performing differential amplification and filtering processing on two paths of original signals output by the output end of the photoelectric encoder to obtain two paths of processed original signals, namely a first processed original signal and a second processed original signal; the signal conversion device 200 has a first input terminal, a second input terminal, a first output terminal and a second output terminal, the first input terminal of the signal conversion device 200 is electrically connected to the first output terminal of the differential filter device 100, the second input terminal of the signal conversion device 200 is electrically connected to the second output terminal of the differential filter device 100, the signal conversion device 200 is configured to convert the first processed original signal into a square wave signal, and convert the second processed original signal into a digital signal; the computing device 300 is electrically connected to a first output terminal of the signal converting device 200 and a second output terminal of the signal converting device 200, respectively, and the computing device 300 is configured to convert the square wave signal and the digital signal into an angle coarse code of the photoelectric encoder and an angle fine code of the photoelectric encoder, respectively, and determine a position value of the photoelectric encoder according to the angle coarse code and the angle fine code.
In the circuit, the square wave signal and the digital signal output by the signal conversion equipment are converted into the angle coarse code of the photoelectric encoder and the angle fine code of the photoelectric encoder respectively through the computing equipment, and the position value of the photoelectric encoder is determined according to the angle coarse code and the angle fine code, so that the control precision of the subsequent photoelectric encoder is greatly improved, and the problem of how to improve the precision of the angle measurement of the photoelectric encoder in the existing scheme is solved.
In an embodiment of the present application, the signal conversion device includes a shaping circuit and an analog-to-digital converter, the shaping circuit has an input end and an output end, the input end of the shaping circuit is electrically connected to the first output end of the differential filter device, the output end of the shaping circuit is electrically connected to the computing device, and the shaping circuit is configured to convert the first processed original signal into the square wave signal; the analog-to-digital converter is provided with an input end and an output end, the analog-to-digital converter is electrically connected with the second output end of the differential filtering device, the output end of the analog-to-digital converter is electrically connected with the computing device, and the analog-to-digital converter is used for converting the second processed original signal into a digital signal.
Specifically, the first processed original signal is converted into a square wave signal through a shaping circuit, and the second processed original signal is converted into a digital signal through an analog-to-digital converter, so that subsequent calculation of an angle coarse code and an angle fine code is facilitated. The analog-to-digital converter is AD7612, and the AD7612 is an analog-to-digital converter (ADC) of a 16-bit charge redistribution Successive Approximation Register (SAR) architecture, and the input range and the working mode of the device can be configured through hardware or a special write-only serial configuration port. The AD7612 incorporates a 16-bit high-speed sampling ADC, an internal conversion clock, an internal reference voltage source (and buffer), error correction circuitry, and serial and parallel system interface ports. On the falling edge of CNVST, it samples the voltage difference between IN + and IN-. The AD7612 is adapted for highest asynchronous throughput in normal mode and power consumption is linearly proportional to throughput in burst mode. For the data reading time sequence in normal operation, EXT/INT = high level is set, an external clock signal provided by an SDCLK pin is used as a reading clock of AD7612 serial data, and in a serial slave mode, the design reads the AD7612 data after setting and converting the data reading mode
In an embodiment of the present application, as shown in fig. 2, the shaping circuit includes a first resistor module R1, a second resistor module R2, a third resistor module R3, a fourth resistor module R4, a first capacitor module C1, a second capacitor module C2, and a first comparator Q1, a first end of the first resistor module R1 and a first end of the second resistor module R2 are respectively electrically connected to a first output end of the differential filter device, a second end of the first resistor module R1 is respectively electrically connected to a first end of the third resistor module R3, a first end of the first capacitor module C1, and a first input end of the first comparator Q1, a first end of the second resistor module R2 is respectively electrically connected to a first end of the second capacitor module C2 and a second input end of the first comparator Q1, an output end of the first comparator Q1 is respectively electrically connected to a second end of the third resistor module R3, a second end of the first capacitor module C1, and a second end of the fourth resistor module R4, and a second end of the second resistor module R2 and a second end of the fourth resistor module R4 are respectively electrically connected to a ground, and a second end of the second resistor module R2 and a ground connection module R2 are respectively electrically connected to the ground connection of the voltage source of the differential filter device. The shaping circuit further comprises a voltage stabilizing resistor R16 which is connected in a manner shown in figure 2. The shaping circuit can compare the voltage of the input signal to obtain a square wave signal.
Specifically, a voltage comparator chip LM339 is adopted to carry out voltage comparison on signals transmitted by the differential filter equipment to obtain a resolved square wave signal for counting, and then the resolved square wave signal is transmitted to computing equipment, namely an I/O pin of the FPGA. The LM339 is internally provided with four independent comparators with lower offset voltage and higher working voltage.
In an embodiment of the present application, the two paths of original signals are a first original signal and a second original signal, respectively, the differential filtering device includes a first differential amplifying circuit, a first filter circuit, a second differential amplifying circuit, and a second filter circuit, the first differential amplifying circuit has an input end and an output end, the input end of the first differential amplifying circuit is configured to receive the first original signal, and the first differential amplifying circuit is configured to perform differential amplification on the first original signal to obtain a differentially amplified first original signal; the first filter circuit has an input end and an output end, the input end of the first filter circuit is electrically connected with the output end of the first differential amplification circuit, the output end of the first filter circuit is electrically connected with the first input end of the signal conversion device, and the first filter circuit is used for filtering the first original signal after differential amplification to obtain the first processed original signal; the second differential amplification circuit is provided with an input end and an output end, the input end of the second differential amplification circuit is used for receiving the second original signal, and the second differential amplification circuit is used for carrying out differential amplification processing on the second original signal to obtain a differentially amplified second original signal; the second filter circuit has an input end and an output end, the input end of the second filter circuit is electrically connected to the output end of the second differential amplifier circuit, the output end of the second filter circuit is electrically connected to the second input end of the signal conversion device, and the second filter circuit is configured to filter the second original signal after differential amplification to obtain the second processed original signal.
Specifically, two paths of original signals are processed through a first differential amplification circuit, a first filter circuit, a second differential amplification circuit and a second filter circuit, so that a first processed original signal and a second processed original signal are obtained, and a subsequent FPGA chip can process the first processed original signal and the second processed original signal conveniently. The first differential amplifying circuit and the second differential amplifying circuit, the first filter circuit and the second filter circuit are respectively the same, so that the first differential amplifying circuit and the first filter circuit are explained only in the application, and the second differential amplifying circuit and the second filter circuit are not repeated.
In an embodiment of the present application, as shown in fig. 3, the first differential amplifier circuit includes a fifth resistor module R5, a sixth resistor module R6, a seventh resistor module R7, an eighth resistor module R8, a ninth resistor module R9, a tenth resistor module R10, an eleventh resistor module R11, a second comparator Q2, and a third comparator Q3, a first end of the fifth resistor module R5 is configured to receive a first signal of the first original signal, a first end of the sixth resistor module R6 is configured to receive a second signal of the first original signal, a first signal of the first original signal and a second signal of the first original signal are opposite-phase signals, a second end of the fifth resistor module R5 is electrically connected to a first end of the seventh resistor module R7 and a first input end of the second comparator Q2, a second end of the sixth resistor module R6 is electrically connected to a first end of the eighth resistor module R8 and a first end of the second comparator Q2, a second end of the sixth resistor module R6 is electrically connected to a second end of the eighth resistor module R8 and a second input end of the second comparator Q2, a second end of the sixth resistor module R3 is electrically connected to a second input end of the ninth resistor module R8, a second resistor module R9 and a tenth resistor module R3 are electrically connected to a second input end of the ninth resistor module R3, and a second terminal of the tenth resistor module R3, and a third resistor module R3 are electrically connected to the tenth input terminal of the filter module R3, and the ninth resistor module R3. The first differential amplifying circuit can suppress the direct current component in the first original signal, and the accuracy of the signal is improved.
In an embodiment of the present application, as shown in fig. 4, the first filter circuit includes a twelfth resistor module R12, a thirteenth resistor module R13, a fourteenth resistor module R14, a fifteenth resistor module R15, a third capacitor module C3, a fourth capacitor module C4, and a fourth comparator Q4, a first end of the twelfth resistor module R12 is electrically connected to an output end of the first differential amplifier circuit, a second end of the twelfth resistor module R12 is electrically connected to a first end of the thirteenth resistor module R13 and a first end of the third capacitor module C3, a second end of the thirteenth resistor module R13 is electrically connected to a first end of the fourth capacitor module C4 and a first input end of the fourth comparator Q4, a second input end of the fourth comparator Q4 is electrically connected to a first end of the fourteenth resistor module R14 and a first end of the fifteenth resistor module R15, an output end of the fourth comparator Q4 is electrically connected to a second end of the fifteenth resistor module R15, a second end of the third resistor module R3, a second end of the fourteenth capacitor module R14, and a second end of the fourth capacitor module R4 are electrically connected to a ground, and a second end of the fourth capacitor module R4 are electrically connected to the ground. The first filter circuit can eliminate a high-frequency signal because the signal processed by the first differential amplifier circuit contains a high-frequency signal.
As shown in fig. 2, 3 and 4, the power supply terminals of the first comparator Q1, the second comparator Q2, the third comparator Q3 and the second comparator Q4 are also electrically connected to a negative feedback voltage source of-15V, respectively.
The signal output by the incremental photoelectric encoder is a differential signal containing a direct current component. These dc components affect the accuracy of the construction and subdivision of the subsequent tangent function, and in this application, the dc components in the original signal are removed. The differential circuit has great amplification capacity on differential mode signals and good inhibition capacity on common mode signals, the direct current component in the output signals belongs to the common mode signals, and for the subsequent circuit processing, the first differential amplification circuit and the second differential amplification circuit of the differential filter device are adopted to process the signals to eliminate the direct current component. The electrical signal output by the encoder is small in amplitude and can be properly amplified by the first differential amplifying circuit and the second differential amplifying circuit. With the OPA2312 comparator, the dc level deviation of the OPA2312 is low and the low-drift supply voltage can be between + 4V to + 22V.
The signal after passing through the differential amplification circuit contains more high-frequency signals, in the design, a second-order Butterworth filter with better smoothness is adopted to eliminate the influence of the high-frequency signals, a negative feedback is connected between an output end and an input end in an amplifier of the filter circuit, the polarity of the feedback is different according to different frequency bands, when the frequency of the signal output from the differential amplification circuit is greater than the cut-off frequency of the filter, the phase is shifted to-180 degrees after passing through two stages of RC circuits (namely C3 and R11, C4 and R14), at the moment, the capacitor C3 is formed into negative feedback, the phase of the output signal is opposite to the input, and therefore the high-frequency signals are effectively restrained.
In an embodiment of the application, the computing device includes an FPGA chip, the FPGA chip has a first input end, a second input end and an output end, the first input end of the FPGA chip is electrically connected to the first output end of the signal conversion device, the second input end of the FPGA chip is electrically connected to the second output end of the signal conversion device, and the FPGA chip is configured to convert the square wave signal and the digital signal into the angle coarse code of the photoelectric encoder and the angle fine code of the photoelectric encoder, respectively, and determine the position value of the photoelectric encoder according to the angle coarse code and the angle fine code.
Specifically, the model of the FPGA chip is 5CSEBA5U23I7.
In an embodiment of the present application, the decoding circuit of the photoelectric encoder further includes a controller, the controller is electrically connected to an output end of the FPGA chip, and the controller is configured to control the photoelectric encoder by using a position value of the photoelectric encoder. The position value obtained after the processing is more accurate compared with the existing scheme, so that the subsequent control of the photoelectric encoder is more accurate.
The FPGA chip and the DSP (namely a digital signal processing chip) carry out data communication through a ZONEO data bus and an address bus of an external interface XINTF, and an address line is set to be 0x2000. The DSP is provided with a 16-bit data bus XINTF, and the 16-bit data bus XINTF can be used as an external interface to be connected with an external memory and equipment. The FPGA chip can realize the connection with a 16-bit data bus by defining the I/O port of the FPGA chip, and then the DSP chip and the FPGA chip can select two optional I/O ports as reading and writing zone bits respectively. By setting 16I/O ports on the FPGA chip to the inout state, these I/O ports are then connected to the 16-bit data bus on the DSP. The GPIOB0 and GPIOB1 ports on the DSP are respectively connected with a Read _ flag and a Write _ flag of the FPGA chip, and the WR and RD ports of the DSP are respectively connected with two free I/O ports in the FPGA during reading and writing. When data in an FPGA chip is transmitted to a DSP, a Read _ flag of the FPGA is set to be 1, the DSP inquires the level of an I/O port of the Read _ flag, and when the inquired level is a high level, the DSP reads the data on a data bus by setting an RD port to be zero; and if the DSP performs read-Write operation on the FPGA, the DSP sets the Write _ flag to be 1 to inform the FPGA chip of the read-Write operation, and when the WR of the enabling end of the DSP is zero, the FPGA chip reads data on the 16-bit bus. In an embodiment of the present application, the controller is a digital signal processing chip. The model of the digital signal processing chip is TMS320F2812DSP.
The application also provides an electronic device comprising the decoding circuit of any one of the photoelectric encoders. The angle coarse code of the photoelectric encoder and the angle fine code of the photoelectric encoder are respectively converted by the computing equipment according to the square wave signal and the digital signal output by the signal conversion equipment, and the position value of the photoelectric encoder is determined according to the angle coarse code and the angle fine code, so that the control precision of the subsequent photoelectric encoder is greatly improved, and the problem of how to improve the precision of the angle measurement of the photoelectric encoder in the existing scheme is solved.
It should be noted that the above electrical connection may be a direct electrical connection or an indirect electrical connection, where a direct electrical connection means that two devices are directly connected, and an indirect electrical connection means that other devices, such as a capacitor and a resistor, are also connected between a and B that are connected.
It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising a … …" does not exclude the presence of another identical element in a process, method, article, or apparatus that comprises the element.
From the above description, it can be seen that the above-described embodiments of the present application achieve the following technical effects:
1) The utility model provides a photoelectric encoder's decoding circuit converts the angle coarse code of above-mentioned photoelectric encoder and the angle fine code of above-mentioned photoelectric encoder into respectively according to the square wave signal and the digital signal of signal conversion equipment output through the calculating equipment to according to above-mentioned angle coarse code and the fine code of above-mentioned angle, confirm above-mentioned photoelectric encoder's position value, thereby improved follow-up above-mentioned photoelectric encoder's control accuracy greatly, and then solved the problem of how to improve photoelectric encoder's among the current scheme angle measurement's precision.
2) The utility model provides an electronic equipment converts the angle coarse code of above-mentioned photoelectric encoder and the angle fine code of above-mentioned photoelectric encoder into respectively through the square wave signal of calculating equipment output and digital signal to according to above-mentioned angle coarse code and the fine code of above-mentioned angle, confirm above-mentioned photoelectric encoder's position value, thereby improved follow-up above-mentioned photoelectric encoder's control accuracy greatly, and then solved the problem of how to improve photoelectric encoder's among the current scheme angle measurement's precision.
The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (10)
1. A decoding circuit of an optical-to-electrical encoder, comprising:
the differential filter device is provided with a first input end, a second input end, a first output end and a second output end, the first input end of the differential filter device and the second input end of the differential filter device are respectively used for being electrically connected with the output end of the photoelectric encoder, and the differential filter device is used for carrying out differential amplification and filtering processing on two paths of original signals output by the output end of the photoelectric encoder in sequence to obtain two paths of processed original signals which are respectively a first processed original signal and a second processed original signal;
the signal conversion equipment is provided with a first input end, a second input end, a first output end and a second output end, the first input end of the signal conversion equipment is electrically connected with the first output end of the differential filter equipment, the second input end of the signal conversion equipment is electrically connected with the second output end of the differential filter equipment, and the signal conversion equipment is used for converting the first processed original signal into a square wave signal and converting the second processed original signal into a digital signal;
and the computing equipment is respectively and electrically connected with the first output end of the signal conversion equipment and the second output end of the signal conversion equipment, and is used for respectively converting the square wave signal and the digital signal into the angle coarse code of the photoelectric encoder and the angle fine code of the photoelectric encoder and determining the position value of the photoelectric encoder according to the angle coarse code and the angle fine code.
2. The decoding circuit of the photoelectric encoder according to claim 1, wherein the signal conversion apparatus comprises:
the shaping circuit is provided with an input end and an output end, the input end of the shaping circuit is electrically connected with the first output end of the differential filter device, the output end of the shaping circuit is electrically connected with the computing device, and the shaping circuit is used for converting the first processed original signal into the square wave signal;
and the analog-to-digital converter is provided with an input end and an output end, the analog-to-digital converter is electrically connected with the second output end of the differential filtering device, the output end of the analog-to-digital converter is electrically connected with the computing device, and the analog-to-digital converter is used for converting the second processed original signal into a digital signal.
3. The decoding circuit of the optical-electrical encoder according to claim 2, wherein the shaping circuit comprises a first resistor module, a second resistor module, a third resistor module, a fourth resistor module, a first capacitor module, a second capacitor module and a first comparator, a first end of the first resistor module and a first end of the second resistor module are electrically connected to the first output end of the differential filter device, a second end of the first resistor module is electrically connected to a first end of the third resistor module, a first end of the first capacitor module and a first input end of the first comparator, a first end of the second resistor module is electrically connected to a first end of the second capacitor module and a second input end of the first comparator, an output end of the first comparator is electrically connected to a second end of the third resistor module, a second end of the first capacitor module and a first end of the fourth resistor module, a second end of the fourth resistor module is electrically connected to the computing device and the voltage source, and a second end of the second capacitor module is grounded.
4. The decoding circuit of claim 1, wherein the two original signals are a first original signal and a second original signal, respectively, and the differential filtering device comprises:
the first differential amplification circuit is provided with an input end and an output end, the input end of the first differential amplification circuit is used for receiving the first original signal, and the first differential amplification circuit is used for carrying out differential amplification processing on the first original signal to obtain a first original signal after differential amplification;
the first filter circuit is provided with an input end and an output end, the input end of the first filter circuit is electrically connected with the output end of the first differential amplification circuit, the output end of the first filter circuit is electrically connected with the first input end of the signal conversion equipment, and the first filter circuit is used for filtering the first original signal after differential amplification to obtain the first processed original signal;
the input end of the second differential amplification circuit is used for receiving the second original signal, and the second differential amplification circuit is used for carrying out differential amplification processing on the second original signal to obtain a differentially amplified second original signal;
and the second filter circuit is provided with an input end and an output end, the input end of the second filter circuit is electrically connected with the output end of the second differential amplification circuit, the output end of the second filter circuit is electrically connected with the second input end of the signal conversion equipment, and the second filter circuit is used for filtering the second original signal after differential amplification to obtain the second processed original signal.
5. The decoding circuit of claim 4, wherein the first differential amplifying circuit comprises a fifth resistor module, a sixth resistor module, a seventh resistor module, an eighth resistor module, a ninth resistor module, a tenth resistor module, an eleventh resistor module, a second comparator and a third comparator, a first end of the fifth resistor module is configured to receive a first signal of the first original signal, a first end of the sixth resistor module is configured to receive a second signal of the first original signal, the first signal of the first original signal and the second signal of the first original signal are opposite signals, and a second end of the fifth resistor module is electrically connected to a first end of the seventh resistor module and a first input end of the second comparator respectively, the second end of the sixth resistance module is electrically connected with the first end of the eighth resistance module and the second input end of the second comparator, the output end of the second comparator is electrically connected with the second end of the seventh resistance module and the first end of the ninth resistance module, the second end of the ninth resistance module is electrically connected with the first input end of the third comparator and the first end of the tenth resistance module, the second input end of the third comparator is electrically connected with the first end of the eleventh resistance module, the output end of the third comparator is electrically connected with the second end of the tenth resistance module and the input end of the first filter circuit, and the second end of the eleventh resistance module and the second end of the eighth resistance module are grounded.
6. The decoding circuit of claim 4, wherein the first filtering circuit comprises a twelfth resistor module, a thirteenth resistor module, a fourteenth resistor module, a fifteenth resistor module, a third capacitor module, a fourth capacitor module, and a fourth comparator, a first end of the twelfth resistor module is electrically connected to an output end of the first differential amplifier circuit, a second end of the twelfth resistor module is electrically connected to a first end of the thirteenth resistor module and a first end of the third capacitor module, a second end of the thirteenth resistor module is electrically connected to a first end of the fourth capacitor module and a first input end of the fourth comparator, a second input end of the fourth comparator is electrically connected to a first end of the fourteenth resistor module and a first end of the fifteenth resistor module, a second end of the fourth comparator is electrically connected to a second end of the fifteenth resistor module, a second end of the third capacitor module, and a first input end of the signal conversion device, and a second end of the fourteenth resistor module and a second end of the fourth capacitor module are electrically connected to a ground.
7. The decoding circuit of an optoelectronic encoder according to any one of claims 1 to 6, wherein the computing device comprises:
the FPGA chip is provided with a first input end, a second input end and an output end, the first input end of the FPGA chip is electrically connected with the first output end of the signal conversion equipment, the second input end of the FPGA chip is electrically connected with the second output end of the signal conversion equipment, the FPGA chip is used for converting the square wave signals and the digital signals into the angle coarse codes of the photoelectric encoder and the angle fine codes of the photoelectric encoder respectively, and determining the position value of the photoelectric encoder according to the angle coarse codes and the angle fine codes.
8. The decoding circuit of the optical-electrical encoder according to claim 7, further comprising a controller electrically connected to the output terminal of the FPGA chip, wherein the controller is configured to control the optical-electrical encoder using the position value of the optical-electrical encoder.
9. The decoding circuit of the optical-electrical encoder according to claim 8, wherein the controller is a digital signal processing chip.
10. An electronic device, characterized in that it comprises a decoding circuit of an optoelectronic encoder according to any one of claims 1 to 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211482374.2A CN115752524A (en) | 2022-11-24 | 2022-11-24 | Decoding circuit of photoelectric encoder and electronic device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211482374.2A CN115752524A (en) | 2022-11-24 | 2022-11-24 | Decoding circuit of photoelectric encoder and electronic device |
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| CN115752524A true CN115752524A (en) | 2023-03-07 |
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| CN202211482374.2A Pending CN115752524A (en) | 2022-11-24 | 2022-11-24 | Decoding circuit of photoelectric encoder and electronic device |
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| Country | Link |
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| CN (1) | CN115752524A (en) |
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