CN115731865B - Array substrate and display panel - Google Patents
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- CN115731865B CN115731865B CN202211520686.8A CN202211520686A CN115731865B CN 115731865 B CN115731865 B CN 115731865B CN 202211520686 A CN202211520686 A CN 202211520686A CN 115731865 B CN115731865 B CN 115731865B
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- 239000000758 substrate Substances 0.000 title claims abstract description 32
- 239000003990 capacitor Substances 0.000 claims description 37
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- 238000010586 diagram Methods 0.000 description 12
- 230000000694 effects Effects 0.000 description 6
- 229920001621 AMOLED Polymers 0.000 description 2
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- 238000005859 coupling reaction Methods 0.000 description 2
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- 238000012986 modification Methods 0.000 description 2
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Abstract
The application discloses an array substrate, which comprises a plurality of scanning lines, a plurality of data lines and a plurality of pixel units which are arranged in an array, wherein each pixel unit comprises an initial pre-charging module, a driving module, a light-emitting module and an initialization node, the initial pre-charging module receives scanning signals from the ith-a scanning lines in a pre-charging period, receives pre-charging voltage to pre-charge an initialization voltage end to a preset potential under the control of the scanning signals, and transmits the initialization voltage to the light-emitting module to execute initialization under the control of the scanning signals output by the ith scanning lines in a data writing period. The driving module receives a data signal under the control of a scan signal output from an ith scan line in a data writing period to drive the light emitting module to emit light and perform image display. The initializing speed of the pixel unit can be effectively improved by precharging the initializing voltage terminal. The application also discloses a display panel comprising the array substrate.
Description
Technical Field
The application relates to the technical field of display, in particular to an array substrate and a display panel.
Background
An Organic Light-Emitting Diode (OLED) display device has many advantages of self-luminescence, low driving voltage, high luminous efficiency, short response time, high definition and contrast, a viewing angle of nearly 180 degrees, wide use temperature range, capability of realizing flexible display, large-area full-color display, and the like, and is considered as a display device with the most development potential in the industry.
Currently, in Active-matrix organic light Emitting diodes (AMOLED), an OLED needs to be initialized with a voltage before each light emission to prevent charges from remaining, so that the display effect is poor. Therefore, increasing the voltage initialization speed of the OLED is a problem to be solved.
Disclosure of Invention
In view of the above-mentioned shortcomings, the present application provides an array substrate and a display panel capable of effectively increasing the voltage initialization speed of an OLED.
The application discloses an array substrate which comprises a plurality of scanning lines, a plurality of data lines and a plurality of pixel units, wherein the scanning lines extend along a first direction and are sequentially arranged along a second direction, the data lines extend along the second direction and are arranged along the first direction, and the pixel units are arranged in an array mode, and the first direction is different from the second direction. The pixel unit comprises an initial pre-charging module, a driving module, a light-emitting module and an initialization node, wherein the initial pre-charging module is connected with the light-emitting module through the initialization node, and the driving module is connected with the light-emitting module through the initialization node. For any pixel unit in the ith row, a precharge period and a data writing period are sequentially included in a frame image display period, wherein an initial precharge module is connected with the ith scanning line, the ith-a scanning line, a precharge voltage end and an initialization voltage end, a is a positive integer, i is a positive integer larger than a, the initial precharge module receives scanning signals from the ith-a scanning line in the precharge period and receives precharge voltage provided by the precharge voltage end under the control of the scanning signals, and the precharge voltage is used for precharging the initialization voltage end to a preset potential; in the data writing period, the initial pre-charging module receives an initialization voltage from an initialization voltage terminal and transmits the initialization voltage to the light emitting module through an initialization node under the control of a scanning signal output by an ith scanning line so as to initialize the light emitting module. The driving module is connected to the ith scanning line, the data line and the power supply voltage, receives a scanning signal from the ith scanning line in a data writing period, receives a data signal under the control of the scanning signal, and is used for driving the light emitting module to emit light and execute image display.
Optionally, the initial pre-charging module includes a pre-charging unit and an initialization control unit, the pre-charging unit is connected to the initialization control unit, the ith-a scanning line, the pre-charging voltage end and the initialization voltage end, and is configured to receive a scanning signal from the ith-a scanning line during a pre-charging period, receive the pre-charging voltage under control of the scanning signal as the initialization voltage end to perform pre-charging to a preset potential, and receive the initialization voltage from the initialization voltage end during a data writing period, and transmit the initialization voltage to the initialization control unit.
Optionally, the initialization control unit is connected to the ith scanning line, the pre-charging unit and the initialization node, and is configured to receive a scanning signal from the ith scanning line in a data writing period, and transmit an initialization voltage received from the pre-charging unit to the light emitting module through the initialization node under control of the scanning signal, so as to perform initialization on the light emitting module.
Optionally, the driving module includes a signal receiving unit and a voltage stabilizing driving unit, where the signal receiving unit is connected to the ith scanning line and the data line, and is configured to receive a scanning signal from the ith scanning line in a data writing period, receive a data signal from the data line under control of the scanning signal, and transmit the data signal to the voltage stabilizing driving unit. The voltage stabilizing driving unit is connected to the power supply voltage end and connected to the light emitting module through the initialization node, and is used for storing the received data signals, transmitting the power supply voltage to the light emitting module under the control of the data signals so as to drive the light emitting module to emit light and execute image display corresponding to the data signals.
Optionally, the pre-charging unit includes a first switch tube, a first capacitor and a pre-charging node, where a gate of the first switch tube is connected to the ith-a scanning line and used for receiving a scanning signal output by the ith-a scanning line, a source of the first switch tube is connected to a pre-charging voltage end and used for receiving a pre-charging voltage from the pre-charging voltage end, a drain of the first switch tube is connected to the first capacitor through the pre-charging node and the first switch tube is used for conducting under control of the scanning signal to control the pre-charging voltage to charge the first capacitor, the first capacitor is connected between the pre-charging node and the common voltage, and the first capacitor is used for controlling the potential of the pre-charging node to be kept at a preset potential.
Optionally, the pre-charging unit includes a trigger, a first switch tube, a first capacitor, a current-limiting resistor and a pre-charging node, wherein an input end of the trigger is connected to a power supply voltage, the current-limiting resistor is connected between the input end and the power supply voltage, a clock end of the trigger is connected to an ith-a scanning line for triggering the clock according to a scanning signal output by the ith-a scanning line, an output end of the trigger is connected to a grid electrode of the first switch tube, a source electrode of the first switch tube is connected to a pre-charging voltage end, a drain electrode of the first switch tube is connected to the first capacitor through the pre-charging node, the trigger controls the first switch tube to be conducted according to the scanning signal so as to control the pre-charging voltage to be transmitted to the first capacitor through the pre-charging node, and the first capacitor is connected between the pre-charging node and a public voltage so as to control the potential of the pre-charging node to be kept at a preset potential.
Optionally, the initialization control unit includes a second switching tube, a gate of the second switching tube is connected to the ith scanning line and is used for receiving a scanning signal from the ith scanning line, a source of the second switching tube is connected to an initialization voltage end through a pre-charging node, a drain of the second switching tube is connected to the initialization node, the second switching tube is used for being conducted under control of the scanning signal and is used for receiving the initialization voltage from the initialization voltage end, and the initialization voltage is transmitted to the light-emitting module through the initialization node and is used for initializing the light-emitting module.
Optionally, the signal receiving unit includes a third switching tube, a gate of the third switching tube is connected to the ith scanning line and is used for receiving the scanning signal from the ith scanning line in the data writing period, a source of the third switching tube is connected to the data line, a drain of the third switching tube is connected to the voltage stabilizing driving unit, and the third switching tube is used for being conducted under the control of the scanning signal so as to transmit the data signal received from the data line to the voltage stabilizing driving unit.
Optionally, the voltage stabilizing driving unit includes a fourth switching tube and a second capacitor, where a gate of the fourth switching tube is connected to a drain of the third switching tube and is used for receiving a data signal from the third switching tube, a source of the fourth switching tube is connected to a power voltage end, a drain of the fourth switching tube is connected to the light emitting module through an initialization node, and the fourth switching tube is used for conducting under control of the data signal and transmitting the power voltage to the light emitting module through the initialization node and is used for driving the light emitting module to emit light.
The application also discloses a display panel, which comprises a data driving circuit, a light-emitting controller and the array substrate, wherein the data driving circuit is used for outputting data signals, the scanning driving circuit arranged on the array substrate is used for outputting scanning signals, and the pixel units are used for receiving the data signals under the control of the scanning signals and displaying images under the control of the light-emitting controller.
Compared with the prior art, the second capacitor is arranged at the pre-charging node, so that the pre-charging node E can be kept at the preset potential after the second capacitor is charged, when the initialization voltage is transmitted to the initialization node through the pre-charging node E, the initialization voltage is increased from the preset potential to the initialization voltage, the increasing time of the initialization voltage is shortened, the writing speed of the initialization voltage to the light emitting module 153 is effectively increased, and the display effect of the pixel unit is effectively improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic structural diagram of a display device according to an embodiment of the application;
FIG. 2 is a schematic side view of the display terminal of FIG. 1
FIG. 3 is a schematic plan view of an array substrate of the display panel shown in FIG. 2;
FIG. 4 is a block diagram of the pixel unit of FIG. 3;
FIG. 5 is a schematic block diagram of the functional module of FIG. 4;
FIG. 6 is an equivalent circuit diagram of the pixel unit of FIG. 5;
FIG. 7 is a schematic diagram of a pixel unit connection of FIG. 6;
fig. 8 is an equivalent circuit schematic diagram of a pixel unit as shown in fig. 5 according to a second embodiment of the present application.
Reference numerals illustrate: the display device comprises a display device 100, a display panel 10, a power module 20, a supporting frame 30, a display area 10a, a non-display area 10b, an array substrate 10C, a counter substrate 10D, a medium layer 10e, m data lines S1-Sm, n scanning lines G1-Gn, a first direction F1, a second direction F2, a time sequence control circuit 11, a data driving circuit 12, a scanning driving circuit 13, a light emitting controller 14, a pixel unit 15, an initial pre-charging module 151, a driving module 152, a light emitting module 153, an initialization node QI, an ith scanning line Gi, a jth data line Sj, a power voltage terminal Vdd, an ith scanning line Gi-a, an initialization voltage terminal VI, a pre-charging unit 1511, an initialization control unit 1512, a signal receiving unit 1521, a voltage stabilizing driving unit 1522, a first switching tube T1, a second switching tube T2, a third switching tube T3, a fourth switching tube T3, a first switching tube C-C, a clock input terminal QC-C2, a clock input terminal FL, a first switching tube and a fourth switching tube.
Detailed Description
In order that the application may be readily understood, a more complete description of the application will be rendered by reference to the appended drawings. The drawings illustrate preferred embodiments of the application. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
The following description of the embodiments refers to the accompanying drawings, which illustrate specific embodiments in which the application may be practiced. The numbering of the components itself, e.g. "first", "second", etc., is used herein merely to distinguish between the described objects and does not have any sequential or technical meaning. The term "coupled" as used herein includes both direct and indirect coupling (coupling), unless otherwise indicated. Directional terms, such as "upper", "lower", "front", "rear", "left", "right", "inner", "outer", "side", etc., in the present application are merely referring to the directions of the attached drawings, and thus, directional terms are used for better, more clear explanation and understanding of the present application, rather than indicating or implying that the apparatus or element being referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present application.
In the description of the present application, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; may be a mechanical connection; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present application will be understood in specific cases by those of ordinary skill in the art. It should be noted that the terms "first," "second," and the like in the description and the claims of the present application and in the drawings are used for distinguishing between different objects and not for describing a particular sequential order.
Furthermore, the terms "comprises," "comprising," "includes," "including," or "having," when used in this specification, are intended to specify the presence of stated features, operations, elements, etc., but do not limit the presence of one or more other features, operations, elements, etc., but are not limited to other features, operations, elements, etc. Furthermore, the terms "comprises" or "comprising" mean that there is a corresponding feature, number, step, operation, element, component, or combination thereof disclosed in the specification, and that there is no intention to exclude the presence or addition of one or more other features, numbers, steps, operations, elements, components, or combinations thereof. Furthermore, when describing embodiments of the application, use of "may" means "one or more embodiments of the application. Also, the term "exemplary" is intended to refer to an example or illustration.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a display device 100 according to a first embodiment of the application. The display device 100 includes a display module 10, a power module 20 and a supporting frame 30, wherein the display module 10 and the power module 20 are fixed on the supporting frame 30, and the power module 20 is disposed on a back surface of the display module 10, i.e. a non-display surface of the display module 10. The power module 20 is used for providing power voltage for the display module 10 to display images, and the support frame 30 provides fixing and protecting functions for the display module 10 and the power module 20.
Referring to fig. 2, fig. 2 is a schematic side view of the terminal 100 shown in fig. 1.
As shown in fig. 2, the display panel 10 includes a display region 10a for an image and a non-display region 10b. The display area 10a is used for performing image display, and the non-display area 10b is disposed around the display area 10a to provide other auxiliary components or modules, and specifically, the display panel 10 includes an array substrate 10c and an opposite substrate 10d, and a display medium layer 10e sandwiched between the array substrate 10c and the opposite substrate 10 d. In this embodiment, the display medium in the display medium layer 10e is light emitting semiconductor material such as Micro LED, mini LED, etc.
Referring to fig. 3, fig. 3 is a schematic plan layout view of an array substrate 10c in the display panel 10 shown in fig. 2. As shown in fig. 3, the array substrate 10c includes a plurality of m×n pixel units 15, m data lines S1 to Sm, and n scan lines G1 to Gn, each of which is a natural number greater than 1, arranged in a matrix in the corresponding image display area 10 a.
The n scan lines G1 to Gn extend along a first direction F1 and are mutually insulated and arranged in parallel along a second direction F2, and the m data lines S1 to Sm extend along the second direction F2 and are mutually insulated and arranged in parallel along the first direction F1, wherein the first direction F1 and the second direction F2 are mutually perpendicular.
The display terminal 100 further includes a timing control circuit 11 for driving the pixel units to display an image, a data driving circuit 12, and a scan driving circuit 13 and a light emission controller 14 provided on the array substrate 10c corresponding to the non-display region 10b (fig. 2) of the display panel 10.
The timing control circuit 11 is electrically connected to the data driving circuit 12 and the scan driving circuit 13, and is used for controlling the working timings of the data driving circuit 12 and the scan driving circuit 13, i.e. outputting corresponding timing control signals to the data driving circuit 12 to the scan driving circuit 13, so as to control when to output corresponding scan signals and data signals.
The Data driving circuit 12 is electrically connected to the m Data lines S1 to Sm, and is configured to transmit a Data signal (Data) for display to the plurality of pixel units 15 in the form of Data voltages through the m Data lines S1 to Sm.
The scan driving circuit 13 is electrically connected to the n scan lines G1 to Gn, and is configured to output scan signals through the n scan lines G1 to Gn for controlling when the pixel unit 15 receives data signals. The scan driving circuit 13 sequentially outputs scan signals from the n scan lines G1 to Gn in the position arrangement order from the scan lines G1, G2, … …, gn in the scan period.
The light emission control unit 14 is configured to output a control signal at a preset timing after the pixel unit 15 is completely precharged to control the pixel unit 15 to emit light for image display.
In the present embodiment, the circuit elements in the scan driving circuit 13 and the pixel units 15 in the array substrate 10c are fabricated in the same process in the array substrate 10c, i.e. GOA (Gate Driver on Array) technology.
Referring to fig. 4, fig. 4 is a schematic block diagram of a circuit of the pixel unit in fig. 3.
As shown in fig. 4, the pixel unit 15 includes an initial precharge module 151, a driving module 152, a light emitting module 153, and an initialization node QI, and includes a precharge period and a data writing period in order in one frame image display period for any one of the pixel units in the i-th row. The initial pre-charge module 151 is connected to the ith scan line Gi-a, the ith scan line Gi, an initializing node QI, a pre-charge voltage end VE, and an initializing voltage end VI, and is configured to receive the ith scan signal G (i-a) from the ith scan line Gi-a during the pre-charge period, and receive a pre-charge voltage from the pre-charge voltage end VE under the control of the ith scan signal G (i-a), the pre-charge voltage is configured to pre-charge the initializing voltage end VI to a preset potential, and during the data writing period, the initial pre-charge module 151 receives the ith scan signal Gi from the ith scan line Gi, and transmits the initializing voltage output by the initializing voltage end VI to the initializing node QI under the control of the ith scan signal Gi, and transmits the initializing voltage to the light emitting module 153 via the initializing node QI, so as to perform initialization on the light emitting module 153. Wherein a is more than or equal to 1 and less than or equal to i and less than or equal to n, and i and a are positive integers.
The driving module 152 is connected to the ith scan line Gi, the jth data line Sj, the power voltage terminal Vdd and the initialization node QI, and is configured to receive the ith scan signal G (i) from the ith scan line Gi in the data writing period, receive the data signal from the jth data line Gj for storage under the control of the ith scan signal G (i), and transmit the power voltage output by the power voltage terminal Vdd to the light emitting module 153 through the initialization node QI under the control of the data signal, so as to drive the light emitting module 153 to emit light.
The light emitting module 153 is configured to receive an initialization voltage from the initial pre-charging module 151 to perform initialization, and receive a power voltage from the driving module 152 to emit light under the driving of the power voltage.
By precharging the initialization voltage terminal VI, when the initialization voltage terminal VI outputs the initialization voltage to initialize the light emitting module 153, the response speed of the initialization voltage can be effectively increased, so that the speed of initializing the light emitting module 153 is increased, and the image display effect of the pixel unit 15 is further improved.
Referring to fig. 5, fig. 5 is a schematic circuit block diagram of a functional module of the pixel unit in fig. 4.
As shown in fig. 5, the initial pre-charge module 151 includes a pre-charge unit 1511 and an initialization control unit 1512, wherein the pre-charge unit 1511 is connected to the initialization control unit 1512, the ith-a scan line Gi-a, the pre-charge voltage terminal VE and the initialization voltage terminal VI, and is configured to receive the ith-a scan signal G (i-a) from the ith-a scan line Gi-a during the pre-charge period, receive the pre-charge voltage from the pre-charge voltage terminal VE for storing in the ith-a scan signal G (i-a), and pre-charge the initialization voltage terminal VI to a preset potential, and receive the initialization voltage from the initialization voltage terminal VI during the data writing period and transmit the initialization voltage to the initialization control unit 1512.
The initialization control unit 1512 is connected to the ith scan line Gi and an initialization node QI, and is configured to receive the ith scan signal G (i) from the ith scan line Gi in a data writing period, transmit a received initialization voltage to the light emitting module 153 through the initialization node QI under the control of the ith scan signal G (i), and perform initialization on the light emitting module 153.
The driving module 152 includes a signal receiving unit 1521 and a voltage stabilizing driving unit 1522, wherein the signal receiving unit 1521 is connected to the ith scanning line Gi and the jth data line Sj, and is configured to receive the ith scanning signal G (i) from the ith scanning line Gi in the signal writing period, receive the data signal from the jth data line Gj under the control of the ith scanning signal G (i), and transmit the data signal to the voltage stabilizing driving unit 1522. The voltage stabilizing driving unit 1522 is connected to the power supply voltage terminal Vdd, and is connected to the light emitting module 153 through the initialization node QI, for storing the received data signal, and conducting the power supply voltage to the light emitting module 153 under the control of the data signal, so as to control the light emitting module 153 to emit light.
Referring to fig. 6, fig. 6 is an equivalent circuit schematic diagram of the pixel unit in fig. 5.
As shown in fig. 6, the pre-charging unit 1511 includes a first switch tube T1, a first capacitor C1 and a pre-charging node QE, wherein a gate of the first switch tube T1 is connected to the i-a scanning line Gi-a for receiving the i-a scanning signal G (i-a) during the pre-charging period, a source of the first switch tube T1 is connected to the pre-voltage end VE, a drain of the first switch tube T1 is connected to the first capacitor C1 via the pre-charging node QE, the first switch tube T1 is used for being turned on under the control of the i-a scanning signal G (i-a) to control the pre-charging voltage output by the pre-charging voltage end VE to charge the first capacitor C1, the first capacitor C1 is connected between the pre-charging node QE and the common voltage, and the first capacitor C1 is used for controlling the potential of the pre-charging node QE to be kept at the preset potential.
The initialization control unit 1512 includes a second switch tube T2, a gate of the second switch tube T2 is connected to the ith scan line Gi, and is configured to receive the ith scan signal G (i) from the ith scan line Gi in a data writing period, a source of the second switch tube T2 is connected to the initialization node QI, a drain of the second switch tube T2 is connected to the pre-charge node QE, and the second switch tube T2 is configured to be turned on under the control of the ith scan signal G (i), receive the initialization voltage from the pre-charge node QE, and transmit the initialization voltage to the light emitting module 153 via the initialization node QI, and perform initialization on the light emitting module 153. Because the first capacitor C1 is disposed at the pre-charging node QE, the pre-charging node QE can be kept at a preset potential after the first capacitor C1 is charged, and when the initialization voltage is transmitted to the initialization node QI through the pre-charging node QE, the writing speed of the initialization voltage to the light emitting module 153 can be effectively improved, so that the display effect is improved.
The signal receiving unit 1521 includes a third switch tube T3, a gate of the third switch tube T3 is connected to the ith scan line Gi, for receiving the ith scan signal G (i) from the ith scan line Gi, a source of the third switch tube T3 is connected to the jth data line Sj, and a drain of the third switch tube T3 is connected to the voltage stabilizing driving unit 1522, for being turned on under the control of the ith scan signal G (i) to transmit the received data signal to the voltage stabilizing driving unit 1522.
The voltage stabilizing driving unit 1522 includes a fourth switching tube T4 and a second capacitor C2, where a gate of the fourth switching tube T4 is connected to a drain of the third switching tube T3 and is configured to receive a data signal from the third switching tube T3, a source of the fourth switching tube T4 is connected to the power voltage terminal Vdd, a drain of the fourth switching tube T4 is connected to the initialization node QI, and the fourth switching tube T4 is configured to be turned on under the control of the data signal, so as to turn on the power voltage output by the power voltage terminal Vdd to the light emitting module 153 through the initialization node QI, so as to drive the light emitting module 153 to emit light.
The first to fourth switching tubes T1 to T4 are P-type MOS tubes, and of course, may be N-type MOS tubes according to specific needs, which is not limited by the present application.
The light emitting module 153 includes a light emitting diode OD having an anode connected to the initialization node QI and a cathode connected to the low voltage terminal Vss.
Referring to fig. 7, fig. 7 is a schematic diagram illustrating connection of the pixel units in fig. 6.
As shown in fig. 7, among a plurality of pixel cells connected to the same data line, each pixel cell is precharged with an initialization voltage controlled by a previous stage scan signal. For example, when i=1, the first pixel unit is connected to the i-1 th scan line Gi-1 for receiving the i-1 th scan signal G (i-1) from the i-1 th scan line Gi-1 and receiving the data signal from the j-th column data line Sj under the control of the i-1 th scan signal G (i-1). Meanwhile, the i-1 th scan signal G (i-1) is transmitted to the pre-charge unit 1511 in the second pixel unit P2, for controlling the pre-charge unit 1511 in the second pixel unit P2 to pre-charge the initialization voltage terminal VI. When the second pixel unit P2 receives the data signal to emit light under the control of the ith scan signal G (i), since the initialization voltage terminal VI is already precharged by the precharge voltage, the initialization voltage increases the speed at which the initialization of the light emitting module 153 is performed. Similarly, each row of pixel units is controlled by the scanning signal corresponding to the previous row of pixel units to precharge the initialization voltage, so that the overall image display effect is improved.
In an exemplary embodiment, the initializing voltage of each row of pixel cells may be further controlled by the first two or three stages of scan signals, for example, when a=2 or a=3, the ith row of pixel cells is precharged by the ith-2 scan signal G (i-2) corresponding to the ith-2 row of pixel cells or by the ith-3 scan signal G (i-3) corresponding to the ith-3 row of pixel cells G-3. Can be set according to specific needs, and the application is not limited.
Referring to fig. 8, fig. 8 is an equivalent circuit schematic diagram of a pixel unit as shown in fig. 5 according to a second embodiment of the present application. As shown in fig. 8, the pre-charging unit 1511 includes a flip-flop FL, a first switching tube T1, a current-limiting resistor R and a pre-charging node QE, wherein an input terminal D of the flip-flop FL is connected to a power voltage terminal Vdd, the current-limiting resistor R is connected between the input terminal D and the power voltage terminal Vdd, a clock terminal CLK of the flip-flop FL is connected to an i-th scan line Gi-a for triggering a clock according to an i-th scan signal G (i-a) outputted from the i-th scan line Gi-a, an output terminal Q of the flip-flop FL is connected to a gate of the first switching tube T1, a source of the first switching tube T1 is connected to the pre-charging voltage terminal VE, and a drain of the first switching tube T1 is connected to the first capacitor C1 through the pre-charging node QE. The flip-flop FL is triggered by the i-a-th scan signal G (i-a) and outputs a high level from the output terminal D to the gate of the first switching tube T1 to control the first switching tube T1 to be turned on, so that the precharge voltage outputted from the precharge voltage terminal VE is transmitted to the first capacitor C1 through the precharge node QE to charge the first capacitor C1, and the first capacitor C1 is connected between the precharge node QE and the common voltage Vcom, for receiving and storing the precharge voltage, and maintaining the precharge node QE at a preset potential.
The initialization control unit 1512 includes a second switch tube T2, a gate of the second switch tube T2 is connected to the ith scan line Gi, and is configured to receive the ith scan signal G (i) from the ith scan line Gi, a source of the second switch tube T2 is connected to the pre-charge node QE, a drain of the second switch tube T2 is connected to the initialization node QI, and the second switch tube T2 is configured to receive the initialization voltage VI from the pre-charge node QE at the ith scan signal G (i), and transmit the initialization voltage VI to the light emitting module 153 via the initialization node QI, and is configured to initialize the light emitting module 153.
The signal receiving unit 1521 includes a third switch tube T3, a gate of the third switch tube T3 is connected to the ith scan line Gi, for receiving the ith scan signal G (i) from the ith scan line Gi, a source of the third switch tube T3 is connected to the jth data line Sj, and a drain of the third switch tube T3 is connected to the voltage stabilizing driving unit 1522, for being turned on under the control of the ith scan signal G (i) to transmit the received data signal to the voltage stabilizing driving unit 1522.
The voltage stabilizing driving unit 1522 includes a fourth switching tube T4 and a second capacitor C2, where a gate of the fourth switching tube T4 is connected to a drain of the third switching tube T3 and is configured to receive a data signal from the third switching tube T3, a source of the fourth switching tube T4 is connected to a power voltage, a drain of the fourth switching tube T4 is connected to an initialization node QI, and the third switching tube T3 is configured to be turned on under control of the data signal to turn on the power voltage to the light emitting module 153 through the initialization node QI so as to drive the light emitting module 153 to emit light.
In the exemplary embodiment, the first switching tube T1 is an N-type MOS tube, the second switching tube T2, the third switching tube T3 and the fourth switching tube T4 are P-type MOS tubes, which can of course be set according to specific needs, the application is not limited thereto,
by setting the second capacitor C2 at the pre-charging node QE, the pre-charging node QE can be kept at a preset potential after the second capacitor C2 is charged, and when the initialization voltage is transmitted to the initialization node QI through the pre-charging node QE, the initialization voltage is increased from the preset potential to the initialization voltage, so that the increasing time of the initialization voltage is shortened, the writing speed of the initialization voltage to the light emitting module 153 is effectively increased, and the display effect of the pixel unit is improved.
It is to be understood that the application is not limited in its application to the examples described above, but is capable of modification and variation in light of the above teachings by those skilled in the art, and that all such modifications and variations are intended to be included within the scope of the appended claims.
Claims (10)
1. An array substrate comprises a plurality of scanning lines, a plurality of data lines and a plurality of pixel units, wherein the scanning lines extend along a first direction and are sequentially arranged along a second direction, the data lines extend along the second direction and are arranged along the first direction, and the pixel units are arranged in an array manner, and the first direction is different from the second direction;
the pixel unit is characterized by comprising an initial pre-charging module, a driving module, a light-emitting module and an initialization node, wherein the initial pre-charging module is connected with the light-emitting module through the initialization node, and the driving module is connected with the light-emitting module through the initialization node;
for any pixel unit in the ith row, a precharge period and a data writing period are sequentially included in a frame image display period, wherein the initial precharge module is connected to the ith scanning line, the ith-a scanning line, a precharge voltage end and an initialization voltage end, a is a positive integer, i is a positive integer greater than a, the initial precharge module receives a scanning signal from the ith-a scanning line in the precharge period and receives a precharge voltage provided by the precharge voltage end under the control of the scanning signal, and the precharge voltage is used for precharging the initialization voltage end to a preset potential; in the data writing period, the initial pre-charging module receives an initialization voltage from the initialization voltage terminal, and transmits the initialization voltage to the light emitting module through the initialization node under the control of a scanning signal output by the ith scanning line so as to initialize the light emitting module;
the driving module is connected to the ith scanning line, the data line and the power supply voltage, receives the scanning signal from the ith scanning line in the data writing period, and receives a data signal under the control of the scanning signal, wherein the data signal is used for driving the light emitting module to emit light and execute image display.
2. The array substrate of claim 1, wherein the initial pre-charge module includes a pre-charge unit and an initialization control unit, the pre-charge unit is connected to the initialization control unit, the i-a-th scan line, the pre-charge voltage terminal and the initialization voltage terminal, and is configured to receive the scan signal from the i-a-th scan line during the pre-charge period, receive the pre-charge voltage under the control of the scan signal, perform pre-charge on the initialization voltage terminal to the preset potential, and receive the initialization voltage from the initialization voltage terminal during the data writing period, and transmit the initialization voltage to the initialization control unit.
3. The array substrate of claim 2, wherein the initialization control unit is connected to the ith scan line, the pre-charge unit, and the initialization node, and is configured to receive the scan signal from the ith scan line during the data writing period, and transmit the initialization voltage received from the pre-charge unit to the light emitting module through the initialization node under the control of the scan signal, for performing initialization on the light emitting module.
4. The array substrate of claim 3, wherein the driving module includes a signal receiving unit and a voltage stabilizing driving unit, the signal receiving unit is connected to the ith scanning line and the data line, and is configured to receive the scanning signal from the ith scanning line in the data writing period, receive the data signal from the data line under the control of the scanning signal, and transmit the data signal to the voltage stabilizing driving unit;
the voltage stabilizing driving unit is connected to a power supply voltage end, is connected to the light emitting module through the initialization node, and is used for storing the received data signals, transmitting the power supply voltage to the light emitting module under the control of the data signals so as to drive the light emitting module to emit light and execute image display corresponding to the data signals.
5. The array substrate of any one of claims 2 to 4, wherein the pre-charge unit includes a first switch tube, a first capacitor and a pre-charge node, a gate of the first switch tube is connected to the i-a scan line and is used for receiving the scan signal output by the i-a scan line, a source of the first switch tube is connected to the pre-charge voltage terminal and is used for receiving the pre-charge voltage from the pre-charge voltage terminal, a drain of the first switch tube is connected to the first capacitor through the pre-charge node, the first switch tube is used for being conducted under the control of the scan signal to control the pre-charge voltage to charge the first capacitor, the first capacitor is connected between the pre-charge node and a common voltage, and the first capacitor is used for controlling the potential of the pre-charge node to be kept at the preset potential.
6. The array substrate of any one of claims 2 to 4, wherein the pre-charge unit includes a trigger, a first switch tube, a first capacitor, a current limiting resistor and a pre-charge node, an input end of the trigger is connected to the power voltage, the current limiting resistor is connected between the input end and the power voltage, a clock end of the trigger is connected to the i-a scan line, the clock is triggered according to the scan signal output by the i-a scan line, an output end of the trigger is connected to a gate of the first switch tube, a source electrode of the first switch tube is connected to the pre-charge voltage end, a drain electrode of the first switch tube is connected to the first capacitor through the pre-charge node, the trigger controls the first switch tube to be turned on according to the scan signal, so as to control the pre-charge voltage to be transmitted to the first capacitor through the pre-charge node, and the first capacitor is connected between the pre-charge node and a common voltage, so as to control the pre-charge potential to be kept at the pre-charge node.
7. The array substrate of claim 5, wherein the initialization control unit includes a second switching tube, a gate of the second switching tube is connected to the ith scan line, for receiving the scan signal from the ith scan line, a source of the second switching tube is connected to the initialization voltage terminal through the pre-charge node, a drain of the second switching tube is connected to the initialization node, the second switching tube is turned on under the control of the scan signal, for receiving the initialization voltage from the initialization voltage terminal, and transmitting the initialization voltage to the light emitting module through the initialization node, for initializing the light emitting module.
8. The array substrate of claim 4, wherein the signal receiving unit includes a third switching tube, a gate of the third switching tube is connected to the ith scan line and is used for receiving the scan signal from the ith scan line in the data writing period, a source of the third switching tube is connected to the data line, a drain of the third switching tube is connected to the voltage stabilizing driving unit, and the third switching tube is used for being turned on under control of the scan signal so as to transmit the data signal received from the data line to the voltage stabilizing driving unit.
9. The array substrate of claim 8, wherein the voltage stabilizing driving unit comprises a fourth switching tube and a second capacitor, a gate electrode of the fourth switching tube is connected to a drain electrode of the third switching tube and is used for receiving the data signal from the third switching tube, a source electrode of the fourth switching tube is connected to the power voltage terminal, a drain electrode of the fourth switching tube is connected to the light emitting module through the initialization node, and the fourth switching tube is used for being conducted under the control of the data signal so as to transmit the power voltage to the light emitting module through the initialization node and is used for driving the light emitting module to emit light.
10. A display panel, comprising a data driving circuit, a light emitting controller and an array substrate according to any one of claims 1 to 9, wherein the data driving circuit is used for outputting the data signal, a scan driving circuit disposed on the array substrate is used for outputting a scan signal, and the pixel unit is used for receiving the data signal under the control of the scan signal and displaying an image under the control of the light emitting controller.
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