CN115729520A

CN115729520A - Divider device suitable for wide fixed condition of quotient

Info

Publication number: CN115729520A
Application number: CN202211460319.3A
Authority: CN
Inventors: 谢小东; 张甜
Original assignee: University of Electronic Science and Technology of China
Current assignee: University of Electronic Science and Technology of China
Priority date: 2022-11-17
Filing date: 2022-11-17
Publication date: 2023-03-03

Abstract

The invention belongs to the field of digital integrated circuit design, and particularly relates to a divider device for division operation with fixed quotient bit width. The invention adopts the serial idea to realize division, and assigns values to each digit of the quotient in serial according to the sequence from the highest digit to the lowest digit. The divider device converts the division operation into relatively simple comparison, subtraction and shift operation, facilitates the hardware realization, and also reduces the area consumed by the division operation circuit; meanwhile, one bit of the quotient is assigned in each clock cycle, the number of clock cycles consumed by operation does not exceed the number of bits of the quotient, and when the bit width of the dividend and the divisor is greater than the bit width of the quotient, compared with the traditional division operation algorithm based on subtraction, the operation time can be saved; in addition, the operation of each clock cycle only comprises comparison, subtraction and shift at most once, so that the delay of a combinational logic path in the circuit is greatly reduced, and the requirement of time sequence is easily met.

Description

Divider device suitable for wide fixed condition of quotient

Technical Field

The invention belongs to the field of digital integrated circuit design, and particularly relates to a special divider device.

Background

In the design of a digital integrated circuit, a divider is a key operation unit, although there is an instruction of division operation in ver i log language, for the case that dividend and divisor are both variables, directly using the division instruction may cause that a synthesis tool cannot synthesize a better result, and in the case that the bit width of the dividend and the divisor is large, division operation may occupy more resources and may not ensure that the operation is completed in one clock cycle, resulting in a problem of circuit timing. Therefore, for the case where the dividend and the divisor are both variables, a corresponding algorithm is usually designed to implement division, such as subtraction-based division, i.e., for unsigned division of n bits, the dividend is converted into an upper n bits of 0, a lower n bits of a first intermediate variable of the dividend, the divisor is converted into an upper n bits of a divisor, and a lower n bits of a second intermediate variable of 0. When each period starts, firstly, shifting the intermediate variable by one bit from the left, complementing 0 at the end, and then comparing the intermediate variable with the divisor; if the intermediate variable is larger than the divisor, subtracting the intermediate variable two from the intermediate variable one and adding 1 to serve as the updated intermediate variable one, otherwise, continuing to execute downwards. The shifting, comparing and subtracting are executed n times, after the execution is finished, the high n bits of the intermediate variable one are remainder, and the low n bits are quotient.

However, in some application scenarios, such as operations in a video codec protocol, since the bit depth of data is limited to n bits, the bit width of the result of division operation in the protocol is also limited. Under the condition that the bit width of the quotient is fixed, if the dividend and the divisor of m bits are operated, the quotient is limited to n bits, the operation is carried out by adopting the algorithm, m clocks are needed to obtain the quotient of the m bits, and the quotient is limited to the range represented by the unsigned number of the n bits. However, when m is much larger than n, the division operation consumes more cycles, and the intermediate variable of the operation has large bit width and occupies more resources. Therefore, for such application scenarios, a novel divider needs to be designed to complete division with a fixed quotient width.

Disclosure of Invention

In view of the above problems or disadvantages, the present invention provides a special divider apparatus, which can implement division operation with a fixed quotient bit width, and when the quotient bit width is smaller than the dividend bit width, the operation time can be reduced, and the area of the integrated circuit can be reduced. The specific scheme is as follows:

the invention discloses a divider device aiming at the condition of fixed quotient bit width, which comprises a preprocessing module, a counting module, an iterative operation module and an output module.

The preprocessing module is used for preprocessing the input dividend and divisor, shifting the dividend by one bit to the left, performing low-order 0 complementing to obtain first data, shifting the divisor by a bit wide and performing low-order 0 complementing to obtain second data; wherein the data bit width is a bit width of the quotient.

The counting module is used for counting the operation period, and the counting value can represent the updated digit of the quotient. Setting a count value with an initial value of 0, and adding 1 to the count value on the original basis in each clock period when a division enabling signal is pulled high; when a flag signal indicating that the division operation is finished is received, the count value is cleared; the count value remains unchanged in the remaining cases.

The iterative operation module executes iterative operation according to the following steps.

S1: when the count value is 0, executing S1, and comparing the sizes of the first data and the second data: if the first data is larger than or equal to the second data, the first data is shifted to the left by one bit, the lower bit is complemented by 0, the second data is subtracted, the difference between the first data and the second data is shifted to the left by one bit, the lower bit is complemented by 0, the operation result is stored in a preset register, the value of the preset register is used as third data, and the highest bit of the quotient register is assigned to be 1; if the first data is smaller than the second data, the operation result of shifting the first data to the left by one bit and then complementing 0 by low order is stored in the preset register, the value of the prediction register is used as the third data, and meanwhile, the highest order of the quotient register is assigned to be 0;

s2: when the counting value is not 0, executing S2, and comparing the sizes of the third data and the second data: if the third data is larger than the second data, the third data is shifted to the left by one bit and then the second data is subtracted, the difference between the third data and the second data is shifted to the left by one bit, the low order is complemented by 0, the operation result is stored in a preset register, the value of the preset register is used as updated third data, meanwhile, a certain data bit of a quotient register is assigned to be 1, and the number of the data bit in the quotient register is as follows: the difference between the quotient bit width and the counting value, the digit is calculated according to the sequence from the low bit to the high bit, and the digit corresponding to the lowest bit is the 1 st bit; if the third data is smaller than the second data, the operation result of shifting the third data by one bit to the left and then complementing 0 by low order is stored in the preset register, the value of the prediction register is used as updated third data, and meanwhile, the data bit of the quotient register is assigned to be 0; and if the third data is equal to the second data, clearing the third data and assigning the data bit of the quotient register to be 1.

And the output module judges the condition of ending the division operation, and outputs a division operation ending mark and a division operation result when the condition is met.

Further, the preprocessing module is specifically configured to:

and when the rising edge of the division starting signal is acquired, the dividend is shifted to the left by one bit, the low bit is complemented by 0 to obtain the first data, the divisor is shifted to the left by a plurality of bits of the data bit width, and the low bit is complemented by 0 to obtain the second data.

Further, the preprocessing module is further configured to:

the counting module is connected with the control module, and when the rising edge of the division starting signal is acquired, the division enabling signal is pulled up and sent to the counting module; and when the rising edge of the division end mark signal is acquired, pulling down the division enable signal.

Further, the preprocessing module is further configured to:

configuring parameters for the data; wherein the configuration parameters include bit widths of the first data, the second data, and the count value.

Further, the preprocessing module is further configured to:

the iterative operation module is connected with the input end of the first data and the input end of the second data, and outputs the division enabling signal, the first data and the second data to the iterative operation module;

further, the counting module is configured to start counting from an initial value 0 after receiving the division enable signal, and add 1 at each clock rising edge; and after receiving the division end mark signal, clearing the count value.

Further, the counting module is further configured to record the number of execution times of S1 and S2.

Further, the counting module is further configured to be connected to the output module, and output a count value of the counter to the output module as one of conditions for judging that the division is finished;

further, the iterative operation module is configured to execute the S1 and the S2 after receiving the division enable signal; and stopping iterative operation after receiving the division end mark signal.

Further, the output module is configured to be connected to the iterative operation module and the counting module, determine whether division is finished after receiving the count value sent by the counting module and the third data and the second data sent by the iterative operation module, generate an effective flag signal indicating that division is finished if the count value is equal to a value obtained by subtracting one from the quotient bit width or the third data is equal to the second data, output the effective flag signal to the counting module, and assign the division operation result to the output of the divider.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments or the conventional technologies of the present application, the drawings used in the descriptions of the embodiments or the conventional technologies will be briefly introduced below, it is obvious that the drawings in the following descriptions are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

FIG. 1 is a flow diagram of a prior art subtraction-based division algorithm;

FIG. 2 is a flowchart of a division algorithm provided by the present invention;

FIG. 3 is a diagram illustrating an exemplary divider apparatus;

FIG. 4 is a block diagram of an iteration module according to an embodiment;

Detailed Description

To facilitate an understanding of the invention, the invention will now be described more fully with reference to the accompanying drawings. Embodiments of the invention are presented in the drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

It will be understood that, as used herein, the terms "first," "second," and the like may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another.

In one embodiment, a special divider apparatus 0005 with a fixed quotient width of 16 is provided, as shown in fig. 3, and includes a preprocessing module 0001, a counting module 0002, an iterative operation module 0003, and an output module 0004.

The preprocessing module 0001 is used for preprocessing an input dividend and a divisor, and two registers are arranged in the preprocessing module 0001 and used for registering first data and second data. After receiving a division starting signal from the outside, shifting the dividend by 1 bit to the left, complementing 0 by the lower 1 bit, and assigning the dividend to first data; the divisor is shifted left by 16 bits, the lower 16 bits are complemented by 0, and the divisor is assigned to the second data. Meanwhile, the preprocessing module 0001 pulls up the division enable flag after acquiring the rising edge of the division start signal, and pulls down the division enable flag after acquiring the rising edge of the division end flag signal.

The counting module 0002 includes a period counter therein, an input end of the counting module 0002 is connected to the preprocessing module 0001 and the output module 0004, when a division enable flag signal output by the preprocessing module 0001 is high, the counting value starts to count from an initial value of 0, the counting value is increased by 1 on the original basis at each clock rising edge, and when a division end flag signal sent by the output module 0004 is high, the counting value is restored to 0 at the next clock rising edge. The output end of the counting module 0002 is connected to the iterating module 0003 and the output module 0004, and outputs the counting value to the iterating module 0003 and the output module 0004 while counting.

Fig. 4 is a schematic structural diagram of an iteration module 0003 provided in this embodiment. The input end of the iteration module 0003 is connected to the counting module 0002, the preprocessing module 0001 and the output module 0004. As can be seen from the figure, the iteration module 0003 has an alternative data selector (abbreviated as alternative MUX) inside, and the output of the alternative MUX is denoted as the fourth data. One input signal of the alternative MUX is the first data sent by the preprocessing module 0001, and the other input signal is the value of the internal register of the iteration module 0003, that is, the third data; when the count value of the counting module 0002 is 0, assigning the first data sent by the preprocessing module 0001 to fourth data; when the count value of the counting module 0002 is not 0, the value of the third data is assigned to the fourth data. The iterator 0003 has a 16-bit register inside, each bit of the register is denoted as M1-M16, and stores the result of the quotient, where M1 represents the least significant bit of the quotient and M16 represents the most significant bit of the quotient. When the reset signal is valid, the initial value of the quotient register is 0, namely M1 to M16 are all 0; when the reset signal is invalid and the division enable flag is high, the iterative operation is started. One iteration per clock may be done and a 0 or 1 is assigned to one of M1-M16 on the rising edge of the clock. The flow of iterative operation is as follows: and sending the fourth data and the second data into a comparator for comparison, and assigning a value to one of M1-M16 according to a comparison result. If the fourth data is larger than the second data, shifting the difference between the fourth data and the second data by one bit to the left, complementing 0 by lower bits, assigning to the third data, and assigning Mm to be 1 (m = 16-count value); if the fourth data is smaller than the second data, shifting the fourth data by one bit to the left, supplementing 0 to the lower bits, assigning to the third data, and assigning Mm to be 0; and if the fourth data is equal to the second data, assigning the third data to be 0 and simultaneously assigning Mm to be 1. And stopping iterative operation when the division end mark signal is high. The output end of the iteration module 0003 is connected with the output module 0004, and the second data and the fourth data are output to the output module 0004.

The output module 0004 is configured to determine a condition for ending the division operation, and output a division operation ending flag and a division operation result when the condition is satisfied. The input end of the output module 0004 is connected to the counting module 0002 and the iteration module 0003, and the count value of the counting module 0002 and the second data and the fourth data of the iteration operation module 0003 are both sent to the output module 0004. The output module 0004 includes two-input comparators, one of which compares the count value with the value of 15, and the other of which compares the fourth data with the second data; when the count value of the counting module 0002 is equal to 15 or the fourth data output by the iteration module 0003 is equal to the second data, on the rising edge of the next clock, the output module 0004 pulls up the division end flag signal to indicate that the division operation is completed, and simultaneously outputs the result of the current quotient as the result of the division operation. Since the bit width of the quotient is fixed to 16 bits, the number of clock cycles consumed for implementing the division operation by using the divider device provided by the embodiment is at most 16 and at least 1.

In summary, for the division operation with fixed quotient bit width in a specific application scenario, the invention designs a special divider device, which implements the division by adopting a serial idea, and assigns values to each quotient bit in series according to the sequence from the highest bit to the lowest bit through the cooperation of the counting module and the iteration module. The divider device converts the division operation into relatively simple comparison, subtraction and shift operation, facilitates the hardware realization, and also reduces the area consumed by the division operation circuit; meanwhile, one bit of the quotient is assigned in each clock cycle, the number of clock cycles consumed by operation does not exceed the number of bits of the quotient, and when the bit width of the dividend and the divisor is greater than the bit width of the quotient, compared with the traditional division operation algorithm based on subtraction, the operation time can be saved; in addition, the operation of each clock cycle only comprises comparison, subtraction and shift at most once, so that the delay of a combinational logic path in the circuit is greatly reduced, and the requirement of time sequence is easily met.

It is to be understood that the present invention has been described with reference to certain embodiments, and that various changes in the features and embodiments, or equivalent substitutions may be made therein by those skilled in the art without departing from the spirit and scope of the invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the invention without departing from the essential scope thereof. Therefore, it is intended that the invention not be limited to the particular embodiment disclosed, but that the invention will include all embodiments falling within the scope of the appended claims.

Claims

1. A divider device for the condition of fixed quotient bit width is characterized by comprising a preprocessing module, a cycle counting module, an iterative operation module and an output module.

The counting module is used for counting the operation period, and the counting value can represent the updated digit of the quotient. Setting a count value with an initial value of 0, and adding 1 to the count value on the original basis in each clock period when a division enabling signal is pulled high; when a sign signal of the completion of division operation is received, the count value is cleared; otherwise the count value remains unchanged.

2. The fixed quotient bit width divider apparatus of claim 1 wherein:

when the preprocessing module acquires the rising edge of a division starting signal, the dividend is shifted to the left by one bit, the low bit is complemented by 0 to obtain first data, the divisor is shifted to the left by a plurality of bits of the data bit width, and the low bit is complemented by 0 to obtain second data.

3. The fixed quotient bit width divider apparatus of claim 1 wherein:

the preprocessing module is connected with the counting module, and when the rising edge of a division starting signal is acquired, the division enabling signal is pulled high and sent to the counting module; and when the rising edge of the division end mark signal is acquired, pulling down the division enable signal.

4. The fixed quotient bit width divider apparatus of claim 1, wherein:

the preprocessing module configures parameters for data; wherein the configuration parameters include bit widths of the first data, the second data, and the count value.

5. The fixed quotient bit width divider apparatus of claim 1 wherein:

the preprocessing module is connected with the iterative operation module and outputs the division enabling signal, the first data and the second data to the iterative operation module.

6. The fixed quotient bit width divider apparatus of claim 1 wherein:

the counting module is used for counting from an initial value of 0 after receiving the division enabling signal, and adding 1 in each clock rising edge; after receiving a valid flag signal indicating the end of the operation, the count value is cleared.

7. The fixed quotient bit width divider apparatus of claim 6 wherein:

and the counting module is used for recording the execution times of the S1 and the S2.

8. The fixed quotient bit width divider apparatus of claim 1 wherein:

the counting module is connected with the output module and outputs the counting value of the counter to the output module as one of conditions for judging the end of division.

9. The fixed quotient bit width divider apparatus of claim 1, wherein:

the iterative operation module is used for executing the S1 and the S2 after receiving the division enabling signal; and stopping iterative operation after receiving the division end mark signal.

10. The fixed quotient bit width divider apparatus of claim 1 wherein:

and the output module is used for connecting the iterative operation module and the counting module, judging whether the division is finished or not after receiving the counting value sent by the counting module and the third data and the second data sent by the iterative operation module, if the counting value is equal to the quotient bit width minus one or the third data is equal to the second data, generating an effective mark signal indicating the end of the division operation, outputting the effective mark signal to the counting module, and assigning the division operation result to the output of the divider.