CN115729337A

CN115729337A - DDR5 power management system

Info

Publication number: CN115729337A
Application number: CN202211640429.8A
Authority: CN
Inventors: 李昌嵩
Original assignee: Inspur Power Commercial Systems Co Ltd
Current assignee: Inspur Power Commercial Systems Co Ltd
Priority date: 2022-12-20
Filing date: 2022-12-20
Publication date: 2023-03-03

Abstract

The application discloses DDR5 power management system relates to computer hardware technical field, includes: a power management chip set including a plurality of power management chips; the electronic fuses are respectively arranged between each power management chip and a power supply, so that when the current output level of any power management chip is low level, the corresponding electronic fuse triggers fusing operation to disconnect the electrical connection between the power management chip and the power supply; and the circuit component group is used for determining the actual output level of the power management chip group according to the level state of the current output level of each power management chip so as to supply power to the DDR5 memory chip through the power supply when the actual output level is the high level. This application ensures through setting up power management chipset and electronic fuse that can also supply power through other power management chips when a power management chip breaks down, guarantees the normal power supply of memory.

Description

DDR5 power management system

Technical Field

The invention relates to the technical field of computer hardware, in particular to a DDR5 power supply management system.

Background

In a server system, the Power supply of DDR4 and previous generations of memories is generally to convert 12V and 3.3V into the Power required by the memory by a Power chip of a motherboard, but the Power supply of DDR5 memories has a relatively large change, and the DDR5 memories only need the motherboard to supply 12V and 3.3V, and are converted into the required voltage by a Power Management Integrated Circuit (PMIC) on the memory without depending on the Power supply of the motherboard. The power supply scheme of the memory from DDR5 is transferred to the memory from the mainboard. This results in a need to modify the design of the memory power scheme. PMIC solutions were proposed by large power suppliers.

The PMIC On the Memory is an integrated buck digital converter for DDR5 On-DIMM (double-Inline-Memory-Modules) Power supply, which provides VDD (Power supply terminal of device), VDDQ (Memory chip output buffer supply voltage) and VPP (Virtual Power Plant) voltages for DRAM (Dynamic Random Access Memory) chips On DIMM (Dual-Inline-Memory-Modules) Modules, and has configurable current capability, and the structure diagram is shown in fig. 1. When the PMIC has a problem, the power supply of the memory bank is affected completely, and the whole memory bank cannot be used, so that the memory is lost by the system.

Disclosure of Invention

In view of this, an object of the present invention is to provide a DDR5 power management system, which can ensure that power can be supplied through other power management chips when one power management chip fails by setting a power management chipset and an electronic fuse, so as to ensure normal power supply of a memory. The specific scheme is as follows:

in a first aspect, the present application discloses a DDR5 power management system, comprising:

a power management chip group including a plurality of power management chips;

the electronic fuses are respectively arranged between each power management chip and a power supply, so that when the current output level of any power management chip is low level, the corresponding electronic fuse triggers fusing operation to disconnect the electrical connection between the power management chip and the power supply;

and the circuit component group is used for determining the actual output level of the power management chip group according to the level state of the current output level of each power management chip so as to supply power to the DDR5 memory chip through the power supply when the actual output level is the high level.

Optionally, the power management chipset includes a first power management chip and a second power management chip, so that the power supply supplies power to the DDR5 memory chip through another power management chip when a line where any power management chip is located fails.

Optionally, the electronic fuses include a first electronic fuse and a second electronic fuse;

the first electronic fuse is arranged between the power supply and the first power management chip; the second electronic fuse is arranged between the power supply and the second power management chip.

Optionally, the circuit element group is an element group constructed based on a nor gate and a phase inverter, and is disposed between the power management chipset and the DDR5 memory chip.

Optionally, the nor gate and the inverter are both devices constructed based on a plurality of metal oxide semiconductor field effect transistors.

Optionally, the DDR5 power management system further includes:

and the bidirectional two-wire system synchronous serial bus is connected with each power management chip and the DDR5 memory chip and is used for determining the corresponding fault information of the power management chip of which the current output level is the low level through address scanning operation.

In a second aspect, the present application discloses a DDR5 power management method, which is applied to the DDR5 power management system according to any one of claims 1 to 6, and includes:

when the current output level of any power management chip in the DDR5 power management system is a low level, triggering fusing operation through a corresponding electronic fuse in the DDR5 power management system to disconnect the electrical connection between the power management chip and a power supply;

determining the actual output level of the power management chip set according to the level state of the current output level of each power management chip in the DDR5 power management system;

and when the actual output level is a high level, supplying power to the DDR5 memory chip through the power supply.

In a third aspect, the application discloses a DDR5 power supply comprising a power supply and a DDR5 power supply management system as claimed in any one of claims 1 to 6.

In a fourth aspect, the present application discloses a DDR5 memory, comprising a DDR5 memory chip and the DDR5 power supply of claim 8.

In a fifth aspect, the present application discloses a server comprising the DDR5 memory of claim 9.

Therefore, the DDR5 power management system comprises a power management chip set of a plurality of power management chips; the electronic fuses are respectively arranged between each power management chip and a power supply, so that when the current output level of any power management chip is low level, the corresponding electronic fuse triggers fusing operation to disconnect the electrical connection between the power management chip and the power supply; and the circuit component group is used for determining the actual output level of the power management chip group according to the level state of the current output level of each power management chip so as to supply power to the DDR5 memory chip through the power supply when the actual output level is the high level. Therefore, if the current output level of any power management chip in the power management chip set is a low level, the electronic fuse can be fused to disconnect the power management chip and the electric connection between the power supply, so that the normal power supply of the DDR5 memory chip by using other power management chips is ensured, and thus, the power management chip set and the electronic fuse can be arranged to ensure that the normal power supply of the DDR5 memory chip cannot be influenced when a certain power management chip fails, the reliability of the system is improved, and the problem that the DDR5 memory cannot be used due to the influence of the DDR5 memory chip when the power supply of only one power management chip fails is avoided.

The application also provides a DDR5 power management method, when the current output level of any power management chip in the DDR5 power management system is a low level, a fusing operation is triggered through a corresponding electronic fuse in the DDR5 power management system, so that the electrical connection between the power management chip and a power supply is disconnected; then determining the actual output level of the power management chip set according to the level state of the respective current output level of each power management chip in the DDR5 power management system; and then supplying power to the DDR5 memory chip through the power supply when the actual output level is a high level. Therefore, when any power management chip outputs a low level, the electronic fuse corresponding to the power management chip can be fused to disconnect the power management chip from a power supply, the current output level is determined based on each power management chip in the DDR5 power management system, and when the actual output level is a high level, the DDR5 is normally supplied with power, so that a plurality of power management chips in the power management chip set are mutually redundant, the normal power supply of a DDR5 memory is guaranteed through other chips when a certain chip fails, the reliability of the DDR5 memory is higher compared with that of the DDR5 memory with only one power management chip, and the availability and serviceability of the memory can be effectively improved.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.

Fig. 1 is a schematic diagram of a conventional DDR5 memory structure disclosed in the present application;

FIG. 2 is a block diagram of a DDR5 power management system as disclosed in the present application;

FIG. 3 is a schematic diagram of a NOR gate structure disclosed in the present application;

FIG. 4 is a schematic diagram of an inverter according to the present disclosure;

FIG. 5 is a block diagram of a specific DDR5 power management system according to the disclosure;

fig. 6 is a flowchart of a DDR5 power management method disclosed in the present application.

The various symbols in the figures are illustrated as follows: 1 is a power management chip set; 7 is a first power management chip; 8 is a second power management chip; 2 is a circuit element group; 9 is a NOR gate; 10 is an inverter; 3 is a power supply; 4 is DDR5 memory chip; 5 is a first electronic fuse; 6 is a second electronic fuse; 11 is a bidirectional two-wire synchronous serial bus.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments in the present application without making any creative effort belong to the protection scope of the present application.

In the server system, the Power supply of DDR4 and previous generations of memories is generally to convert 12V and 3.3V into the Power required by the memory by a Power chip of a motherboard, but the Power supply of DDR5 memories has a relatively large change, and the DDR5 memories only need the motherboard to supply 12V and 3.3V, and are converted into the required voltage by a PMIC (Power Management chip) on the memory without depending on the Power supply of the motherboard. The power supply scheme of the memory from DDR5 is transferred to the memory from the mainboard. This results in a need to modify the design of the memory power scheme. When the PMIC has a problem, the power supply of the memory bank is affected completely, and the whole memory bank cannot be used, so that the memory is lost by the system.

Referring to fig. 2, the embodiment of the present application discloses a DDR5 power management system, where the DDR5 power management system includes a power management chipset 1, configured to convert a voltage provided by a power supply into a voltage required by a DDR5 memory chip, and includes a first power management chip 7 and a second power management chip 8, so that the power supply 3 supplies power to the DDR5 memory chip 4 through another power management chip when a line where any power management chip is located fails. It can be understood that the first power management chip 7 and the second power management chip 8 are two identical power management chips, and are connected in parallel between the power supply 3 and the DDR5 memory chip 4, and the two power management chips are redundant to each other and commonly supply power to the DDR5 memory chip to ensure normal operation of the DDR5 memory chip, so that the problem that the DDR5 memory chip cannot normally operate due to failure of the power management chip when only one power management chip is set can be prevented, and RAS (Reliability, availability, serviceability, that is, reliability, availability, serviceability) characteristics of the memory are improved.

In this embodiment, a plurality of electronic fuses (efuses) are respectively disposed between each of the power management chips and the power supply 3, that is, a first electronic fuse 5 is disposed between the first power management chip 7 and the power supply 3, and a second electronic fuse 6 is disposed between the second power management chip 8 and the power supply 3, so that when the current output level of any one of the power management chips is a low level, the corresponding electronic fuse triggers a fusing operation to disconnect the electrical connection between the power management chip and the power supply. For example, if the current output level of the first power management chip 7 is a low level, it indicates that the first power management chip 7 fails, and then the first electronic fuse 5 is triggered to perform a fusing operation to disconnect the electrical connection between the first power management chip 7 and the power supply 3, so as to ensure that the DDR5 memory chip 4 is not damaged due to the influence of the first power management chip 7.

In this embodiment, the DDR5 Power management system further includes a circuit element group 2, where the circuit element group 2 includes a nor gate 9 and a phase inverter 10, is disposed between the DDR5 memory chip 4 and the Power management chipset 1, and is configured to determine an actual output level of the Power management chipset 1 according to a level state of a current output level of each of the Power management chips, so as to supply Power to the DDR5 memory chip 4 through the Power supply 3 when the actual output level is a high level, that is, determine an actual output level output to the DDR5 memory chip 4 according to a level state of a current output level of each of the first Power management chip 7 and the second Power management chip 8, and output a normal PGOOD (Power good) signal to the DDR5 memory chip 4 through the nor gate 9 and the phase inverter 10 if the current output levels of the first Power management chip 7 and the second Power management chip 8 are both high levels, and simultaneously supply Power to the memory chip and other DRAM chips on the DDR5 memory; if the current output level of one power management chip in the two power management chips is a low level and the current output level of the other power management chip is a high level, determining that the actual output level is a high level, and outputting the high level to the DDR5 memory chip 4; however, if the current output levels of the two power management chips are both low levels, it indicates that both the two power management chips have a fault and stop supplying power to the DDR5 memory chip 4, and it should be noted that the possibility that both the two chips have a fault at the same time is very low, so the case that both the two chips have a fault at the same time is not considered in this scheme. The nor gate 9 and the inverter 10 can be used to ensure that only one of the two power management chips needs to have a high current output level, and then the high current output level can be output to a pin (Personal identification number) of the PCAMP on the interface of the DDR5 memory chip 4 to tell whether the power supply of the system memory is normal or not, so that it can be ensured that when one power management chip fails, the other power management chip is used to ensure the normal power supply and operation of the memory.

In this embodiment, the nor gate 9 and the inverter 10 are both devices constructed based on a plurality of Metal-Oxide-Semiconductor Field-Effect transistors (MOS). Referring to fig. 3, the nor gate 9 is composed of two P-channel enhancement type MOS transistors connected in series and two N-channel enhancement type MOS transistors connected in parallel, and referring to fig. 4, the inverter 10 is composed of one N-channel enhancement type MOS transistor and one P-channel enhancement type MOS transistor. As can be seen from the above embodiments, an or gate may be actually formed and implemented by combining the nor gate 9 and the inverter 10 to realize that the actual output level can be determined to be a high level only if one of the two power management chips outputs a high level.

In this embodiment, a CPU in a server manages two power management chips and a part of chips on a memory through an I2C, that is, a bidirectional two-wire system synchronous serial bus 11, connects each of the power management chips and the DDR5 memory chip 4, and when an output level of a certain power management chip is a low level, it can know that a fault occurs in one power management chip in a manner of scanning an address through the I2C bus 11, and determine fault information corresponding to the power management chip whose current output level is the low level, so that a user can perform operations such as replacement and maintenance on the power management chip in which the fault occurs based on the fault information.

Referring to fig. 5, in the memory design of the present application, 12V and 3.3V power supplies provided by a power supply respectively supply power to PMICs of two memories, i.e., power management chips, through two efuses, i.e., electronic fuses, after passing through a DIMM connector of a DDR5 memory motherboard, the PMICs of each DDR5 memory are converted into power supplies required by other chips on the DDR5 memory, and then supply power to the PMICs through circuit elements formed by MOS, and a CPU manages the two PMICs and some chips on the memory through an I2C bus to determine information related to a faulty chip.

Therefore, the DDR5 power management system comprises a power management chip set 1 of a plurality of power management chips; a plurality of electronic fuses respectively arranged between each power management chip and the power supply 3, so that when the current output level of any one of the power management chips is low level, the corresponding electronic fuse triggers a fusing operation to disconnect the electrical connection between the power management chip and the power supply; and the circuit component group 2 is used for determining the actual output level of the power management chip group according to the level state of the current output level of each power management chip, so that when the actual output level is high level, the power supply 3 supplies power to the DDR5 memory chip 4. Therefore, if the current output level of any power management chip in the power management chip set 1 is a low level, the electronic fuse can be fused to disconnect the power management chip from the electric connection between the power supply 3, and the normal power supply of the DDR5 memory chip 4 by using other power management chips is ensured, so that the normal power supply of the DDR5 memory chip 4 cannot be influenced when a certain power management chip fails by setting the power management chip set 1 and the electronic fuse, the reliability of the system is improved, and the problem that the DDR5 memory chip 4 cannot be used due to the influence when the power supply of only one power management chip is failed is avoided.

Referring to fig. 6, an embodiment of the present application discloses a DDR5 power management method, which is applied to a DDR5 power management system, and includes:

step S11: when the current output level of any power management chip in the DDR5 power management system is low level, the fusing operation is triggered through the corresponding electronic fuse in the DDR5 power management system, so that the electric connection between the power management chip and a power supply is disconnected.

In this embodiment, when the current output level of any one power management chip in the power management chipset 1 in the DDR5 power management system is a low level, it indicates that the power management chip fails, and then the fusing operation is triggered through a corresponding electronic fuse connected to the power management chip in the DDR5 power management system, so as to disconnect the electrical connection between the power management chip and the power supply 3, that is, in the power management chipset, if the output level of the first power management chip 7 is a low level and the output level of the second power management chip 8 is a high level, it indicates that the first power management chip 7 fails at this time, the first electronic fuse 5 DDR connected to the first power management chip 7 is fused, and the power is normally supplied to the memory chip 4 of 5 through the second power management chip 8. Therefore, when the rear end of one power management chip is short-circuited, the electronic fuse can also be timely powered off to protect the DDR5 memory chip from being damaged.

Step S12: and determining the actual output level of the power management chip set according to the level state of the current output level of each power management chip in the DDR5 power management system.

In this embodiment, the nor gate 9 and the inverter 10 in the circuit element group 2 may be used to determine the actual output circuit of the power management chipset 1 according to the level state of the current output level of each power management chip in the DDR5 power management system. That is, if the level output by any one of the first power management chip 7 and the second power management chip 8 is a high level, the actual output level may be determined as a high level, and if the levels output by both the first power management chip 7 and the second power management chip 8 are low levels, the actual output level may be determined as a low level, so that the two power management chips are redundant to each other, so as to ensure that only one of the two power management chips is normal, the normal power supply of the DDR5 memory may be ensured, and the RAS characteristic of the memory is improved.

Step S13: and when the actual output level is a high level, supplying power to the DDR5 memory chip through the power supply.

In this embodiment, after the actual output level is determined by using the circuit element group 2, when the actual output level is a high level, the DDR5 memory chip 4 is powered by the power supply 3 and the power management chip, so as to ensure that the DDR5 memory works normally.

It can be seen that, in this embodiment, when the current output level of any power management chip in the DDR5 power management system is a low level, the fusing operation is triggered through a corresponding electronic fuse in the DDR5 power management system, so as to disconnect the electrical connection between the power management chip and the power supply 3; then, according to the level state of the current output level of each power management chip in the DDR5 power management system, determining the actual output level of the power management chip set 1; and then, when the actual output level is a high level, the DDR5 memory chip 4 is supplied with power through the power supply 3. Therefore, when any power management chip outputs a low level, the electronic fuse corresponding to the power management chip can be fused to disconnect the power management chip from the power supply 3, the current output level is determined based on each power management chip in the DDR5 power management system, and when the actual output level is a high level, the DDR5 is normally supplied with power, so that a plurality of power management chips in the power management chipset 1 can be redundant with each other, and the normal power supply of the DDR5 memory is ensured through other chips when a certain chip fails, compared with the DDR5 memory with only one power management chip, the reliability of the memory is higher, and the availability and serviceability of the memory can be effectively improved.

Further, the embodiment of the application also discloses a DDR5 power supply, which comprises a power supply and the DDR5 power supply management system, and is used for supplying power to the DDR5 memory by using the DDR5 power supply. For the specific structure of the device, reference may be made to the corresponding contents disclosed in the foregoing embodiments, and details are not repeated here.

Further, the embodiment of the application also discloses a DDR5 memory, which comprises a DDR5 memory chip, the DDR5 power supply and, of course, the DDR5 power supply management system, and is used for storing operation data in the CPU in the DDR5 memory that supplies power by using the DDR5 power supply management system. For the specific structure of the device, reference may be made to the corresponding contents disclosed in the foregoing embodiments, and details are not repeated here.

Further, an embodiment of the present application further discloses a server, which includes the DDR5 memory described above, and is configured to manage computer resources using the DDR5 memory. For the specific structure of the device, reference may be made to the corresponding contents disclosed in the foregoing embodiments, and details are not repeated here.

In the present specification, the embodiments are described in a progressive manner, and each embodiment focuses on differences from other embodiments, and the same or similar parts between the embodiments are referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description.

Those of skill would further appreciate that the various illustrative components and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the components and steps of the various examples have been described above generally in terms of their functionality in order to clearly illustrate this interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the technical solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in Random Access Memory (RAM), memory, read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

Finally, it should also be noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrases "comprising one of 8230; \8230;" 8230; "does not exclude the presence of additional like elements in a process, method, article, or apparatus that comprises the element.

The technical solutions provided by the present application are introduced in detail, and specific examples are applied in the description to explain the principles and embodiments of the present application, and the descriptions of the above examples are only used to help understanding the method and the core ideas of the present application; meanwhile, for a person skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.

Claims

1. A DDR5 power management system, comprising:

a power management chip group including a plurality of power management chips;

2. The DDR5 power management system of claim 1, wherein the power management chipset comprises a first power management chip and a second power management chip, so that the power supply supplies power to the DDR5 memory chip through the other power management chip when a fault occurs in a line where any one of the power management chips is located.

3. The DDR5 power management system of claim 2, wherein the number of electronic fuses comprises a first electronic fuse and a second electronic fuse;

4. The DDR5 power management system of claim 1, wherein the set of circuit elements is a set of elements based on a nor gate and an inverter, and is disposed between the power management chipset and the DDR5 memory chips.

5. The DDR5 power management system of claim 4, wherein the NOR gate and the inverter are both devices constructed based on metal oxide semiconductor field effect transistors.

6. The DDR5 power management system of any of claims 1 to 5, further comprising:

7. A DDR5 power management method, applied to the DDR5 power management system as claimed in any one of claims 1 to 6, comprising:

8. A DDR5 power supply, comprising a power supply and a DDR5 power management system as claimed in any of claims 1 to 6.

9. A DDR5 memory comprising DDR5 memory chips and the DDR5 power supply of claim 8.

10. A server comprising the DDR5 memory of claim 9.