CN115719049A - Automatic layout method of circuit schematic diagram - Google Patents
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Abstract
The invention discloses an automatic layout method of a circuit schematic diagram, belongs to the field of electronic information, and improves the efficiency and accuracy of circuit schematic diagram inversion engineering. The invention comprises the following steps: firstly, reading net list information and component library information, performing data conversion, and then performing cluster division on all components according to pin information and connection information of the components; then, local layout is respectively carried out on each subdivision, and the local layout mainly comprises digraph conversion, logic column dismounting and changing positioning, logic row positioning and physical expansion positioning; finally, outputting the placing coordinates and the rotating angle of each component; the problems of low manual inversion speed and high error rate of the conventional circuit schematic diagram are solved.
Description
Technical Field
The invention belongs to the field of electronic information, and particularly relates to an automatic layout method of a circuit schematic diagram.
Background
The electronic equipment is changed from good to bad, which is a necessary process, and the more and more common application causes the electronic equipment with faults to be accumulated. Due to the limitation of equipment property protection and technical patents, the electronic equipment is sold without being attached with a circuit schematic diagram of the equipment, or the circuit schematic diagram of the equipment is damaged or lost, which causes insurmountable obstacles for the autonomous repair and maintenance of the electronic equipment.
Although the existing electronic equipment repair technology is broken through, the current situation that the fault of the electronic equipment cannot be maintained in time due to the lack of a circuit schematic diagram still cannot be changed. Expensive electronic equipment is left unused or operated with a fault, so that resource waste and environmental pollution are more and more serious. The practice of extensive equipment maintenance has proven that most of these malfunctioning electronic equipment, if any, are easily repaired. From the perspective of equipment maintenance, the equipment circuit schematic diagram is an important basis for carrying out equipment maintenance operation, and as long as the equipment circuit schematic diagram is provided, a test and maintenance scheme of the equipment can be formulated under the existing conditions, and the reason of equipment failure is analyzed and fault maintenance is carried out.
The PCB circuit restoration technology is also researched and developed domestically, and generally comprises a measurement fixed table, a passage detector and a local area network. From the steps of circuit restoration and the realization principle, the method comprises a front-end detection part and a back-end logic synthesis part, wherein the front-end detection part is used for measuring the communication relation among all element pins on a circuit board and generating a measurement netlist through bookkeeping; and the back-end logic synthesis is to perform reverse analysis according to the measured netlist to restore a circuit schematic diagram. The manual inversion technique has certain practical limitations, and physical tests, also called contact inversion, need to be borrowed. The study in this field abroad reports the related data, most typically a PCB testing instrument, which is advanced to generate a network table file with a general format, but the schematic diagram inversion is very poor, and the reference function cannot be achieved, not to mention the use.
The concept CIS, a schematic diagram design part of the Cadence OrCAD, is an excellent schematic diagram design software in the industry because of its beautiful interface, easy access and operation, and powerful functions such as simulation. However, such software can only be used for manually drawing schematic diagrams, and cannot automatically process and draw related schematic diagrams. Practical situations show that when manual schematic diagram drawing is performed by adopting the software, the manual workload is large, the design efficiency is low, the repeated labor is high, the consistency of design data among all design stages cannot be guaranteed, and errors are easy to occur, so that schematic diagram drawing software such as Capture CIS cannot meet requirements of all aspects in a schematic diagram reverse recovery process.
Disclosure of Invention
The invention provides an automatic layout method of a circuit schematic diagram, which solves the problems of circuit division and automatic layout in the current circuit schematic diagram inversion project.
In order to achieve the purpose, the invention adopts the following technical scheme:
an automatic layout algorithm for a schematic of a circuit comprising the steps of:
(1) A circuit dividing process: the method comprises the steps that a complete circuit diagram corresponding to a netlist is quite complex, all components need to be reasonably clustered and divided, the method divides the whole circuit through network cross-comparison based on a network connection relation, and then secondary combination is conducted on certain minimum divisions based on an obtained initial partition group;
(2) And (3) a directed graph conversion process: pin redirection operation is carried out on each divided group, although manual drawing is generally carried out from left to right according to the current trend, due to the fact that a large number of feedback circuits exist, layout is not strictly carried out from left to right according to the current trend, and therefore the step is mainly based on network relation to redirect the in-and-out direction of the pins so as to consider the front-back relation among components on the whole;
(3) And (3) logic ring-detaching column positioning process: firstly, a ring disassembling operation is carried out, namely, a loop in the directed network obtained in the step is disassembled, then the column position of each divided component is determined based on a loop-free directed graph, the column position is a logic position at the moment, and the left-right interval and the length and the width of the component are not considered;
(4) And (3) logic row positioning process: firstly, adjusting the position of each column of components based on an independent fan-in set strategy, and then adjusting the logic row position of the components based on a gravity center rule;
(5) And (3) a physical extension positioning process: the actual coordinate information is calculated based on the logical row and column positions calculated in the above steps, firstly, the longest column in the divided group is expanded based on the principle that the longest column is first prioritized, then, the rest columns are expanded from the longest column to the front and back, and pins allowed by the conditions are all strictly aligned based on the pin alignment principle when the row position is calculated, which is beneficial to the aesthetic appearance of the following wiring. In addition, if the corresponding condition of pin alignment is not satisfied, the line position is calculated using the rule of the center of gravity.
In the above steps, the step (2) specifically includes the following steps:
(21) Firstly, identifying a power amplifier structure in each subdivision according to the subdivision, binding a double-end component which is completely connected with a power amplifier component with the power amplifier component according to the pin direction, and then deleting the double-end component bound by the power amplifier structure from the subdivision, wherein the bound double-end component is attached to the power amplifier component and is not considered temporarily, so that the network in a schematic diagram is simplified to a certain extent;
(22) Then, all networks with external connection are extracted according to the subdivision, one network is selected as an input network, and the network selection principle is as follows: the pin number of the largest component contained in the network is minimum compared with other networks, and if the pin numbers are the same, the network with the minimum component number is selected;
(23) Then, performing breadth-first traversal by the selected input network according to a left-in right-out principle, during traversal, only pressing the output end node in each network into a queue, and only performing assignment on pin attributes of the input end nodes without pressing the input end nodes into the queue to be traversed, namely, only extending backwards from left to right and not extending backwards from front to back; in addition, a power supply network and a grounding network, namely a network comprising a power supply and a grounding network, are not considered during traversal; during the traversal, the attribute of the input end pin is set as input, the other end pins are set as output, the other ends are traversed, and some components are rotated according to the left-in right-out principle so as to meet the condition that the input end is on the left side and the output end is on the right side, but the components with the pin number larger than 4 cannot be rotated; the components with the pin number of 1 are uniformly assigned as output nodes; for the condition that all nodes in a network are judged as input end nodes or output end nodes, if the network has external connection, the network is judged as an output network or an input network of the whole subdivision, all the nodes are input end nodes or output end nodes, and if the network has no external connection, a smallest component which is not accessed is selected for overturning;
(24) Then, the rest networks with external connection are continuously processed, for the rest networks, if all nodes in the networks are accessed, the networks are deleted and are not independently processed, then one network is selected to continuously traverse search in a wide range, and the set of the networks is deleted once each traversal is finished;
(25) Then all power networks are processed, if the pin number of the power network connection node is less than 3, the power network connection node is rotated according to specific conditions, and the rest ends are traversed backwards; if the number of the pins is more than 3, only the component with the pins connected with the power supply at the left end or the upper end of the component is traversed downwards continuously, and if the number of the pins at the right end or the lower end of the component is not traversed continuously; the processed nodes can not be changed during traversal;
(26) Then processing the bound power amplifier structure and the double-end structure before, namely processing the pin property and the angle of the double-end component bound together according to the angle of the power amplifier component;
(27) Redefining the network according to the determined new pin direction, and converting into a directed graph.
The step (3) specifically comprises the following steps:
(31) Firstly, placing all components without internal input in the first row;
(32) Then, recognizing all feedback loops according to the front-back connection relation of the components, sequentially calculating loop detaching coefficients and detaching loops according to the number of the feedback loops from large to small, and then placing the components according to a placement rule, wherein the placement rule is as follows: traversing all front connecting node positions of the current node, and placing the current component in a column behind the maximum column of all front connecting nodes; for the rest components which are not placed, if all the front connecting nodes are placed, placing according to a placing rule, or placing later;
the step (4) specifically comprises the following steps:
(41) Traversing all nodes, searching all existing independent fan-in sets, and adjusting all components in the fan-in sets to the column head of each row, wherein the definition of the independent fan-in sets is as follows: searching forwards deeply until no front connection node exists by taking the current component as a root node, and if the backward connection of the front connection node is one point, taking the current component as an independent fan-in set;
(42) And then calculating the gravity center value of each component for position adjustment: calculating the gravity center position according to the position of the front connecting node of each node and the connecting weight so as to rearrange the sequence of the components in each column;
the step (5) specifically comprises the following steps:
(51) Firstly, performing row expansion, performing basic row expansion on each column according to the height of the component, then preferentially laying out the longest column, and then laying out backwards based on the longest column, wherein the laying-out rule is as follows: a. if the current component only has one front connection component, calculating the physical position of the component according to a pin alignment principle, wherein the pin alignment principle is to strictly align corresponding connection pins of the two components in a graph according to information such as the height, the rotation angle, the pin position and the like of the component; b. if the current component has a plurality of front connection components, calculating a physical position according to a pin alignment principle by taking a first front connection component in a front row of the current component as a reference; c. sorting according to the calculated physical positions, sequentially placing from top to bottom in sequence, and moving down the position of the next component if the components are overlapped;
(52) Then, the layout is carried out forward by taking the longest column and the laid column as the reference, and the layout rule of the components with the back connection is as follows: a. traversing all the post-connection of the components, judging whether the pin alignment principle is met, and calculating the physical position by taking the latest row of the most upstream post-connection components which meet the conditions as a reference; b. if no rear connection component meeting pin alignment exists, calculating the physical position according to a gravity center calculation rule based on the position of the rear connection component in the closest column; the layout rule for components without post-connection is as follows: a. firstly, laying out components which are not laid out continuously from a first row to the next row, wherein the position calculation rule is that the physical position of each component is calculated under the condition that each component is not overlapped with the next component; b. then, the rest components without post connection are distributed, the position calculation rule is that if the last component is distributed, the physical position is calculated under the condition that the last component is not overlapped, and if the last component is not distributed, the current component is distributed again; finally, sorting is carried out according to the calculated physical positions, if the position of the minimum component is less than 0, the whole layout components need to be moved downwards, the position of the minimum component is ensured to be 1, then the columns are sequentially placed from top to bottom, and if the components are overlapped, the position of the next component is moved downwards;
(53) And finally, selecting the maximum component width of each column of components from front to back as the width of the column for carrying out physical column expansion.
Has the advantages that: the invention provides an automatic layout algorithm of a circuit schematic diagram, which is characterized in that a whole circuit schematic diagram is subjected to circuit division through a clustering algorithm based on network intersection and comparison; converting the original many-to-many undirected network graph into a directed graph with a precedence order through directed graph conversion; positioning column logic positions of the components through ring dismantling processing of a feedback ring and a traversal algorithm based on a breadth-first strategy; the row logic position of each column of components is further adjusted through the identification processing of the independent fan-in set; and finally, the actual coordinate position of each component is obtained by physically expanding the longest column backwards and forwards according to the obtained logical position and the principle of managed alignment.
Drawings
FIG. 1 is an overall flow diagram of an embodiment of the present invention;
FIG. 2 is a flow chart of step 2 of an embodiment of the present invention;
fig. 3 is an exemplary diagram of the power amplifier structure in step 2 according to the embodiment of the present invention;
fig. 4 is an exemplary diagram of a double-ended connection structure of step 2 of the embodiment of the present invention;
fig. 5 is a diagram illustrating a generated result in the embodiment of the present invention.
Detailed Description
The invention is described in detail below with reference to the following figures and specific examples:
as shown in fig. 1, an automatic layout algorithm of a schematic diagram of a circuit includes the following steps:
step 1: dividing the whole circuit by adopting network cross-matching based on the network connection relation, and then carrying out secondary combination based on the obtained initial division group to process some tiny division groups;
step 2: performing pin redirection and directed graph conversion on each partition group obtained after the partition in the step 1;
and step 3: disassembling loops in the directed network, and then determining the column position of each divided group of components based on a loop-free directed graph, wherein the column positions are all logic positions, and the left-right interval and the length and width of the components are not considered;
and 4, step 4: adjusting the row position of each column of components based on an independent fan-in set strategy, and then adjusting the logic row position of the components based on a gravity center rule;
and 5: and calculating actual coordinate information based on the logic row and column positions calculated in the step.
In the above steps, step 1 specifically includes: firstly, each component in the circuit is assumed as a subset, the association weights among different divided subsets are evaluated by using a weight evaluation function based on network cross-over ratio, then two subsets with the maximum association weights are selected according to the connection weights among the subsets to be combined, and the weight evaluation function is as follows:
in the formula: n is a radical of an alkyl radical i The number of networks in which the subset i resides; n is ij Number of networks in which both subset i and subset j are present at the same time, n j The number of networks in which subset j resides;
the relevant constraints in the clustering process are as follows:
(11) The threshold value of the merging ratio is 0.5, namely the associated weight of one party of the two merging subsets is not lower than 0.5;
(12) Two pins greater than 20 are not allowed to be in the same group; the components with the pin number larger than 40 and the components with the pin number larger than 3 are not allowed to be in the same group;
and after the primary clustering is finished, carrying out secondary merging on the minimum division groups, wherein the minimum division groups refer to the sub-division groups with the number of the components being less than 8 and the number of the pins of the components being less than or equal to 3, and the minimum division groups are preferentially merged with the minimum division groups without the large components during secondary merging.
As shown in fig. 2, the specific steps of step 2 are as follows:
step 201: identifying a power amplifier structure in each subdivision according to the subdivision, binding a double-end component which is completely connected with a power amplifier component with the power amplifier component according to the pin direction, and then deleting the double-end component bound by the power amplifier structure from the subdivision, wherein the bound double-end component is attached to the power amplifier component and is not considered temporarily, so that the network in the schematic diagram is simplified to a certain extent;
step 202: extracting all networks with external connection aiming at the subdivision, selecting one network as an input network, wherein the network selection principle is as follows: the pin number of the largest component contained in the network is minimum compared with other networks, and if the pin numbers are the same, the network with the minimum component number is selected;
step 203: the selected input network is used for traversing the components according to the principle of left-in and right-out, only the output end nodes in each network are pressed into the queue during traversing, the input end nodes only reset the pin attributes and cannot be pressed into the queue to be traversed, namely, the input end nodes extend backwards from left to right and do not extend backwards from front to back. In addition, a power supply network and a grounding network, namely a network comprising a power supply and a grounding network, are not considered during traversal; during the traversal, the attribute of the input end pin is set as input, the other end pins are set as output, the other ends are traversed, and some components are rotated according to the left-in right-out principle so as to meet the condition that the input end is on the left side and the output end is on the right side, but the components with the pin number larger than 4 cannot be rotated; the components with the pin number of 1 are uniformly assigned as output nodes; for the condition that all nodes in a network are judged as input ends or output ends, if the network has external connection, the network is judged as an input network or an output network of the whole subdivision, all the nodes are input end nodes or output end nodes, and if the network has no external connection, a smallest component which is not accessed is selected for overturning;
step 204: continuously processing the rest networks with external connection, firstly deleting the networks, deleting the networks with all nodes accessed without independent processing, then selecting one network to continuously traverse and search in a breadth mode, and deleting the network set once after traversing;
step 205: processing all power networks, if the pin number of the power network connection node is less than 3, rotating according to specific conditions, and traversing the rest ends backwards; if the number of the pins is more than 3, only the component with the pins connected with the power supply at the left end or the upper end of the component is traversed downwards, and if the number of the pins at the right end or the lower end of the component is not traversed continuously; during traversal, the nodes processed in the front are not changed;
step 206: processing the bound power amplifier structure and the double-end structure before, namely setting the pin property and the angle of the double-end component bound with the power amplifier component according to the angle of the power amplifier component;
step 207: redefining the network according to the new pin direction, and converting the redefined network into a directed graph;
fig. 3 and 4 show the power amplifier structure and the double-end full-connection structure for performing the individual identification and the pretreatment in step 2.
The specific development steps of step 3 are as follows:
step 301: all components without internal input are arranged as the 1 st column
Step 302: recognizing all feedback loops according to the front-back connection relation of the components, then calculating loop detaching coefficients in sequence and detaching the loops, then placing the components according to a placing rule, wherein the placing rule is as follows: traversing all front connection node positions of the current node, and placing the current component in a column behind the maximum column of all the front connection nodes; for traversed components which are not placed, if all front connection nodes are placed, placing according to a placing rule, otherwise, placing later, wherein the number p of ring-disassembling systems i The calculation formula of (c) is as follows:
in the formula: n is the total number of nodes contained in the feedback loop; dis (i, j) represents the distance in the ring between node i and node j, indegree i Represents the degree of entry, outdegree, of node i i And (3) representing the degree of the node i, wherein the isoOutnode (i) represents that whether the node i is an output node is judged, and the output node means that the current node is connected with other networks besides the current ring network.
The specific development steps of step 4 are as follows:
step 401: identifying all existing independent fan-in sets, and adjusting all components in the fan-in sets to the column head of each column; the definition of the independent fan-in sets is as follows: searching forwards and deeply until no front connection node exists by taking the current component as a root node, and if the backward connection of the front connection node is in one point, taking the current component as an independent fan-in set;
step 402: calculating the gravity center position according to the position of the front connection node of each node and the connection weight, rearranging the sequence of the components in each column, wherein the gravity center value calculation formula is as follows:
in the formula, c represents the total number of front connecting nodes of the node i, weight (i, j) represents the number of the leaders for connecting the node i and the node j, and row (j) represents the row number of the node j;
the specific unfolding steps of step 5 are as follows:
step 501: and performing basic row expansion on each column according to the height of the components, and then performing backward layout by taking the longest column as a reference, wherein the layout rule is as follows: a. if the current component only has one front connection component, the physical position of the component is calculated according to a pin alignment principle, namely, the corresponding connection pins of the two components are strictly aligned in the drawing according to the height, the rotation angle, the pin position and other information of the component. b. And if the current component has a plurality of front connection components, calculating the physical position by taking the first front connection component in the front row of the current component as a reference according to the pin alignment principle. c. Sorting according to the calculated physical positions, sequentially placing from top to bottom in sequence, and moving down the position of the next component if the components are overlapped;
step 502: and carrying out layout forwards by taking the longest row and the laid row as reference, wherein the layout rule of the components with the rear connection is as follows: a. traversing all the post-connection of the components, judging whether the pin alignment principle is met, and calculating the physical position by taking the most upstream post-connection component in the nearest row which meets the condition as a reference; b. if no rear connection component meeting pin alignment exists, calculating the physical position according to a gravity center calculation rule based on the position of the rear connection component in the closest column, wherein the gravity center calculation rule is similar to that in the step 4; the layout rules for components without back connection are as follows: a. firstly, laying out components which are not laid out continuously from a first row to the next row, wherein the position calculation rule is that the physical position of each component is calculated under the condition that each component is not overlapped with the next component; b. then, laying out the remaining components without post connection, wherein the position calculation rule is that if the last component is laid, the physical position is calculated under the condition that the last component is not overlapped, and if the last component is not laid, the current component is laid later; finally, sorting is carried out according to the calculated physical positions, if the position of the minimum component is less than 0, all the components which are already arranged need to be integrally moved downwards, the minimum row position of the components is ensured to be 1, then the rows are sequentially placed from top to bottom, and if the components are overlapped, the position of the next component is moved downwards;
step 503: and selecting the maximum component width of each column of components from front to back as the width of the column to perform physical column expansion in sequence.
FIG. 5 shows the result of the principle diagram of the invention combined with cadence software and the result of the principle diagram of the invention.
The above-mentioned embodiments are merely illustrative of the preferred embodiments of the present invention, and the scope of the present invention should not be limited thereto, and any modifications made on the basis of the technical solutions according to the technical ideas presented by the present invention are within the scope of the present invention.
Claims (10)
1. An automatic layout method of a schematic circuit diagram is characterized by comprising the following steps:
step 1: dividing the whole circuit by adopting network cross-combining ratio based on the network connection relation, and then carrying out secondary combination based on the obtained initial division group;
step 2: performing pin redirection and directed graph conversion for each partition group;
and 3, step 3: disassembling loops in the directed network, and then determining the column position of each divided group of components based on a loop-free directed graph, wherein the column positions are all logic positions, and the left-right interval and the length and width of the components are not considered;
and 4, step 4: adjusting the row position of each column of components based on an independent fan-in set strategy, and then adjusting the logic row position of the components based on a gravity center rule;
and 5: and calculating actual coordinate information based on the logic row and column positions calculated in the step.
2. The method according to claim 1, wherein step 1 comprises the following steps: firstly, each component in the circuit is assumed as a subset, the association weights among different divided subsets are evaluated by using a weight evaluation function based on network intersection ratio, and then two subsets with the maximum association weights are selected according to the connection weights among the subsets to be combined, wherein the weight evaluation function is as follows:
in the formula: n is i The number of networks in which the subset i resides; n is ij N is the number of networks in which both subset i and subset j are present at the same time j The number of networks in which subset j resides;
and after the primary combination is finished, carrying out secondary combination on the minimum division groups, wherein the minimum division groups are preferentially combined with the minimum division groups without the large components during the secondary combination.
3. The method of claim 2, wherein the constraints in the merging process are as follows: the threshold value of the merging ratio is 0.5, namely the association weight of one party subset of the two merging subsets is not lower than 0.5; two pins greater than 20 are not allowed to be in the same group; components with pin numbers greater than 40 are not allowed to be in the same group as components with pin numbers greater than 3.
4. The method for automatically laying out a circuit schematic according to claim 1, wherein the step 2 specifically comprises the steps of:
step 201: identifying a power amplifier structure in each subdivision according to the subdivision, binding a double-end component which is completely connected with a power amplifier component with the power amplifier component according to the pin direction, and then deleting the double-end component bound by the power amplifier structure from the subdivision;
step 202: extracting all externally connected networks for the subdivision, and selecting one network as an input network
Step 203: performing breadth-first traversal by using the selected input network according to a left-in right-out principle and resetting corresponding pin attributes;
step 204: and (4) continuously processing the rest networks with external connection, firstly deleting the networks, and deleting the networks with all nodes accessed without independent processing. Then, selecting a network to continue the breadth traversal, and deleting the network set once after the traversal is finished;
step 205: processing all power networks, if the pin number of the power network connection node is less than 3, rotating according to specific conditions, and traversing the rest ends backwards; if the number of the pins is more than 3, only the component with the pins connected with the power supply at the left end or the upper end of the component is traversed downwards, and if the number of the pins at the right end or the lower end of the component is not traversed continuously; the processed nodes can not be changed during traversal;
step 206: processing the bound power amplifier structure and the double-end structure before, namely setting the pin property and the angle of the double-end component bound with the power amplifier component according to the angle of the power amplifier component;
step 207: redefining the network according to the new pin direction, and converting into a directed graph.
5. The method according to claim 4, wherein the traversal in step 203 sets the input end pin attribute as input, sets the other end pins as output, and traverses the other ends, and rotates some components according to the left-in-right-out principle to conform to the condition that the input end is on the left, the output end is on the right, but the components with the pin number greater than 4 do not rotate; the components with the pin number of 1 are uniformly assigned as output nodes; and if the network has no external connection, selecting one minimum element device which is not accessed to turn over.
6. The method for automatically laying out a schematic circuit diagram according to claim 1, wherein step 3 specifically comprises the steps of:
step 301: all components without internal input are arranged as the 1 st column
Step 302: all feedback loops are identified according to the front-back connection relation of the components, then loop detaching coefficients and loops are sequentially calculated and detached, then the components are placed according to a placement rule, and the placement rule is as follows: traversing all front connection node positions of the current node, and placing the current component in a column behind the maximum column of all the front connection nodes; and for the traversed and unset components, if all the front connecting nodes are placed, placing the components according to a placing rule, otherwise, placing the components later.
7. The method according to claim 6, wherein the ring-splitting number p in step 302 is i The calculation formula of (a) is as follows:
in the formula: n is the total number of nodes contained in the feedback loop; dis (i, j) represents the distance in the ring between node i and node j, indegree i Represents the degree of entry, outdegree, of node i i Representing the out degree of the node.
8. The method according to claim 1, wherein step 4 comprises the following steps:
step 401: identifying all existing independent fan-in sets, and adjusting all components in the fan-in sets to the column head of each column;
step 402: calculating the gravity center position according to the position of the front connecting node of each node and the connecting weight, and rearranging the sequence of the components in each column, wherein the gravity center value calculation formula is as follows:
in the formula, n represents the total number of front connection nodes of the node i, weight (i, j) represents the number of the custody of the connection between the node i and the node j, and row (j) represents the row number of the node j.
9. The method according to claim 1, wherein step 5 comprises the following steps:
step 501: performing basic row expansion on each column according to the height of the components, and then performing backward layout by taking the longest column as a reference, wherein the layout rule is as follows: if the current component only has one front connection component, calculating the physical position of the component according to a pin alignment principle, wherein the pin alignment principle is to strictly align corresponding connection pins of the two components in a graph according to information such as the height, the rotation angle, the pin position and the like of the component; if the current component has a plurality of front connection components, calculating a physical position according to a pin alignment principle by taking a first front connection component in a front row of the current component as a reference; sorting according to the calculated physical positions, sequentially placing from top to bottom in sequence, and moving down the position of the next component if the components are overlapped;
step 502: carrying out layout forward by taking the longest column and the laid column as reference;
step 503: and from front to back, selecting the maximum component width of each column of components as the width of the column to perform physical column expansion in sequence.
10. The method of claim 9, wherein the layout rule for the components with post-connection in step 502 is: traversing all the post-connection of the components, judging whether the pin alignment principle is met, and calculating the physical position by taking the most upstream post-connection component in the nearest row which meets the condition as a reference; if no rear connection component meeting the pin alignment exists, calculating the physical position according to the gravity center calculation rule in the step 4 based on the position of the rear connection component in the closest row; the layout rule of the components without post connection is as follows: firstly, laying out components which are not laid out continuously from a first row to the next row, wherein the position calculation rule is that the physical position of each component is calculated under the condition that each component is not overlapped with the next component; then, laying out the remaining components without post connection, wherein the position calculation rule is that if the last component is laid, the physical position is calculated under the condition that the last component is not overlapped, and if the last component is not laid, the current component is laid later; and finally, sorting according to the calculated physical positions, if the position of the minimum component is less than 0, moving all the distributed components downwards integrally to ensure that the position of the minimum row of the components is 1, then sequentially placing the row from top to bottom, and if the components are overlapped, moving the position of the next component downwards.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116542188A (en) * | 2023-07-06 | 2023-08-04 | 深圳市鑫迅维科技有限公司 | PCB schematic diagram generation method, electronic equipment and storage medium |
| CN117436399A (en) * | 2023-12-22 | 2024-01-23 | 深圳鸿芯微纳技术有限公司 | Automatic layout method and device of circuit schematic diagram device and electronic equipment |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116542188A (en) * | 2023-07-06 | 2023-08-04 | 深圳市鑫迅维科技有限公司 | PCB schematic diagram generation method, electronic equipment and storage medium |
| CN116542188B (en) * | 2023-07-06 | 2024-04-05 | 深圳市鑫迅维科技有限公司 | PCB schematic diagram generation method, electronic equipment and storage medium |
| CN117436399A (en) * | 2023-12-22 | 2024-01-23 | 深圳鸿芯微纳技术有限公司 | Automatic layout method and device of circuit schematic diagram device and electronic equipment |
| CN117436399B (en) * | 2023-12-22 | 2024-03-26 | 深圳鸿芯微纳技术有限公司 | Automatic layout method and device of circuit schematic diagram device and electronic equipment |
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