CN115718620A

CN115718620A - Code program migration method, device, equipment and storage medium

Info

Publication number: CN115718620A
Application number: CN202211468944.2A
Authority: CN
Inventors: 张一弘; 程茂; 毛玉泽; 栾学广; 岳泽宇
Original assignee: Kedong Guangzhou Software Technology Co Ltd
Current assignee: Kedong Guangzhou Software Technology Co Ltd
Priority date: 2022-11-22
Filing date: 2022-11-22
Publication date: 2023-02-28

Abstract

The embodiment of the invention discloses a code program migration method, a device, equipment and a storage medium, wherein the method comprises the following steps: creating a first address mapping table, and applying the first address mapping table to a Memory Management Unit (MMU) for address mapping; the method comprises the steps of obtaining a code thermodynamic diagram aiming at a target program at fixed time, and determining a target code block with the highest use times according to the code thermodynamic diagram, wherein the code thermodynamic diagram comprises the use times of each code block; and migrating the target code block with the highest use number to the SRAM for storage based on the address mapping result of the MMU. And obtaining a target code block with the highest use frequency according to the obtained code thermodynamic diagram of the target program, and remapping the target code block to an SRAM physical address with a higher read rate from a virtual address mapped under a DDR physical address based on an address mapping result of a Memory Management Unit (MMU), so that the access speed and the operating efficiency of the target program are obviously improved.

Description

Code program migration method, device, equipment and storage medium

Technical Field

The embodiment of the invention relates to the technical field of computer science, in particular to a code program migration method, a device, equipment and a storage medium.

Background

At present, most of the CPUs have three memories, which are a Cache, a Static Random Access Memory (SRAM), and a Double Data Rate (DDR). The Cache speed is the fastest, the size is usually 2MB or less, the SRAM speed is centered, the size is usually more than 32MB, the DDR speed is the slowest, and the size is usually more than 2 GB.

Since Cache and SRAM are both internal to the CPU, and DDR is external to the CPU. DDR speed can be tens of times slower than SRAM and Cache. Because the space occupied by the code program is very large, the code program is usually stored in the DDR, although the Cache can automatically Cache the DDR to improve the overall performance, because the Cache is too small, the overall performance is often reduced because the Cache misses a large amount when a large amount of memory is read and written. Therefore, the current processor reads the code program from the DDR, which significantly reduces the access speed and thus the running efficiency of the code program.

Disclosure of Invention

The embodiment of the invention provides a code heat degree statistical method, a device, equipment and a storage medium, which are used for realizing automatic statistics of code heat degrees.

In a first aspect, an embodiment of the present invention provides a method for migrating a code program, including: creating a first address mapping table, and applying the first address mapping table to a Memory Management Unit (MMU) for address mapping, wherein the first address mapping table comprises a first mapping relation between an original double-rate synchronous dynamic random access memory (DDR) physical address and an original virtual address of each code block of a stored target program, and a second mapping relation between a reserved first virtual address and a Static Random Access Memory (SRAM) physical address;

the code thermodynamic diagram of the target program is obtained regularly, and a target code block with the highest use times is determined according to the code thermodynamic diagram, wherein the code thermodynamic diagram comprises the use times of each code block;

migrating the target code block with the highest use number to the SRAM physical address for storage based on the address mapping result of the MMU.

In a second aspect, an embodiment of the present invention provides a code program migration apparatus, including: the memory management unit MMU comprises a first address mapping table creating module, a second address mapping table creating module and a third address mapping table creating module, wherein the first address mapping table creating module is used for creating a first address mapping table and applying the first address mapping table to the memory management unit MMU for address mapping, and the first address mapping table comprises a first mapping relation between an original double-rate synchronous dynamic random access memory DDR physical address and an original virtual address of each code block of a stored target program and a second mapping relation between a reserved first virtual address and a static random access memory SRAM physical address;

the target code block determining module is used for acquiring a code thermodynamic diagram of the target program at fixed time and determining a target code block with the highest use times according to the code thermodynamic diagram, wherein the code thermodynamic diagram comprises the use times of each code block;

and the target code block migration module is used for migrating the target code block with the highest use number to the SRAM physical address for storage based on the address mapping result of the MMU.

In a third aspect, an embodiment of the present invention provides a computer device, where the computer device includes:

one or more processors;

a storage device for storing one or more programs,

when executed by the one or more processors, cause the one or more processors to implement the code program migration method as described above.

In a fourth aspect, the present invention provides a computer-readable storage medium, on which a computer program is stored, which when executed by a processor implements the code program migration method described above.

According to the technical scheme of the embodiment of the invention, the target code block with the highest use frequency is migrated from the DDR physical address to the SRAM physical address with the higher reading speed through the memory management unit MMU according to the obtained code thermodynamic diagram of the target program, so that the access speed and the operation efficiency of the target program are obviously improved.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and those skilled in the art can also obtain other related drawings based on the drawings without inventive efforts.

FIG. 1 is a flowchart of a migration method of a code program according to an embodiment of the present invention;

FIG. 2 is a flowchart of a migration method of a code program according to a second embodiment of the present invention;

fig. 3 is a schematic structural diagram of a migration apparatus of a code program according to a third embodiment of the present invention;

fig. 4 is a schematic structural diagram of a computer device according to a fourth embodiment of the present invention.

Detailed Description

In order to make those skilled in the art better understand the technical solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the invention described herein are capable of operation in sequences other than those illustrated or described herein. Moreover, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

Example one

Fig. 1 is a flowchart of a code program migration method according to an embodiment of the present invention, where this embodiment is applicable to a scenario of migrating a code program, and the method may be executed by a code program migration apparatus according to an embodiment of the present invention, where the apparatus may be implemented in a form of hardware and/or software. As shown in fig. 1, the method includes:

step S101, a first address mapping table is created, and the first address mapping table is applied to the MMU for address mapping.

Optionally, creating a first address mapping table includes: acquiring a pre-created original address mapping table, wherein the original address mapping table comprises a first mapping relation between an original DDR physical address and an original virtual address of each code block of a storage target program; determining an SRAM physical address from an SRAM, and acquiring a reserved first virtual address; and establishing a second mapping relation between the SRAM physical address and the first virtual address, and updating the original address mapping table according to the second mapping relation to obtain the first address mapping table.

Specifically, the target program in the embodiment occupies a very large storage space, and therefore is completely stored in the DDR at the initial time, and the processor specifically refers to a pre-created original address mapping table to access the target program stored in the DDR, and the corresponding relationship between the original DDR physical address and the original virtual address in the original address mapping table is referred to as a first mapping relationship, as shown in table 1 below, which is an example of the pre-created original address mapping table:

TABLE 1

Code block numbering	Virtual address space	Physical address space
			1	Virtual address A	DDR physical address X
2	Virtual address B	DDR physical address Y
			....
n	Virtual address M	DDR physical address N

If a specified code block in the target program is accessed based on table 1, for example, code block 1, the processor specifically sends the virtual address space-virtual address a of code block 1 to the memory management unit MMU, and the MMU determines the physical address space-DDR physical address X corresponding to the virtual address a according to table 1, reads code block 1 from DDR, and feeds back the code block 1 to the processor for execution. However, since the read speed of the DDR is very slow, the processor has very slow access efficiency when reading the target program from the DDR.

Therefore, in this embodiment, the processing machine may determine an SRAM physical address Z which does not store data from an SRAM with a faster access speed and a suitable storage space, map the SRAM physical address Z to a reserved unused first virtual address C, thereby establishing a second mapping relationship between the SRAM physical address and the first virtual address, and update the original address mapping table according to the second mapping relationship to obtain the first address mapping table, as shown in table 2 below, which is an example of the obtained first address mapping table:

TABLE 2

Code block numbering	Virtual address space	Physical address space
			1	Virtual address A	DDR physical address X
2	Virtual address B	DDR physical address Y
			....
n	Virtual address M	DDR physical address N
				Virtual address C	SRAM physical address Z

The first address mapping table comprises a first mapping relation between an original DDR physical address and an original virtual address of the DDR of each code block of the target program, and a second mapping relation between the reserved first virtual address and a Static Random Access Memory (SRAM) physical address. However, the second mapping relationship constructed in the first address mapping table in table 2 is not determined specifically which code block corresponds to, and needs to be determined subsequently according to the code thermodynamic diagram of the target program. After the processor creates the first address mapping table, the first mapping table is applied to the MMU, so that the MMU performs actual address mapping according to the correspondence between the virtual address and the physical address.

And step S102, periodically acquiring a code thermodynamic diagram of the target program, and determining a target code block with the highest use frequency according to the code thermodynamic diagram.

Optionally, the method for obtaining the code thermodynamic diagram of the target program at fixed time includes obtaining a context of a highest priority ready thread at each statistical moment in a specified time range, wherein the context of the highest priority ready thread includes a numerical value of a program counting register PC; determining the number of code blocks used in a target program at each statistical moment according to the numerical value of the PC, wherein the target program comprises a highest-priority ready thread; and updating the code array which stores the use times of each code block according to the number of the code block so as to acquire the code thermodynamic diagram in the target program.

Specifically, the device in this embodiment includes multiple threads, including a statistical thread for performing heat statistics and at least two threads formed by a target program, and sets the highest priority of the statistical thread among all the threads, so that when the statistical thread queries the execution state of the target program to obtain the heat of the code, because the priority of the statistical thread is the highest, the statistical thread can perform priority execution, and thus other threads stop running and enter a ready state. After the counting thread is started each time, all threads corresponding to the current counting time are determined, and the thread which is in the running state at the latest in all the threads is used as the highest-priority ready thread.

Specifically, the device records specific parameters of each thread in the running process to generate a context, and queries the context of each thread in the local database, so that after the statistical thread acquires an identifier of a highest-priority ready thread of each statistical thread within a specified time range, the device queries the database according to the identifier to acquire the context of the highest-priority ready thread, where the context of the highest-priority ready thread includes a value of a Program Counter Register (PC), and the PC value is specifically used for indicating a code execution position.

Specifically, for each statistical time, the statistical thread obtains the start address text _ start of the code address space in the target program, and determines the code address space offset according to the difference between the obtained PC value and the start address of the code address space. Since the target program includes a plurality of code blocks, and each code block occupies a certain code space length, for example, the unit length of the code block may be 4096, which is, of course, only for example, and is not limited to the specific unit length of the code block, and in this embodiment, the usage frequency of each code block is mainly counted, so that after the code address space offset PC-text _ start is determined, the code address space offset is divided by the unit length (PC-text _ start)/4096 to obtain a quotient.

In this embodiment, a code array is created for the target program, and the code array includes a plurality of elements that match the code cross, such as { [ 2 ]] ₁ [] ₂ 。。。[] _N Where N denotes the total number of code blocks in the target program, [ 2 ]] ₁ Indicates the element corresponding to the code block with number 1, in each elementThe method is used for counting the use times of each code block in a specified time range, and the initial value of each element is 0. For example, when the specified time range is 1 hour, the primary statistical time is 1] ₂ Adding 1, and repeating the above steps, when the time 2] ₁ [6] ₂ 。。。[10] _N And acquiring a code thermodynamic diagram of the target program according to the updated use times of each code block in the code array, so that the code thermodynamic diagram comprises the use times of each code block.

It should be noted that, in this embodiment, the above operation is specifically implemented by executing a data migration thread, so that a timing wakeup cycle of the data migration thread is consistent with a timing cycle of the statistical thread, that is, after the statistical thread starts to acquire the updated code thermodynamic diagram, the data migration thread determines, according to the code thermodynamic diagram newly determined by the statistical thread, a target code block with the highest use number. For example, the target code block with the highest number of uses is determined to be code block 1 according to the currently acquired code thermodynamic diagram.

Step S103, migrating the target code block with the highest use number to the SRAM physical address for storage based on the address mapping result of the MMU.

Optionally, migrating the target code block with the highest use number to a physical address of an SRAM for storage based on an address mapping result of the MMU, including: migrating the target code block from the second virtual address to the first virtual address; determining an original DDR physical address mapped by the second virtual address and an SRAM physical address mapped by the first virtual address according to an address mapping result; and migrating the target code block from the original DDR physical address to the SRAM physical address for storage.

Specifically, when the processor determines that the target code block with the highest number of uses is the code block 1, the processor side can only implement migration of the virtual address of the data, but the code block is actually stored in the physical address, so that the data migration on the virtual address side can be translated to the actual data migration on the physical address side based on the address mapping result of the MMU. For example, when determining that the code block 1 with the highest number of uses currently corresponds to the second virtual address, i.e. the virtual address a, the code block 1 is migrated from the second virtual address to the newly added first virtual address, i.e. the virtual address C. Based on the address mapping result of the MMU according to the lookup table 2, it can be determined that the actual physical address space mapped by the virtual address a is the DDR physical address X, and the actual physical address space mapped by the virtual address C is the SRAM physical address Z, and at this time, the code block 1 stored in the DDR physical address X is migrated to the SRAM physical address Z.

Optionally, after migrating the target code block with the highest use number to the physical address of the SRAM for storage based on the address mapping result of the MMU, the method further includes: removing a first mapping relation between a second virtual address corresponding to a target code block in a first address mapping table and an original DDR physical address; and mapping the SRAM physical address to a second virtual address corresponding to the target code block so as to update the first address mapping table.

Specifically, in this embodiment, the code block with the largest number of times of use is migrated from the DDR with a lower read rate to the SRAM with a higher read rate, so as to significantly improve the access rate of the entire target program, but at this time, only the target code block is migrated under the sub-physical address, and in order to ensure that the processor can achieve effective reading of the target code block when accessing the original virtual address corresponding to the target code block, for table 2, the mapping relationship between the virtual address a and the DDR physical address X, which is the second virtual address corresponding to the code block 1, is released, and the SRAM physical address Z is mapped to the virtual address a corresponding to the code block 1, so as to achieve updating of the first mapping table, as shown in table 3 below, which is an example of an updated first mapping table:

TABLE 3

Code block numbering	Virtual address space	Physical address space
			1	Virtual address A	SRAM physical address Z
2	Virtual address B	DDR physical address Y
			....
n	Virtual address M	DDR physical address N
			1	Virtual address C	SRAM physical address Z

When the processor accesses the virtual address a again based on the updated first mapping table, since the target code block is migrated at the physical address side, the code block 1 with the highest number of use can be directly acquired from the SRAM address Z with a high access rate. The mapping relationship between the first virtual address, i.e., the virtual address C, and the SRAM physical address Z may be released or reserved, and this embodiment is not limited thereto. In the case of reservation, i.e. the handler can also effect the reading of the target code block by accessing the virtual address C.

Optionally, after mapping the physical address of the SRAM to the second virtual address corresponding to the target code block, the method further includes: sending a data reading instruction aiming at the target code block to the MMU through the instruction bus, wherein the data reading instruction comprises a second virtual address corresponding to the target code block; and the receiving MMU inquires the updated first address mapping table according to the data reading instruction, and executes a target code block fed back by reading the determined SRAM physical address.

Specifically, after the processor migrates a target code block with the highest number of times of use in a target program through the MMU, when the target code block is accessed again, a data read instruction for the target code block, for example, the code block 1, may be sent to the MMU through the instruction bus, where the data read instruction includes a virtual address a that is an original virtual address corresponding to the code block 1, and after the MMU acquires the data read instruction, the MMU acquires a physical address space that is an SRAM physical address Z that is a physical address space corresponding to the virtual address a according to the updated first mapping table, and after reading the code block 1 from the SRAM physical address Z, feeds back the code block to the processor for execution.

According to the code thermodynamic diagram of the obtained target program, the target code block with the highest use frequency is migrated from the DDR physical address to the SRAM physical address with the higher reading speed through the memory management unit MMU, and therefore the access speed and the running efficiency of the target program are remarkably improved.

Example two

Fig. 2 is a flowchart of a code program migration method according to a second embodiment of the present invention, where this embodiment is based on the foregoing embodiment, after sending a migration instruction for a target code block to an MMU, the method further includes detecting a migration result of the MMU, and performing an alarm prompt when it is determined that the migration fails. As shown in fig. 2, the method includes:

step S201, a first address mapping table is created, and the first address mapping table is applied to the MMU for address mapping.

Step S202, a code thermodynamic diagram for the target program is acquired regularly, and the target code block with the highest use frequency is determined according to the code thermodynamic diagram.

Optionally, the method for obtaining the code thermodynamic diagram of the target program at fixed time includes obtaining a context of a highest priority ready thread at each statistical moment in a specified time range, wherein the context of the highest priority ready thread includes a numerical value of a program counting register PC; determining the number of a code block used in a target program at each statistical moment according to the numerical value of the PC, wherein the target program comprises a highest priority ready thread; and updating the code array which stores the use times of each code block according to the number of the code block so as to acquire the code thermodynamic diagram in the target program.

In step S203, the target code block with the highest number of uses is migrated to the SRAM physical address for storage based on the address mapping result of the MMU.

Optionally, migrating the target code block with the highest use number to a physical address of an SRAM for storage based on an address mapping result of the MMU, including: migrating the target code block from the second virtual address to the first virtual address; determining an original DDR physical address mapped by the second virtual address and an SRAM physical address mapped by the first virtual address according to an address mapping result; and migrating the target code block from the original DDR physical address to an SRAM physical address for storage.

And step S204, detecting the migration result of the target program, and giving an alarm when the migration failure is determined.

Specifically, in this embodiment, after the migration of the target code block is completed, the migration result is also detected, specifically, the detection manner may be to send a detection instruction of the target program to the MMU, the MMU may invoke the target program after obtaining the detection instruction, and the processor calculates a time T1 when the MMU feeds back the entire target program, and also obtains a time T2 when the MMU feeds back the entire target program before the migration is completed, if the migration is successful, a difference between the two times should be very large, and if the time T2-T1 is less than a preset time length, it is determined that a difference between the times occupied by the two times is not large, which obviously does not meet an actual situation, so that it may be directly determined that the target program migration has failed.

It should be noted that, an alarm prompt may be sent when it is determined that the migration has failed, where the alarm prompt may be a voice or a picture, for example, a voice broadcast "target program migration has failed, please note", and the cause of the migration failure may be a communication failure or a hardware device failure of the processing machine or MMU, and at this time, by sending the alarm prompt, a maintenance worker may be timely reminded to timely repair a network or a device, so as to further improve the accuracy of code program migration and further improve the efficiency of code program migration.

According to the code thermodynamic diagram of the target program, the target code block with the highest use frequency is migrated from the DDR physical address to the SRAM physical address with the higher reading speed through the MMU, and therefore the access speed and the running efficiency of the target program are remarkably improved. By detecting the migration result of the target program and sending an alarm prompt when the migration failure is determined, maintenance personnel are reminded to overhaul the network or equipment in time, the accuracy of code program migration is further improved, and the efficiency of code program migration is further improved.

EXAMPLE III

Fig. is a schematic structural diagram of a code program migration apparatus according to a third embodiment of the present invention. As shown in fig. 3, the apparatus includes: a first address mapping table creation module 310, a target code block determination module 320, and a target code block migration module 330.

A first address mapping table creating module 310, configured to create a first address mapping table, and apply the first address mapping table to a memory management unit MMU for address mapping, where the first address mapping table includes a first mapping relationship between an original DDR physical address and an original virtual address of each code block of a target program, and a second mapping relationship between a reserved first virtual address and a reserved SRAM physical address of a static random access memory;

the target code block determining module 320 is configured to periodically obtain a code thermodynamic diagram for a target program, and determine a target code block with the highest number of usage times according to the code thermodynamic diagram, where the code thermodynamic diagram includes the number of usage times of each code block;

and the target code block migration module 330 is configured to migrate the target code block with the highest number of uses to the SRAM physical address for storage based on the address mapping result of the MMU.

Optionally, the apparatus further includes a first address mapping table updating module, configured to release a first mapping relationship between a second virtual address corresponding to the target code block in the first address mapping table and the original DDR physical address;

and mapping the SRAM physical address to a second virtual address corresponding to the target code block so as to update the first address mapping table.

Optionally, the first address mapping table creating module is configured to obtain a pre-created original address mapping table, where the original address mapping table includes a first mapping relationship between an original DDR physical address and an original virtual address of each code block of the storage target program;

determining an SRAM physical address from an SRAM, and acquiring a reserved first virtual address;

and establishing a second mapping relation between the SRAM physical address and the first virtual address, and updating the original address mapping table according to the second mapping relation to obtain the first address mapping table.

Optionally, the target code block determining module includes a code thermodynamic diagram obtaining sub-module, configured to obtain a context of a highest-priority ready thread at each statistical time within a specified time range, where the context of the highest-priority ready thread includes a value of a program count register PC;

determining the number of a code block used in a target program at each statistical moment according to the numerical value of the PC, wherein the target program comprises a highest priority ready thread;

and updating the code array in which the use times of each code block are stored according to the number of the code block so as to acquire the code thermodynamic diagram in the target program.

Optionally, the target code block migration module is configured to migrate the target code block from the second virtual address to the first virtual address;

determining an original DDR physical address mapped by the second virtual address and an SRAM physical address mapped by the first virtual address according to an address mapping result;

and migrating the target code block from the original DDR physical address to an SRAM physical address for storage.

Optionally, the apparatus further includes a target code block access module, configured to send a data read instruction for the target code block to the MMU through the instruction bus, where the data read instruction includes a second virtual address corresponding to the target code block;

and the receiving MMU inquires the updated first address mapping table according to the data reading instruction, and executes the target code block fed back by reading the determined SRAM physical address.

Optionally, the apparatus further includes a migration detection module, configured to detect a migration result of the target program;

and when the migration failure is determined, alarming and prompting are carried out.

The code program migration device provided by the embodiment of the invention can execute the code program migration method provided by any embodiment of the invention, and has corresponding functional modules and beneficial effects of the execution method.

Example four

FIG. 4 shows a schematic block diagram of an electronic device 10 that may be used to implement an embodiment of the invention. Electronic devices are intended to represent various forms of digital computers, such as laptops, desktops, workstations, personal digital assistants, servers, blade servers, mainframes, and other appropriate computers. The electronic device may also represent various forms of mobile devices, such as personal digital assistants, cellular phones, smart phones, wearable devices (e.g., helmets, glasses, watches, etc.), and other similar computing devices. The components shown herein, their connections and relationships, and their functions, are meant to be exemplary only, and are not meant to limit implementations of the inventions described and/or claimed herein.

As shown in fig. 4, the electronic device 10 includes at least one processor 11, and a memory communicatively connected to the at least one processor 11, such as a Read Only Memory (ROM) 12, a Random Access Memory (RAM) 13, and the like, wherein the memory stores a computer program executable by the at least one processor, and the processor 11 may perform various suitable actions and processes according to the computer program stored in the Read Only Memory (ROM) 12 or the computer program loaded from the storage unit 18 into the Random Access Memory (RAM) 13. In the RAM 13, various programs and data necessary for the operation of the electronic apparatus 10 may also be stored. The processor 11, the ROM 12, and the RAM 13 are connected to each other via a bus 14. An input/output (I/O) interface 15 is also connected to bus 14.

A number of components in the electronic device 10 are connected to the I/O interface 15, including: an input unit 16 such as a keyboard, a mouse, or the like; an output unit 17 such as various types of displays, speakers, and the like; a storage unit 18 such as a magnetic disk, an optical disk, or the like; and a communication unit 19 such as a network card, modem, wireless communication transceiver, etc. The communication unit 19 allows the electronic device 10 to exchange information/data with other devices via a computer network such as the internet and/or various telecommunication networks.

The processor 11 may be a variety of general and/or special purpose processing components having processing and computing capabilities. Some examples of processor 11 include, but are not limited to, a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), various specialized Artificial Intelligence (AI) computing chips, various processors running machine learning model algorithms, a Digital Signal Processor (DSP), and any suitable processor, controller, microcontroller, or the like. The processor 11 performs the various methods and processes described above, such as a code program migration method.

In some embodiments, the code program migration method may be implemented as a computer program tangibly embodied on a computer-readable storage medium, such as storage unit 18. In some embodiments, part or all of the computer program may be loaded and/or installed onto the electronic device 10 via the ROM 12 and/or the communication unit 19. When the computer program is loaded into RAM 13 and executed by processor 11, one or more steps of the code program migration method described above may be performed. Alternatively, in other embodiments, the processor 11 may be configured to perform the code program migration method by any other suitable means (e.g., by means of firmware).

Various implementations of the systems and techniques described here above may be implemented in digital electronic circuitry, integrated circuitry, field Programmable Gate Arrays (FPGAs), application Specific Integrated Circuits (ASICs), application Specific Standard Products (ASSPs), system on a chip (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and/or combinations thereof. These various embodiments may include: implemented in one or more computer programs that are executable and/or interpretable on a programmable system including at least one programmable processor, which may be special or general purpose, receiving data and instructions from, and transmitting data and instructions to, a storage system, at least one input device, and at least one output device.

A computer program for implementing the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus, such that the computer programs, when executed by the processor, cause the functions/acts specified in the flowchart and/or block diagram block or blocks to be performed. A computer program can execute entirely on a machine, partly on a machine, as a stand-alone software package partly on a machine and partly on a remote machine or entirely on a remote machine or server.

In the context of the present invention, a computer-readable storage medium may be a tangible medium that can contain, or store a computer program for use by or in connection with an instruction execution system, apparatus, or device. A computer readable storage medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. Alternatively, the computer readable storage medium may be a machine readable signal medium. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

To provide for interaction with a user, the systems and techniques described here can be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to a user; and a keyboard and a pointing device (e.g., a mouse or a trackball) by which a user can provide input to the electronic device. Other kinds of devices may also be used to provide for interaction with a user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form, including acoustic, speech, or tactile input.

The systems and techniques described here can be implemented in a computing system that includes a back-end component (e.g., as a data server), or that includes a middleware component (e.g., an application server), or that includes a front-end component (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with an implementation of the systems and techniques described here), or any combination of such back-end, middleware, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: local Area Networks (LANs), wide Area Networks (WANs), blockchain networks, and the internet.

The computing system may include clients and servers. A client and server are generally remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other. The server can be a cloud server, also called a cloud computing server or a cloud host, and is a host product in a cloud computing service system, so that the defects of high management difficulty and weak service expansibility in the traditional physical host and VPS service are overcome.

It should be understood that various forms of the flows shown above may be used, with steps reordered, added, or deleted. For example, the steps described in the present invention may be executed in parallel, sequentially, or in different orders, and are not limited herein as long as the desired result of the technical solution of the present invention can be achieved.

The above-described embodiments should not be construed as limiting the scope of the invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions may be made in accordance with design requirements and other factors. Any modification, equivalent replacement, and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for code program migration, comprising:

creating a first address mapping table, and applying the first address mapping table to a Memory Management Unit (MMU) for address mapping, wherein the first address mapping table comprises a first mapping relation between an original double-rate synchronous dynamic random access memory (DDR) physical address and an original virtual address for storing each code block of a target program, and a second mapping relation between a reserved first virtual address and a Static Random Access Memory (SRAM) physical address;

2. The method of claim 1, wherein after migrating the target code block with the highest number of uses to the SRAM physical address for storage based on the address mapping result of the MMU, further comprising:

removing the first mapping relation between the second virtual address corresponding to the target code block in the first address mapping table and the original DDR physical address;

3. The method of claim 1, wherein creating the first address mapping table comprises:

acquiring a pre-created original address mapping table, wherein the original address mapping table comprises a first mapping relation between an original DDR physical address and an original virtual address of each code block of a storage target program;

determining the SRAM physical address from an SRAM, and acquiring the reserved first virtual address;

4. The method of claim 1, wherein the timing obtaining a code thermodynamic diagram for the target program comprises:

acquiring the context of the highest priority ready thread at each statistical moment in a specified time range, wherein the context of the highest priority ready thread comprises the numerical value of a program counting register (PC);

determining the number of the code block used in the target program at each statistical moment according to the value of the PC, wherein the target program comprises the highest priority ready thread;

5. The method of claim 1, wherein migrating the target code block with the highest number of uses to the SRAM physical address for storage based on the address mapping result of the MMU comprises:

migrating the target code block from the second virtual address to the first virtual address;

determining an original DDR physical address mapped by the second virtual address and an SRAM physical address mapped by the first virtual address according to the address mapping result;

migrating the target code block from the original DDR physical address to the SRAM physical address for storage.

6. The method of claim 2, wherein after mapping the SRAM physical address to the second virtual address corresponding to the target code block, further comprising:

sending a data reading instruction aiming at the target code block to the MMU through an instruction bus, wherein the data reading instruction comprises the second virtual address corresponding to the target code block;

and receiving the first address mapping table which is updated by the MMU according to the data reading instruction, and executing the target code block fed back by reading the determined SRAM physical address.

7. The method of any of claims 1 to 6, wherein after sending the migration instruction for the target code block to the MMU, the method further comprises:

detecting the migration result of the target program;

8. A code program migration apparatus, comprising:

the memory management unit MMU comprises a first address mapping table creating module, a first address mapping table creating module and a second address mapping table creating module, wherein the first address mapping table creating module is used for creating a first address mapping table and applying the first address mapping table to the memory management unit MMU for address mapping, and the first address mapping table comprises a first mapping relation between an original double-rate synchronous dynamic random access memory DDR physical address and an original virtual address of each code block of a stored target program and a second mapping relation between a reserved first virtual address and a static random access memory SRAM physical address;

9. A computer device, characterized in that the computer device comprises:

one or more processors;

a storage device for storing one or more programs,

when executed by the one or more processors, cause the one or more processors to implement the method of any one of claims 1-7.

10. A computer-readable storage medium, on which a computer program is stored which, when being executed by a processor, carries out the method according to any one of claims 1-7.