CN115716370A

CN115716370A - Integrated circuit for driving thermal head and semiconductor device

Info

Publication number: CN115716370A
Application number: CN202210953962.3A
Authority: CN
Inventors: 橘田达也
Original assignee: Ablic Inc
Current assignee: Ablic Inc
Priority date: 2021-08-24
Filing date: 2022-08-10
Publication date: 2023-02-28

Abstract

The invention provides an integrated circuit for driving a thermal head, which can be input from either the left side or the right side of a chip without fixing the input direction of a signal for operating the integrated circuit for driving the thermal head, and can suppress the attenuation of the signal. An integrated circuit (1) for driving a thermal head, comprising: an input/output circuit (30) for cascade connection; and input/output switching signal input terminals (22, 24) for switching between using the input/output circuit (30) as an input circuit and using the input/output circuit as an output circuit.

Description

Integrated circuit for driving thermal head and semiconductor device

Technical Field

The present invention relates to an integrated circuit for driving a thermal head (thermal head) and a semiconductor device.

Background

In many cases, a plurality of thermal head driving ICs are connected in cascade to each other and used as an integrated circuit for thermal head driving (hereinafter, the integrated circuit may be simply referred to as an IC). In order to increase the area of a substrate on which a thermal head driving IC is mounted, the thermal head driving IC includes an IC internal wiring that traverses the inside of the IC (see, for example, patent document 1).

Patent document 1: japanese patent laid-open publication No. Sho 63-56466

In many cases, the thermal head driving IC is functionally rectangular with a large vertical and horizontal ratio of the IC chip. The signal for operating the thermal head driving IC is, for example, unidirectional such that the signal is input from the right side of the IC chip and output from the left side. Further, if only the same signal PAD at both ends of the IC chip is wired inside the IC chip, the signal attenuation is large, and the convenience of use is poor. Therefore, there are limitations that the degree of freedom in designing a rigid substrate or a flexible substrate on which the thermal head driving IC is mounted is low, or a plurality of IC chips cannot be arranged.

Disclosure of Invention

An object of the present invention is to provide a thermal head driving IC capable of inputting and outputting a signal from either the left side of an IC chip or the right side of the IC chip without fixing the input/output direction of the signal for operating the thermal head driving IC, and capable of suppressing attenuation of the signal.

The integrated circuit for driving a thermal head of the present invention includes: a signal input/output circuit for operating the thermal head driving IC; and an input/output switching signal input terminal for switching between the signal input/output circuit and an input circuit and an output circuit.

According to the thermal head driving IC of the present invention, a signal for operating the thermal head driving IC can be input from the left side of the IC chip or from the right side of the IC chip, and the degree of freedom in designing the rigid substrate or the flexible substrate on which the thermal head driving IC is mounted is increased, thereby suppressing signal attenuation.

Drawings

Fig. 1 is a block diagram showing an example of an IC for driving a thermal head according to embodiment 1 of the present invention.

Fig. 2 is a circuit diagram showing an example of an input/output circuit according to embodiment 1 of the present invention.

Fig. 3 shows an example of cascade connection of a semiconductor device using the thermal head driving IC of the present invention.

Fig. 4 shows another example of cascade connection of a semiconductor device using the thermal head driving IC of the present invention.

Fig. 5 is a circuit diagram showing an example of an input/output circuit according to embodiment 2 of the present invention.

Fig. 6 is a block diagram showing an example of the thermal head driving IC according to embodiment 2 of the present invention.

Fig. 7 is a circuit diagram showing an example of a PMOS transistor according to embodiment 3 of the present invention.

Fig. 8 is a diagram showing an example of the structure of the MOS transistor according to embodiment 4 of the present invention.

Fig. 9 shows another example of the structure of the MOS transistor according to embodiment 4 of the present invention.

Fig. 10 is a diagram showing an example of the structure of the MOS transistor.

Description of the reference symbols

1. 100, and (2) a step of: an Integrated Circuit (IC) for driving a thermal head;

2: an output circuit;

3. 3a: an AND circuit;

4. 4a: a latch circuit;

5: a shift register;

6. 7, 10: a buffer circuit;

8: an input terminal of a data signal line;

9: an output terminal of the data signal line;

11: a data transmission clock signal input terminal;

12: a data transmission clock signal output terminal;

15. 16: a strobe signal input/output terminal;

19. 20: a latch signal input/output terminal;

21. 23: an inverter;

22. 24: an input/output switching signal input terminal;

30. 30a, 30b, 30c, 30d: an input-output circuit;

34b1, 34b2, 34b3, 34b4: a fuse;

57: the gate length.

Detailed Description

[ embodiment 1 ]

Hereinafter, embodiment 1 of the present invention will be described with reference to the drawings. Fig. 1 is a circuit diagram showing an example of the thermal head driving IC 1 according to the present embodiment.

The thermal head driving IC 1 shown in fig. 1 includes: a shift register 5 having a plurality of D-type flip-flops (hereinafter referred to as D-FF), a serial data input terminal 8, a serial data output terminal 9, a serial data transfer clock input terminal 11, a serial data transfer clock output terminal 12,

buffer circuits

6, 7, 10, a latch circuit 4, latch signal input/

output terminals

19, 20, an AND circuit (AND circuit) 3, strobe signal input/

output terminals

15, 16, input/

output circuits

30a, 30b, 30c, 30D, an output circuit 2, input/output switching

signal input terminals

22, 24, AND

inverters

21, 23.

The connection inside the thermal head driving IC 1 will be described. The serial data input terminal 8 is connected to the shift register 5 via the buffer circuit 6. The input terminals and the output terminals of the plurality of D-FFs of the shift register 5 are connected in series. The output terminal of the D-FF in the shift register 5 is connected to the input terminal of the next D-FF and the input terminal of the latch circuit 4 corresponding to each D-FF. The output terminal of the D-FF of the final stage is connected to the input terminal of the corresponding latch circuit 4, and is connected to the serial data output terminal 9 via the buffer circuit 7. The serial data transfer clock input terminal 11 is connected to the serial data transfer clock output terminal 12, and is connected to the clock input terminal of each D-FF inside the shift register 5 via the buffer circuit 10.

The latch signal input/output terminal 19 is connected to the latch signal input terminal of each latch circuit 4 via an input/output circuit 30a, and further connected to the latch signal input/output terminal 20 via an input/output circuit 30 b. Each output of each latch circuit 4 is connected to the 1 st input terminal of the corresponding AND circuit 3. The input/output switching signal input terminal 22 is connected to the input/output switching terminal DIRb of the input/output circuit 30b, and is connected to the input/output switching terminal DIRa of the input/output circuit 30a via the inverter 21.

The gate signal input/output terminal 15 is connected to the 2 nd input terminal of each AND circuit 3 via an input/output circuit 30c, AND further connected to the gate signal input/output terminal 16 via an input/output circuit 30 d. The respective outputs of the AND circuits 3 are connected to the input terminals of the output circuit 2. The input/output switching signal input terminal 24 is connected to the input/output switching terminal DIRd of the input/output circuit 30d, and is connected to the input/output switching terminal DIRc of the input/output circuit 30c via the inverter 23. The output circuit 2 outputs a signal for driving the thermal head.

Fig. 2 is a circuit diagram showing an example of the input/output circuit 30 according to the present embodiment. The input/output circuit 30 of the present embodiment includes a1 st input/output terminal TA31, a2 nd input/output terminal TB32, an input/output switching terminal DIR33, a1 st P channel MOS transistor (hereinafter referred to as a PMOS transistor) 34, a2 nd PMOS transistor 35, a3 rd PMOS transistor 37, a1 st N channel MOS transistor (hereinafter referred to as an NMOS transistor) 38, a2 nd NMOS transistor 39, a3 rd NMOS transistor 40, a 4 th NMOS transistor 41, a NAND circuit (NAND circuit) 42, a NOR circuit (NOR circuit) 43, a1 st inverter 44, a2 nd inverter 45, a1 st resistor 46, and a2 nd resistor 47.

The connection of the input-output circuit 30 will be described. The 1 st input/output terminal TA31 is connected to the drain terminal of the 2 nd PMOS transistor 35, the drain terminal of the 1 st NMOS transistor 38, the 1 st input terminal of the NAND circuit 42, and the 1 st input terminal of the NOR circuit 43. The 2 nd input/output terminal TB32 is connected to the drain terminal of the 3 rd PMOS transistor 37, the drain terminal of the 4 th NMOS transistor 41, the 1 st terminal of the 1 st resistor 46, and the 1 st terminal of the 2 nd resistor 47. The input/output switching terminal DIR33 is connected to the 2 nd input terminal of the NAND circuit 42, the input terminal of the 1 st inverter 44, and the gate terminal of the 1 st PMOS transistor 34. The output of the 1 st inverter 44 is connected to the 2 nd input terminal of the NOR circuit 43 and the gate terminal of the 2 nd NMOS transistor 39.

The source terminal of the 1 st PMOS transistor 34 is connected to the VDD terminal. The drain terminal of the 1 st PMOS transistor 34 is connected to the source terminal of the 2 nd PMOS transistor 35. The gate terminal of the 2 nd PMOS transistor 35 and the gate terminal of the 1 st NMOS transistor 38 are connected to the output terminal of the 2 nd inverter 45. The source terminal of the 1 st NMOS transistor is connected to the drain terminal of the 2 nd NMOS transistor 39. The source terminal of the 2 nd NMOS transistor 39 is connected to the GND terminal.

The output of the NAND circuit 42 is connected to the gate terminal of the 3 rd PMOS transistor 37. The source terminal of the 3 rd PMOS transistor 37 is connected to the VDD terminal. The output of the NOR circuit 43 is connected to the gate terminal of the 3 rd NMOS transistor 40. The drain terminal of the 3 rd NMOS transistor 40 is connected to the 2 nd terminal of the 1 st resistor 46. The source terminal of the 3 rd NMOS transistor 40 is connected to the GND terminal.

The gate terminal and the source terminal of the 4 th NMOS transistor 41 are connected to the GND terminal. The 2 nd terminal of the 2 nd resistor 47 is connected to the input terminal of the 2 nd inverter 45.

The operation of the input/output circuit 30 will be described. When a high-level signal is input to the input/output switching terminal DIR33, the 1 st PMOS transistor 34 and the 2 nd NMOS transistor 39 are turned off. The inverter including the 2 nd PMOS transistor 35 and the 1 st NMOS transistor 38 is not supplied with power and does not operate. When a high-level signal is input to the 1 st input/output terminal TA31, the 3 rd PMOS transistor 37 is turned on via the NAND circuit 42, and the 3 rd NMOS transistor 40 is turned off via the NOR circuit 43. The 2 nd input/output terminal TB32 outputs a high-level signal. When a low-level signal is input to the 1 st input/output terminal TA31, the 3 rd PMOS transistor 37 is turned off via the NAND circuit 42, and the 3 rd NMOS transistor 40 is turned on via the NOR circuit 43. The 2 nd input/output terminal TB32 outputs a low-level signal. The input/output circuit 30 operates as a buffer circuit that outputs a signal of the 1 st input/output terminal TA31 to the 2 nd input/output terminal TB 32.

When a low-level signal is input to the input/output switching terminal DIR33, the 3 rd PMOS transistor 37 is turned off via the NAND circuit 42, and the 3 rd NMOS transistor 40 is turned off via the NOR circuit 43. The 1 st PMOS transistor 34 and the 2 nd NMOS transistor 39 are turned on. The inverter including the 2 nd PMOS transistor 35 and the 1 st NMOS transistor 38 is supplied with power and operates as an inverter. The signal input to the 2 nd input/output terminal TB32 is output from the 1 st input/output terminal TA31 via the 2 nd inverter 45 and the inverter including the 2 nd PMOS transistor 35 and the 1 st NMOS transistor 38. The input/output circuit 30 operates as a buffer circuit that outputs a signal of the 2 nd input/output terminal TB32 to the 1 st input/output terminal TA 31.

The 4 th NMOS transistor 41, the 1 st resistor 46, and the 2 nd resistor 47 are inserted as measures against static Electricity (ESD) of the 2 nd input/output terminal TB 32.

In the input/output circuit 30, the

MOS transistors

34, 35, and 37 are PMOS transistors, and the

MOS transistors

38, 39, and 41 are NMOS transistors, but the polarities of the VDD terminal and the VSS terminal may be reversed, and the

MOS transistors

34, 35, and 37 may be NMOS transistors, and the

MOS transistors

38, 39, and 41 may be PMOS transistors. In this case, the PMOS transistor and the NMOS transistor can be distinguished from each other by describing one as a1 st conductivity type MOS transistor and the other as a2 nd conductivity type MOS transistor. The VDD terminal and the VSS terminal can be distinguished from each other by describing one as a1 st power supply terminal and the other as a2 nd power supply terminal.

Fig. 3 shows an example of a semiconductor device in which 4 thermal head driving ICs from the thermal head driving IC 1a to the thermal head driving IC 1d of the present invention are built in cascade connection. In fig. 3 (a), a high-level signal is input to the input/output switching signal input terminals 22a to 22d and 24a to 24d of each IC. The gate signal is input to the gate signal input/output terminal 15a of the thermal head driving IC 1a, output from the gate signal input/output terminal 16a, and further input to the gate signal input/output terminal 15b of the thermal head driving IC 1b connected in cascade. Similarly, the gate signal is sequentially transmitted from the thermal head driving IC 1b to the thermal head driving IC 1d via the thermal head driving IC 1 c. Similarly to the strobe signal, the latch signal is sequentially transmitted from the thermal head driving IC 1a to the thermal head driving IC 1 d.

In fig. 3 (b), a high-level signal is input to the input/output switching signal input terminals 22a to 22d of the ICs. A low-level signal is input to the input/output switching signal input terminals 24a to 24d of the ICs. Similarly to fig. 3 (a), the strobe signals are sequentially transmitted from the thermal head driving IC 1a to the thermal head driving IC 1 d. The latch signals are sequentially transmitted from the thermal head driving IC 1d to the thermal head driving IC 1a in the reverse order of the gate signals.

In fig. 3 (c), a low-level signal is input to the input/output switching signal input terminals 22a to 22d of the ICs. High-level signals are input to the input/output switching signal input terminals 24a to 24d of the ICs. The gate signal is sequentially transmitted from the thermal head driving IC 1d to the thermal head driving IC 1 a. The latch signal is sequentially transmitted from the thermal head driving IC 1a to the thermal head driving IC 1d in reverse order to the strobe signal.

In fig. 3 (d), a low-level signal is input to the input/output switching signal input terminals 22a to 22d and 24a to 24d of each IC. The gate signal is sequentially transmitted from the thermal head driving IC 1d to the thermal head driving IC 1 a. Similarly to the strobe signal, the latch signal is sequentially transmitted from the thermal head driving IC 1d to the thermal head driving IC 1 a.

As described above, according to the thermal head driving IC 1 of the present invention, the semiconductor device incorporating the thermal head driving IC 1 can be flexibly designed with respect to whether the terminals for inputting the strobe signal and the latch signal to the thermal head driving IC 1 are on the left side of the IC chip or on the right side of the IC chip. The degree of freedom in designing a rigid substrate or a flexible substrate on which the thermal head driving IC 1 is mounted can be increased. Here, although the example of the gate signal and the latch signal is described, the data transfer clock signal input terminal 11 and the data transfer clock signal output terminal 12 can be applied as the input/output terminals.

Fig. 4 shows another embodiment of a semiconductor device in which thermal head driving ICs 1 according to the present invention are cascade-connected. In fig. 4 (a), a low-level signal is input to the input/output switching

signal input terminals

22a, 22b, 24a, and 24b of the thermal

head driving ICs

1a and 1b, and a high-level signal is input to the input/output switching

signal input terminals

22c, 22d, 24c, and 24d of the thermal head driving ICs 1c and 1 d. The gate signal is input to the gate signal input/output terminal 16b of the thermal head driving IC 1b, output from the gate signal input/output terminal 15b, and further input to the gate signal input/output terminal 16a of the thermal head driving IC 1a connected in cascade. At the same time, the gate signal is input to the gate signal input/output terminal 15c of the thermal head driving IC 1c, output from the gate signal input/output terminal 16c, and further input to the gate signal input/output terminal 15d of the thermal head driving IC 1d connected in cascade.

The latch signal is input to the latch signal input/output terminal 20b of the thermal head driving IC 1b, is output from the latch signal input/output terminal 19b, and is further input to the latch signal input/output terminal 20a of the thermal head driving IC 1a connected in cascade. At the same time, the latch signal is input to the latch signal input/output terminal 19c of the thermal head driving IC 1c, is output from the latch signal input/output terminal 20c, and is further input to the latch signal input/output terminal 19d of the thermal head driving IC 1d connected in cascade.

The semiconductor device incorporating the thermal head driving IC 1 of the present invention shown in fig. 4 (a) can input a strobe signal and a latch signal from the center portion of the cascade connection. The degree of freedom in designing the signal wiring is improved. Further, since the number of thermal head driving ICs 1 through which the strobe signal and the latch signal pass becomes half, the delay of the strobe signal and the latch signal due to the thermal head driving ICs 1 is reduced. The thermal head driving IC 1 can operate at a higher speed.

In fig. 4 (b), a high-level signal is input to the input/output switching

signal input terminals

22a, 22b, 24a, and 24b of the thermal

head driving ICs

1a and 1b, and a low-level signal is input to the input/output switching

signal input terminals

22c, 22d, 24c, and 24d of the thermal head driving ICs 1c and 1 d. The gate signal is input to the gate signal input/output terminal 15a of the thermal head driving IC 1a, output from the gate signal input/output terminal 16a, and further input to the gate signal input/output terminal 15b of the thermal head driving IC 1b connected in cascade. At the same time, the gate signal is input to the gate signal input/output terminal 16d of the thermal head driving IC 1d, output from the gate signal input/output terminal 15d, and further input to the gate signal input/output terminal 16c of the thermal head driving IC 1c connected in cascade.

The latch signal is input to the latch signal input/output terminal 19a of the thermal head driving IC 1a, is output from the latch signal input/output terminal 20a, and is further input to the latch signal input/output terminal 19b of the thermal head driving IC 1b connected in cascade. At the same time, the latch signal is input to the latch signal input/output terminal 20d of the thermal head driving IC 1d, is output from the latch signal input/output terminal 19d, and is further input to the latch signal input/output terminal 20c of the thermal head driving IC 1c connected in cascade.

The semiconductor device incorporating the thermal head driving IC 1 of the present invention shown in fig. 4 (b) can input a strobe signal and a latch signal from both ends of the two-divided cascade connection. The degree of freedom in designing signal wiring is improved. In addition, as in the example of fig. 4 (a), since the number of thermal head driving ICs 1 through which the strobe signal and the latch signal pass is half, the delay of the strobe signal and the latch signal due to the thermal head driving ICs 1 is reduced. The thermal head driving IC 1 can operate at a higher speed.

As described above, according to the thermal head driving IC of the present embodiment, the degree of freedom in designing the signal wiring of the semiconductor device incorporating the thermal head driving IC is improved. Further, by inserting the input/output circuit, attenuation of the signal can be suppressed. By dividing the cascade connection of the thermal head driving ICs, the number of thermal head driving ICs through which a driving signal such as a gate signal passes (the number of cascade connection stages) can be reduced, and a signal delay can be reduced, whereby a higher-speed signal can be input and operated. In the present embodiment, an example in which the cascade connection is divided into two is described in fig. 4 (b), but the cascade connection may be divided into three or more parts. By dividing the cascade connection into a plurality of parts, the semiconductor device can input a higher-speed signal and operate the semiconductor device. In the examples shown in fig. 3 and 4 of the present embodiment, an example in which the thermal head driving IC is arranged with 4 IC chips is shown, but even when a plurality of IC chips, for example, thermal head driving ICs of 10 or more IC chips are cascade-connected, a good operation can be obtained without signal attenuation.

[ 2 nd embodiment ]

Hereinafter, embodiment 2 of the present invention will be described with reference to the drawings. Fig. 5 is a circuit diagram showing an example of the input/output circuit 30a according to the present embodiment. The same components as those in embodiment 1 are denoted by the same reference numerals, and description thereof is omitted.

The input/output circuit 30a according to embodiment 2 is a circuit obtained by changing the insertion position of the 2 nd inverter 45 of the input/output circuit 30 according to embodiment 1. The input terminal of the 2 nd inverter 45 is connected to the 1 st input/output terminal TA 31. An output terminal of the 2 nd inverter 45 is connected to a1 st input terminal of the NAND circuit 42 and a1 st input terminal of the NOR circuit 43. The gate terminal of the 2 nd PMOS transistor 35a and the gate terminal of the 1 st NMOS transistor 38a are connected to the 2 nd terminal of the 2 nd resistor 47.

Fig. 6 is a circuit diagram showing an example of the thermal head driving IC 100 according to the present embodiment. The input signal of the input/output circuit 30a of the present embodiment is opposite in logic to the output signal, and operates as an inverter. The terminal of the latch circuit 4a to which the latch signal is input is an input terminal of negative logic. Similarly, the terminal of the AND circuit 3a to which the strobe signal is input is an input terminal of negative logic.

In the present embodiment, the transistor size of the 2 nd PMOS transistor 35a and the 1 st NMOS transistor 38a having their gate terminals connected to the 2 nd input/output terminal TB32, and the 1 st PMOS transistor 34a and the 2 nd NMOS transistor 39a that supply current to the 2 nd PMOS transistor 35a and the 1 st NMOS transistor 38a is larger than the transistor size of the 1 st inverter 44 or the 2 nd inverter 45 (not shown) that constitutes the signal input into the thermal head driving IC 100.

The 2 nd input/output terminal TB32 is led out to the outside of the thermal head driving IC 100. By increasing the size of the 2 nd PMOS transistor 35a and the 1 st NMOS transistor 38a whose gate terminals are connected to the 2 nd input/output terminal TB, the gate terminal withstand voltages of both transistors are increased, and the 2 nd input/output terminal TB is less susceptible to static electricity or the like from the outside. The thermal head driving IC 100 has improved ESD (Electro Static Discharge) resistance. The 1 st input/output terminal TA31 is connected to an internal wiring along the long side of the IC chip inside the thermal head driving IC 100. By increasing the sizes of the 1 st PMOS transistor 34a, the 2 nd PMOS transistor 35a, the 1 st NMOS transistor 38a, and the 2 nd NMOS transistor 39a, the current supply capability of the 1 st input/output terminal TA31 to the internal wiring of the thermal head driving IC 100 increases, and distortion of the signal waveform via the internal wiring can be suppressed.

As described above, according to the thermal head driving IC of the present embodiment, the ESD resistance of the input terminal of the thermal head driving IC is improved, and distortion of the signal waveform via the internal wiring of the IC can be suppressed.

[ embodiment 3 ]

Embodiment 3 of the present invention will be explained. In this embodiment, at least one of the 1 st PMOS transistor 34a, the 2 nd PMOS transistor 35a, the 1 st NMOS transistor 38a, and the 2 nd NMOS transistor 39a of embodiment 2 is formed by connecting a plurality of MOS transistors connected in series in parallel with a fuse element. The 1 st PMOS transistor 34a and the 2 nd NMOS transistor 39a operate as current supply to the inverter formed by the 2 nd PMOS transistor 35a and the 1 st NMOS transistor 38 a.

An example of the MOS transistor of the present embodiment is described with reference to fig. 7. In fig. 7, a1 st PMOS transistor 34a is configured by connecting in parallel a plurality of PMOS transistors 34an (n =1, 2, 3, … …) such as a PMOS transistor 34a1 and a PMOS transistor 34a2, and a group of a plurality of fuse elements 34bn (n =1, 2, 3, … …) such as a fuse element 34b1 and a fuse element 34b2 connected in series to the PMOS transistor 34 an.

The internal wiring connected to the 1 st input/output terminal TA31 has a wiring resistance and a wiring capacitance. When the current supply capability of the input-output circuit 30a is excessively large with respect to the internal wiring, an overshoot is generated in the output signal. When the current supply capability of the input-output circuit 30a is too small with respect to the internal wiring, the output signal is waveform-blunted. By cutting off the plurality of fuse elements 34bn, the number of MOS transistors forming the 1 st PMOS transistor 34a can be adjusted, and the current supply capability of the input-output circuit 30a in which the distortion of the output signal of the internal wiring is minimized can be set. The cutting of the fuse element 34bn produces the same effect as changing the gate width of the 1 st PMOS transistor 34a. The fuse element 34bn can be configured by a fuse element that is cut by a large current flowing therethrough, a fuse element that is cut by a laser, a MOS transistor that has a floating gate and can electrically rewrite an on-off state, and the like.

Here, although the example in which the 1 st PMOS transistor 34a is configured by the plurality of PMOS transistors 34an has been described, the 2 nd PMOS transistor 35a, the 1 st NMOS transistor 38a, and the 2 nd NMOS transistor 39a may have the same configuration.

As described above, according to the thermal head driving IC of the present embodiment, distortion of a signal waveform passing through the internal wiring of the thermal head driving IC can be minimized.

[ 4 th embodiment ]

Embodiment 4 of the present invention will be explained. In this embodiment, the size (length) in the direction connecting the source electrode and the drain electrode of at least one of the 1 st PMOS transistor 34a, the 2 nd PMOS transistor 35a, the 1 st NMOS transistor 38a, and the 2 nd NMOS transistor 39a of embodiment 2 is formed larger than the size (length) of a transistor (not shown) constituting the 1 st inverter 44 or the 2 nd inverter 45 to which a signal inside the thermal head driving IC 100 is input. In such a MOS transistor, the current supply capability of the MOS transistor can be changed by changing the gate length.

The MOS transistor of this embodiment will be described with reference to fig. 8 and 9. Fig. 8 (a) is a view of the MOS transistor 34b1 as viewed from above. Fig. 8 (b) is an AB cross-sectional view of the PMOS transistor 34b 1. Fig. 9 (a) is a view of the PMOS transistor 34b2 as viewed from above. Fig. 9 (b) is a cross-sectional CD view of the PMOS transistor 34b2. The PMOS transistor 34b1 shown in fig. 8 is formed by the source electrode 51, the drain electrode 52, the gate electrode 53, the oxide insulating film 54, the source electrode contact hole 55, and the drain electrode contact hole 56. The gate length 57 is the spacing between the source electrode 51 and the drain electrode 52. The PMOS transistor 34b2 shown in fig. 9 is formed by the source electrode 51, the drain electrode 52a, the gate electrode 53a, the oxide insulating film 54a, the source electrode contact hole 55, and the drain electrode contact hole 56 a. The gate length 57a is the interval between the source electrode 51 and the drain electrode 52 a. The gate length 57 of the PMOS transistor 34b1 is smaller than the gate length 57a of the PMOS transistor 34b2. The size 58 in the direction in which the source electrode and the drain electrode are connected to each other of the PMOS transistor 34b1 is the same as the size 58 in the direction in which the source electrode and the drain electrode are connected to each other of the PMOS transistor 34b2.

A comparative example of the MOS transistor is explained with reference to fig. 10. Fig. 10 (a) is a view of the PMOS transistor 34b as viewed from above. Fig. 10 (b) is an EF cross-sectional view of the PMOS transistor 34 b. The PMOS transistor 34b shown in fig. 10 is formed by the source electrode 51, the drain electrode 52b, the gate electrode 53, the oxide insulating film 54b, the source electrode contact hole 55, and the drain electrode contact hole 56 b. The gate length 57 is the interval between the source electrode 51 and the drain electrode 52 b. The gate length 57 of MOS transistor 50b is equal to the gate length 57 of PMOS transistor 34b 1. The PMOS transistor 34b has a smaller size 58b in the direction connecting the source electrode and the drain electrode than the PMOS transistors 34b1 and 34b2.

The PMOS transistor 34b1 shown in fig. 8 and the PMOS transistor 34b shown in fig. 10 have the same gate length. The PMOS transistor 34b1 and the PMOS transistor 34b have substantially the same on-resistance. Here, the transistor size 58 in the direction connecting the source electrode and the drain electrode of the PMOS transistor 34b1 is larger than the transistor size 58b of the PMOS transistor 34 b. The PMOS transistor 34b1 can be replaced with a PMOS transistor 34b2 in which the gate length 57 is increased as much as the gate length 57a without changing the transistor size 58.

Generally, the MOS transistor can adjust the on-resistance of the MOS transistor by adjusting the gate length. By adjusting the on-resistance of the MOS transistor, the current supply capability of the MOS transistor can be changed. In this way, the PMOS transistor 34b1 and the PMOS transistor 34b2 having larger transistor sizes than the PMOS transistor 34b can change the current supply capability by changing the gate lengths. The source electrode 51 and the drain electrode 52 of the PMOS transistor 34b1 may be formed by ion implantation from the upper side using the gate electrode 53 as a part of a mask. According to such a manufacturing method, the width 57 and the gate length 57 of the gate electrode can be formed to the same size. The gate length 57 can be changed by changing the mask of the gate electrode 53.

Here, although the example in which the 1 st PMOS transistor 34a is configured by the PMOS transistor 34b1 has been described, the 2 nd PMOS transistor 35a, the 1 st NMOS transistor 38a, and the 2 nd NMOS transistor 39a may have the same configuration.

The internal wiring connected to the 1 st input/output terminal TA31 has a wiring resistance and a wiring capacitance. When the current supply capability of the input-output circuit 30a is excessively large with respect to the internal wiring, an overshoot is generated in the output signal. When the current supply capability of the input-output circuit 30a is too small with respect to the internal wiring, the output signal is waveform-blunted. By making the size in the direction connecting the source electrode and the drain electrode of at least one of the 1 st PMOS transistor 34, the 2 nd PMOS transistor 35, the 1 st NMOS transistor 38, and the 2 nd NMOS transistor 39 larger than the 3 rd PMOS transistor 37 or the like, the input-output circuit of the present embodiment can be provided with a current supply capability that minimizes waveform distortion of an output signal to internal wiring.

Claims

1. An integrated circuit for driving a thermal head, comprising:

an input/output circuit for cascade connection of signals; and

and an input/output switching signal input terminal for switching between an input circuit and an output circuit of the cascade connection signal.

2. The integrated circuit for driving a thermal head according to claim 1,

the input/output circuit for cascade connection signal has a first MOS transistor of 1 st conductivity type to a third MOS transistor of 1 st conductivity type, a first MOS transistor of 2 nd conductivity type to a third MOS transistor of 2 nd conductivity type, a NAND circuit, a NOR circuit, a1 st inverter, and 1 st to 3 rd terminals,

the 1 st terminal is connected to a drain terminal of the second MOS transistor of the 1 st conductivity type, a drain terminal of the first MOS transistor of the 2 nd conductivity type, a1 st input terminal of the NAND circuit, and a1 st input terminal of the NOR circuit,

the 2 nd terminal is connected to the drain terminal of the third MOS transistor of the 1 st conductivity type, the drain terminal of the third MOS transistor of the 2 nd conductivity type, the gate terminal of the second MOS transistor of the 1 st conductivity type, and the gate terminal of the first MOS transistor of the 2 nd conductivity type,

the 3 rd terminal is connected to the 2 nd input terminal of the NAND circuit, the input terminal of the 1 st inverter, and the gate terminal of the first MOS transistor of the 1 st conductivity type,

an output terminal of the 1 st inverter is connected to a2 nd input terminal of the NOR circuit and a gate terminal of the second MOS transistor of the 2 nd conductivity type,

an output terminal of the NAND circuit is connected to a gate terminal of the third MOS transistor of the 1 st conductivity type,

an output terminal of the NOR circuit is connected to a gate terminal of the third MOS transistor of the 2 nd conductivity type,

a source terminal of the first MOS transistor of the first conductivity type 1 is connected to a power supply terminal of the 1 st transistor, a drain terminal of the first MOS transistor of the first conductivity type 1 is connected to a source terminal of the second MOS transistor of the first conductivity type 1,

the drain terminal of the second MOS transistor of the 2 nd conductivity type is connected to the source terminal of the first MOS transistor of the 2 nd conductivity type,

a source terminal of the second MOS transistor of the second conductivity type 2 is connected to a2 nd power supply terminal, a source terminal of the third MOS transistor of the 1 st conductivity type is connected to a1 st power supply terminal,

the source terminal of the third MOS transistor of the 2 nd conductivity type is connected to the 2 nd power supply terminal.

3. The integrated circuit for driving a thermal head according to claim 2,

the input/output circuit for the cascade connection signal further has a2 nd inverter,

the 2 nd inverter is inserted between the 2 nd terminal, the gate terminal of the second 1 st conductivity type MOS transistor and the gate terminal of the first 2 nd conductivity type MOS transistor,

an input terminal of the 2 nd inverter is connected to the 2 nd terminal,

an output terminal of the 2 nd inverter is connected to a gate terminal of the second MOS transistor of the 1 st conductivity type and a gate terminal of the first MOS transistor of the 2 nd conductivity type.

4. The integrated circuit for driving a thermal head according to claim 2,

the 2 nd inverter is inserted between the 1 st terminal, the 1 st input terminal of the NAND circuit and the 1 st input terminal of the NOR circuit,

an input terminal of the 2 nd inverter is connected to the 1 st terminal,

an output terminal of the 2 nd inverter is connected to a1 st input terminal of the NAND circuit and a1 st input terminal of the NOR circuit.

5. The integrated circuit for driving a thermal head according to claim 4,

the input/output circuit for cascade connection signals further includes a fourth MOS transistor of the 2 nd conductivity type,

the fourth MOS transistor of the 2 nd conductivity type has a drain terminal connected to the 2 nd terminal, and a gate terminal and a source terminal connected to the 2 nd power supply terminal.

6. The integrated circuit for driving a thermal head according to claim 4,

at least one of the first 1 st conductivity type MOS transistor, the second 1 st conductivity type MOS transistor, the first 2 nd conductivity type MOS transistor, and the second 2 nd conductivity type MOS transistor is formed of a transistor having a size larger than a size of a transistor forming one of the 1 st inverter and the 2 nd inverter.

7. The integrated circuit for driving a thermal head according to claim 4,

at least one of the first MOS transistor of the first conductivity type 1, the second MOS transistor of the first conductivity type 1, the first MOS transistor of the second conductivity type 2, and the second MOS transistor of the second conductivity type 2 is formed by connecting a plurality of MOS transistors in parallel.

8. The integrated circuit for driving a thermal head according to claim 4,

at least one of the first 1 st conductivity type MOS transistor, the second 1 st conductivity type MOS transistor, the first 2 nd conductivity type MOS transistor, and the second 2 nd conductivity type MOS transistor is formed of a transistor having a larger distance between a source electrode and a drain electrode than a distance between a source electrode and a drain electrode of a transistor forming one of the 1 st inverter and the 2 nd inverter.

9. A semiconductor device having the integrated circuit for driving a thermal head according to any one of claims 1 to 8.

10. The semiconductor device according to claim 9,

the integrated circuit for driving the thermal head is composed of a group of 2 or more in cascade connection.