CN115713955A - 2D1R array structure and preparation method thereof - Google Patents

Abstract

The invention provides a 2D1R array structure and a preparation method thereof, wherein the 2D1R array structure comprises m word lines and m reset lines which are transversely arranged and in one-to-one correspondence, and n bit lines which are longitudinally arranged; wherein m and n are integers, and m is not less than 2,n not less than 2; memory cells are arranged at the intersection of each word line and each bit line; the memory unit comprises a first diode, a second diode and a resistor, wherein one end of the resistor is connected with a corresponding bit line, the other end of the resistor is respectively connected with the anode of the first diode and the cathode of the second diode, the cathode of the first diode is connected with a corresponding word line, and the anode of the second diode is connected with a corresponding reset line. The 2D1R array structure provided by the invention can solve the problems that the isolation performance between wells is poor and large IR drop is easy to generate in the existing 2D1R array structure.

Description

2D1R array structure and preparation method thereof

Technical Field

The invention relates to the technical field of arithmetic circuit design, in particular to a 2D1R array structure and a preparation method thereof.

Background

The array structure of the 2D1R (2-diode-1-Resistance) can realize SET (write operation), RESET (RESET operation) and READ (READ operation) on the bipolar Resistance random access memory device.

For the 2D1R array structure, the conventional 2D1R array structure is a control unit formed by connecting two diodes back to back and then connecting them in series with a resistor, and the conventional implementation methods in the industry include the following methods, for example, the patent scheme of patent publication No. CN110047867, in which, because a driving current needs to flow through a well resistor with a relatively high resistance value, a large IR drop (voltage drop) is generated, so that when reaching a selected resistor far from a well leading-out terminal, the voltage drop is large, which is not favorable for SET operation or RESET operation. As another example, patent publication No. CN109427839 discloses a method for manufacturing a diode, in which all diodes are used with the same type of well (both n-type well or p-type well), so that it is difficult to achieve complete isolation between wells through deep isolation trenches.

In view of the above, there is a need for a 2D1R array of IR drop that has a good isolation effect between wells and can effectively reduce well resistance.

Disclosure of Invention

In view of the foregoing problems, an object of the present invention is to provide a 2D1R array structure and a method for fabricating the same, so as to solve the problems of poor isolation performance between wells and easy generation of large IR drop in the conventional 2D1R array structure.

The 2D1R array structure provided by the invention comprises m word lines and m reset lines which are transversely arranged and in one-to-one correspondence, and n bit lines which are longitudinally arranged; wherein m and n are integers, and m is not less than 2,n not less than 2; and the number of the first and second electrodes,

memory cells are arranged at the intersection of each word line and each bit line; the memory unit comprises a first diode, a second diode and a resistor, wherein one end of the resistor is connected with a corresponding bit line, the other end of the resistor is respectively connected with the anode of the first diode and the cathode of the second diode, the cathode of the first diode is connected with a corresponding word line, and the anode of the second diode is connected with a corresponding reset line.

It is furthermore preferred that, during reading,

for the selected memory cell in the 2D1R array structure, setting Vrd voltage on a bit line, setting 0V voltage on a word line and setting 0V voltage on a reset line; for unselected memory cells in the 2D1R array structure, setting a bit line to be 0V voltage, setting a word line to be Vrd voltage and setting a reset line to be 0V voltage;

wherein Vrd is more than or equal to 0.3V and less than or equal to 1V.

It is furthermore preferred that, during writing,

for the selected memory cell in the 2D1R array structure, the bit line is set with Vset voltage, the word line is set with 0V voltage, and the reset line is set with 0V voltage; for the unselected memory cells in the 2D1R array structure, setting the bit line to be 0V voltage, setting the word line to be Vset voltage, and setting the reset line to be 0V voltage;

wherein Vset is more than or equal to 2.0V and less than or equal to 3.5V.

It is furthermore preferred that, during the resetting process,

for the selected memory cell in the 2D1R array structure, setting a bit line to be 0V voltage, setting a word line to be Vreset voltage, and setting a reset line to be the Vreset voltage; for unselected memory cells in the 2D1R array structure, setting a Vreset voltage on a bit line, setting a Vreset voltage on a word line and setting a 0V voltage on a reset line;

wherein, vreset is more than or equal to 1.5V and less than or equal to 3.5V.

In another aspect, the present invention further provides a method for preparing the 2D1R array, the method comprising:

forming an n-well region and a p-well region which are alternately arranged in an ion implantation mode;

forming deep groove regions at the junctions of the n well regions and the p well regions through an etching process, and arranging shallow groove regions in each n well region and each p well region through the etching process;

processing the deep trench region and the shallow trench region through a filling and grinding process so as to separate adjacent n-well regions from p-well regions through the deep trench region, and simultaneously forming separated active regions in each n-well region and each p-well region through the shallow trench region;

processing each active region in an ion implantation mode to form an n-type active region and a p-type active region in each n-well region and each p-well region;

intercepting corresponding n-type active regions, p-type active regions, deep groove regions and shallow groove regions, and connecting the n-type active regions, the p-type active regions, the deep groove regions and the shallow groove regions with resistors in a preset resistor matrix to form a 2D1R unit;

all the 2D1R cells are connected to preset word lines, bit lines and reset lines to form a 2D1R array.

In addition, the size of the 2D1R unit is preferably 12F ^2.

In addition, preferably, for each n-well region, one n-type active region is arranged every two p-type active regions, and the n-type active region is used as an n + leading-out terminal;

for each p-well region, one p-type active region is arranged every two n-type active regions, and the p-type active region is used as a p + leading-out terminal.

In addition, preferably, the step of intercepting the corresponding n-type active region, p-type active region, deep trench region and shallow trench region and connecting them with the resistors in the preset resistor matrix to form a 2D1R cell comprises:

selecting a group of n-well regions and p-well regions which are adjacent;

and connecting a p-type active region in the n-well region and an n-type active region in the p-well region in parallel and then connecting the p-type active region and the n-type active region with the bottom of a resistor in a preset resistor matrix.

In addition, it is preferable that the process of connecting all the 2D1R cells to the preset word lines, bit lines, and reset lines to form the 2D1R array includes:

for each of the 2D1R units,

connecting the top of the resistor with the corresponding bit line; and connecting the selected n well region with the corresponding word line through an n + leading-out terminal, and connecting the selected p well region with the corresponding reset line through a p + leading-out terminal.

In addition, preferably, for each n well region, all the n + leading-out terminals are led out and then connected in parallel to form a corresponding word line;

for each p-well region, all the p + leading-out terminals are led out and then connected in parallel to form a corresponding reset wire.

Compared with the prior art, the 2D1R array structure and the preparation method thereof have the following beneficial effects:

the 2D1R array structure and the preparation method thereof provided by the invention have the advantages that an n well region and a p well region are isolated through a deep isolation groove (namely a deep groove region DTI), a pn junction is formed in each n well region by arranging a p-type active region, and a pn junction is formed in each p well region by arranging an n-type active region; an n-type n-well leading-out end (essentially an n-type active area) is adjacently arranged for each p-type active area in the n-well area, similarly, a p-type p-well leading-out end (essentially a p-type active area) is adjacently arranged for each n-type active area in the p-well area, and all active areas (comprising the n-type active area and the p-type active area) are isolated through shallow isolation grooves (namely Shallow Trench Isolation (STI)); by the method, the well resistance in the pn junction array can be effectively reduced on the premise of ensuring stronger isolation performance between wells, the driving current can be effectively improved, and the compact resistance random access memory array with the size of 12F ^2 can be realized.

To the accomplishment of the foregoing and related ends, one or more aspects of the invention comprise the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative aspects of the invention. These aspects are indicative, however, of but a few of the various ways in which the principles of the invention may be employed. Further, the present invention is intended to include all such aspects and their equivalents.

Drawings

Other objects and results of the present invention will become more apparent and more readily appreciated as the same becomes better understood by reference to the following description and appended claims, taken in conjunction with the accompanying drawings. In the drawings:

FIG. 1 is a schematic circuit diagram of a 2D1R array structure according to the present invention;

FIG. 2 is a top view of an alternating arrangement of n-well and p-well regions formed by means of ion implantation;

FIG. 3 is a top view of an alternating arrangement of n-well regions and p-well regions forming deep trench regions, shallow trench regions, n-type active regions, and p-type active regions;

FIG. 4 is a cross-sectional view taken along the direction X1 in FIG. 3;

FIG. 5 is a cross-sectional view taken along the direction X2 in FIG. 3;

FIG. 6 is a cross-sectional view taken along the direction Y1 in FIG. 3;

FIG. 7 is a cross-sectional view taken along the direction Y2 in FIG. 3;

the same reference numbers in all figures indicate similar or corresponding features or functions.

Detailed Description

In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of one or more embodiments. It may be evident, however, that such embodiment(s) may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form in order to facilitate describing one or more embodiments.

In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, but do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present invention; the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance; furthermore, unless expressly stated or limited otherwise, the terms "mounted," "connected," and "coupled" are to be construed broadly and encompass, for example, both fixed and removable coupling as well as integral coupling; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.

Fig. 1 shows the circuit principle of the 2D1R array structure provided by the present invention.

As can be seen from fig. 1, the 2D1R array structure provided by the present invention includes m word lines WL and m reset lines R/L arranged in a transverse (or longitudinal) manner in a one-to-one correspondence manner, and n bit lines BL arranged in a longitudinal (or transverse) manner; the number of the word lines is equal to that of the reset lines, and the word lines and the reset lines are in one-to-one correspondence, the corresponding word lines and the reset lines are parallel to each other (e.g., WLn-1 and R/Ln-1 in FIG. 1 correspond to each other, WLn and R/Ln correspond to each other, WLn +1 and R/Ln +1 correspond to each other), m and n are integers, m is greater than or equal to 2, and is greater than or equal to 2; a plurality of word lines WL and reset lines R/L are arranged, and bit lines BL are vertical to the word lines WL (or the reset lines R/L); a storage unit is arranged at the intersection of each word line and each bit line; the memory unit comprises a first diode, a second diode and a resistor, wherein one end of the resistor is connected with a corresponding bit line BL, the other end of the resistor is respectively connected with the anode of the first diode and the cathode of the second diode, the cathode of the first diode is connected with a corresponding word line, and the anode of the second diode is connected with a corresponding reset line.

It should be noted that the transverse arrangement, the longitudinal arrangement, the vertical arrangement and the parallel arrangement are only for the purpose of describing the staggered distribution relationship between the word lines WL and the reset lines R/L and the bit lines BL, so as to represent the whole 2D1R array structure, and the arrangement is not necessarily arranged in the actual circuit design process and the actual matrix preparation process.

Specifically, for the 2D1R array with the above structure, during reading, for the selected memory cell in the 2D1R array structure, the following are set: bit line Vrd voltage, word line 0V voltage, and reset line 0V voltage; for unselected memory cells in the 2D1R array structure, the bit line is set to be 0V voltage, the word line is set to be Vrd voltage, and the reset line is set to be 0V voltage; wherein Vrd is more than or equal to 0.3V and less than or equal to 1V.

In the writing process, for the selected memory cell in the 2D1R array structure, the Vset voltage is set on the bit line, the 0V voltage is set on the word line, and the 0V voltage is set on the reset line; for unselected memory cells in the 2D1R array structure, the bit line is set to be 0V voltage, the word line is set to be Vset voltage, and the reset line is set to be 0V voltage; wherein Vset is more than or equal to 2.0V and less than or equal to 3.5V.

In the resetting process, for the selected memory cell in the 2D1R array structure, the bit line is set to be 0V voltage, the word line is set to be Vreset voltage, and the reset line is set to be Vreset voltage; for unselected memory cells in the 2D1R array structure, setting a Vreset voltage on a bit line, setting a Vreset voltage on a word line and setting a 0V voltage on a reset line; wherein, vreset is more than or equal to 1.5V and less than or equal to 3.5V.

To further illustrate the detailed setting process of the 2D1R array structure implementing READ (READ), write (SET), erase (RESET) operations provided by the present invention, the following table shows the specific setting mode of the 2D1R array structure:

in the above-described reading and writing processes, the RESET lines (RESET lines, R/L) need to suppress leakage, and are set to 0V. During the RESET process, the RESET line of the selected memory cell needs to be added with a RESET voltage (Vreset), BL is added with 0V, the unselected BL is added with the RESET voltage to inhibit the leakage, so that the memory cells of the selected RESET line but the unselected BL are inhibited from being RESET, and at the moment, the RESET voltage is added to all WL to inhibit the leakage path.

In addition, during the read operation, the current direction flows from BL to WL, and since the diode is reverse biased on the RESET line and the diode can realize the leakage current of <1e-12A, it can be seen from Table 1 that Vwl voltage is greater than or equal to Vrl in any case, therefore, the good process window can be maintained by utilizing the reverse bias effect of n-well and p-well under the condition of realizing the isolation.

In another aspect, the present invention further provides a method for preparing the 2D1R array, as can be seen from fig. 2 to 7, the method includes:

forming n well regions (NW) and p well regions (PW) which are alternately arranged by means of ion implantation; the opening size of the n-well region and the p-well region is 2F, and the space size is 4F;

forming deep trench regions (DTI) at the junctions of the n-well regions and the p-well regions by an etching process, and arranging shallow trench regions (STI) in each n-well region and each p-well region by the etching process;

processing the deep trench region and the shallow trench region by filling and grinding processes to separate adjacent n-well regions from p-well regions through the deep trench region, and simultaneously forming separated active regions in each n-well region and each p-well region through the shallow trench region;

processing each active region in an ion implantation mode to form n-type active regions n + and p-type active regions p + in each n-well region and each p-well region; a PN junction (corresponding to the PN junction of the first diode) is formed between the n-well region and the p-type active region in the n-well region, and a PN junction (corresponding to the PN junction of the second diode) is formed between the p-well region and the n-type active region in the p-well region; the DTI can better isolate the n-well region and the p-well region, and the STI can better isolate a PN junction in the secondary tube;

intercepting corresponding n-type active area, p-type active area, deep trench area and shallow trench area, and connecting with resistors in a preset resistor matrix through CT and Metal lines to form a 2D1R unit (such as the area outlined in figure 3); the size of the 2D1R unit is 12F ^2;

all the 2D1R cells are connected to the preset word lines, bit lines and reset lines to form a 2D1R array.

Specifically, for each n-well region, one n-type active region is provided every two p-type active regions, and the n-type active region is used as an n + leading-out terminal; for each p-well region, one p-type active region is provided every two n-type active regions, and the p-type active region is used as a p + lead-out terminal.

More specifically, the process of intercepting the corresponding n-type active region, p-type active region, deep trench region and shallow trench region and connecting the n-type active region, p-type active region, deep trench region and shallow trench region with the resistors in the preset resistor matrix to form a 2D1R unit includes:

selecting a group of n-well regions and p-well regions which are adjacent;

and connecting a p-type active region in the n-well region and an n-type active region in the p-well region in parallel and then connecting the p-type active region and the n-type active region with the bottom of a resistor in a preset resistor matrix.

In addition, the process of connecting all the 2D1R cells to the preset word lines, bit lines, and reset lines to form the 2D1R array includes:

for each of the 2D1R units,

connecting the top of the resistor with the corresponding bit line; and the selected n well region is connected with the corresponding word line through an n + leading-out terminal, and the selected p well region is connected with the corresponding reset line through a p + leading-out terminal.

In addition, for each n well region, all n + leading-out terminals are led out and then connected in parallel to form a corresponding word line; for each p-well region, all the p + leading-out terminals are led out and then connected in parallel to form a corresponding reset wire.

In addition, for the preparation method of the 2D1R array, the order of forming the DTI, the STI, and the n-well and p-well regions is not limited to the order in the above embodiment, for example, a process flow of first providing the STI, then providing the n-well and p-well regions, and finally providing the DTI may also be used.

It should be noted that the 2D1R array structure and the preparation method thereof provided by the present invention are not limited to the application of RRAM, but can also be applied to all new memories, such as MRAM, PCRAM, FERAM, etc.

The 2D1R array structure and the method of manufacturing the same according to the present invention are described above by way of example with reference to fig. 1 to 7. However, it will be understood by those skilled in the art that various modifications may be made to the 2D1R array structure and the method for fabricating the same proposed by the present invention without departing from the scope of the present invention. Therefore, the scope of the present invention should be determined by the contents of the appended claims.

Claims (10)

1. A2D 1R array structure is characterized by comprising m word lines, m reset lines and n bit lines, wherein the m word lines and the m reset lines are arranged transversely and correspond to one another one by one; wherein m and n are integers, and m is not less than 2,n is not less than 2; and the number of the first and second electrodes,

memory cells are arranged at the intersections of the word lines and the bit lines; the memory unit comprises a first diode, a second diode and a resistor, wherein one end of the resistor is connected with a corresponding bit line, the other end of the resistor is respectively connected with the anode of the first diode and the cathode of the second diode, the cathode of the first diode is connected with a corresponding word line, and the anode of the second diode is connected with a corresponding reset line.

2. The 2D1R array structure of claim 1,

in the course of the reading process,

for a selected memory cell in the 2D1R array structure, setting Vrd voltage on a bit line, setting 0V voltage on a word line and setting 0V voltage on a reset line; for unselected memory cells in the 2D1R array structure, setting a bit line to be 0V voltage, setting a word line to be Vrd voltage and setting a reset line to be 0V voltage;

wherein Vrd is more than or equal to 0.3V and less than or equal to 1V.

3. The 2D1R array structure of claim 1,

in the course of the writing process,

for the selected memory cell in the 2D1R array structure, the bit line is set with Vset voltage, the word line is set with 0V voltage, and the reset line is set with 0V voltage; for the unselected memory cells in the 2D1R array structure, setting the bit line to be 0V voltage, setting the word line to be Vset voltage, and setting the reset line to be 0V voltage;

wherein Vset is more than or equal to 2.0V and less than or equal to 3.5V.

4. The 2D1R array structure of claim 1,

in the process of the reset, the reset circuit is started,

for the selected memory cell in the 2D1R array structure, setting a bit line to be 0V voltage, setting a word line to be Vreset voltage, and setting a reset line to be the Vreset voltage; for unselected memory cells in the 2D1R array structure, setting a Vreset voltage on a bit line, setting a Vreset voltage on a word line and setting a 0V voltage on a reset line;

wherein, vreset is more than or equal to 1.5V and less than or equal to 3.5V.

5. A method of making a 2D1R array according to any of claims 1 to 4, comprising:

forming an n-well region and a p-well region which are alternately arranged in an ion implantation mode;

forming deep groove regions at the junctions of the n-well regions and the p-well regions through an etching process, and arranging shallow groove regions in each n-well region and each p-well region through the etching process;

processing the deep trench region and the shallow trench region through a filling and grinding process so as to separate adjacent n-well regions from p-well regions through the deep trench region, and simultaneously forming separated active regions in each n-well region and each p-well region through the shallow trench region;

processing each active region in an ion implantation mode to form an n-type active region and a p-type active region in each n-well region and each p-well region;

intercepting corresponding n-type active area, p-type active area, deep groove area and shallow groove area and connecting with the resistors in the preset resistor matrix to form a 2D1R unit;

all the 2D1R cells are connected to preset word lines, bit lines and reset lines to form a 2D1R array.

6. The method of claim 5, wherein the step of preparing the 2D1R,

the size of the 2D1R unit is 12F ^2.

7. The method of claim 5, wherein the step of preparing the 2D1R array comprises,

for each n-well region, arranging an n-type active region at every two p-type active regions, and taking the n-type active region as an n + leading-out terminal;

for each p-well region, one p-type active region is arranged every two n-type active regions, and the p-type active region is used as a p + leading-out terminal.

8. The method of claim 7, wherein the step of preparing the 2D1R array comprises,

the process of intercepting corresponding n-type active area, p-type active area, deep groove area and shallow groove area and connecting with the resistors in the preset resistor matrix to form a 2D1R unit comprises the following steps:

selecting a group of n-well regions and p-well regions which are adjacent;

and connecting a p-type active region in the n-well region and an n-type active region in the p-well region in parallel and then connecting the p-type active region and the n-type active region with the bottom of a resistor in a preset resistor matrix.

9. The method of claim 8, wherein the step of preparing a 2D1R array,

the process of connecting all the 2D1R cells to the preset word lines, bit lines and reset lines to form the 2D1R array includes:

for each of the 2D1R units,

connecting the top of the resistor with the corresponding bit line; and connecting the selected n well region with the corresponding word line through an n + leading-out terminal, and connecting the selected p well region with the corresponding reset line through a p + leading-out terminal.

10. The method of claim 9, wherein the step of preparing the 2D1R,

for each n well region, all n + leading-out terminals are led out and then connected in parallel to form corresponding word lines;

for each p-well region, all the p + leading-out terminals are led out and then connected in parallel to form a corresponding reset wire.

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