CN115712337A - Scheduling method and device of processor, electronic equipment and storage medium - Google Patents

Abstract

The present application discloses a processor scheduling method, device, electronic equipment, and storage medium. The processor scheduling method is applied to electronic equipment. The processor of the electronic equipment includes a first processor core and a second processor core. A processor core and the second processor core share one power domain, the processing capability of the first processor core is higher than that of the second processor core, and the scheduling method of the processor includes: if the first processor core The condition corresponding to the idle state is satisfied, and the second processor core is in the working state, and the current operating frequency of the first processor core is obtained as the first frequency; the operating frequency of the second processor core is obtained as the second frequency; if the first frequency The corresponding voltage is greater than the voltage corresponding to the second frequency, and the operating frequency of the first processor core is adjusted to a third frequency, wherein the voltage corresponding to the third frequency is smaller than the voltage corresponding to the second frequency. The method can reduce the power consumption of the electronic equipment.

Description

Processor scheduling method, device, electronic device and storage medium

technical field

The present application relates to the technical field of electronic equipment, and more specifically, to a processor scheduling method, device, electronic equipment, and storage medium.

Background technique

With the rapid advancement of technology and living standards, the use of electronic equipment is becoming more and more extensive. Moreover, people have higher and higher performance requirements for electronic devices, and electronic devices equipped with multi-core processors appear. However, while increasing the configuration level of the electronic equipment, it also brings relatively large power consumption to the electronic equipment.

Contents of the invention

In view of the above problems, the present application proposes a processor scheduling method, device, electronic equipment, and storage medium.

In the first aspect, an embodiment of the present application provides a method for scheduling a processor, which is applied to an electronic device. The processor of the electronic device includes a first processor core and a second processor core. The first processor core And the second processor core shares one power domain, the processing capability of the first processor core is higher than the processing capability of the second processor core, and the method includes: if the first processor core satisfies The condition corresponding to the idle state, and the second processor core is in the working state, obtaining the current operating frequency of the first processor core as the first frequency; obtaining the operating frequency of the second processor core as the second frequency ; If the voltage corresponding to the first frequency is greater than the voltage corresponding to the second frequency, adjusting the operating frequency of the first processor core to a third frequency, wherein the voltage corresponding to the third frequency is less than the voltage corresponding to the second frequency The voltage corresponding to the second frequency.

In a second aspect, an embodiment of the present application provides a processor scheduling device, which is applied to an electronic device. The processor of the electronic device includes a first processor core and a second processor core. The first processor core And the second processor core shares one power domain, the processing capability of the first processor core is higher than the processing capability of the second processor core, and the device includes: a first frequency acquisition module, a second frequency The acquisition module and the frequency adjustment module, wherein the first frequency acquisition module is configured to acquire the current first frequency if the first processor core satisfies the condition corresponding to the idle state and the second processor core is in the working state. The working frequency of a processor core is used as the first frequency; the second frequency obtaining module is used to obtain the working frequency of the second processor core as the second frequency; the frequency adjustment module is used to if the first frequency The corresponding voltage is greater than the voltage corresponding to the second frequency, and the operating frequency of the first processor core is adjusted to a third frequency, wherein the voltage corresponding to the third frequency is smaller than the voltage corresponding to the second frequency.

In a third aspect, the embodiment of the present application provides an electronic device, including: one or more processors, the processors include a first processor core and a second processor core; memory; one or more application programs, Wherein the one or more application programs are stored in the memory and configured to be executed by the one or more processors, the one or more programs are configured to execute the processor provided in the first aspect above scheduling method.

In the fourth aspect, the embodiment of the present application provides a computer-readable storage medium, the computer-readable storage medium stores program codes, and the program codes can be invoked by a processor to perform the processing provided in the above-mentioned first aspect The scheduler method.

In the solution provided by this application, the processor of the electronic device includes a first processor core and a second processor core sharing one power supply domain, and the processing capability of the first processor core is higher than that of the second processor core. When the first processor core satisfies the condition corresponding to the idle state and the second processor core is in the working state, the current operating frequency of the first processor core is obtained as the first frequency, and the operating frequency of the second processor core is obtained as the first frequency. For the second frequency, if the voltage corresponding to the first frequency is greater than the voltage corresponding to the second frequency, adjust the operating frequency of the first processor core to a third frequency, wherein the voltage corresponding to the third frequency is lower than the voltage corresponding to the second frequency. Thus, when the first processor core and the second processor core share one power supply domain, when the first processor core enters the idle state, the operating frequency of the second processor core in the working state can correspond to and the voltage corresponding to the working frequency of the second processor core is relatively small, so the power consumption of the electronic device can be reduced.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings that need to be used in the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application. For those skilled in the art, other drawings can also be obtained based on these drawings without any creative effort.

FIG. 1 shows a schematic diagram of a system architecture provided by an embodiment of the present application.

Fig. 2 shows a flowchart of a processor scheduling method according to an embodiment of the present application.

Fig. 3 shows a flowchart of a processor scheduling method according to another embodiment of the present application.

Fig. 4 shows a flowchart of a processor scheduling method according to another embodiment of the present application.

Fig. 5 shows a flowchart of a processor scheduling method according to another embodiment of the present application.

Fig. 6 shows a flowchart of a processor scheduling method according to yet another embodiment of the present application.

Fig. 7 shows a block diagram of an apparatus for scheduling a processor according to an embodiment of the present application.

Fig. 8 is a block diagram of an electronic device for executing the processor scheduling method according to the embodiment of the present application according to the embodiment of the present application.

FIG. 9 is a storage unit for storing or carrying program codes for implementing the processor scheduling method according to the embodiment of the present application according to the embodiment of the present application.

Detailed ways

In order to enable those skilled in the art to better understand the solutions of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application.

With the rapid development of mobile Internet technology, electronic devices (such as smart phones, tablet computers, etc.) cover all aspects of life. Moreover, users have higher and higher demands on the performance of electronic devices, so electronic devices with multi-core processors appear. A multi-core processor refers to a processor including multiple processor cores. However, when the processor adopts a multi-core architecture, it also brings about an increase in power consumption of electronic devices, so a BIG-LITTLE processor architecture appears. Among them, BIG-LITTLE's processor architecture is used to allocate appropriate processor cores for appropriate tasks, thereby reducing the power consumption of electronic devices.

Furthermore, because different processor cores need to use a separate power supply module for power supply and voltage control, some manufacturers divide different processor cores into the same power domain (power domain) based on cost considerations. For the processor cores in the same power domain, the same independent voltage power supply and module can be used to provide unified power supply and unified voltage control for the processor cores, thereby saving the number of power modules and thus saving costs. In particular, for a processor architecture using a super-core, a big-core and a small-core, the super-core and the big-core will share one power domain.

In the related art, processor cores with different processing capabilities are allocated to the same power domain. In particular, for a processor architecture using a super-core, a big-core and a small-core, the super-core and the big-core will share one power domain.

After a long period of research, the inventor found that in some scenarios, the processor core with relatively strong processing capability will enter the idle state (idle state) at a high frequency. Share one power supply domain with the processor core with weaker processing capability. If the processor core with weaker processing capability is in working state and the processor core with weaker processing capability is at a low The voltage corresponding to the selected low frequency point is lower than the voltage corresponding to the high frequency selected by a processor core with a stronger processor capability. At this time, a relatively high voltage is used for power supply, but the processor core with a strong processing capability is in an idle state and does not need to process tasks, thus increasing power consumption. For example, in the scenario where the super-core and the big-core share one power domain, when the web page loads the scene, the super-core will be enabled due to the heavy load of the processor, and the operating frequency of the super-core will be higher; When it is not too large, the super-large core will enter the idle state (the frequency of the super-large core is still high frequency at this time), and the rest of the tasks will be performed by the small core or large core; after the super-large core enters the idle state at a high frequency, due to the current load is not Large, large cores also trigger frequency modulation due to the scheduler and try to enter a low frequency point. If the voltage corresponding to the low frequency point selected by the large core is lower than the voltage corresponding to the high frequency of the super large core, the high frequency corresponding to the super large core will be maintained during hardware voting. The high voltage will increase the power consumption.

In view of the above problems, the inventor proposes a processor scheduling method, device, electronic device, and storage medium provided by the embodiments of the present application, which can realize that when the first processor core and the second processor core share one power supply domain, in the When the first processor core enters the idle state, it can supply power with the voltage corresponding to the operating frequency of the second processor core in the working state, and since the voltage corresponding to the operating frequency of the second processor core is relatively small, it can be reduced Power consumption of electronic equipment. Wherein, the specific processor scheduling method will be described in detail in the subsequent embodiments.

The system architecture of the electronic device to which the processor scheduling method provided in the embodiment of the present application is applied is firstly introduced below.

Please refer to FIG. 1 , the electronic device may include the system architecture 10 shown in FIG. 1 . Wherein, the system architecture 10 may include an operating system 20 , a processor 110 and multiple power domains (such as the first power domain 141 and the second power domain 142 shown in FIG. 1 ). The processor 110 may include multiple processor cores, for example, the first processor core 111 , the second processor core 112 , the third processor core 113 and the fourth processor core 114 shown in FIG. 1 .

In some manners, the multiple processor cores of the processor 110 can be divided into multiple power domains according to the physical hardware structure, and each power domain includes at least two processor cores, thereby reducing the number of power modules and reducing the cost. For example, in the system architecture shown in FIG. 1, the first processor core 111 and the second processor core 112 can be divided into the first power domain 141, and the third processor core 113 and the fourth processor core 114 can be divided into the second power domain 141. Two power domains 142 .

Wherein, the power domain refers to an area that allows uniform power supply and uniform voltage control, and the same power domain can use an independent power module to power and control the voltage of the processor core. One or more power domains (only two are shown in FIG. 1 ) may be included in the system architecture 10 . Of course, for the processor cores in the same power domain, the devices associated with the processor cores can also be powered and controlled by the power domain. Wherein, the device associated with the processor core may be a cache, a storage controller, etc., which is not limited here.

The scheduler 11 may be a computer program running in the operating system 200 for task scheduling. Wherein, the operating system 20 can interact with the front-end application 12, and the front-end application 12 can generate one or more processing tasks (processing task 1 to processing task n shown in FIG. 1, where n is a positive integer). The scheduler 11 may schedule the processing tasks generated by the front-end application 12 to one or more processor cores in the processor 110 so that the processor cores execute the tasks. The scheduler 11 can allocate the processing tasks according to the processing tasks generated by the front-end application 12 and the actual load of each processor core, thereby reducing the power consumption of the electronic device.

Optionally, the scheduler 11 may run on any working processor core. Of course, the scheduler 11 can also determine the processor core to run itself based on the load of the processor cores in the working state, and then migrate to the processor core to run, thereby ensuring load balancing among the processor cores; A processor core or other hardware (for example, an application specific integrated circuit, a programmable logic device, etc.) dedicated to running the scheduler 11 may be set to increase the running speed of the scheduler 11 .

In the embodiment of the present application, processor cores located in the same power domain may include processor cores with different processing capabilities. In subsequent embodiments, the first processor core 111 and the second processor core 112 share one power domain, and the first processor core 111 and the second processor core 112 have different processing capabilities. Exemplarily, the processor 110 may include four 2.04GHz AMD A55 processor cores, three 2.54GHz AMD A77 processor cores and one 3.13GHz AMD A77 processor core, wherein the 3.13GHz AMD A77 processor The core can be used as a super core, the 2.54GHz AMD A77 processor core can be used as a large core, and the 2.04GHz AMD A55 processor core can be used as a small core. Share one power domain with all large cores.

It should be noted that the system architecture 10 shown in FIG. 1 is illustrated by including one processor 300 as an example, and may include multiple processors in practical applications. It should be understood that the system architecture shown in FIG. 1 is only illustrative, and the system architecture 10 of the electronic device may also include more or less devices or software modules. For example, in the system architecture 10 shown in FIG. 1 , may include more processors or processor cores, etc., which are not limited here.

Embodiments of the processor scheduling method provided by the present application will be described in detail below with reference to the accompanying drawings.

Referring to FIG. 2 , FIG. 2 shows a schematic flowchart of a processor scheduling method provided by an embodiment of the present application. In a specific embodiment, the processor scheduling method is applied to the above-mentioned electronic device, and the specific process of this embodiment will be described below by taking the electronic device as an example. Of course, it can be understood that the electronic device applied in this embodiment may be a smart phone, a tablet computer, a smart watch, smart glasses, a notebook computer, etc., which is not limited here. The process shown in FIG. 2 will be described in detail below, and the scheduling method of the processor may specifically include the following steps:

Step S110: If the first processor core satisfies the condition corresponding to the idle state and the second processor core is in the working state, obtain the current working frequency of the first processor core as the first frequency.

In the embodiment of the present application, since one power domain includes processor cores with different processing capabilities, if the processor core with relatively stronger processing capability enters the idle state at a higher frequency, while the processor core with relatively weaker processing capability If the voltage corresponding to the operating frequency of the processor core is lower than the voltage corresponding to the operating frequency of the processor core with relatively strong processing capability, the power domain will be powered on at the voltage corresponding to the operating frequency of the processor core with relatively strong processing capability. power supply, thereby increasing the power consumption of electronic equipment. Therefore, one power supply domain in the electronic device includes the first processor core and the second processor core, and when the processing capability of the first processor core is relatively higher than that of the second processor core, it can be determined that the second processor core Whether a processor core satisfies the condition corresponding to the idle state, so as to determine whether the above-mentioned situation of increasing power consumption will occur. Moreover, when the first processor core satisfies the condition corresponding to the idle state and the second processor core is in the working state, the operating frequencies of the two may be obtained to determine whether the above-mentioned situation of increasing power consumption is met. Wherein, the operating frequency of the first processor core may be obtained, and the operating frequency of the first processor core may be used as the first frequency. The processing capability refers to the processing speed of the processor core when obtaining the same processing effect for the same processing task, that is to say, when the first processor core and the second processor core process the same task, the first processor core The processing task of is higher than the processing speed of the second processor core. In addition, processor cores with stronger processing capabilities can also handle more complex processing tasks, that is, among the first processor core and the second processor core, the first processor core can handle more complex processing tasks .

In some implementations, when it is determined that the first processor core enters the idle state and the second processor core is in the working state, acquiring the operating frequencies of the first processor core and the second processor core may be performed to determine Is it consistent with the above increased power consumption. Optionally, the state of the processor core can be monitored by the scheduler in real time. If the first processor core enters the idle state and the second processor core is in the working state, the above-mentioned situation of increasing power consumption may occur, so the The next step is to obtain the operating frequency of both.

In some other implementation manners, when the first processor core is about to enter an idle state and the second processor core is in a working state, acquiring the operating frequencies of the first processor core and the second processor core may also be performed, To determine whether the above conditions of increased power consumption are met. Optionally, since the working status of the processor cores is scheduled by the scheduler, that is, the scheduler determines the processor cores that need to work and controls the operating frequency of the processor cores according to the generated processing tasks. Therefore, it can be determined in the scheduler When it is necessary to control the first processor core to enter the idle state, it is determined that the first processor core is about to enter the idle state and the second processor core is in the working state.

In some implementations, the correspondence between processor cores and power domains may be stored. That is, the processor cores in the electronic device are divided into the same power domain, so based on the corresponding relationship, it can be determined that the first processor core and the second processor core are in the same power domain, and then execute the The flow of the scheduling method of the processor.

In some implementations, the first processor core enters the idle state. It may be that the scheduler controls the first processor core to enter the idle state when determining that the current load is lower than the first load threshold, so that the processing capacity is relatively low. The powerful but high power consumption first processor core is dormant, thereby reducing the power consumption of the electronic device. In this case, it may be that the electronic device still has processing tasks that need to be processed by the second processor core, so the scheduler controls the second processor core to still be in a working state. Exemplarily, the first processor core can be the super core mentioned above, and the second processor core can be the large core mentioned above, and the two share one power domain. In the application scenario with high load, the scheduler will Enable the ultra-large core and adjust it to a higher operating frequency. When exiting the application scenario, due to the low load, the ultra-large core will be controlled to idle.

Step S120: Obtain the operating frequency of the second processor core as a second frequency.

In the embodiment of the present application, the operating frequency of the second processor core may also be obtained as the second frequency. Optionally, the operating frequency of the second processor core can be obtained from the frequency management module of the scheduler. Of course, when obtaining the operating frequency of the first processor core, the operating frequency of the first processor core is also obtained from the frequency management module. frequency. Certainly, the manner of acquiring the operating frequencies of the first processor core and the second processor core may not be limited.

It should be noted that the order of obtaining the operating frequency of the first processor core and obtaining the operating frequency of the second processor core may not be limited, and it may be that if the first processor core satisfies the condition corresponding to the idle state, and When the second processor core is in the working state, first obtain the current operating frequency of the first processor core as the first frequency, and then obtain the operating frequency of the second processor core as the second frequency; core operating frequency as the second frequency, and then obtain the current operating frequency of the first processor core as the first frequency; it is also possible to simultaneously obtain the operating frequency of the first processor core as the first frequency, and obtain the operating frequency of the second processor core The working frequency is used as the second frequency.

Step S130: If the voltage corresponding to the first frequency is greater than the voltage corresponding to the second frequency, adjust the operating frequency of the first processor core to a third frequency, wherein the voltage corresponding to the third frequency is less than The voltage corresponding to the second frequency.

In the embodiment of the present application, after the first frequency and the second frequency are obtained, the voltage corresponding to the first frequency of the first processor core can be obtained, and the voltage corresponding to the second frequency of the second processor core can be obtained, Compare the voltage corresponding to the first frequency with the voltage corresponding to the second frequency; determine whether the voltage corresponding to the first frequency is greater than the voltage corresponding to the second frequency according to the comparison result; if the voltage corresponding to the first frequency is greater than the voltage corresponding to the second frequency voltage, at this time the power domains corresponding to the two will use a relatively high voltage, that is, the voltage corresponding to the frequency of the first processor core for power supply, and at this time the first processor core meets the conditions corresponding to the idle state, at this time It does not need to work, so it will increase power consumption, so the operating frequency of the first processor core can be adjusted to the third frequency, so that the voltage corresponding to the operating frequency of the first processor core is lower than that of the second processor core. The voltage corresponding to the operating frequency, so that the power supply voltage of the power domain will be the power supply voltage corresponding to the second frequency, so that the power supply voltage will be lower than before, thereby reducing the power consumption of the electronic device, and the first processor core meets the requirements of the idle state. conditions without affecting the normal operation of the electronic equipment. On the contrary, if the voltage corresponding to the first frequency is not greater than the voltage corresponding to the second frequency, the adjustment of the operating frequency may not be performed.

In some embodiments, when adjusting the operating frequency of the first processor core, since the relationship between the required voltage and the operating frequency is usually positively correlated, the scheduler can reduce the operating frequency of the first processor core , so that the voltage corresponding to the reduced third frequency is not greater than the voltage corresponding to the second frequency of the second processor core. Optionally, the operating frequency of the first processor core may be adjusted to the lowest frequency point, that is, the above-mentioned third frequency is the lowest frequency point.

In a possible implementation, after the scheduler determines the third frequency that the first processor core needs to adjust to, it can send a frequency modulation request to adjust the operating frequency to the third frequency to the hardware frequency conversion module through Cpufreq, and accordingly, the hardware frequency conversion The module adjusts the operating frequency of the first processor core to the third frequency based on the frequency adjustment request. Wherein, Cpufreq is a driver used for dynamic voltage regulation and frequency modulation (DVFS), and the scheduler can realize the adjustment of the operating frequency of the processor core through the driver program.

In some implementations, due to the different configurations of different processor cores, the corresponding relationship between different operating frequencies and required voltages is also different. Therefore, the corresponding relationship between the voltage of the first processor core and the operating frequency and the corresponding relationship between the voltage of the second processor core and the operating frequency can be stored, and then based on the stored corresponding relationship, the first The voltage corresponding to the first frequency of the processor core, and the voltage corresponding to the second frequency of the second processor core are acquired.

It should be noted that, in the embodiment of the present application, in the power domain shared by the first processor core and the second processor core, the number of the first processor core and the second processor core may not be limited, that is to say , it can be understood that the power domain includes two types of processor cores. When the number of the first processor core is multiple and the second processor core is single, for example, the power domain includes a plurality of the above-mentioned large cores and one of the above-mentioned small cores, then all the first processor cores satisfy the idle The condition corresponding to the state, and the second processor core is in the working state, execute the above process; when the first processor core is single and the second processor core is multiple, for example, the power domain includes a super core, and When there are multiple large cores, when the voltage corresponding to the first frequency is greater than the voltage corresponding to the operating frequency of each second processor core in the working state, the operating frequency of the first processor core is adjusted to the third frequency; When the number of the first processor core and the number of the second processor core are multiple, it is necessary to execute the above process when all the first processor cores meet the conditions corresponding to the idle state and the second processor core is in the working state, And when the voltage corresponding to the operating frequency of any first processor core is greater than the voltage corresponding to the operating frequency of all the second processor cores in the working state, the operating frequency of the first processor core is adjusted to the third frequency.

Optionally, the processor scheduling method provided in the embodiment of the present application may be executed by a scheduler, and the scheduler may run on any processor core in a working state, or a specially configured hardware device.

The processor scheduling method provided in the embodiment of the present application can realize that the first processor core and the second processor core share one power domain, thereby reducing the number of power modules and reducing the cost. And when the first processor core with relatively strong processing capability enters the idle state, it can supply power with the voltage corresponding to the operating frequency of the second processor core in the working state, and because the operating frequency of the second processor core corresponds to The voltage is relatively small, so it can reduce the power consumption of electronic equipment.

Referring to FIG. 3 , FIG. 3 shows a schematic flowchart of a processor scheduling method provided by another embodiment of the present application. The scheduling method of the processor is applied to the above-mentioned electronic equipment, and the process shown in FIG. 3 will be described in detail below. The scheduling method of the processor may specifically include the following steps:

Step S210: if the first processor core is in the working state, obtain the probability that the first processor core enters the idle state from the working state as the first probability.

In the embodiment of the present application, when the first processor core is in the working state and is about to enter the idle state, and the second processor core is in the working state, the operating frequency of the two can be obtained to determine whether the operating frequency of the two satisfies The above-mentioned cases of increased power consumption. Specifically, when the processor core is in the working state, the probability that the first processor core enters the idle state from the working state may be acquired as the first probability. Wherein, the probability that the first processor core enters the idle state from the working state indicates the possibility that the first processor core currently enters the idle state, and the higher the probability, the more likely it is to enter the idle state.

In some implementations, obtaining the probability that the first processor core enters the idle state from the working state as the first probability may include: obtaining the task queue of the processor; The processing tasks corresponding to the processor cores, determine the probability that the first processor core enters the idle state from the working state as the first probability, and the probability is negatively correlated with the number of the processing tasks. It can be understood that when the first processor core has more processing tasks, it means that it currently needs to process more tasks, so it is less likely to enter the idle state, therefore, the above probability is lower; on the contrary, the first processing The more processing tasks a processor core corresponds to, the greater the possibility it will enter the idle state, so the number of processing tasks corresponding to the first processor core in the task queue can be obtained to determine the above probability. Optionally, when the number of processing tasks of the first processor core is 0, the above probability may be determined as 100%.

In some other implementation manners, the load of the processor may also be obtained, so as to determine the above probability according to the load of the processor. Wherein, the load amount may be acquired through a task load tracking (per-entity loadtracking, PELT) module in the device. Optionally, the utilization rate of the processor may be used to describe the load of the processor, for example, the value used to describe the processor load may be the value of the utilization rate of the processor core.

In a possible implementation manner, when the processor of the electronic device includes a super-large core, a large core, and a small core, the super-large core is the above-mentioned first processor core, and the large core is the above-mentioned second processor core. In this case, the requirement When the ultra-large core processes tasks, usually when the load on the processor is high, that is, when there are many processing tasks, the ultra-large core is enabled to optimize the power consumption of electronic devices. Therefore, in this case, the load of the processor may be acquired, so as to determine the probability that the first processor core enters the idle state according to the load of the processor.

Optionally, it may be determined whether the load of the processor is less than a second load threshold, and the second load threshold is the basis for judging whether the first processor core will be adjusted to an idle state, if the load of the processor is less than the second If the threshold value of the load is lower, the above probability may be determined as 100%, otherwise, the above probability may be determined as 0%.

Optionally, it may be determined whether the load of the processor is less than a second load threshold, and the second load threshold is the basis for judging whether the first processor core will be adjusted to an idle state, if the load of the processor is less than the second load threshold, then the above probability can be determined as 100%; if the processor load is not less than the second load threshold, it can be further judged whether the processor load is less than the third load threshold, the third load threshold If it is greater than the second load threshold, the third load threshold is used as the judgment basis for entering the idle state; if it is less than the third load threshold, it can be further based on the load data within the preset time period before the current moment. , to obtain the change trend of the load of the processor, and when the change trend is a decreasing trend, based on the magnitude of the decrease, the above probability is determined, of course, the above is determined when the load of the processor is not less than the second load threshold The probability should be less than 100%. In addition, the above determined probabilities are positively correlated with the decreasing range, for example, proportional. If the load of the processor is not less than the third load threshold, it means that there is no possibility of adjusting to the idle state at present, so the above probability is determined as 0.

Of course, there is no limitation to a specific manner of obtaining the probability that the first processor core enters the idle state from the working state.

Step S220: If the first probability is greater than the first preset probability, and the second processor core is in a working state, obtain the current working frequency of the first processor core as the first frequency.

In the embodiment of the present application, after the above first probability is obtained, the first probability can be compared with the first preset probability, and the first preset probability is used as an indicator of whether the first processor core enters the idle state from the working state. Judgment basis; according to the comparison result, if it is determined that the first probability is greater than the first preset probability, it means that the first processor core will enter the idle state from the working state, so the acquisition process can be executed so as to satisfy the above-mentioned increase in power consumption In some cases, the operating frequency of the first processor core is adjusted to reduce power consumption; otherwise, if it is determined that the first probability is not greater than the first preset probability, the subsequent processes may not be executed. Wherein, the specific value of the first preset probability may not be limited, for example, the first preset probability may be 90%, 95% and so on.

Step S230: Obtain the operating frequency of the second processor core as a second frequency.

Step S240: If the voltage corresponding to the first frequency is greater than the voltage corresponding to the second frequency, adjust the operating frequency of the first processor core to a third frequency, wherein the voltage corresponding to the third frequency is less than The voltage corresponding to the second frequency.

In the embodiment of the present application, reference may be made to the contents of other embodiments for step S230 and step S240, and details are not repeated here.

Step S250: Based on the voltage corresponding to the third frequency and the voltage corresponding to the second frequency, determine that the supply voltage corresponding to the power domain is the voltage corresponding to the second frequency.

In the embodiment of the present application, after adjusting the operating frequency of the first processor core to the third frequency, the voltage corresponding to the third frequency is lower than the voltage corresponding to the second frequency. At this time, based on the voltage corresponding to the third frequency, voltage and the voltage corresponding to the second frequency, and then determine the power supply voltage corresponding to the power domain as the voltage corresponding to the second frequency. That is to say, a relatively high voltage, that is, the voltage of the second frequency is determined from the voltage corresponding to the third frequency and the voltage corresponding to the second frequency as the power supply voltage.

Step S260: Adjust the power supply voltage of the power domain to the voltage corresponding to the second frequency.

In the embodiment of the present application, after it is determined that the power supply voltage of the power domain is the voltage corresponding to the second frequency, the power supply voltage of the power domain can be adjusted to the voltage corresponding to the second frequency, thereby preventing the first processor core from being When a frequency with a relatively high voltage enters an idle state, the power domain still uses a relatively high voltage for power supply, thereby avoiding an increase in power consumption.

It should be noted that steps S250 and S260 can also be used in other embodiments, that is, in other embodiments, after the operating frequency of the first processor core is adjusted to the third frequency, the processes of steps S250 and S260 can also be executed.

The processor scheduling method provided by the embodiment of the present application obtains the probability that the first processor core enters the idle state from the working state when the first processor core is in the working state as the first probability, and when the first probability is greater than the first predetermined If the probability is set and the second processor core is in the working state, the current operating frequency of the first processor core is obtained as the first frequency, and the operating frequency of the second processor core is obtained as the second frequency. If the first frequency corresponds to The voltage corresponding to the second frequency is greater than the voltage corresponding to the second frequency, and the operating frequency of the first processor core is adjusted to a third frequency, wherein the voltage corresponding to the third frequency is lower than the voltage corresponding to the second frequency. Thus, when the first processor core and the second processor core share one power supply domain, when the first processor core is about to enter the idle state, the operating frequency of the second processor core in the working state can be The corresponding voltage is used for power supply, and since the voltage corresponding to the working frequency of the second processor core is relatively small, the power consumption of the electronic device can be reduced.

Referring to FIG. 4 , FIG. 4 shows a schematic flowchart of a processor scheduling method provided in another embodiment of the present application. The scheduling method of the processor is applied to the above-mentioned electronic equipment, and the process shown in FIG. 4 will be described in detail below. The scheduling method of the processor may specifically include the following steps:

Step S310: If the first processor core enters an idle state and the second processor core is in a working state, obtain the current working frequency of the first processor core as a first frequency.

Different from the previous embodiment, in the embodiment of the present application, after the first processor core is in the working state and enters the idle state, and when the second processor core is in the working state, the operating frequencies of the two can be obtained, so as to Determine whether the operating frequency of both meets the above-mentioned increase in power consumption.

In some implementations, since the working status of the processor cores is scheduled by the scheduler, that is, the scheduler determines the processor cores that need to work and controls the working frequency of the processor cores according to the generated processing tasks. When the controller controls the first processor core to enter the idle state, it is determined that the first processor core enters the idle state, and the scheduler can acquire the fact that the second processor core is in the working state.

Step S320: Obtain the operating frequency of the second processor core as a second frequency.

Step S330: If the voltage corresponding to the first frequency is greater than the voltage corresponding to the second frequency, adjust the operating frequency of the first processor core to a third frequency, wherein the voltage corresponding to the third frequency is less than The voltage corresponding to the second frequency.

In the embodiment of the present application, reference may be made to the contents of other embodiments for step S320 and step S330, and details are not repeated here.

The processor scheduling method provided by the embodiment of the present application can realize that when the first processor core and the second processor core share one power domain, after the first processor core enters the idle state, it can be in the working state The voltage corresponding to the operating frequency of the second processor core is powered, and since the voltage corresponding to the operating frequency of the second processor core is relatively small, the power consumption of the electronic device can be reduced

Referring to FIG. 5 , FIG. 5 shows a schematic flowchart of a processor scheduling method provided in another embodiment of the present application. The scheduling method of the processor is applied to the above-mentioned electronic equipment. The process shown in FIG. 5 will be described in detail below, and the scheduling method of the processor may specifically include the following steps:

Step S410: if the first processor core satisfies the condition corresponding to the idle state and the second processor core is in the working state, obtain the current working frequency of the first processor core as the first frequency.

Step S420: Obtain the operating frequency of the second processor core as a second frequency.

Step S430: If the voltage corresponding to the first frequency is greater than the voltage corresponding to the second frequency, adjust the operating frequency of the first processor core to a third frequency, wherein the voltage corresponding to the third frequency is less than The voltage corresponding to the second frequency.

In the embodiment of the present application, reference may be made to the contents of the foregoing embodiments for steps S410 to S430, and details are not repeated here.

Step S440: If the first processor core satisfies the condition corresponding to the working state, adjust the working frequency of the first processor core to the first frequency.

In this embodiment of the application, the first processor core satisfies the conditions corresponding to the idle state, the second processor core is in the working state, and the voltage corresponding to the operating frequency of the first processor core is greater than the voltage corresponding to the operating frequency of the second processor core. In the case of the voltage of the first processor core, after reducing the operating frequency of the first processor core to the third frequency, the operating frequency of the first processor core can also be adjusted when the first processor core meets the conditions corresponding to the working state Return to the previous first frequency. Understandably, after the first processor core exits the idle state, it needs to run at a higher operating frequency when it is in the working state, so it can be adjusted back to the previous first frequency to ensure that the first processor core can Smooth execution of processing tasks to ensure performance. For example, when the first processor core is the above-mentioned ultra-large core, it usually needs to handle more complex processing tasks during operation, and in order to ensure the processing effect, it will run at a higher operating frequency. Therefore, when the ultra-large core enters the After the idle state, it will be required to work at a higher frequency when exiting the idle state; for another example, the first frequency of the first processor core may be its operating frequency during normal operation, so it can be processed after exiting the idle state. , it can be adjusted back to the previous first frequency; another example, the first processor core entered the idle state before, it may be that the processing task was suddenly shut down, and after a period of time, it needs to continue processing the previous processing task, so in After it exits the idle state, it can be adjusted back to the previous first frequency to ensure normal processing of the processing task.

In some implementations, if it is determined above that the voltage corresponding to the first frequency is greater than the voltage corresponding to the second frequency, after adjusting the operating frequency of the first processor core to the third frequency, the first processor core may also be stored The corresponding relationship between the core and the first frequency. Thus, when the first processor core satisfies the condition corresponding to the working state, the working frequency of the first processor core may be adjusted back to the previous first frequency based on the stored correspondence.

In some embodiments, when the first processor core is about to enter the working state from the idle state, the operating frequency of the first processor core may be adjusted to the first frequency, so as to adjust the first processor core back to the first frequency in advance. frequency, so that it can be ensured that the first processor core can understand to run at the first frequency after entering the working state, so as to process the processing task. Wherein, the probability that the first processor core enters the working state from the idle state can be obtained as the second probability; if the second probability is greater than the second preset probability, the operating frequency of the first processor core is adjusted to the first frequency.

In this embodiment, the probability that the first processor core enters the working state from the idle state indicates the possibility that the first processor core currently enters the working state, and the higher the probability, the more likely it is to enter the working state.

As an implementation manner, the load of the processor may be obtained, so as to determine the above probability according to the load of the processor. Wherein, the load amount may be acquired through a task load tracking (per-entity load tracking, PELT) module in the device. Optionally, the utilization rate of the processor may be used to describe the load of the processor, for example, the value used to describe the processor load may be the value of the utilization rate of the processor core. Since the first processor core is a processor core with relatively strong processing capability, it is more likely to enter the working state when the processor load is larger, so the above probability can be determined based on the processor load , and the probability is positively correlated with the processor load.

In some other implementation manners, it is also possible to adjust the operating frequency of the first processor core to the first frequency when the first processor core enters the working state, so as to ensure that the first processor core can understand the The first frequency runs so as to process the processing tasks. Optionally, since the working state of the processor core is scheduled by the scheduler, that is, the scheduler determines the processor core that needs to work and controls the operating frequency of the processor core according to the generated processing tasks, therefore, the scheduler can control When the first processor core enters the working state, it is determined that the first processor core is about to enter the working state.

It should be noted that step S440 in the embodiment of the present application can also be applied in other embodiments, that is, after the operating frequency of the first processor core is adjusted to the third frequency, the first processor core can If the condition corresponding to the working state is satisfied, the working frequency of the first processor core is adjusted to the first frequency.

The processor scheduling method provided in the embodiment of the present application can realize that the first processor core and the second processor core share one power domain, thereby reducing the number of power modules and reducing the cost. And when the first processor core with relatively strong processing capability enters the idle state, it can supply power with the voltage corresponding to the operating frequency of the second processor core in the working state, and because the operating frequency of the second processor core corresponds to The voltage is relatively small, so it can reduce the power consumption of electronic equipment. In addition, when the first processor core exits the idle state and enters the working state, the operating frequency of the first processor core is adjusted to the first frequency, thereby ensuring processing performance.

Referring to FIG. 6 , FIG. 6 shows a schematic flowchart of a processor scheduling method provided in yet another embodiment of the present application. The scheduling method of the processor is applied to the above-mentioned electronic equipment, and the process shown in FIG. 6 will be described in detail below, and the scheduling method of the processor may specifically include the following steps:

Step S510: If the first processor core satisfies the condition corresponding to the idle state and the second processor core is in the working state, obtain the current working frequency of the first processor core as the first frequency.

In the embodiment of the present application, for step S510, reference may be made to the content of the foregoing embodiments, and details are not repeated here.

Step S520: When the current load of the second processor core is lower than a preset load, adjust the operating frequency of the second processor to a second frequency.

In this embodiment of the application, if the first processor core and the second processor core are included in the same power domain, and the processing capability of the first processor core is higher than that of the second processor core, in this case, if When the first processor core is in the idle state, the second processor core may also reduce the operating frequency because the load of the current processor is reduced. Therefore, the scheduler can acquire the current load of the second processor core to determine whether the current load is lower than the preset load; if the current load is lower than the preset load, the work of the second processor core can be The frequency is adjusted to the second frequency, so that the working state of the processor core corresponds to the load of the processor core.

Step S530: Obtain the operating frequency of the second processor core as a second frequency.

Step S540: If the voltage corresponding to the first frequency is greater than the voltage corresponding to the second frequency, adjust the operating frequency of the first processor core to a third frequency, wherein the voltage corresponding to the third frequency is less than The voltage corresponding to the second frequency.

In the embodiment of the present application, reference may be made to the contents of the foregoing embodiments for step S530 and step S540, and details are not repeated here.

In some scenarios, the first processor core can be the above-mentioned super large core, and the second processor core can be the above-mentioned large core, then it can be realized that when the super large core enters the idle state from a higher frequency, when the large core at this time Adjust to a lower frequency point. At this time, the voltage corresponding to the operating frequency of the super-large core is greater than the voltage corresponding to the operating frequency of the large core. Adjust the operating frequency of the super-large core so that the follow-up can use the operating frequency of the large core Voltage for power supply, thereby reducing power consumption.

In some embodiments, the electronic device may also include other power domains. For example, the power domains corresponding to the aforementioned first processor core and the second processor core are the first power domain, and the electronic device further includes a second power domain, a third power domain, and a third power domain. power domain, etc.; the processor also includes other processor cores, such as a third processor core, a fourth processor core, and the like. Other processor cores can be assigned to other power domains. For example, the third processor core and the fourth processor core can share the second power domain. In the case that the voltage corresponding to the first frequency is greater than the voltage corresponding to the second frequency , it can also be determined whether the load corresponding to the second processor core is less than the fourth load threshold; if the load corresponding to the second processor core is not less than (greater than or equal to) the fourth load threshold, it means that the current second processor core There are many processing tasks corresponding to the core, so the second processor core can continue to process the task according to the above second frequency, so as to adjust the operating frequency of the first processor core to the third frequency, thereby reducing power consumption; if the second The load corresponding to the processor core is less than the fourth load threshold, which means that the current processing tasks corresponding to the second processor core are less. In this case, the processing tasks of the second processor core can be migrated to processors in other power domains In the core, for example, migrate to the third processor core in the second power supply domain, thereby making both the first processor core and the second processor core enter the idle state, at this time the first processor core and the second processor core Even if the power supply domain corresponding to the processor core is powered by a higher voltage, since the first processor core and the second processor core are both in an idle state, no large power consumption will be brought, and the task allocation will be more reasonable.

The processor scheduling method provided in the embodiment of the present application can realize that the first processor core and the second processor core share one power domain, thereby reducing the number of power modules and reducing the cost. And when the first processor core with relatively strong processing capability enters the idle state and the operating frequency of the second processor core is adjusted, the voltage corresponding to the operating frequency of the second processor core in the working state can be used for power supply , and since the voltage corresponding to the working frequency of the second processor core is relatively small, the power consumption of the electronic device can be reduced.

Please refer to FIG. 7 , which shows a structural block diagram of a processor scheduling apparatus 400 provided in an embodiment of the present application. The processor scheduling device 400 is applied to the above-mentioned electronic equipment, and is applied to the electronic equipment. The processor of the electronic equipment includes a first processor core and a second processor core, and the first processor core and the second processor core The processor cores share one power domain, the processing capability of the first processor core is higher than that of the second processor core, and the scheduling device 400 of the processor includes: a first frequency acquisition module 410, a second frequency An acquisition module 420 and a frequency adjustment module 430 . Wherein, the first frequency acquiring module 410 is configured to acquire the current working frequency of the first processor core if the first processor core satisfies the condition corresponding to the idle state and the second processor core is in the working state. frequency as the first frequency; the second frequency obtaining module 420 is used to obtain the operating frequency of the second processor core as the second frequency; the frequency adjustment module 430 is used to if the voltage corresponding to the first frequency is greater than The voltage corresponding to the second frequency adjusts the operating frequency of the first processor core to a third frequency, wherein the voltage corresponding to the third frequency is smaller than the voltage corresponding to the second frequency.

In some implementations, the first frequency obtaining module 410 may be configured to: if the first processor core is in the working state, obtain the probability that the first processor core enters the idle state from the working state as the first probability; if The first probability is greater than a first preset probability, and the second processor core is in a working state, and the current working frequency of the first processor core is acquired as the first frequency.

In a possible implementation manner, the first frequency obtaining module 410 obtains the probability that the first processor core enters the idle state from the working state as the first probability, which may include: obtaining the task queue of the processor; The processing tasks corresponding to the first processor core in the task queue, determine the probability that the first processor core enters the idle state from the working state as the first probability, and the probability is negatively correlated with the number of processing tasks .

In some implementations, the first frequency acquiring module 410 may be configured to: if the first processor core enters the idle state and the second processor core is in the working state, acquire the current frequency of the first processor core The working frequency is used as the first frequency.

In some implementations, the frequency adjustment module 430 may also be configured to adjust the operating frequency of the first processor core to the second frequency if the voltage corresponding to the first frequency is greater than the voltage corresponding to the second frequency. After three frequencies, if the first processor core satisfies a condition corresponding to the working state, adjust the working frequency of the first processor core to the first frequency.

In a possible implementation manner, the frequency adjustment module 430 may also be configured to: acquire the probability that the first processor core enters the working state from the idle state as the second probability; if the second probability is greater than the second preset probability, adjusting the operating frequency of the first processor core to the first frequency.

In a possible implementation manner, the frequency adjustment module 430 may also be configured to: adjust the operating frequency of the first processor core to the first frequency.

In a possible implementation manner, the processor scheduling apparatus 400 may further include: a frequency storage module. The frequency storage module may be used for: after adjusting the operating frequency of the first processor core to a third frequency if the voltage corresponding to the first frequency is greater than the voltage corresponding to the second frequency, storing the Correspondence between the first processor core and the first frequency. The frequency adjustment module 430 may be configured to: adjust the operating frequency of the first processor core to the first frequency based on the corresponding relationship if the first processor core satisfies a condition corresponding to the working state.

In some implementations, the frequency adjustment module 430 may also be configured to, before acquiring the operating frequency of the second processor core as the second frequency, when the current load of the second processor core is lower than the preset When the load is large, the operating frequency of the second processor is adjusted to the second frequency.

In some implementations, the processor scheduling device 400 may further include: a power supply determination module and a voltage adjustment module. The power supply determination module is configured to adjust the operating frequency of the first processor core to a third frequency if the voltage corresponding to the first frequency is greater than the voltage corresponding to the second frequency, based on the third The voltage corresponding to the frequency and the voltage corresponding to the second frequency determine that the power supply voltage corresponding to the power domain is the voltage corresponding to the second frequency; the voltage adjustment module is used to adjust the power supply voltage of the power domain to the first The voltage corresponding to the second frequency.

Those skilled in the art can clearly understand that for the convenience and brevity of the description, the specific working process of the devices and modules described above can refer to the corresponding process in the foregoing method embodiments, which will not be repeated here.

In several embodiments provided in the present application, the coupling between the modules may be electrical, mechanical or other forms of coupling.

In addition, each functional module in each embodiment of the present application may be integrated into one processing module, each module may exist separately physically, or two or more modules may be integrated into one module. The above-mentioned integrated modules can be implemented in the form of hardware or in the form of software function modules.

To sum up, in the solution provided by this application, the processor of the electronic device includes a first processor core and a second processor core sharing one power supply domain, and the processing capability of the first processor core is higher than that of the second processor core processing capability, when the first processor core satisfies the conditions corresponding to the idle state and the second processor core is in the working state, the current operating frequency of the first processor core is obtained as the first frequency, and the second processor core is obtained The operating frequency of the core is used as the second frequency. If the voltage corresponding to the first frequency is greater than the voltage corresponding to the second frequency, the operating frequency of the first processor core is adjusted to a third frequency, wherein the voltage corresponding to the third frequency is lower than the voltage corresponding to the second frequency. The voltage corresponding to the frequency. Thus, when the first processor core and the second processor core share one power supply domain, when the first processor core enters the idle state, the operating frequency of the second processor core in the working state can correspond to and the voltage corresponding to the working frequency of the second processor core is relatively small, so the power consumption of the electronic device can be reduced.

Please refer to FIG. 8 , which shows a structural block diagram of an electronic device provided by an embodiment of the present application. The electronic device 100 may be an electronic device capable of running application programs, such as a smart phone, a tablet computer, a smart watch, smart glasses, and a notebook computer. The electronic device 100 in the present application may include one or more of the following components: a processor 110, a memory 120, and one or more application programs, wherein one or more application programs may be stored in the memory 120 and configured to be used by One or more processors 110 are executed, and one or more programs are configured to execute the methods described in the foregoing method embodiments.

Processor 110 may include multiple processor cores. The processor 110 uses various interfaces and lines to connect various parts of the entire electronic device 100, and executes or executes instructions, programs, code sets or instruction sets stored in the memory 120, and calls data stored in the memory 120 to execute Various functions of the electronic device 100 and processing data. Wherein, the plurality of processor cores may at least include a first processor core and a second processor core, the first processor core and the second processor core share one power domain, and the first processor core The processing capability is higher than the processing capability of the second processor core.

Optionally, the processor 110 may use at least one of Digital Signal Processing (Digital Signal Processing, DSP), Field-Programmable Gate Array (Field-Programmable Gate Array, FPGA), and Programmable Logic Array (Programmable Logic Array, PLA). implemented in the form of hardware. The processor 110 may integrate one or a combination of a central processing unit (Central Processing Unit, CPU), a graphics processing unit (Graphics Processing Unit, GPU), a modem, and the like. Among them, the CPU mainly handles the operating system, user interface and application programs, etc.; the GPU is used to render and draw the displayed content; the modem is used to handle wireless communication. It can be understood that, the above-mentioned modem may not be integrated into the processor 110, but may be realized by a communication chip alone.

The memory 120 may include a random access memory (Random Access Memory, RAM), and may also include a read-only memory (Read-Only Memory). The memory 120 may be used to store instructions, programs, codes, sets of codes, or sets of instructions. The memory 120 may include a program storage area and a data storage area, wherein the program storage area may store instructions for implementing an operating system and instructions for implementing at least one function (such as a touch function, a sound playback function, an image playback function, etc.) , instructions for implementing the following method embodiments, and the like. The storage data area can also store data created during use of the electronic device 100 (such as phonebook, audio and video data, chat record data) and the like.

Please refer to FIG. 9 , which shows a structural block diagram of a computer-readable storage medium provided by an embodiment of the present application. Program codes are stored in the computer-readable medium 800, and the program codes can be invoked by a processor to execute the methods described in the foregoing method embodiments.

The computer readable storage medium 800 may be an electronic memory such as flash memory, EEPROM (Electrically Erasable Programmable Read Only Memory), EPROM, hard disk, or ROM. Optionally, the computer-readable storage medium 800 includes a non-transitory computer-readable storage medium (non-transitory computer-readable storage medium). The computer-readable storage medium 800 has a storage space for program code 810 for executing any method steps in the above-mentioned methods. These program codes can be read from or written into one or more computer program products. Program code 810 may, for example, be compressed in a suitable form.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, but not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: it can still Modifications are made to the technical solutions described in the foregoing embodiments, or equivalent replacements are made to some of the technical features; and these modifications or replacements do not drive the essence of the corresponding technical solutions away from the spirit and scope of the technical solutions of the various embodiments of the present application.

Claims (13)

1. A scheduling method of a processor is applied to an electronic device, wherein the processor of the electronic device includes a first processor core and a second processor core, the first processor core and the second processor core share a power domain, and a processing capability of the first processor core is higher than a processing capability of the second processor core, and the method includes:

if the first processor core meets the condition corresponding to the idle state and the second processor core is in the working state, acquiring the working frequency of the current first processor core as a first frequency;

acquiring the working frequency of the second processor core as a second frequency;

if the voltage corresponding to the first frequency is greater than the voltage corresponding to the second frequency, the operating frequency of the first processor core is adjusted to a third frequency, wherein the voltage corresponding to the third frequency is less than the voltage corresponding to the second frequency.

2. The method of claim 1, wherein the obtaining the current operating frequency of the first processor core as the first frequency if the first processor core meets the condition corresponding to the idle state and the second processor core is in the operating state comprises:

if the first processor core is in a working state, acquiring the probability that the first processor core enters an idle state from the working state as a first probability;

and if the first probability is greater than a first preset probability and the second processor core is in a working state, acquiring the current working frequency of the first processor core as a first frequency.

3. The method of claim 2, wherein obtaining, as the first probability, the probability that the first processor core enters the idle state from the operating state comprises:

acquiring a task queue of the processor;

and determining the probability of the first processor core entering an idle state from a working state as a first probability based on the processing tasks corresponding to the first processor core in the task queue, wherein the probability is in negative correlation with the number of the processing tasks.

4. The method of claim 1, wherein the obtaining the current operating frequency of the first processor core as the first frequency if the first processor core meets the condition corresponding to the idle state and the second processor core is in the operating state comprises:

and if the first processor core enters an idle state and the second processor core is in a working state, acquiring the current working frequency of the first processor core as a first frequency.

5. The method of claim 1, wherein after the adjusting the operating frequency of the first processor core to a third frequency if the voltage corresponding to the first frequency is greater than the voltage corresponding to the second frequency, the method further comprises:

and if the first processor core meets the condition corresponding to the working state, adjusting the working frequency of the first processor core to the first frequency.

6. The method of claim 5, wherein the adjusting the operating frequency of the first processor core to the first frequency if the first processor core meets the condition corresponding to the operating state comprises:

acquiring the probability of the first processor core entering a working state from an idle state as a second probability;

and if the second probability is greater than a second preset probability, adjusting the working frequency of the first processor core to the first frequency.

7. The method of claim 5, wherein the adjusting the operating frequency of the first processor core to the first frequency if the first processor core meets the condition corresponding to the operating state comprises:

and if the first processor core enters a working state from an idle state, adjusting the working frequency of the first processor core to the first frequency.

8. The method of claim 5, wherein after the adjusting the operating frequency of the first processor core to a third frequency if the voltage corresponding to the first frequency is greater than the voltage corresponding to the second frequency, the method further comprises:

storing the corresponding relation between the first processor core and the first frequency;

if the first processor core meets the condition corresponding to the working state, the adjusting the working frequency of the first processor core to the first frequency comprises the following steps:

and if the first processor core meets the condition corresponding to the working state, adjusting the working frequency of the first processor core to the first frequency based on the corresponding relation.

9. The method of any of claims 1-8, wherein prior to the obtaining the operating frequency of the second processor core as the second frequency, the method further comprises:

and when the current load capacity of the second processor core is lower than a preset load capacity, adjusting the working frequency of the second processor to the second frequency.

10. The method of any of claims 1-8, wherein after the adjusting the operating frequency of the first processor core to a third frequency if the voltage corresponding to the first frequency is greater than the voltage corresponding to the second frequency, the method further comprises:

determining the power supply voltage corresponding to the power domain as the voltage corresponding to the second frequency based on the voltage corresponding to the third frequency and the voltage corresponding to the second frequency;

and adjusting the power supply voltage of the power domain to be the voltage corresponding to the second frequency.

11. A scheduling apparatus of a processor, applied to an electronic device, where the processor of the electronic device includes a first processor core and a second processor core, the first processor core and the second processor core share a power domain, and a processing capability of the first processor core is higher than a processing capability of the second processor core, the apparatus includes: a first frequency acquisition module, a second frequency acquisition module, and a frequency adjustment module, wherein,

the first frequency obtaining module is used for obtaining the current working frequency of the first processor core as a first frequency if the first processor core meets the condition corresponding to the idle state and the second processor core is in the working state;

the second frequency acquisition module is used for acquiring the working frequency of the second processor core as a second frequency;

the frequency adjustment module is configured to adjust the operating frequency of the first processor core to a third frequency if the voltage corresponding to the first frequency is greater than the voltage corresponding to the second frequency, where the voltage corresponding to the third frequency is less than the voltage corresponding to the second frequency.

12. An electronic device, comprising:

one or more processors comprising a first processor core and a second processor core;

a memory;

one or more applications, wherein the one or more applications are stored in the memory and configured to be executed by the one or more processors, the one or more programs configured to perform the method of any of claims 1-10.

13. A computer-readable storage medium, having stored thereon program code that can be invoked by a processor to perform the method according to any one of claims 1 to 10.

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