CN115712337A

CN115712337A - Scheduling method and device of processor, electronic equipment and storage medium

Info

Publication number: CN115712337A
Application number: CN202110969985.9A
Authority: CN
Inventors: 白文超
Original assignee: Zeku Technology Shanghai Corp Ltd
Current assignee: Weiguang Co ltd
Priority date: 2021-08-23
Filing date: 2021-08-23
Publication date: 2023-02-24

Abstract

The application discloses a scheduling method and a scheduling device of a processor, electronic equipment and a storage medium, wherein the scheduling method of the processor is applied to the electronic equipment, the processor of the electronic equipment comprises a first processor core and a second processor core, the first processor core and the second processor core share a power domain, the processing capacity of the first processor core is higher than that of the second processor core, and the scheduling method of the processor comprises the following steps: if the first processor core meets the condition corresponding to the idle state and the second processor core is in the working state, acquiring the working frequency of the current first processor core as a first frequency; acquiring the working frequency of the second processor core as a second frequency; if the voltage corresponding to the first frequency is greater than the voltage corresponding to the second frequency, the operating frequency of the first processor core is adjusted to a third frequency, wherein the voltage corresponding to the third frequency is less than the voltage corresponding to the second frequency. The method can reduce the power consumption of the electronic equipment.

Description

Scheduling method and device of processor, electronic equipment and storage medium

Technical Field

The present application relates to the field of electronic device technologies, and in particular, to a scheduling method and apparatus for a processor, an electronic device, and a storage medium.

Background

With the rapid progress of the technology level and the living standard, the electronic devices are more and more widely used. In addition, people have higher and higher performance requirements on electronic devices, and electronic devices equipped with multi-core processors are appeared. However, while the configuration level of the electronic device is increased, a large amount of power consumption is also caused to the electronic device.

Disclosure of Invention

In view of the foregoing problems, the present application provides a scheduling method and apparatus for a processor, an electronic device, and a storage medium.

In a first aspect, an embodiment of the present application provides a scheduling method for a processor, which is applied to an electronic device, where the processor of the electronic device includes a first processor core and a second processor core, the first processor core and the second processor core share a power domain, and a processing capability of the first processor core is higher than a processing capability of the second processor core, and the method includes: if the first processor core meets the condition corresponding to the idle state and the second processor core is in the working state, acquiring the working frequency of the current first processor core as a first frequency; acquiring the working frequency of the second processor core as a second frequency; if the voltage corresponding to the first frequency is greater than the voltage corresponding to the second frequency, the operating frequency of the first processor core is adjusted to a third frequency, wherein the voltage corresponding to the third frequency is less than the voltage corresponding to the second frequency.

In a second aspect, an embodiment of the present application provides a scheduling apparatus for a processor, which is applied to an electronic device, where the processor of the electronic device includes a first processor core and a second processor core, the first processor core and the second processor core share a power domain, and a processing capability of the first processor core is higher than a processing capability of the second processor core, and the apparatus includes: the device comprises a first frequency acquisition module, a second frequency acquisition module and a frequency adjustment module, wherein the first frequency acquisition module is used for acquiring the current working frequency of the first processor core as a first frequency if the first processor core meets the condition corresponding to the idle state and the second processor core is in the working state; the second frequency acquisition module is used for acquiring the working frequency of the second processor core as a second frequency; the frequency adjustment module is configured to adjust the operating frequency of the first processor core to a third frequency if the voltage corresponding to the first frequency is greater than the voltage corresponding to the second frequency, where the voltage corresponding to the third frequency is less than the voltage corresponding to the second frequency.

In a third aspect, an embodiment of the present application provides an electronic device, including: one or more processors comprising a first processor core and a second processor core; a memory; one or more applications, wherein the one or more applications are stored in the memory and configured to be executed by the one or more processors, the one or more programs configured to perform the scheduling method of processors as provided in the first aspect above.

In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, where a program code is stored in the computer-readable storage medium, and the program code may be called by a processor to execute the scheduling method of the processor provided in the first aspect.

According to the scheme, a processor of the electronic device comprises a first processor core and a second processor core which share one power domain, the processing capacity of the first processor core is higher than that of the second processor core, under the condition that the first processor core meets the condition corresponding to the idle state and the second processor core is in the working state, the current working frequency of the first processor core is obtained as a first frequency, the current working frequency of the second processor core is obtained as a second frequency, if the voltage corresponding to the first frequency is higher than the voltage corresponding to the second frequency, the working frequency of the first processor core is adjusted to be a third frequency, and the voltage corresponding to the third frequency is lower than the voltage corresponding to the second frequency. Therefore, under the condition that the first processor core and the second processor core share one power domain, when the first processor core enters an idle state, the first processor core can supply power with the voltage corresponding to the working frequency of the second processor core in the working state, and the voltage corresponding to the working frequency of the second processor core is relatively small, so that the power consumption of the electronic equipment can be reduced.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 shows a schematic diagram of a system architecture provided in an embodiment of the present application.

FIG. 2 shows a flow diagram of a scheduling method of a processor according to one embodiment of the present application.

FIG. 3 shows a flow diagram of a scheduling method of a processor according to another embodiment of the present application.

FIG. 4 is a flow diagram illustrating a method for scheduling a processor according to yet another embodiment of the present application.

FIG. 5 is a flow diagram illustrating a scheduling method of a processor according to yet another embodiment of the present application.

FIG. 6 is a flow diagram illustrating a scheduling method of a processor according to yet another embodiment of the present application.

FIG. 7 shows a block diagram of a scheduling apparatus of a processor according to an embodiment of the present application.

Fig. 8 is a block diagram of an electronic device for executing a scheduling method of a processor according to an embodiment of the present application.

Fig. 9 is a memory unit for storing or carrying program codes implementing a scheduling method of a processor according to an embodiment of the present application.

Detailed Description

In order to make the technical solutions better understood by those skilled in the art, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application.

With the rapid development of mobile internet technology, electronic devices (such as smart phones, tablet computers, and the like) cover aspects of life. Also, users are increasingly demanding on the performance of electronic devices, and thus electronic devices with multi-core processors are emerging. The multi-core processor refers to a processor including a plurality of processor cores, but the processor adopts a multi-core architecture, and the power consumption of the electronic device is also increased, so that a BIG-Little processor architecture appears. The processor architecture of the BIG-LITTLE is used for allocating proper processor cores for proper operation, and therefore power consumption of the electronic equipment is reduced.

Furthermore, since different processor cores need to use a power module for power supply and voltage control, some manufacturers divide the different processor cores into the same power domain (power domain) based on cost considerations. For the processor cores in the same power domain, the same independent voltage power supply and the same independent voltage module can be adopted to carry out unified power supply and unified voltage control on the processor cores, so that the number of the power supply modules can be saved, and the cost is saved. In particular, for a processor architecture employing a very large core, a large core and a small core, the very large core and the large core may share one power domain.

In the related art, processor cores of different processing capabilities are assigned to the same power domain. In particular, for a processor architecture employing a very large core, a large core and a small core, the very large core and the large core may share one power domain.

The inventor has studied for a long time and found that in some scenes, a processor core with relatively strong processing capability enters an idle state (idle state) at a relatively high frequency, and at the moment, because the processor core with relatively strong processing capability and the processor core with relatively weak processing capability share one power domain, if the processor core with relatively weak processing capability is in a working state and the processor core with relatively weak processing capability is in a low frequency point, the voltage corresponding to the low frequency point selected by the processor core with relatively weak processing capability is lower than the voltage corresponding to the high frequency selected by the processor core with relatively strong processing capability. At this time, a relatively high voltage is used for power supply, but the processor core with a relatively high processing capability is in an idle state and does not need a processing task, so that power consumption is increased. For example, in a scenario where the super-large core and the large core share one power domain, when a webpage loads a scenario, the super-large core is enabled due to a heavy load of the processor, and the operating frequency of the super-large core is high; when the load is not large in the loading process, the super-large core enters an idle state (at the moment, the frequency of the super-large core is still high frequency), and other tasks are executed for the small core or the large core; after the super core enters an idle state at a high frequency, because the current load is not large, the scheduler triggers frequency modulation and tries to enter a low frequency point, if the voltage corresponding to the low frequency point selected by the super core is lower than the voltage corresponding to the high frequency of the super core, the high voltage corresponding to the high frequency of the super core is kept during hardware voting, and therefore power consumption is increased.

In view of the above problems, the inventor provides a scheduling method and apparatus for a processor, an electronic device, and a storage medium, which can implement that when a first processor core and a second processor core share one power domain, when the first processor core enters an idle state, power can be supplied by a voltage corresponding to an operating frequency of the second processor core in an operating state, and since the voltage corresponding to the operating frequency of the second processor core is relatively small, power consumption of the electronic device can be reduced. The specific scheduling method of the processor is described in detail in the following embodiments.

The following first introduces a system architecture of an electronic device to which the scheduling method of a processor provided in the embodiment of the present application is applied.

Referring to fig. 1, an electronic device may include the system architecture 10 shown in fig. 1. System architecture 10 may include, among other things, an operating system 20, a processor 110, and a plurality of power domains (e.g., a first power domain 141 and a second power domain 142 shown in fig. 1). The processor 110 may include multiple processor cores, such as a first processor core 111, a second processor core 112, a third processor core 113, and a fourth processor core 114 shown in FIG. 1.

In some embodiments, the plurality of processor cores of the processor 110 may be divided into a plurality of power domains according to a physical hardware structure, and each power domain includes at least two processor cores, so that the number of power modules may be reduced, and the cost may be reduced. For example, in the system architecture shown in fig. 1, the first processor core 111 and the second processor core 112 may be divided into a first power domain 141, and the third processor core 113 and the fourth processor core 114 may be divided into a second power domain 142.

The power domain refers to a region allowing unified power supply and unified voltage control, and the same power domain can adopt independent power modules to supply power and control voltage to the processor core. One or more power domains (only two shown in fig. 1) may be included in system architecture 10. Of course, for a processor core located in the same power domain, devices associated with the processor core may also be powered and voltage controlled by the power domain. The device associated with the processor core may be a cache, a memory controller, etc., and is not limited herein.

Scheduler 11 may be a computer program running in operating system 200 for performing task scheduling. The operating system 20 may interact with the front-end application 12, and the front-end application 12 may generate one or more processing tasks (e.g., processing task 1 to processing task n shown in fig. 1, where n is a positive integer). The scheduler 11 may schedule processing tasks generated by the front-end application 12 to one or more processor cores in the processor 110 for execution by the processor cores. The scheduler 11 may allocate the processing tasks according to the processing tasks generated by the front-end application 12 and the actual load amount of each processor core, thereby reducing the power consumption of the electronic device.

Alternatively, the scheduler 11 may run on any processor core in an active state. Of course, the scheduler 11 may also determine to run its own processor core based on the load condition of the processor core in the working state, and then migrate to the processor core to run, thereby ensuring load balancing among the processor cores; a processor core or other hardware (e.g., an application specific integrated circuit, a programmable logic device, etc.) dedicated to running the scheduler 11 may also be provided to increase the running speed of the scheduler 11.

In the embodiment of the present application, the processor cores located in the same power domain may include processor cores with different processing capabilities. In the following embodiments, the first processor core 111 and the second processor core 112 share a power domain, and the processing capabilities of the first processor core 111 and the second processor core 112 are different. Illustratively, the processor 110 may include four 2.04GHz AMD a55 processor cores, three 2.54GHz AMD a77 processor cores, and one 3.13GHz AMD a77 processor core, wherein the 3.13GHz AMD a77 processor core may be an extra core, the 2.54GHz AMD a77 processor core may be a big core, the 2.04GHz AMD a55 processor core may be a little core, the processing capabilities of the extra core, the big core, and the little core are sequentially reduced, and the extra core shares one power domain with all the big cores.

It should be noted that the system architecture 10 shown in fig. 1 is described by way of example as including one processor 300, and in practical applications, may include a plurality of processors. It should be understood that the system architecture shown in fig. 1 is only an example, and more or fewer devices or software modules and the like may also be included in the system architecture 10 of the electronic device, for example, more processors or processor cores and the like may be included in the system architecture 10 shown in fig. 1, and the invention is not limited thereto.

Embodiments of a scheduling method for a processor provided in the present application are described in detail below with reference to the accompanying drawings.

Referring to fig. 2, fig. 2 is a flowchart illustrating a scheduling method for a processor according to an embodiment of the present application. In a specific embodiment, the scheduling method of the processor is applied to the electronic device, and a specific flow of this embodiment will be described below by taking the electronic device as an example. Certainly, it can be understood that the electronic device applied in this embodiment may be a smart phone, a tablet computer, a smart watch, smart glasses, a notebook computer, and the like, which is not limited herein. As will be described in detail with respect to the flow shown in fig. 2, the scheduling method of the processor may specifically include the following steps:

step S110: and if the first processor core meets the condition corresponding to the idle state and the second processor core is in the working state, acquiring the current working frequency of the first processor core as the first frequency.

In the embodiment of the application, when one power domain includes processor cores with different processing capabilities, if the processor core with relatively higher processing capability enters an idle state at a higher frequency, and the voltage corresponding to the operating frequency of the processor core with relatively lower processing capability is lower than the voltage corresponding to the operating frequency of the processor core with relatively higher processing capability, the power domain supplies power at the voltage corresponding to the operating frequency of the processor core with relatively higher processing capability, so that the power consumption of the electronic device is increased. Therefore, in the case that one power domain in the electronic device includes the first processor core and the second processor core, and the processing capability of the first processor core is relatively higher than that of the second processor core, it may be determined whether the first processor core satisfies the condition corresponding to the idle state to determine whether the above-mentioned condition of increasing power consumption may occur. And when the first processor core meets the condition corresponding to the idle state and the second processor core is in the working state, the working frequencies of the first processor core and the second processor core can be acquired to determine whether the condition of increasing the power consumption is met. The operating frequency of the first processor core may be obtained, and the operating frequency of the first processor core may be used as the first frequency. The processing capability refers to a processing speed when the processor cores obtain the same processing effect for the same processing task, that is, when the first processor core and the second processor core process the same task, the processing task of the first processor core is higher than the processing speed of the second processor core. In addition, the processor core with the stronger processing capability can also process more complex processing tasks, that is, the first processor core can process more complex processing tasks in the first processor core and the second processor core.

In some embodiments, obtaining the operating frequency of the first processor core and the second processor core may be performed in the case where it is determined that the first processor core enters the idle state and the second processor core is in the operating state to determine whether the above-described condition of increasing power consumption is met. Alternatively, the state of the processor cores may be monitored by the scheduler in real time, and if the first processor core enters an idle state and the second processor core is in an operating state, the above-mentioned situation of increasing power consumption may occur, so that the subsequent step may be performed, that is, the operating frequencies of the two processor cores are obtained.

In other embodiments, obtaining the operating frequencies of the first processor core and the second processor core may also be performed when the first processor core is going to enter an idle state and the second processor core is in an operating state to determine whether the above-mentioned condition of increasing power consumption is met. Optionally, the working state of the processor core is scheduled by the scheduler, that is, the scheduler determines the processor core to be operated according to the generated processing task and controls the working frequency of the processor core, so that when the scheduler determines that the first processor core needs to be controlled to enter the idle state, it may be determined that the first processor core is about to enter the idle state and the second processor core is in the working state.

In some embodiments, a correspondence between processor cores and power domains may be stored. That is, the processor cores divided into the same power domain in the electronic device may determine that the first processor core and the second processor core are in the same power domain based on the correspondence, and further execute the process of the scheduling method of the processor provided in the embodiment of the present application.

In some embodiments, the first processor core enters the idle state, which may be that the scheduler controls the first processor core to enter the idle state when determining that the current load is lower than the first load threshold, so that the first processor core with stronger processing capability but higher power consumption sleeps, thereby reducing the power consumption of the electronic device. In this case, the scheduler may control the second processor core to be still in the operating state, because the processing task that requires the second processor core to process still exists in the electronic device. For example, the first processor core may be the above-mentioned example very large core, the second processor core may be the above-mentioned example very large core, and both of them share one power domain, and in an application scenario with a high load, the scheduler may enable the very large core and adjust it to a high operating frequency, and in an application scenario exiting the application scenario, due to a low load, may control the very large core to perform an idle state.

Step S120: and acquiring the working frequency of the second processor core as a second frequency.

In this embodiment, the operating frequency of the second processor core may also be obtained as the second frequency. Alternatively, the operating frequency of the second processor core may be acquired from a frequency management module of the scheduler, and of course, when the operating frequency of the first processor core is acquired, the operating frequency of the first processor core is also acquired from the frequency management module. Of course, the manner of obtaining the operating frequencies of the first processor core and the second processor core may not be limited.

It should be noted that, the order between the obtaining of the operating frequency of the first processor core and the obtaining of the operating frequency of the second processor core may not be limited, and it may first obtain the current operating frequency of the first processor core as the first frequency and then obtain the operating frequency of the second processor core as the second frequency if the first processor core meets the condition corresponding to the idle state and the second processor core is in the operating state; or the working frequency of the second processor core is firstly obtained as the second frequency, and then the working frequency of the current first processor core is obtained as the first frequency; the operating frequency of the first processor core can be simultaneously acquired as the first frequency, and the operating frequency of the second processor core can be simultaneously acquired as the second frequency.

Step S130: if the voltage corresponding to the first frequency is greater than the voltage corresponding to the second frequency, the operating frequency of the first processor core is adjusted to a third frequency, wherein the voltage corresponding to the third frequency is less than the voltage corresponding to the second frequency.

In the embodiment of the application, after the first frequency and the second frequency are obtained, the voltage corresponding to the first frequency of the first processor core and the voltage corresponding to the second frequency of the second processor core can be obtained, and the voltage corresponding to the first frequency and the voltage corresponding to the second frequency are compared; according to the comparison result, whether the voltage corresponding to the first frequency is larger than the voltage corresponding to the second frequency is determined; if the voltage corresponding to the first frequency is greater than the voltage corresponding to the second frequency, the power domains corresponding to the first frequency and the second frequency adopt relatively higher voltage, namely the voltage corresponding to the frequency of the first processor core is used for supplying power, and at the moment, the first processor core meets the condition corresponding to the idle state, and does not need to work, so that the power consumption is increased. Otherwise, if the voltage corresponding to the first frequency is not greater than the voltage corresponding to the second frequency, the adjustment of the operating frequency may not be performed.

In some embodiments, when the operating frequency of the first processor core is adjusted, since the relationship between the required voltage and the operating frequency is generally in positive correlation, the scheduler may decrease the operating frequency of the first processor core, so that the voltage corresponding to the decreased third frequency is not greater than the voltage corresponding to the second frequency of the second processor core. Optionally, the operating frequency of the first processor core may be adjusted to a lowest frequency point, that is, the third frequency is the lowest frequency point.

In a possible embodiment, after determining the third frequency to which the first processor core needs to be adjusted, the scheduler may send, to the hardware frequency conversion module, a frequency modulation request for adjusting the operating frequency to the third frequency through Cpufreq, and accordingly, the hardware frequency conversion module adjusts the operating frequency of the first processor core to the third frequency based on the frequency modulation request. Cpufreq is a driver for dynamic voltage and frequency modulation (DVFS), and the scheduler may adjust the operating frequency of the processor core through the driver.

In some embodiments, the correspondence between different operating frequencies and required voltages is different due to different configurations of different processor cores. Therefore, the correspondence between the voltage and the operating frequency of the first processor core and the correspondence between the voltage and the operating frequency of the second processor core may be stored, and then, based on the stored correspondence, the voltage corresponding to the first frequency of the first processor core and the voltage corresponding to the second frequency of the second processor core may be acquired.

It should be noted that, in the embodiment of the present application, in the power domain shared by the first processor core and the second processor core, the number of the first processor core and the second processor core may not be limited, that is, it may be understood that the power domain includes two types of processor cores. When the number of the first processor cores is multiple and the second processor core is single, for example, the power domain includes multiple large cores and one small core, the process is executed when all the first processor cores meet the condition corresponding to the idle state and the second processor core is in the working state; when the first processor core is single and the second processor cores are multiple, for example, the power domain comprises a super core and the power domain comprises multiple large cores, when the voltage corresponding to the first frequency is greater than the voltage corresponding to the working frequency of each second processor core in a working state, the working frequency of the first processor core is adjusted to be a third frequency; when the number of the first processor cores and the number of the second processor cores are multiple, the process is executed when all the first processor cores meet the condition corresponding to the idle state and the second processor cores are in the working state, and when the voltage corresponding to the working frequency of any one first processor core is greater than the voltage corresponding to the working frequency of all the second processor cores in the working state, the working frequency of the first processor cores is adjusted to be the third frequency.

Optionally, the scheduling method of the processor provided in the embodiment of the present application may be executed by a scheduler, and the scheduler may be run in any processor core in a working state, or a specially configured hardware device.

The scheduling method of the processor provided by the embodiment of the application can realize that the first processor core and the second processor core share one power domain, thereby reducing the number of power modules and lowering the cost. And when the first processor core with relatively strong processing capacity enters an idle state, the voltage corresponding to the working frequency of the second processor core in the working state can be used for supplying power, and the voltage corresponding to the working frequency of the second processor core is relatively small, so that the power consumption of the electronic equipment can be reduced.

Referring to fig. 3, fig. 3 is a flowchart illustrating a scheduling method for a processor according to another embodiment of the present application. The scheduling method of the processor is applied to the electronic device, and will be described in detail with respect to the flow shown in fig. 3, where the scheduling method of the processor may specifically include the following steps:

step S210: and if the first processor core is in a working state, acquiring the probability that the first processor core enters an idle state from the working state as a first probability.

In this embodiment of the application, when the first processor core is in an operating state and is about to enter an idle state, and the second processor core is in an operating state, the operating frequencies of the first processor core and the second processor core may be obtained to determine whether the operating frequencies of the first processor core and the second processor core satisfy the above-mentioned power consumption increase condition. Specifically, when the processor core is in the operating state, the probability that the first processor core enters the idle state from the operating state may be obtained as the first probability. The probability that the first processor core enters the idle state from the working state represents the possibility that the first processor core currently enters the idle state, and the higher the probability, the more likely it is to enter the idle state.

In some embodiments, obtaining, as the first probability, a probability that the first processor core enters the idle state from the operating state may include: acquiring a task queue of the processor; and determining the probability of the first processor core entering an idle state from a working state as a first probability based on the processing tasks corresponding to the first processor core in the task queue, wherein the probability is in negative correlation with the number of the processing tasks. It can be understood that, the more processing tasks corresponding to the first processor core, the more tasks that need to be processed currently, and therefore the less likely it will enter the idle state, and therefore the lower the above probability; conversely, the more processing tasks corresponding to the first processor core, the higher the possibility that the processing tasks enter the idle state, so the number of processing tasks corresponding to the first processor core in the task queue can be obtained to determine the probability. Alternatively, the above probability may be determined to be 100% when the number of processing tasks of the first processor core is 0.

In other embodiments, the load of the processor may also be obtained to determine the probability according to the load of the processor. The load amount may be obtained by a task load tracking (pel) module in the device. Alternatively, the load of the processor may be described by the utilization rate of the processor, for example, the value for describing the load of the processor may be a value of the utilization rate of the processor core.

In a possible implementation manner, when the processor of the electronic device includes a super core, a large core, and a small core, the super core is the first processor core, and the large core is the second processor core, in this case, when the super core is required to process a task, generally when the load of the processor is high, that is, when there are many processing tasks, the super core is enabled, so as to optimize the power consumption of the electronic device. Therefore, in this case, the load amount of the processor may be acquired to determine the probability that the first processor core enters the idle state according to the load amount of the processor.

Optionally, it may be determined whether a load amount of the processor is smaller than a second load amount threshold, where the second load amount threshold is a determination basis for determining whether the first processor core is to be adjusted to the idle state, and if the load amount of the processor is smaller than the second load amount threshold, the probability may be determined to be 100%, and otherwise, the probability may be determined to be 0%.

Optionally, it may be determined whether a load amount of the processor is smaller than a second load amount threshold, where the second load amount threshold is a determination criterion for determining whether the first processor core is to be adjusted to the idle state, and if the load amount of the processor is smaller than the second load amount threshold, the probability may be determined to be 100%; if the load capacity of the processor is not less than the second load capacity threshold, further determining whether the load capacity of the processor is less than a third load capacity threshold, wherein the third load capacity threshold is greater than the second load capacity threshold and is used as a determination basis for entering a state to be adjusted to an idle state; if the load amount is smaller than the third load amount threshold, the change trend of the load amount of the processor may be further obtained according to the data of the load amount within the preset time period before the current time, and when the change trend is a decreasing trend, the probability is determined based on the decreasing amplitude, of course, the determined probability should be smaller than 100% under the condition that the load amount of the processor is not smaller than the second load amount threshold, and in addition, the determined probability is positively correlated with the decreasing amplitude, for example, in a direct ratio, and the like. If the amount of load of the processor is not less than the third load amount threshold, it indicates that there is no possibility that the processor is currently about to adjust to the idle state, and thus the above probability is determined to be 0.

Of course, the specific manner of obtaining the probability that the first processor core enters the idle state from the operating state may not be limited.

Step S220: and if the first probability is greater than a first preset probability and the second processor core is in a working state, acquiring the current working frequency of the first processor core as a first frequency.

In the embodiment of the present application, after the first probability is obtained, the first probability may be compared with a first preset probability, where the first preset probability is used as a criterion for determining whether the first processor core enters the idle state from the operating state; according to the comparison result, if the first probability is determined to be greater than the first preset probability, the first processor core is indicated to enter an idle state from a working state, so that the acquired process can be executed, and the working frequency of the first processor core is adjusted to reduce the power consumption when the condition that the power consumption is increased is met; otherwise, if it is determined that the first probability is not greater than the first preset probability, the subsequent process may not be executed. The specific value of the first preset probability may not be limited, for example, the first preset probability may be 90%,95%, or the like.

Step S230: and acquiring the working frequency of the second processor core as a second frequency.

Step S240: if the voltage corresponding to the first frequency is greater than the voltage corresponding to the second frequency, the operating frequency of the first processor core is adjusted to a third frequency, wherein the voltage corresponding to the third frequency is less than the voltage corresponding to the second frequency.

In the embodiment of the present application, step S230 and step S240 may refer to contents of other embodiments, which are not described herein again.

Step S250: and determining the power supply voltage corresponding to the power domain as the voltage corresponding to the second frequency based on the voltage corresponding to the third frequency and the voltage corresponding to the second frequency.

In this embodiment of the application, after the operating frequency of the first processor core is adjusted to be the third frequency, the voltage corresponding to the third frequency is smaller than the voltage corresponding to the second frequency, and then the power supply voltage corresponding to the power domain is determined to be the voltage corresponding to the second frequency based on the voltage corresponding to the third frequency and the voltage corresponding to the second frequency. That is, a relatively high voltage, that is, a voltage of the second frequency is determined as the power supply voltage from the voltage corresponding to the third frequency and the voltage corresponding to the second frequency.

Step S260: and adjusting the power supply voltage of the power domain to a voltage corresponding to the second frequency.

In the embodiment of the application, after it is determined that the power supply voltage of the power domain is the voltage corresponding to the second frequency, the power supply voltage of the power domain may be adjusted to be the voltage corresponding to the second frequency, so that it is avoided that the power domain still uses the relatively high voltage for power supply when the first processor core enters the idle state from the relatively high frequency of the voltage, and the increase of power consumption is also avoided.

It should be noted that steps S250 and S260 may also be used in other embodiments, that is, after the operating frequency of the first processor core is adjusted to the third frequency in other embodiments, the processes of steps S250 and S260 may also be executed.

According to the scheduling method of the processor provided by the embodiment of the application, when the first processor core is in the working state, the probability that the first processor core enters the idle state from the working state is obtained as the first probability, and when the first probability is greater than the first preset probability and the second processor core is in the working state, the current working frequency of the first processor core is obtained as the first frequency, the current working frequency of the second processor core is obtained as the second frequency, and if the voltage corresponding to the first frequency is greater than the voltage corresponding to the second frequency, the working frequency of the first processor core is adjusted to the third frequency, wherein the voltage corresponding to the third frequency is less than the voltage corresponding to the second frequency. Therefore, under the condition that the first processor core and the second processor core share one power domain, when the first processor core is about to enter an idle state, the power can be supplied by the voltage corresponding to the working frequency of the second processor core in the working state, and the power consumption of the electronic equipment can be reduced because the voltage corresponding to the working frequency of the second processor core is relatively small.

Referring to fig. 4, fig. 4 is a schematic flowchart illustrating a scheduling method for a processor according to another embodiment of the present application. The scheduling method of the processor is applied to the electronic device, and will be described in detail with respect to the flow shown in fig. 4, where the scheduling method of the processor may specifically include the following steps:

step S310: and if the first processor core enters an idle state and the second processor core is in a working state, acquiring the current working frequency of the first processor core as a first frequency.

Different from the previous embodiment, in the embodiment of the present application, after the first processor core enters the idle state in the operating state, and when the second processor core is in the operating state, the operating frequencies of the first processor core and the second processor core may be obtained to determine whether the operating frequencies of the first processor core and the second processor core meet the condition of the power consumption increase.

In some embodiments, since the operating state of the processor cores is scheduled by the scheduler, that is, the scheduler determines the processor cores that need to operate according to the generated processing tasks and controls the operating frequency of the processor cores, when the scheduler controls the first processor core to enter the idle state, it may be determined that the first processor core enters the idle state, and the scheduler may acquire that the second processor core is in the operating state.

Step S320: and acquiring the working frequency of the second processor core as a second frequency.

Step S330: if the voltage corresponding to the first frequency is greater than the voltage corresponding to the second frequency, the operating frequency of the first processor core is adjusted to a third frequency, wherein the voltage corresponding to the third frequency is less than the voltage corresponding to the second frequency.

In the embodiment of the present application, step S320 and step S330 may refer to contents of other embodiments, which are not described herein again.

The scheduling method of the processor provided by the embodiment of the application can realize that the first processor core and the second processor core can supply power with the voltage corresponding to the working frequency of the second processor core in the working state after the first processor core enters the idle state under the condition that the first processor core and the second processor core share one power domain, and can reduce the power consumption of the electronic equipment because the voltage corresponding to the working frequency of the second processor core is relatively small

Referring to fig. 5, fig. 5 is a flowchart illustrating a scheduling method for a processor according to still another embodiment of the present application. The scheduling method of the processor is applied to the electronic device, and will be described in detail with respect to the flow shown in fig. 5, where the scheduling method of the processor may specifically include the following steps:

step S410: and if the first processor core meets the condition corresponding to the idle state and the second processor core is in the working state, acquiring the current working frequency of the first processor core as the first frequency.

Step S420: and acquiring the working frequency of the second processor core as a second frequency.

Step S430: if the voltage corresponding to the first frequency is greater than the voltage corresponding to the second frequency, the operating frequency of the first processor core is adjusted to a third frequency, wherein the voltage corresponding to the third frequency is less than the voltage corresponding to the second frequency.

In the embodiment of the present application, steps S410 to S430 may refer to the contents of the foregoing embodiments, and are not described herein again.

Step S440: and if the first processor core meets the condition corresponding to the working state, adjusting the working frequency of the first processor core to the first frequency.

In the embodiment of the application, after the operating frequency of the first processor core is reduced to the third frequency under the condition that the first processor core meets the condition corresponding to the idle state, the second processor core is in the operating state, and the voltage corresponding to the operating frequency of the first processor core is higher than the voltage corresponding to the operating frequency of the second processor core, the operating frequency of the first processor core can be adjusted back to the previous first frequency under the condition that the first processor core meets the condition corresponding to the operating state. It is understood that, after exiting the idle state, the first processor core may need to operate at a higher operating frequency when it is in the operating state, and therefore, it may be adjusted back to the previous first frequency to ensure that the first processor core can smoothly execute the processing task, thereby ensuring performance. For example, when the first processor core is the above-mentioned super core, generally, the operation of the first processor core needs to process a more complex processing task, and a higher operating frequency is used for ensuring the processing effect, so that the super core needs to operate at a higher frequency when entering the idle state and exiting the idle state after entering the idle state at a higher frequency; for another example, the first frequency of the first processor core may be an operating frequency at which it normally operates, and thus may be adjusted back to the previous first frequency after it exits the idle state; for another example, the first processor core may enter the idle state before, where the processing task is suddenly turned off, and needs to continue processing the previous processing task after a period of time, so that after exiting the idle state, the first processor core may be adjusted back to the previous first frequency to ensure normal processing of the processing task.

In some embodiments, after the operating frequency of the first processor core is adjusted to the third frequency under the condition that it is determined that the voltage corresponding to the first frequency is greater than the voltage corresponding to the second frequency, the corresponding relationship between the first processor core and the first frequency may be further stored. Thus, when the first processor core satisfies the condition for operating state correspondence, the operating frequency of the first processor core can be adjusted back to the previous first frequency based on the stored correspondence.

In some embodiments, the adjusting of the operating frequency of the first processor core to the first frequency may be performed when the first processor core is about to enter the operating state from the idle state, so as to adjust the first processor core back to the first frequency in advance, thereby ensuring that the first processor core can understand to run at the first frequency after entering the operating state, so as to process the processing task. The probability that the first processor core enters the working state from the idle state can be obtained as a second probability; and if the second probability is greater than a second preset probability, adjusting the working frequency of the first processor core to the first frequency.

In this embodiment, the probability that the first processor core enters the working state from the idle state indicates the possibility that the first processor core currently enters the working state, and the higher the probability, the more likely it is to enter the working state.

As an embodiment, the load amount of the processor may be obtained to determine the probability according to the load amount of the processor. The load amount may be obtained by a task load tracking (pel) module in the device. Alternatively, the load of the processor may be described by the utilization rate of the processor, for example, the value for describing the load of the processor may be a value of the utilization rate of the processor core. Since the first processor core is a processor core with relatively strong processing capability, when the load of the processor is large, the probability that the first processor core enters the working state is higher, so that the probability can be determined based on the load of the processor, and the probability is in positive correlation with the load of the processor.

In other embodiments, the adjusting of the operating frequency of the first processor core to the first frequency may also be performed when the first processor core enters the operating state, so as to ensure that the first processor core can understand to run at the first frequency after entering the operating state, thereby processing the processing task. Optionally, since the operating state of the processor core is scheduled by the scheduler, that is, the scheduler determines the processor core to be operated according to the generated processing task and controls the operating frequency of the processor core, it may be determined that the first processor core is to enter the operating state when the scheduler controls the first processor core to enter the operating state.

It should be noted that step S440 in this embodiment of the application may also be applied to other embodiments, that is, after the operating frequency of the first processor core is adjusted to the third frequency, the operating frequency of the first processor core may be adjusted to the first frequency when the first processor core meets the condition corresponding to the operating state.

The scheduling method of the processor provided by the embodiment of the application can realize that the first processor core and the second processor core share one power domain, thereby reducing the number of power modules and reducing the cost. And when the first processor core with relatively strong processing capacity enters an idle state, the voltage corresponding to the working frequency of the second processor core in the working state can be used for supplying power, and the voltage corresponding to the working frequency of the second processor core is relatively small, so that the power consumption of the electronic equipment can be reduced. In addition, under the condition that the first processor core exits from the idle state and enters the working state, the working frequency of the first processor core is increased to the first frequency, and therefore the processing performance is guaranteed.

Referring to fig. 6, fig. 6 is a flowchart illustrating a scheduling method for a processor according to yet another embodiment of the present application. The scheduling method of the processor is applied to the electronic device, and will be described in detail with respect to the flow shown in fig. 6, where the scheduling method of the processor may specifically include the following steps:

step S510: and if the first processor core meets the condition corresponding to the idle state and the second processor core is in the working state, acquiring the current working frequency of the first processor core as the first frequency.

In the embodiment of the present application, step S510 may refer to the contents of the foregoing embodiments, and is not described herein again.

Step S520: and when the current load capacity of the second processor core is lower than the preset load capacity, adjusting the working frequency of the second processor to a second frequency.

In the embodiment of the present application, for a first processor core and a second processor core included in the same power domain, and the processing capability of the first processor core is higher than that of the second processor core, in this case, if the first processor core performs an idle state, the second processor core may also lower the operating frequency, possibly because the load of the current processor is reduced. Therefore, the scheduler may acquire a current load amount of the second processor core to determine whether the current load amount is lower than a preset load amount; if the current load capacity is lower than the preset load capacity, the working frequency of the second processor core can be adjusted to the second frequency, so that the working state of the processor core corresponds to the load capacity of the processor core.

Step S530: and acquiring the working frequency of the second processor core as a second frequency.

Step S540: if the voltage corresponding to the first frequency is greater than the voltage corresponding to the second frequency, the operating frequency of the first processor core is adjusted to a third frequency, wherein the voltage corresponding to the third frequency is less than the voltage corresponding to the second frequency.

In the embodiment of the present application, the contents of step S530 and step S540 may refer to the contents of the foregoing embodiments, and are not described herein again.

In some scenarios, the first processor core may be the above-mentioned super core, and the second processor core may be the above-mentioned large core, so that when the super core enters an idle state from a higher frequency, when the large core is adjusted to a lower frequency point at the time, the voltage corresponding to the working frequency of the super core is greater than the voltage corresponding to the working frequency of the large core, and the working frequency of the super core is adjusted, so that power can be supplied with the voltage corresponding to the working frequency of the large core subsequently, and power consumption is reduced.

In some embodiments, the electronic device may further include other power domains, for example, the power domains corresponding to the first processor core and the second processor core are first power domains, and the electronic device further includes a second power domain, a third power domain, and the like; the processor also includes other processor cores, such as a third processor core, a fourth processor core, and so on. The other processor cores may be allocated to other power domains, for example, the third processor core and the fourth processor core may share the second power domain, and when the voltage corresponding to the first frequency is greater than the voltage corresponding to the second frequency, it may also be determined whether the load amount corresponding to the second processor core is less than a fourth load amount threshold; if the load amount corresponding to the second processor core is not less than (greater than or equal to) the fourth load amount threshold, it indicates that the processing tasks corresponding to the current second processor core are more, so that the second processor core can continue to process the tasks according to the second frequency, and the operating frequency of the first processor core is adjusted to the third frequency, thereby reducing the power consumption; if the load amount corresponding to the second processor core is smaller than the fourth load amount threshold, it indicates that the processing tasks corresponding to the current second processor core are fewer, in this case, the processing tasks of the second processor core may be migrated to the processor cores of other power domains, for example, to a third processor core in the second power domain, so that both the first processor core and the second processor core enter an idle state, and at this time, even if the power domains corresponding to the first processor core and the second processor core supply power at a higher voltage, since both the first processor core and the second processor core are in the idle state, greater power consumption is not brought, and task allocation is more reasonable.

The scheduling method of the processor provided by the embodiment of the application can realize that the first processor core and the second processor core share one power domain, thereby reducing the number of power modules and lowering the cost. When the first processor core with relatively strong processing capacity enters an idle state and the working frequency of the second processor core is adjusted, the voltage corresponding to the working frequency of the second processor core in the working state can be used for supplying power, and the voltage corresponding to the working frequency of the second processor core is relatively small, so that the power consumption of the electronic equipment can be reduced.

Referring to fig. 7, a block diagram of a scheduling apparatus 400 for a processor according to an embodiment of the present disclosure is shown. The scheduling apparatus 400 of the processor is applied to the electronic device, and is applied to an electronic device, where a processor of the electronic device includes a first processor core and a second processor core, the first processor core and the second processor core share a power domain, and a processing capability of the first processor core is higher than a processing capability of the second processor core, and the scheduling apparatus 400 of the processor includes: a first frequency acquisition module 410, a second frequency acquisition module 420, and a frequency adjustment module 430. The first frequency obtaining module 410 is configured to obtain a current operating frequency of the first processor core as a first frequency if the first processor core meets a condition corresponding to an idle state and the second processor core is in a working state; the second frequency obtaining module 420 is configured to obtain the operating frequency of the second processor core as a second frequency; the frequency adjustment module 430 is configured to adjust the operating frequency of the first processor core to a third frequency if the voltage corresponding to the first frequency is greater than the voltage corresponding to the second frequency, where the voltage corresponding to the third frequency is less than the voltage corresponding to the second frequency.

In some embodiments, the first frequency acquisition module 410 may be configured to: if the first processor core is in a working state, acquiring the probability that the first processor core enters an idle state from the working state as a first probability; and if the first probability is greater than a first preset probability and the second processor core is in a working state, acquiring the current working frequency of the first processor core as a first frequency.

In a possible implementation manner, the obtaining, by the first frequency obtaining module 410, a probability that the first processor core enters the idle state from the operating state as the first probability may include: acquiring a task queue of the processor; and determining the probability of the first processor core entering an idle state from a working state as a first probability based on the processing tasks corresponding to the first processor core in the task queue, wherein the probability is in negative correlation with the number of the processing tasks.

In some embodiments, the first frequency acquisition module 410 may be configured to: and if the first processor core enters an idle state and the second processor core is in a working state, acquiring the current working frequency of the first processor core as a first frequency.

In some embodiments, the frequency adjustment module 430 may be further configured to, after the operating frequency of the first processor core is adjusted to a third frequency if the voltage corresponding to the first frequency is greater than the voltage corresponding to the second frequency, adjust the operating frequency of the first processor core to the first frequency if the first processor core meets a condition corresponding to an operating state.

In one possible implementation, the frequency adjustment module 430 may be further configured to: acquiring the probability of the first processor core entering a working state from an idle state as a second probability; and if the second probability is greater than a second preset probability, adjusting the working frequency of the first processor core to the first frequency.

In one possible implementation, the frequency adjustment module 430 may be further configured to: and if the first processor core enters a working state from an idle state, adjusting the working frequency of the first processor core to the first frequency.

In a possible implementation, the scheduling apparatus 400 of the processor may further include: and a frequency storage module. The frequency storage module may be to: and after the working frequency of the first processor core is adjusted to a third frequency if the voltage corresponding to the first frequency is greater than the voltage corresponding to the second frequency, storing the corresponding relation between the first processor core and the first frequency. The frequency adjustment module 430 may be configured to: and if the first processor core meets the condition corresponding to the working state, adjusting the working frequency of the first processor core to the first frequency based on the corresponding relation.

In some embodiments, the frequency adjustment module 430 may further be configured to, before the obtaining of the operating frequency of the second processor core as the second frequency, adjust the operating frequency of the second processor to the second frequency when the current load amount of the second processor core is lower than a preset load amount.

In some embodiments, the scheduling apparatus 400 of the processor may further include: the device comprises a power supply determining module and a voltage adjusting module. The power supply determining module is configured to determine, based on the voltage corresponding to the third frequency and the voltage corresponding to the second frequency, that the power supply voltage corresponding to the power domain is the voltage corresponding to the second frequency after the operating frequency of the first processor core is adjusted to the third frequency if the voltage corresponding to the first frequency is greater than the voltage corresponding to the second frequency; the voltage adjusting module is used for adjusting the power supply voltage of the power domain to a voltage corresponding to the second frequency.

It can be clearly understood by those skilled in the art that, for convenience and simplicity of description, the specific working processes of the above-described devices and modules may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.

In the several embodiments provided in the present application, the coupling between the modules may be electrical, mechanical or other type of coupling.

In addition, functional modules in the embodiments of the present application may be integrated into one processing module, or each of the modules may exist alone physically, or two or more modules are integrated into one module. The integrated module can be realized in a hardware mode, and can also be realized in a software functional module mode.

To sum up, in the solution provided by the present application, a processor of an electronic device includes a first processor core and a second processor core sharing a power domain, and a processing capability of the first processor core is higher than a processing capability of the second processor core, and when the first processor core meets a condition corresponding to an idle state and the second processor core is in a working state, a working frequency of the current first processor core is obtained as a first frequency, a working frequency of the second processor core is obtained as a second frequency, and if a voltage corresponding to the first frequency is greater than a voltage corresponding to the second frequency, the working frequency of the first processor core is adjusted to a third frequency, where the voltage corresponding to the third frequency is less than the voltage corresponding to the second frequency. Therefore, under the condition that the first processor core and the second processor core share one power domain, when the first processor core enters an idle state, the first processor core can supply power with the voltage corresponding to the working frequency of the second processor core in the working state, and the voltage corresponding to the working frequency of the second processor core is relatively small, so that the power consumption of the electronic equipment can be reduced.

Referring to fig. 8, a block diagram of an electronic device according to an embodiment of the present disclosure is shown. The electronic device 100 may be an electronic device capable of running an application, such as a smart phone, a tablet computer, a smart watch, smart glasses, and a notebook computer. The electronic device 100 in the present application may include one or more of the following components: a processor 110, a memory 120, and one or more applications, wherein the one or more applications may be stored in the memory 120 and configured to be executed by the one or more processors 110, the one or more programs configured to perform a method as described in the aforementioned method embodiments.

Processor 110 may include multiple processor cores. The processor 110 connects various parts within the overall electronic device 100 using various interfaces and lines, and performs various functions of the electronic device 100 and processes data by executing or executing instructions, programs, code sets, or instruction sets stored in the memory 120 and calling data stored in the memory 120. The plurality of processor cores may include at least a first processor core and a second processor core, the first processor core and the second processor core share a power domain, and a processing capability of the first processor core is higher than a processing capability of the second processor core.

Alternatively, the processor 110 may be implemented in hardware using at least one of Digital Signal Processing (DSP), field-Programmable Gate Array (FPGA), and Programmable Logic Array (PLA). The processor 110 may integrate one or more of a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), a modem, and the like. Wherein, the CPU mainly processes an operating system, a user interface, an application program and the like; the GPU is used for rendering and drawing display content; the modem is used to handle wireless communications. It is understood that the modem may not be integrated into the processor 110, but may be implemented by a communication chip.

The Memory 120 may include a Random Access Memory (RAM) or a Read-Only Memory (Read-Only Memory). The memory 120 may be used to store instructions, programs, code, sets of codes, or sets of instructions. The memory 120 may include a stored program area and a stored data area, wherein the stored program area may store instructions for implementing an operating system, instructions for implementing at least one function (such as a touch function, a sound playing function, an image playing function, etc.), instructions for implementing various method embodiments described below, and the like. The data storage area may also store data created by the electronic device 100 during use (e.g., phone book, audio-video data, chat log data), and the like.

Referring to fig. 9, a block diagram of a computer-readable storage medium according to an embodiment of the present application is shown. The computer-readable medium 800 has stored therein a program code that can be called by a processor to execute the method described in the above-described method embodiments.

The computer-readable storage medium 800 may be an electronic memory such as a flash memory, an EEPROM (electrically erasable programmable read only memory), an EPROM, a hard disk, or a ROM. Alternatively, the computer-readable storage medium 800 includes a non-volatile computer-readable storage medium. The computer readable storage medium 800 has storage space for program code 810 to perform any of the method steps of the method described above. The program code can be read from or written to one or more computer program products. The program code 810 may be compressed, for example, in a suitable form.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit the same; although the present application has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not necessarily depart from the spirit and scope of the corresponding technical solutions in the embodiments of the present application.

Claims

1. A scheduling method of a processor is applied to an electronic device, wherein the processor of the electronic device includes a first processor core and a second processor core, the first processor core and the second processor core share a power domain, and a processing capability of the first processor core is higher than a processing capability of the second processor core, and the method includes:

if the first processor core meets the condition corresponding to the idle state and the second processor core is in the working state, acquiring the working frequency of the current first processor core as a first frequency;

acquiring the working frequency of the second processor core as a second frequency;

if the voltage corresponding to the first frequency is greater than the voltage corresponding to the second frequency, the operating frequency of the first processor core is adjusted to a third frequency, wherein the voltage corresponding to the third frequency is less than the voltage corresponding to the second frequency.

2. The method of claim 1, wherein the obtaining the current operating frequency of the first processor core as the first frequency if the first processor core meets the condition corresponding to the idle state and the second processor core is in the operating state comprises:

if the first processor core is in a working state, acquiring the probability that the first processor core enters an idle state from the working state as a first probability;

and if the first probability is greater than a first preset probability and the second processor core is in a working state, acquiring the current working frequency of the first processor core as a first frequency.

3. The method of claim 2, wherein obtaining, as the first probability, the probability that the first processor core enters the idle state from the operating state comprises:

acquiring a task queue of the processor;

and determining the probability of the first processor core entering an idle state from a working state as a first probability based on the processing tasks corresponding to the first processor core in the task queue, wherein the probability is in negative correlation with the number of the processing tasks.

4. The method of claim 1, wherein the obtaining the current operating frequency of the first processor core as the first frequency if the first processor core meets the condition corresponding to the idle state and the second processor core is in the operating state comprises:

and if the first processor core enters an idle state and the second processor core is in a working state, acquiring the current working frequency of the first processor core as a first frequency.

5. The method of claim 1, wherein after the adjusting the operating frequency of the first processor core to a third frequency if the voltage corresponding to the first frequency is greater than the voltage corresponding to the second frequency, the method further comprises:

and if the first processor core meets the condition corresponding to the working state, adjusting the working frequency of the first processor core to the first frequency.

6. The method of claim 5, wherein the adjusting the operating frequency of the first processor core to the first frequency if the first processor core meets the condition corresponding to the operating state comprises:

acquiring the probability of the first processor core entering a working state from an idle state as a second probability;

and if the second probability is greater than a second preset probability, adjusting the working frequency of the first processor core to the first frequency.

7. The method of claim 5, wherein the adjusting the operating frequency of the first processor core to the first frequency if the first processor core meets the condition corresponding to the operating state comprises:

and if the first processor core enters a working state from an idle state, adjusting the working frequency of the first processor core to the first frequency.

8. The method of claim 5, wherein after the adjusting the operating frequency of the first processor core to a third frequency if the voltage corresponding to the first frequency is greater than the voltage corresponding to the second frequency, the method further comprises:

storing the corresponding relation between the first processor core and the first frequency;

if the first processor core meets the condition corresponding to the working state, the adjusting the working frequency of the first processor core to the first frequency comprises the following steps:

and if the first processor core meets the condition corresponding to the working state, adjusting the working frequency of the first processor core to the first frequency based on the corresponding relation.

9. The method of any of claims 1-8, wherein prior to the obtaining the operating frequency of the second processor core as the second frequency, the method further comprises:

and when the current load capacity of the second processor core is lower than a preset load capacity, adjusting the working frequency of the second processor to the second frequency.

10. The method of any of claims 1-8, wherein after the adjusting the operating frequency of the first processor core to a third frequency if the voltage corresponding to the first frequency is greater than the voltage corresponding to the second frequency, the method further comprises:

determining the power supply voltage corresponding to the power domain as the voltage corresponding to the second frequency based on the voltage corresponding to the third frequency and the voltage corresponding to the second frequency;

and adjusting the power supply voltage of the power domain to be the voltage corresponding to the second frequency.

11. A scheduling apparatus of a processor, applied to an electronic device, where the processor of the electronic device includes a first processor core and a second processor core, the first processor core and the second processor core share a power domain, and a processing capability of the first processor core is higher than a processing capability of the second processor core, the apparatus includes: a first frequency acquisition module, a second frequency acquisition module, and a frequency adjustment module, wherein,

the first frequency obtaining module is used for obtaining the current working frequency of the first processor core as a first frequency if the first processor core meets the condition corresponding to the idle state and the second processor core is in the working state;

the second frequency acquisition module is used for acquiring the working frequency of the second processor core as a second frequency;

the frequency adjustment module is configured to adjust the operating frequency of the first processor core to a third frequency if the voltage corresponding to the first frequency is greater than the voltage corresponding to the second frequency, where the voltage corresponding to the third frequency is less than the voltage corresponding to the second frequency.

12. An electronic device, comprising:

one or more processors comprising a first processor core and a second processor core;

a memory;

one or more applications, wherein the one or more applications are stored in the memory and configured to be executed by the one or more processors, the one or more programs configured to perform the method of any of claims 1-10.

13. A computer-readable storage medium, having stored thereon program code that can be invoked by a processor to perform the method according to any one of claims 1 to 10.