CN115708199A - Chip packaging structure, chip packaging system and method for forming chip packaging structure - Google Patents

Chip packaging structure, chip packaging system and method for forming chip packaging structure Download PDF

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Publication number
CN115708199A
CN115708199A CN202210991340.XA CN202210991340A CN115708199A CN 115708199 A CN115708199 A CN 115708199A CN 202210991340 A CN202210991340 A CN 202210991340A CN 115708199 A CN115708199 A CN 115708199A
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chip
adhesion promoter
thermal interface
structure according
packaging structure
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Inventor
简振威
M·迈耶
E·里德尔
E·福尔古特
H·W·萨斯
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Infineon Technologies AG
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Infineon Technologies AG
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3672—Foil-like cooling fins or heat sinks
    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3737—Organic materials with or without a thermoconductive filler
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
    • H01L23/4334—Auxiliary members in encapsulations
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49562—Geometry of the lead-frame for devices being provided for in H01L29/00
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29186—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83399—Material
    • H01L2224/834—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83399—Material
    • H01L2224/8349—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/46—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids

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  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

A chip package structure, a chip package system and a method of forming a chip package structure. A chip packaging structure is provided. The chip package may include a chip, an encapsulant material, and exposed pads conductively connected to the chip, a porous or dendrite adhesion promoter-containing layer on a surface of the exposed pads, and a thermal interface material attached to the exposed pads through the layer.

Description

Chip packaging structure, chip packaging system and method for forming chip packaging structure
Technical Field
Various embodiments relate generally to chip package structures and to methods of forming chip package structures.
Background
The chip package may be coupled to a heat sink (heat sink) through a Thermal Interface Material (TIM). In many cases, the thermal interface material may have a Coefficient of Thermal Expansion (CTE) that does not match well with the CTE of the exposed metal and/or polymer of the chip package. The cause of the mismatch may be a polymer matrix (e.g., silicone) such as TIM (e.g., silicone has a very high CTE), and/or filler particles/materials may be included in the polymer matrix, and which may correspond to, for example, 85-95 wt% of the thermal interface material.
The thermo-mechanical stress resulting from the CTE mismatch may lead to delamination (delaminations) between the interfaces. In particular, the adhesion of TIM materials to cured epoxy materials that release (desorb) wax can be critical. Delamination may lead to thermal resistance R th Which may cause the device to overheat. Furthermore, delamination may lead to electrical failures in some cases. Some devices (e.g., discrete power packages, power modules, smart power modules) are not allowed to be layered for creepage (creepage) compliance.
Advanced heat transport may be required in order to keep the chip at a reasonable operating temperature even in high power modules, but at the same time, improved isolation may be necessary.
Fig. 5A shows a prior art example of providing a chip package structure 500 with such properties by having a stack 512, 550, 552 of thermal interface material, such as aluminum 512, and e.g. epoxy (epoxy) films 550, 552 between the chip and the external package surface, wherein the first epoxy film 550 may be a fully cured epoxy film (also referred to as C-stage) and the second epoxy film 552 may be only partially cured (also referred to as B-stage), which may be useful for softening the second epoxy film 552 and attaching the chip 104 and/or leadframe 560 to the softened epoxy film 552.
However, as shown in fig. 5B, which illustrates the chip package structure 500 of fig. 5A, a problem that may arise is that, in particular, the large chip package structure 500 may be subjected to high stresses within the package structure 500, which may cause undesirable delamination (indicated by thick bars and arrows) between the various layers of the encapsulation material 562 (e.g., mold compound, EMC) and TIM stack (aluminum plate 512, epoxy sheets 552, 554).
Disclosure of Invention
A chip package structure is provided. The chip package may include a chip, an encapsulant material, and an exposed pad (pad) conductively connected to the chip, a layer of a porous or dendrite-containing adhesion promoter on a surface of the exposed pad, and a thermal interface material attached to the exposed pad through the layer.
Drawings
In the drawings, like numerals generally refer to like parts throughout the different views. The drawings are not necessarily to scale, emphasis instead generally being placed upon illustrating the principles of the invention. In the following description, various embodiments of the present invention are described with reference to the following drawings, in which:
fig. 1A to 1E each show a schematic cross-sectional view of a chip package structure according to various embodiments;
fig. 2A and 2B each illustrate a method of forming a chip package structure according to various embodiments;
fig. 3 shows a schematic cross-sectional view of a chip package structure according to various embodiments;
fig. 4 shows a flow diagram of a method of forming a chip package structure according to various embodiments;
FIG. 5A illustrates a method of forming a chip package structure according to the prior art, and FIG. 5B illustrates the resulting chip package structure;
fig. 6A illustrates a method of forming a chip package structure according to various embodiments;
fig. 6B and 6C each show a schematic cross-sectional view of a chip package structure according to various embodiments; and
fig. 7 illustrates a flow diagram of a method of forming a chip package structure, in accordance with various embodiments.
Detailed Description
The following detailed description refers to the accompanying drawings that show, by way of illustration, specific details and embodiments in which the invention may be practiced.
The word "exemplary" is used herein to mean "serving as an example, instance, or illustration. Any embodiment or design described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments or designs.
Various aspects of the present disclosure are provided for a device, and various aspects of the present disclosure are provided for a method. It will be understood that the basic properties of the device also apply to the method and vice versa. Therefore, a repeated description of such properties may have been omitted for the sake of brevity.
To ensure good heat flow between the interfaces and optionally reliable electrical isolation, the connection between the chip package and the heat sink needs to be robust over lifetime.
In various embodiments, a porous or dendritic adhesion promoter may be provided between the chip package (e.g., exposed (e.g., metal) pads) and the thermal interface material. In various embodiments, an adhesion promoter may additionally be disposed between the encapsulation material and the thermal interface material of the chip package.
In the case of an adhesion promoter having a porous structure, the adhesion promoter may have a cavity into which the thermal interface material may flow before it solidifies when the thermal interface material is disposed in a paste-like (liquid) or liquid form.
In the case of a tackifier having a dendritic structure, the (initially liquid or paste-like) thermal interface material may enclose the dendritic structure of the (annular) tackifier before it solidifies.
In various embodiments, the tackifier may be provided with both pores and dendrites.
The structure of the adhesion promoter (e.g., as described above, e.g., having pores and/or dendrites) may result in a mechanical interlock (also referred to as mechanical anchoring) between the adhesion promoter and the thermal interface material.
The adhesion promoter may additionally have excellent adhesion to the chip package, for example to exposed (e.g. metal) pads, and/or to the packaging material, for example a molding material as known in the art. For example, the adhesion promoter may have a CTE that is closer to the CTE of the chip packaging material(s) on which the adhesion promoter is formed than the thermal interface material. In other words,
Figure 766979DEST_PATH_IMAGE001
and/or
Figure 746437DEST_PATH_IMAGE002
. Alternatively or additionally, the chemical and/or physical adhesion of the first adhesion pair (exposed pad-adhesion promoter) and/or the second adhesion pair (encapsulant-adhesion promoter) may be higher than between the prior art adhesion pairs (exposed pad-thermal interface material; encapsulant-thermal interface material).
In the prior art (no dendrimer/porous adhesion promoter is used), long term stability of high thermal conductivity may be critical (e.g., at risk) due to the CTE mismatch described above and/or due to other adhesion limiting factors.
In various embodiments, the porous or dendrimer containing adhesion promoter may compensate for CTE mismatch on the one hand, and may be temperature stable and exhibit no degradation on the other hand.
In various embodiments, a chip package structure may include a dendrimer-containing adhesion promoter combined with, for example, a compression molded TIM layer.
The dendrimer containing adhesion promoter may for example be an inorganic adhesion promoter, for example formed by a so-called A2 plating (plating) process. The A2 plating process may use a commercially available plating bath, which may be used, for example, to form a dendrite adhesion promoter comprising zirconium and chromium, or as a dendrite combination of a so-called Cr 6-free A2, zinc-vanadium layer and zinc-vanadium oxide layer.
Atomic Layer Deposition (ALD) may be applied on conductive and/or non-conductive surfaces. In other words, using ALD, in various embodiments adhesion promoters may be deposited on conductive and/or non-conductive materials, and thus in various embodiments dendrite structures may be deposited on the entire (e.g., back side) side of the chip package structure, wherein the side may include both conductive (e.g., metal) and non-conductive (e.g., polymer) surfaces.
In various embodiments, the porous adhesion promoter may be formed by a hydrothermally (hydrothermally) treated alumina layer.
In various embodiments, the porous or dendrimer containing adhesion promoter may be formed as a layer of nanoparticles, which may be formed using spark ablation. The nanoparticles may for example comprise or consist of a conducting or semiconducting material, such as a metal, metal alloy or semiconductor material. In various embodiments, the layer of nanoparticles with cavities/dendrites forming the adhesion promoter may for example comprise or consist of a metal forming the surface of the exposed pad.
As yet another example, in various embodiments, silica aerogel (silica aerogel) may be used as the viscosifier.
After deposition of the porous or dendritic adhesion promoter, a thermal interface material (which may be an electrically insulating layer) may be formed on the adhesion promoter, e.g., molded onto the adhesion promoter. In various embodiments, the thermal interface material may be disposed by compression molding or other molding processes such as transfer molding, or by printing or lamination, for example. The thermal interface material (e.g. electrically insulating material) may be, for example, a silicone or epoxy material, or any other kind of polymer provided in a fluid state to be able to fill the dendrites or porous shell-like structures of the adhesion promoter layer.
Exemplary materials for the thermal interface material may include or consist of a thermoplastic such as polyethylene, polyvinyl chloride, polytetrafluoroethylene (polytetrafluroethylene), polyester, polycarbonate or polypropylene, a thermoset such as polyurethane, melamine resin or epoxy, or an elastomer such as silicone, ethylene-propylene copolymer.
In various embodiments, these materials may be highly filled with ceramic fillers, such as Al 2 O 3 、BN、AlN、MgO。
For so-called "advanced isolation", in other words for high quality electrical isolation, a layer that is very robust with respect to scratches (scratche) may be required. Thus, a relatively hard material (e.g. compared to the material used for chip packaging having less stringent requirements on scratch resistance) may be used as e.g. a packaging material, e.g. a molding material. The above embodiments comprising a porous/dendritic adhesion promoter may be particularly well suited to avoid the risk of delamination.
Each of fig. 1A to 1E shows a schematic cross-sectional view of a chip package structure 100 according to various embodiments, and each of fig. 2A and 2B shows a method of forming the chip package structure 100 according to various embodiments.
Chip package 100 may include a chip 104, an encapsulation material 106, and exposed pads 108 conductively connected to chip 104. Chip 104, the encapsulation, and exposed pads 108 may together form chip package 102. In various embodiments, chip package 102 may include additional components, such as, for example, electrical leads (e.g., for contacting chip contacts disposed on an opposite side of chip 104 from exposed pads 108), additional layers, such as, for example, at interfaces between chip 104 and encapsulation 106 and/or between exposed pads 108 and encapsulation 106, additional chips, and/or the like.
In various embodiments, die 104 may be or include any suitable type of semiconductor die that is typically included in die package 102, particularly power circuit elements such as power transistors or the like that particularly benefit from good cooling enabled by securely attached thermal interface material 112 (and, as shown in fig. 3, a heat spreader 330 attached to thermal interface material 112).
In various embodiments, exposed pad 108 may be an exposed portion of a leadframe to which chip 104 is attached, or a chip contact pad (e.g., a drain contact covering, for example, the entire major surface of chip 104), a clip (clip) that electrically contacts chip 104, or the like. The exposed pads 108 may include or consist of a conductive material, such as a metal commonly used to electrically contact the chip, such as copper or a copper alloy. In various embodiments, the exposed pads 108 may include a stack of layers of different metals, or a metal body with one or more metal layers formed thereon.
The exposed pads 108 may remain exposed during placement of the encapsulation material 106 (see fig. 2A and 2B, which illustrate an exemplary molding process involving a top mold (mold) 220T and a bottom mold 220B, wherein the bottom mold is configured to prevent the encapsulation material 106 from reaching the exposed pads 108), or may be peeled away (not shown) from the encapsulation material 106 and/or protective layer after the encapsulation process.
Encapsulant material 106 may be or include any suitable type of encapsulant material commonly used in chip packages 102, such as a polymer material, such as a molding material.
Chip package structure 100 may include, in various embodiments, a porous or dendrite adhesion promoter 110-containing layer (also referred to as a porous/dendrite layer, a porous/dendrite adhesion promoter, an adhesion promoter, or simply a layer, if it is clear from the context that a porous/dendrite layer is mentioned) on the surface of exposed pad 108. The adhesion promoter 110 may be in direct contact with the exposed pad 108. For example, the adhesion promoter 110 may be formed directly on the exposed pad 108.
In the case of adhesion promoter 110 with dendrites, adhesion promoter 110 may be, for example, an inorganic adhesion promoter, such as an adhesion promoter formed by an A2 plating process, for example including zirconium and chromium, or as a combination of a so-called Cr 6-free A2, zinc-vanadium layer and zinc-vanadium oxide layer, including dendrites on its exposed surface, in other words on the surface facing away from exposed pad 108. During the electroplating process, the electroplating conditions may be controlled, for example as known in the art, to allow or force the electroplated layer to grow in a dendritic structure, for example to a desired average thickness and/or surface roughness.
Exemplary electrolyte compositions and plating conditions are described below for the chromium-free A2 process.
An electroplating process can be used to form a dendrite-containing adhesion promoter on a conductive surface, such as on an exposed metal pad.
The electrolyte may include sodium or potassium silicate (sodium or potassium silicate), sodium or potassium hydroxide, sodium or potassium vanadate, and zincate (Na or K).
Variety of the same Metal Concentration of metal in electrolyte [ mol/l ]] V Range [ mol/l]
NaOH NaOH 0,2861 0,1-0,5
Na 2 O:SiO 2 （27% SiO 2 ） Si 0,0025 0,001-0,01
K 3 VO 4 V（VII） 0,0118 0,1-0,001
ZnO Zn 0,0210 0,1-0,001
The current density of the direct current may be about 45 mA/cm during deposition 2 . For pulse plating, 228 mA/cm may be used 2 Peak current with a ripple/dwell (dwell) function of 10ms on and 10ms off. The temperature may range from about 30 ℃ to about 95 ℃ (with a target temperature of about 50 ℃, and the electrolyte flow may range from about 2 to about 200 cm/s.
Using electroplating, such as an A2 process, the nature of which may cause adhesion promoter 110 to form only on the conductive surface, such as only on exposed pad 108, for example as shown in fig. 1C, 1D, 1E, and 2B. The adhesion promoter 110 may be disposed prior to forming the encapsulation 106 (see, e.g., fig. 2B) or after forming the encapsulation 106 (see, e.g., fig. 2A).
In various embodiments (not shown), the exposed pads 108 may be the only surface facing the heat spreader 330. In other words, the area of the encapsulation material 106 covering the exposed pads 108 (e.g., leadframe) from the backside may match the area of the exposed pads 108 or be smaller than this area.
In various embodiments, the adhesion promoter 110 may be limited to the exposed pads 108 by other techniques, such as by using a mask to limit the area where the adhesion promoter 110 is formed to the exposed pads 108.
In various embodiments, an adhesion promoter 110 may be additionally disposed over encapsulant material 106, for example, in contact with encapsulant material 106. In other words, adhesion promoter 110 may extend from exposed pad 108 to encapsulant 106. In various embodiments, encapsulation material 106 may be adjacent to exposed pads 108. In various embodiments, the exposed pads 108 and the encapsulation material 106 may form a common surface, wherein the encapsulation material 106 may at least partially, e.g., completely, surround the exposed pads 108.
In various embodiments, the tackifier 110 may be disposed to cover at least a portion of the encapsulant material 106, see the exemplary embodiments shown in fig. 1A, 1B, and 2A. Adhesion promoter 110 may be disposed to completely or nearly completely cover one of the major surfaces of chip package 102, e.g., the surface including exposed pads 108. In various embodiments, adhesion promoter 110 may be arranged to cover only a portion of the major surface, e.g., extending over the edges of exposed pads 108 in at least one direction toward the edges of chip package 102. In various embodiments, the adhesion promoter 110 may be arranged to extend symmetrically onto the encapsulant 106 over one or more edges of the exposed pads 108, e.g., on all sides.
To deposit a material that can adhere to both the conductively exposed pad 108 and the encapsulation material, for example as described above, atomic Layer Deposition (ALD) or other suitable techniques that otherwise allow for the formation of porous and/or dendritic structures may be used in various embodiments. In other words, using ALD, in various embodiments adhesion promoters may be deposited on conductive and/or non-conductive materials.
In various embodiments, a porous adhesion promoter may be formed, for example, by depositing alumina in an ALD process and by subjecting the layer to hot water treatment, thereby forming a rough/porous (boehmite) AlOOH layer, for example, as described in DE 10 2018 118 544 A1.
In various embodiments, the porous or dendrite-containing adhesion promoter may be formed as a layer of nanoparticles, which may be formed using spark ablation of an electrode made of the material to be deposited as nanoparticles. The nanoparticles may for example comprise or consist of a conducting or semiconducting material, such as a metal, metal alloy or semiconductor material. In various embodiments, the layer of nanoparticles with cavities/dendrites forming the adhesion promoter may, for example, comprise or consist of a metal forming the surface of the exposed pad.
As yet another example, silica aerogels may be used as tackifiers in various embodiments.
In various embodiments, chip package structure 100 may include a thermal interface material 112 attached to exposed pads 108 through a porous/dendritic body layer 110.
When the thermal interface material 112 is disposed, the Thermal Interface Material (TIM) 112 may be liquid or paste-like at the temperature of application. Thereby, it may be ensured that the thermal interface material 112 may flow or be pressed into the pores or more generally cavities of the adhesion promoter 110, or may arrange itself around the dendrites. After solidification of the thermal interface material 112 (e.g., by thermal curing, UV irradiation, or the like), a strong interlocking structure may be formed by the thermal interface material 112 and the adhesion promoter 110. In various embodiments, the thermal interface material 112 may be disposed by a molding process, such as by compression molding or transfer molding, or such as by printing, lamination, or 3D printing.
In various embodiments, the thermal interface material 112 may include or consist of a thermoset resin, silicone, epoxy, rubber, epoxy polyimide, and/or thermoplastic or the like.
The thermal interface material 112 may extend all the way to the edges of the adhesion promoter 110. In other words, the area covered by the thermal interface material 112 may substantially or completely match the area covered by the adhesion promoter 110. For an exemplary embodiment, see fig. 1B, 1D, 2A, and 2B.
In various embodiments, the thermal interface material 112 may not completely cover the adhesion promoter 110. An exemplary embodiment is shown in fig. 1A and 1C.
In various embodiments, it may be avoided that thermal interface material 112 extends beyond adhesion promoter 110 onto the surface of encapsulation material 106, at least where the adhesion promoter at least partially covers the encapsulation material, since thermal interface material 112 is in direct contact with the encapsulation material and areas of reduced adhesion between thermal interface material 112 and encapsulation material 106 may otherwise form a starting point for peeling of thermal interface material 112 also over exposed pads 108.
In the case of direct contact between the thermal interface material 112 and the encapsulant material, such as by a specially selected material, good adhesion is also ensured, which may allow the thermal interface material 112 to come into direct contact with the encapsulant material 106. A corresponding exemplary embodiment of such a chip package structure 100 is shown in fig. 1E, where adhesion promoter 110 is formed only on exposed pads 108, thermal interface material 112 is attached to exposed pads 108 by adhesion promoter 110, and thermal interface material 112 is formed to extend onto encapsulation material 106 (on which adhesion promoter 110 is not formed).
In various embodiments, the thermal interface material 112 may form an interface with the heat sink 330, typically a structure with excellent thermal conductivity (e.g., metal) and a large surface, which may be cooled, for example, by a coolant such as air or water. Fig. 3 shows an exemplary embodiment of a chip packaging system 300, which may include any of the chip packaging structures 100 described above, and may further include a heat spreader 330 directly attached (particularly with a thermally conductive connection) to the thermal interface material. The heat spreader 330 may be mounted to the thermal interface material 112 substantially as known in the art.
Fig. 4 shows a flow diagram 400 of a method of forming a chip package structure, in accordance with various embodiments.
The method can include forming a chip package by encapsulating at least a chip with an encapsulation material and exposing a pad conductively connected to the chip (410), forming a porous or dendrite adhesion promoter-containing layer on a surface of the exposed pad (420), and attaching a thermal interface material to the exposed pad using the layer (430).
In various embodiments, the thermal interface material 112, 512 may include or consist of a metal, and the porous or dendrite-containing adhesion promoter 110 may be formed on a surface of the thermal interface material 112, 512, such as on a surface internal to the chip packaging structure 100, 300, 600, and/or on a surface exposed by the chip packaging structure 100, 600. This may apply to any of the embodiments described above, unless it is explicitly described or clear from the context that the non-metallic thermal interface material 112, 512 is described as the only option.
As described above, fig. 5A illustrates a method of forming a chip package structure 500 according to the prior art, and fig. 5B illustrates a cross-sectional view of the resulting chip package structure 500.
Fig. 6A illustrates how the method of fig. 5A may be modified to provide a chip package structure 600 according to various embodiments, and fig. 6B and 6C each illustrate a schematic cross-sectional view of a chip package structure 600 according to various embodiments, which may optionally include the chip package structure 600 of fig. 6A. In fig. 6B, die 104 may be arranged out of the plane of the cross-section and thus is only shown as a dashed line, but fig. 6C includes die 104 and bond wires 666 that electrically connect die 104 to leadframe 560.
In various embodiments, chip-packaging structure 600 may include a chip package including chip 104 and encapsulant 562, a thermal interface 512 including or consisting of a metal and thermally connected to the chip package, e.g., thermally connected to chip 104 and/or encapsulant 562 and/or interface materials 552, 554, and a layer 660 of a porous or dendrite-containing adhesion promoter 660 on a surface of thermal interface 512.
In other words, in various embodiments, a porous or dendrite adhesion promoter 110-containing layer may be disposed on the thermal interface 512, which may include or consist of a metal, instead of or in addition to the exposed pads.
For ease of reference, the adhesion promoter 660 on the thermal interface 512 is provided with its own reference number 660, even though at least in various embodiments, the materials of the adhesion promoter 660 and the adhesion promoter 110 may be the same and they may even be applied/formed during a common process, e.g., after the thermal interface 512 is attached to the exposed pad 108.
In various embodiments, the porous or dendrite-containing adhesion promoter 110 on the exposed pad 108 may be different than the porous or dendrite-containing adhesion promoter 660 on the thermal interface 512. This may be useful, for example, where the exposed pad 108 and thermal interface 512 are provided with their respective porous or dendrite-containing adhesion promoters 110 and 660, respectively, before they are joined.
The surface of the thermal interface 512 on which the porous or dendritic-containing adhesion promoter 660 is formed may include any surface of the thermal interface 512, such as the surface(s) forming the interface with and/or exposed from the chip package.
In various embodiments, for example, an aluminum plate-The adhesion between a thermal interface 512, such as an aluminum block, and a structure to which it is attached, such as an encapsulant 562, e.g., a mold compound, may be improved by roughening the surface of the thermal interface 512 (e.g., an aluminum plate/aluminum block) by immersion in hot Deionized (DI) water. Thus, naturally occurring or intentionally applied aluminum oxide (Al) on the thermal interface 512 2 O 3 ) The layer may be converted to a boehmite containing dendrites (AlOOH) layer with increased adhesion properties. Experiments have shown that a dendrimer-containing boehmite (AlOOH) layer on an aluminum surface increases adhesion even after stress testing. The process itself is easy and inexpensive. The thermal interface 512 may be immersed in hot DI water for about ten minutes, for example. This process may be performed in parallel across a large number of thermal interfaces 512.
Alternatively, other porous or dendrimer containing tackifiers 110 as described above may be used for the tackifier 660 and may be formed as described therein.
In various embodiments, as shown in fig. 6A, the porous or dendrite-containing adhesion promoter 110 may be formed on the thermal interface 512 before the thermal interface 512 is attached to any other element of the chip package structure 600. As such, it may be ensured that all interfaces between thermal interface 512 and other components of chip package structure 600, such as encapsulation material 562, chip 104, interface material 550 (in various embodiments, it may be sufficient to provide only one interface material 550, rather than a combination of C-stage and B-stage materials as used in the prior art), heat spreader 330, and the like, are similar to the embodiment shown in fig. 3.
In various embodiments (examples of which are shown in fig. 6A-6C), thermal interface 512 may have a shape with a hexagonal cross-section through its major surface. In other words, as shown in fig. 6A-6C, the thermal interface 512 may have a shape with large opposing major surfaces and V-shaped edges of the engagement surfaces, with the bottom of the V pointing outward. This shape of thermal interface 512 may combine two advantages over other shapes of thermal interface 512, for example over thermal interface 512 having a rectangular cross-section, because thermal interface 512 having a hexagonal cross-section may be more securely anchored in encapsulant 562, and because it is easier to manufacture (for example, by simply forming two opposing V-shaped grooves in a plate, as shown in fig. 6A) than thermal interface 512 (arranged with a wider portion of thermal interface 512 towards the interior of chip package 600) that is securely anchorable by providing it with a shape having a stepped cross-section. In various embodiments, thermal interface 512 may have any suitable shape, for example, as is known in the art.
Fig. 7 shows a flow diagram 700 of a method of forming a chip package structure, in accordance with various embodiments.
The method may include forming a chip package by encapsulating at least a chip with an encapsulation material (710), forming a porous or dendrimer adhesion promoter-containing layer on a surface of a thermal interface (720), and attaching the thermal interface to the chip package using the adhesion promoter (730).
Various examples will be described below:
example 1 is a chip package structure. The chip package may include a chip, an encapsulation material, and exposed pads conductively connected to the chip, a porous or dendrimer adhesion promoter-containing layer on a surface of the exposed pads, and a thermal interface material attached to the exposed pads through the layer.
In example 2, the subject matter of example 1 can optionally include that the thermal interface material is an organic material.
In example 3, the subject matter of example 1 can optionally include that the thermal interface material is an inorganic material.
In example 4, the subject matter of any of examples 1 to 3 can optionally include that the adhesion promoter is an organic adhesion promoter.
In example 5, the subject matter of any of examples 1 to 3 can optionally include that the tackifier is an inorganic tackifier.
In example 6, the subject matter of example 5 can optionally include that the inorganic adhesion promoter comprises alumina.
In example 7, the subject matter of example 6 can optionally include that the inorganic adhesion promoter comprises hot water treated alumina.
In example 8, the subject matter of example 5 can optionally include that the inorganic adhesion promoter comprises a layer of nanoparticles deposited by an A2 process and/or by Atomic Layer Deposition (ALD) and/or obtained by spark ablation.
In example 9, the subject matter of any of examples 1 to 8 can optionally include the thermal interface material being compression molded, printed, laminated, molded, 3D printed, and/or transfer molded.
In example 10, the subject matter of any of examples 1 to 9 can optionally include that the thermal interface material comprises or consists of a thermoset resin, silicone, rubber, and/or thermoplastic.
In example 11, the subject matter of example 10 can optionally include that the resin is an epoxy resin.
In example 12, the subject matter of any of examples 1 to 11 can optionally include that the adhesion promoter extends beyond the exposed pad to at least partially cover a surface of the encapsulation material.
In example 13, the subject matter of example 12 can optionally include that the thermal interface material extends beyond the exposed pad in contact with the adhesion promoter to at least partially cover the encapsulation material.
In example 14, the subject matter of any of examples 1 to 13 can optionally include the exposed pad is a chip contact, a portion of the redistribution structure, or a clip.
Example 15 is a method of forming a chip package structure. The method may include forming a chip package by encapsulating at least a chip with an encapsulating material and exposing a pad conductively connected to the chip, forming a porous or dendrite adhesion promoter-containing layer on a surface of the exposed pad, and attaching a thermal interface material to the exposed pad using the layer.
In example 16, the subject matter of example 15 can optionally include that the thermal interface material is an organic material.
In example 17, the subject matter of example 15 can optionally include that the thermal interface material is an inorganic material.
In example 18, the subject matter of any of examples 15 to 17 can optionally include that the tackifier is an organic tackifier.
In example 19, the subject matter of any of examples 15 to 17 can optionally include that the tackifier is an inorganic tackifier.
In example 20, the subject matter of example 19 can optionally include that the inorganic adhesion promoter comprises alumina.
In example 21, the subject matter of example 20 can optionally include forming the layer of the inorganic adhesion promoter to include hot water treated alumina.
In example 22, the subject matter of example 19 can optionally include that forming the layer of the inorganic adhesion promoter includes depositing the layer by an A2 process and/or by Atomic Layer Deposition (ALD) and/or forming the nanoparticle layer by spark ablation.
In example 23, the subject matter of any of examples 15 to 22 can optionally include the attaching the thermal interface material comprises at least one of the group of processes, the group comprising compression molding, printing, laminating, molding, and transfer molding.
In example 24, the subject matter of any of examples 15 to 23 can optionally include that the thermal interface material comprises or consists of a thermoset resin, a silicone, a rubber, and/or a thermoplastic.
In example 25, the subject matter of example 24 can optionally include that the resin is an epoxy resin.
In example 26, the subject matter of any of examples 15 to 25 can optionally include that the adhesion promoter extends beyond the exposed pad to at least partially cover a surface of the encapsulation material.
In example 27, the subject matter of example 26 can optionally include that the thermal interface material extends beyond the exposed pad in contact with the adhesion promoter to at least partially cover the encapsulation material.
In example 28, any of example subject matter of examples 15 to 27 may optionally include the exposed pad is a chip contact, a portion of the redistribution structure, or a clip.
In example 29, the subject matter of any of examples 15 to 25 can optionally include forming the adhesion promoter prior to encapsulation of the chip.
In example 30, the subject matter of any of examples 15 to 28 can optionally include forming the adhesion promoter after encapsulation of the chip.
In example 31, the chip packaging structure of any of examples 1, 3 to 8, or 12 to 14 may optionally include the thermal interface material comprising or consisting of a metal, the chip packaging structure further comprising a porous or dendrimer adhesion promoter-containing layer on a surface of the thermal interface.
In example 32, the chip packaging structure of example 31 may optionally include that the adhesion promoter on the surface of the exposed pad and the adhesion promoter on the surface of the thermal interface comprise or consist of the same material, optionally formed during a common process.
Example 33 is a chip package structure. The chip packaging structure may include: a chip package comprising a chip and an encapsulating material, a thermal interface comprising or consisting of a metal and thermally connected to the chip package, and a porous or dendrimer adhesion promoter-containing layer on a surface of the thermal interface.
In example 34, the chip packaging structure of example 33 may optionally include that the adhesion promoter is an inorganic adhesion promoter.
In example 35, the chip packaging structure of example 34 may optionally include that the inorganic adhesion promoter comprises aluminum oxide.
In example 36, the chip packaging structure of examples 34 or 35 may optionally include that the inorganic adhesion promoter comprises hot water treated alumina.
In example 37, the chip packaging structure of example 33 may optionally include that the adhesion promoter is an organic adhesion promoter.
In example 38, the chip packaging structure of any of examples 33 to 37 may optionally include an adhesion promoter disposed between the thermal interface and the chip and/or between the thermal interface and the encapsulation material.
In example 39, the chip packaging structure of any of examples 33 to 38 may optionally include that the metal of the thermal interface material is at least one of a group of metals, the group including aluminum and copper.
In example 40, the chip packaging structure of any of examples 33 to 39 may optionally include the thermal interface partially integrated in the encapsulation material.
In example 41, the chip packaging structure of any of examples 33 to 40 may optionally include that the thermal interface has a shape with a hexagonal cross-section through a major surface thereof.
Example 42 is a method of forming a chip package structure. The method can include forming a chip package by encapsulating at least a chip with an encapsulation material, forming a porous or dendrimer adhesion promoter-containing layer on a surface of a thermal interface, and attaching the thermal interface to the chip package using the adhesion promoter.
In example 43, the method of example 42 may optionally include that the tackifier is an inorganic tackifier.
In example 44, the method of example 43 may optionally include that the inorganic adhesion promoter comprises alumina.
In example 45, the method of example 43 or 44 can optionally include that the inorganic adhesion promoter comprises hot water treated alumina.
In example 46, the method of example 42 may optionally include that the adhesion promoter is an organic adhesion promoter.
In example 47, the method of any of examples 42 to 46 may optionally include forming a porous or dendrimer adhesion promoter-containing layer on a surface of the thermal interface before the chip package is attached to the thermal interface.
In example 48, the method of any of examples 42 to 46 may optionally include, after attaching the chip to the thermal interface and before encapsulating the chip and at least a portion of the thermal interface with an encapsulation material, forming a porous or dendrimer adhesion promoter-containing layer on a surface of the thermal interface.
In example 49, the method of example 48 may optionally include the chip package further comprising a leadframe conductively connected to the chip, and during forming the adhesion promoter on the thermal interface, additionally forming the adhesion promoter on the leadframe and encapsulating at least partially the leadframe.
Example 50 is a chip packaging system. The chip packaging system may include the chip packaging structure of any of examples 1 to 14 or 31 to 41, and a heat spreader attached to the thermal interface material.
While the invention has been particularly shown and described with reference to a particular embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. The scope of the invention is, therefore, indicated by the appended claims and all changes that come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.

Claims (48)

1. A chip package structure, comprising:
a chip package including a chip, an encapsulation material, and exposed pads conductively connected to the chip;
a porous or dendrite adhesion promoter-containing layer on the exposed pad surface; and
a thermal interface material attached to the exposed pad through the layer.
2. The chip package structure according to claim 1,
wherein the thermal interface material is an organic material.
3. The chip packaging structure according to claim 1,
wherein the thermal interface material is an inorganic material.
4. The chip packaging structure according to any of claims 1 to 3,
wherein the tackifier is an organic tackifier.
5. The chip packaging structure according to any of claims 1 to 3,
wherein the tackifier is an inorganic tackifier.
6. The chip packaging structure according to claim 5,
wherein the inorganic adhesion promoter comprises alumina.
7. The chip packaging structure according to claim 6,
wherein the inorganic adhesion promoter comprises a hot water treated alumina.
8. The chip package structure according to claim 5,
wherein the inorganic adhesion promoter comprises a nanoparticle layer obtained by A2 process and/or by Atomic Layer Deposition (ALD) deposited material and/or by spark ablation.
9. The chip packaging structure according to any of claims 1 to 8,
wherein the thermal interface material comprises or consists of a thermosetting resin, silicone, epoxy, rubber, epoxy polyimide and/or thermoplastic.
10. The chip packaging structure according to any of claims 1 to 9,
wherein the adhesion promoter extends beyond the exposed pad to at least partially cover a surface of the encapsulation material.
11. The chip package structure according to claim 10,
wherein the thermal interface material extends beyond the exposed pad in contact with the adhesion promoter to at least partially cover the encapsulation material.
12. The chip packaging structure according to any of claims 1 to 11,
wherein the exposed pad is a chip contact, a portion of a redistribution structure, or a clip.
13. A method of forming a chip package structure, the method comprising:
forming a chip package by encapsulating at least a chip with an encapsulating material and exposing pads conductively connected to the chip;
forming a porous or dendrite adhesion promoter-containing layer on the exposed surface of the pad; and
a layer is used to attach the thermal interface material to the exposed pads.
14. The method of claim 13, wherein the first and second light sources are selected from the group consisting of,
wherein the thermal interface material is an organic material.
15. The method of claim 13, wherein the first and second light sources are selected from the group consisting of,
wherein the thermal interface material is an inorganic material.
16. The method of any of claims 13 to 15,
wherein the tackifier is an organic tackifier.
17. The method of any of claims 13 to 15,
wherein the tackifier is an inorganic tackifier.
18. The method of claim 17, wherein the first and second light sources are selected from the group consisting of,
wherein the inorganic adhesion promoter comprises alumina.
19. The method as set forth in claim 18, wherein,
wherein forming the layer of inorganic adhesion promoter comprises hot water treated alumina.
20. The method as set forth in claim 17, wherein,
wherein forming the layer of inorganic adhesion promoter comprises depositing a layer by an A2 process and/or by Atomic Layer Deposition (ALD) and/or by spark ablation to form a nanoparticle layer.
21. The method according to any of the claims 13 to 20,
wherein attaching the thermal interface material comprises at least one of the group of processes, the group comprising:
compression molding;
printing;
laminating;
3D printing;
molding; and
and (4) transfer molding.
22. The method according to any of the claims 13 to 21,
wherein the thermal interface material comprises or consists of a thermosetting resin, silicone, rubber and/or thermoplastic.
23. The method of claim 22, wherein the first and second portions are selected from the group consisting of,
wherein the resin is an epoxy resin.
24. The method of any of claims 13 to 23,
wherein the adhesion promoter extends beyond the exposed pad to at least partially cover a surface of the encapsulation material.
25. The method as set forth in claim 24, wherein,
wherein the thermal interface material extends beyond the exposed pad in contact with the adhesion promoter to at least partially cover the encapsulation material.
26. The method of any of claims 13 to 25,
wherein the exposed pad is a chip contact, a portion of a redistribution structure, or a clip.
27. The method of any of claims 13 to 23,
wherein the adhesion promoter is formed prior to encapsulation of the chip.
28. The method of any of claims 13 to 26,
wherein the adhesion promoter is formed after encapsulation of the chip.
29. The chip packaging structure according to any one of claims 1, 3 to 8, or 10 to 12,
wherein the thermal interface material comprises or consists of a metal,
the chip packaging structure further comprises:
a porous or dendrimer adhesion promoter-containing layer on a surface of the thermal interface.
30. The chip packaging structure according to claim 29,
wherein the adhesion promoter on the surface of the exposed pad and the adhesion promoter on the surface of the thermal interface comprise or consist of the same material, optionally formed during a common process.
31. A chip package structure, comprising:
a chip package comprising a chip and an encapsulating material; and
a thermal interface comprising or consisting of metal and thermally connected to the chip package; and
a porous or dendrimer adhesion promoter-containing layer on a surface of the thermal interface.
32. The chip packaging structure according to claim 31,
wherein the tackifier is an inorganic tackifier.
33. The chip packaging structure according to claim 32,
wherein the inorganic adhesion promoter comprises alumina.
34. The chip packaging structure according to claim 32 or 33,
wherein the inorganic adhesion promoter comprises a hot water treated alumina.
35. The chip packaging structure according to claim 31,
wherein the tackifier is an organic tackifier.
36. The chip packaging structure according to any of claims 31 to 35,
wherein the adhesion promoter is disposed between the thermal interface and the chip and/or between the thermal interface and the encapsulant.
37. The chip packaging structure according to any of claims 31 to 36,
wherein the metal of the thermal interface material is at least one of the group of metals, the group comprising:
aluminum; and
copper.
38. The chip packaging structure according to any of claims 31 to 37,
wherein the thermal interface is partially integrated in the encapsulation material.
39. The chip packaging structure according to any of claims 31 to 38,
wherein the thermal interface has a shape with a hexagonal cross-section through a major surface thereof.
40. A method of forming a chip package structure, the method comprising:
forming a chip package by encapsulating at least a chip with an encapsulating material;
forming a porous or dendritic adhesion promoter-containing layer on a surface of the thermal interface; and
the thermal interface is attached to the chip package using an adhesion promoter.
41. The method of claim 40, wherein said step of selecting said target,
wherein the tackifier is an inorganic tackifier.
42. The method of claim 41, wherein said step of selecting said target,
wherein the inorganic adhesion promoter comprises alumina.
43. The method according to claim 41 or 42,
wherein the inorganic adhesion promoter comprises a hot water treated alumina.
44. The method as set forth in claim 40, wherein,
wherein the tackifier is an organic tackifier.
45. The method of any of claims 40 to 44,
wherein a porous or dendrimer adhesion promoter-containing layer is formed on a surface of the thermal interface prior to attaching the chip package to the thermal interface.
46. The method of any of claims 40 to 44,
wherein a porous or dendrimer adhesion promoter-containing layer is formed on a surface of the thermal interface after the chip is attached to the thermal interface and before the chip and at least a portion of the thermal interface are encapsulated by the encapsulation material.
47. In accordance with the method set forth in claim 46,
wherein the chip package further comprises a lead frame electrically connected to the chip, an
Wherein during the formation of the adhesion promoter on the thermal interface, the adhesion promoter is additionally formed on the lead frame; and
wherein the encapsulation at least partially encapsulates the lead frame.
48. A chip packaging system, comprising:
the chip packaging structure according to any of claims 1 to 12 or 29 to 39; and
a heat spreader attached to the thermal interface material.
CN202210991340.XA 2021-08-18 2022-08-18 Chip packaging structure, chip packaging system and method for forming chip packaging structure Pending CN115708199A (en)

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