CN115708034A - Linear voltage stabilizing circuit and frequency compensation method thereof - Google Patents
Linear voltage stabilizing circuit and frequency compensation method thereof Download PDFInfo
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- CN115708034A CN115708034A CN202110951402.XA CN202110951402A CN115708034A CN 115708034 A CN115708034 A CN 115708034A CN 202110951402 A CN202110951402 A CN 202110951402A CN 115708034 A CN115708034 A CN 115708034A
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Abstract
The application provides a linear voltage stabilizing circuit and a frequency compensation method thereof, a compensation capacitor and a compensation resistor provided in the linear voltage stabilizing circuit can be adjusted according to a load to improve the frequency characteristic of the linear voltage stabilizing circuit, a capacitor amplification unit is provided in the linear voltage stabilizing circuit to amplify an entity capacitor, the area of a capacitor arranged in the linear voltage stabilizing circuit can be reduced, and further the chip area of the linear voltage stabilizing circuit is reduced.
Description
Technical Field
The present disclosure relates to integrated circuit technologies, and in particular, to a linear voltage regulator and a frequency compensation method thereof.
Background
The linear voltage stabilizing circuit is a circuit capable of outputting an input voltage after adjustment, and has the characteristics of high stability, high precision, small ripple, high power supply rejection ratio, high response speed, low cost and the like, so that the linear voltage stabilizing circuit is widely applied to electronic products and used for stabilizing and adjusting the voltage on the circuit.
In the prior art, a linear voltage stabilizing circuit includes an amplifier, a first voltage-dividing resistor, a second voltage-dividing resistor, and a first transistor, where the first voltage-dividing resistor and the second voltage-dividing resistor may jointly generate a feedback voltage according to a voltage at an output interface and send the feedback voltage to a first input terminal of the amplifier, and a second input terminal of the amplifier is configured to receive a reference voltage. The amplifier adjusts the output voltage according to the difference between the feedback voltage and the reference voltage.
However, in the prior art, the linear voltage regulator circuit has a poor compensation effect on the frequency when performing voltage regulation on the voltage, which affects the stability of the output voltage of the linear voltage regulator circuit. When the output interface is connected with a large load, the linear voltage stabilizing circuit needs to be provided with a large capacitor to provide a large pole so as to improve the loop stability of the linear voltage stabilizing circuit, and when the capacitance value of the compensation capacitor is larger, the area of the compensation capacitor is larger, so that the area of a chip where the linear voltage stabilizing circuit is located is increased.
Disclosure of Invention
The application provides a linear voltage stabilizing circuit and a frequency compensation method thereof, which are used for solving the technical problems that in the linear voltage stabilizing circuit in the prior art, the compensation effect on the frequency is poor when voltage is regulated, the stability of the output voltage of the linear voltage stabilizing circuit is influenced, the area of a set capacitance value is too large, and the area of a chip where the linear voltage stabilizing circuit is located is increased.
The present application provides in a first aspect a linear voltage regulator circuit, including: an input interface for inputting a voltage; an output interface for outputting a voltage; the voltage adjusting unit is arranged between the input interface and the output interface and used for adjusting the voltage of the input interface according to the feedback voltage of the output interface and then outputting the adjusted voltage from the output interface; the compensation resistance unit is connected with the voltage adjusting unit and is used for providing compensation resistance required when adjusting voltage for the voltage adjusting unit; wherein the compensation resistance is determined from a current of the output interface; the compensation capacitor unit is connected with the voltage adjusting unit and is used for providing compensation capacitors required by voltage adjustment to the voltage adjusting unit; wherein the compensation capacitance unit includes: the capacitor amplifying unit is used for amplifying the capacitance value of the first capacitor to obtain the compensation capacitor.
In an embodiment of the first aspect of the present application, the voltage adjustment unit includes: an amplifier, a first voltage dividing resistor, a second voltage dividing resistor and a first transistor; the first transistor is disposed between the input interface and the output interface, a first end of the first voltage-dividing resistor is connected to the output interface, a second end of the first voltage-dividing resistor is connected to a first end of the second voltage-dividing resistor and a first input end of the amplifier, a second end of the second voltage-dividing resistor is grounded, a second input end of the amplifier is configured to receive a reference voltage, and an output end of the amplifier is connected to a control end of the first transistor and a first end of the first capacitor.
In an embodiment of the first aspect of the present application, the compensation resistance unit includes: a second transistor and a third transistor; the second end of the first capacitor is connected to the second end and the control end of the second transistor and the first end of the third transistor, the first end of the second transistor is connected to the input interface, and the second end of the third transistor is grounded.
In an embodiment of the first aspect of the present application, the compensation resistor Rc provided by the compensation resistor unit includes:
wherein, mu P Is the mobility of the electron carrier of the second transistor, C ox Is the capacitance of the gate oxide layer in unit area,
is the width-to-length ratio of the second transistor, I d(MP4) Is the current of the second transistor, I d(MP1) For the current of the output interface, I d(MP4) ＝k·I d(MP1) 。
In an embodiment of the first aspect of the present application, the capacitance amplifying unit includes: a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor; a first end of the fourth transistor is connected to the input interface, a second end of the fourth transistor is connected to the first end and the control end of the fifth transistor and the control end of the third transistor, a second end of the fifth transistor is grounded, a first end of the sixth transistor is connected to the input interface, a second end and the control end of the sixth transistor are connected to the first end of the seventh transistor, and a second end of the seventh transistor is grounded.
In an embodiment of the first aspect of the present application, the capacitance amplifying unit specifically amplifies the compensation capacitance C according to a capacitance value C1 of the first capacitance c The method comprises the following steps:
wherein, mu P Is the mobility of the electron carriers of the second transistor,
is the width-to-length ratio, mu, of the second transistor N Is the mobility of the electron carriers of the seventh transistor MN1,
is the width-to-length ratio of the seventh transistor MN1.
In an embodiment of the first aspect of the present application, the pole of the output voltage of the amplifier is calculated by the compensation capacitor and the resistance of the amplifier; and the zero point of the output voltage of the amplifier is obtained by calculation through the compensation capacitor and the compensation resistor.
In an embodiment of the first aspect of the application, the pole p of the amplifier output voltage 1 Is composed of
Zero z of the amplifier output voltage 1 Is composed of
In an embodiment of the first aspect of the present application, the compensation capacitor unit further includes: a selection switch and a plurality of candidate second transistors; the width-to-length ratio of each of the candidate second transistors is different; a first end of the candidate second transistor is connected with the input interface, and a second end of the first capacitor is connected with a second end and a control end of the candidate second transistor through the selection switch; or the first end of the candidate second transistor is connected with the input interface through the selection switch, and the second end of the first capacitor is connected with the second end and the control end of the candidate second transistor; the selection switch is to determine one of the plurality of candidate second transistors as the second transistor.
A second aspect of the present application provides a frequency compensation method for a linear voltage regulator circuit, including: determining a compensation capacitor, the current of an output interface and a feedback voltage; determining a compensation resistor according to the current of the output interface; and performing frequency compensation on the linear voltage stabilizing circuit according to the feedback voltage, the compensation capacitor and the compensation resistor.
To sum up, the linear voltage stabilizing circuit and the frequency compensation method thereof provided by the embodiment of the present application can achieve the following technical effects: 1. because the compensation resistor of the linear voltage stabilizing circuit can be adjusted according to the current of the output interface, when the output interface is connected with different loads, different zero points can be obtained under different conditions for frequency compensation, so that the stability of the linear voltage stabilizing circuit can be ensured when the current of the load is greatly changed, and a better frequency compensation effect which is more matched with the current load is realized. 2. Because the capacitance amplifying unit is arranged in the capacitance compensating unit to amplify the first capacitor, the compensating capacitor with a larger capacitance value can be obtained in a manner that the capacitance amplifying unit amplifies the first capacitor under the condition that the first capacitor arranged in the capacitance compensating unit is smaller, the area of the first capacitor arranged in the capacitance compensating unit of the linear voltage stabilizing circuit is reduced, the area of a chip where the linear voltage stabilizing circuit is arranged is further reduced, and the cost of the chip is reduced. 3. The linear voltage stabilizing circuit has a simple circuit structure and therefore has high reliability. 4. Because the frequency is not compensated by the ESR generating zero point of the output capacitor, the ESR value of the output capacitor connected with the linear voltage stabilizing circuit is not required, and the output can be kept stable when the ESR is approximately equal to 0.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the description below are only some embodiments of the present application, and for those skilled in the art, other drawings may be obtained according to these drawings without inventive labor.
FIG. 1 is a schematic diagram of a scenario in which the present application is applied;
FIG. 2 is a schematic diagram of a linear voltage regulator circuit according to the prior art;
FIG. 3 is a schematic diagram of an embodiment of a linear regulator;
FIG. 4 is a schematic diagram of a circuit configuration of an embodiment of a linear voltage regulating circuit according to the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be described clearly and completely with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only some embodiments of the present application, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The terms "first," "second," "third," "fourth," and the like in the description and in the claims of the present application and in the drawings described above, if any, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged under appropriate circumstances such that the embodiments of the application described herein may be implemented, for example, in sequences other than those illustrated or described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
Before a formal description of the embodiments of the present application, the application scenario, the functions and definitions of each part in the scenario, and the problems existing in the prior art provided by the present application are described with reference to fig. 1 to 2. Fig. 1 is a schematic diagram of a scenario in which the present application is applied, and as shown in fig. 1, the linear voltage regulator circuit provided in the present application has an input interface a and an output interface B, where the input interface a may be connected to a first device and configured to receive a voltage signal from the first device and mark the received voltage as Vin, and the output interface B may be connected to a second device and configured to send an output voltage to the second device and mark the output voltage as Vout. The linear voltage stabilizing circuit can also be used for controlling the output voltage according to the feedback voltage V of the output end of the linear voltage stabilizing circuit FB In the process, the linear voltage stabilizing circuit plays a role of stabilizing the input voltage Vin and outputting the regulated voltage Vout.
Fig. 2 is a schematic structural diagram of a linear voltage stabilizing circuit in the prior art, when the linear voltage stabilizing circuit shown in fig. 2 performs voltage stabilizing adjustment, a compensation capacitor and a compensation resistor for compensating for a frequency in the linear voltage stabilizing circuit are both fixed, and the fixed compensation capacitor and the compensation resistor enable the linear voltage stabilizing circuit to have only one fixed pole and zero inside, and the zero and the pole can achieve an optimal frequency compensation effect only under a specific load condition connected to an input interface of the linear voltage stabilizing circuit, and the frequency compensation effect on other load conditions is not good, which affects the loop stability of the linear voltage stabilizing circuit. In addition, when the output interface is connected with a large load, the output of the operational amplifier in the linear voltage stabilizing circuit needs to provide a large pole and a zero point to ensure the stability of the loop, according to the calculation mode of the pole, the capacitance value of the compensation capacitor arranged in the linear voltage stabilizing circuit is required to be large, and when the compensation capacitor with a large capacitance value is arranged in the linear voltage stabilizing circuit, the area of the compensation capacitor is large, so that the area of a chip where the linear voltage stabilizing circuit is located is increased.
Therefore, the present application further provides a linear voltage stabilizing circuit and a frequency compensation method thereof, wherein a compensation resistor provided by the linear voltage stabilizing circuit can be adjusted according to a load, so that the linear voltage stabilizing circuit provides different zero points to compensate for a frequency under different load conditions, thereby improving a frequency compensation effect which can be realized by the linear voltage stabilizing circuit. And moreover, the capacitor amplification unit is provided in the linear voltage stabilizing circuit to amplify the entity capacitor, so that the compensation capacitor with a larger capacitance value can be obtained by amplifying the entity capacitor without setting a larger entity capacitor in the linear voltage stabilizing circuit, the area of the capacitor arranged in the linear voltage stabilizing circuit is reduced, and the area of a chip where the linear voltage stabilizing circuit is located is further reduced.
The technical solution of the present application will be described in detail below with specific examples. These several specific embodiments may be combined with each other below, and details of the same or similar concepts or processes may not be repeated in some embodiments.
Fig. 3 is a schematic structural diagram of an embodiment of a linear regulator according to the present application, where the linear regulator shown in fig. 3 includes: input interface A, output interface B, voltage adjusting unit 11, compensation resistance unit 12 and compensation capacitance unit 13. Wherein, the input interface a is used for receiving an input voltage Vin, the output interface B is used for outputting a voltage Vout, the voltage adjusting unit 11 is disposed between the input interface a and the output interface B, and obtains a feedback voltage V according to the output interface B FB And regulating the voltage Vin of the input interface to obtain Vout, and outputting the Vout from the output interface B.
The compensation resistance unit 12 is connected to the voltage adjustment unit 11, and is configured to provide a compensation resistance Rc required for frequency compensation of a zero point provided at an output of the output terminal of the amplifier EA when the voltage adjustment unit 11 adjusts the voltage. In the embodiment of the present application, the compensation resistance Rc provided by the compensation resistance unit 12 is determined according to the current of the output interface B. Therefore, the compensation resistor Rc of the linear voltage stabilizing circuit provided by the present application is not fixed, but can be adjusted according to the current of the output interface B, so that when the output interface B is connected to different loads, the compensation resistor Rc corresponding to the current load current can be determined under different conditions, and when the voltage adjusting unit 11 adjusts the frequency according to the compensation resistor Rc and the compensation capacitor pair, a better frequency compensation effect more matched with the current load can be achieved.
The compensation capacitor unit 13 is connected to the voltage adjustment unit 11, and is configured to provide a compensation capacitor Cc required for frequency compensation of a zero point provided at an output terminal of the amplifier EA when the voltage adjustment unit adjusts the voltage. Wherein, the compensation capacitor unit in this application embodiment specifically includes: the first capacitor is an entity capacitor arranged in the linear voltage stabilizing circuit, and the capacitance amplifying unit is used for amplifying the capacitance value of the first capacitor to obtain the compensation capacitor Cc. Therefore, in the capacitance compensation unit 13 provided in the present application, since the capacitance amplifying unit is provided to amplify the first capacitor C1, under the condition that the first capacitor C1 provided in the capacitance compensation unit 13 is small, the compensation capacitor with a large capacitance value can still be obtained in a manner that the capacitance amplifying unit amplifies the first capacitor C1, the area of the first capacitor C1 provided in the capacitance compensation unit 13 of the linear voltage stabilizing circuit is reduced, and further the area of a chip where the linear voltage stabilizing circuit is located is reduced.
In some embodiments, FIG. 4 is a circuit diagram of an embodiment of a linear voltage regulator circuit provided herein, and the circuit shown in FIG. 4 illustrates one possible circuit implementation of the linear voltage regulator circuit shown in FIG. 3. As shown in fig. 4:
the voltage adjustment unit 11 includes; the amplifier EA, the first voltage-dividing resistor R1, the second voltage-dividing resistor R2 and the first Transistor MP1, the first Transistor may be a Metal Oxide Semiconductor Field Effect Transistor (Metal Oxide Semiconductor Field Effect Transistor, abbreviated as "MOSFET" or MOS, etc.) MOSFET T, taking the example that the first Transistor MP1 is a P-type MOS, the source of the first Transistor MP1 is connected to the input interface A and the drain thereof is connected to the output interface B, the first voltage-dividing resistor R1 is connected to the first Transistor MP1One end of the first divider resistor R1 is connected with the output interface B, the second end of the first divider resistor R1 is connected with the first end of the second divider resistor R2, and the second end of the second divider resistor R2 is grounded. The first voltage-dividing resistor R1 and the second voltage-dividing resistor R2 can jointly generate a feedback voltage V according to the voltage at the output interface B FB And combine V FB To a first input of an amplifier EA, a second input of which is intended to receive a reference voltage V REF . The amplifier EA can control the current flowing through the first transistor MP1 according to the difference between the feedback voltage and the reference voltage, so as to realize the voltage stabilization and adjustment of the output voltage Vout REF Vout = V REF *[(R1+R2)/R2]。
The compensation resistance unit 12 includes: a second transistor MP4 and a third transistor MN3, wherein, as shown in fig. 4, a first end of the second transistor MP4 is connected to the input interface a, a second end of the second transistor MP4 is connected to the second end of the first capacitor C1 and the first end of the third transistor MP4, a second end of the third transistor MP4 is grounded, and a first end of the first capacitor C1 is connected to the output end of the amplifier EA. The second transistor MP4 may be a P-type MOS transistor, and the third transistor MN3 may be an N-type MOS transistor. The second transistor MP4 and the third transistor MN3 are connected in parallel between the first capacitor C1 and the ground point, so that the voltage V at the second terminal of the first capacitor C1 is increased Y The impedance of the second transistor MP4 is the compensation resistor Rc provided in the compensation circuit inside the linear voltage regulator circuit, and at this time, the second transistor MP4 and the third transistor MN3 commonly obtain the compensation resistor Rc in a parallel connection manner through their respective impedances.
In some embodiments, the impedance r of the second transistor MP4 0(MP4) Can be expressed by the following formula one:
wherein, mu P Is the mobility of the electron carriers, C, of the second transistor MP4 ox Is the capacitance of the gate oxide layer in unit area,
is the width-to-length ratio, I, of the second transistor MP4 d(MP4) Is a current flowing through the second transistor MP 4.
Impedance r of the second transistor MN3 0(MN3) Can be expressed by the following formula two:
wherein, mu n Is the mobility of electron carriers, C, of the third transistor MN3 ox Is the capacitance of the gate oxide layer in unit area,
is the width-to-length ratio, I, of the third transistor MN3 d(MN3) Is the current, V, flowing through the third transistor MN3 GS Is the gate-source voltage, V, of the third transistor MN3 TH Is the threshold voltage of the third transistor MN3, and λ is the channel length modulation factor.
According to the above formula one and formula two, in the practical implementation process, the second transistor MP4 is diode-connected as in formula one
The value of the part is in the same order of magnitude as the parameter lambda in the formula two, but due to I d(MN3) ＝I d(MP4) And the current value in the circuit is a few microamperes, so that in formula one
The part will be much larger than I in equation two d(MN3) Thus, at r 0(MN3) Far greater than r 0(MP4) In this case, the impedance provided by the third transistor MN3 can be neglected, and finally the compensation resistor Rc is obtained by the following formula three:
R C ＝r o(MP4) ||r o(MN3) ≈r o(MP4) formula III
And due to the current I flowing through the second transistor MP4 d(MP4) Output current I of output interface d(MP1) Exist as followsThe relation is as follows: I.C. A d(MP4) ＝k*I d(MP1) After the above relationship is substituted into the first formula and the third formula, the following formula four is finally obtained:
as can be seen from the above formula four, the compensation resistance Rc provided by the compensation resistance unit provided by the present application is related to the current of the output interface, so that the current output to the load by the output interface in fig. 4 changes, and the compensation resistance provided by the compensation resistance unit will also change along with the current of the load.
The capacitance amplifying unit for amplifying the first capacitance C1 in the compensation capacitance unit 13 specifically includes: a second transistor MP4, a third transistor MN3, a fourth transistor MP3, a fifth transistor MN2, a sixth transistor MP2, and a seventh transistor MN1. On the basis of the connection relationship between the second transistor MP4, the third transistor MN3 and the seventh transistor MN1 in the voltage adjustment unit 11 and the compensation resistor unit 12, the first end of the fourth transistor MP3 is connected to the input interface a, the second end of the fourth transistor MP3 is connected to the first end and the control end of the fifth transistor MN2 and the control end of the third transistor MN3, the second end of the fifth transistor MN2 is grounded, the first end of the sixth transistor MP2 is connected to the input interface a, the second end and the control end of the sixth transistor MP2 are connected to the first end of the seventh transistor MN1, and the second end of the seventh transistor MN1 is grounded. In some embodiments, the fourth transistor MP3 and the sixth transistor MP2 are P-type MOS transistors, and the fifth transistor MN2 and the seventh transistor MN1 are N-type MOS transistors.
Then, when the capacitor amplifying unit is disposed between the first end and the second end formed by the upper and lower two electrode plates of the first capacitor C1, the second transistor MP4, the third transistor MN3, the fourth transistor MP3, the fifth transistor MN2, the sixth transistor MP2, and the seventh transistor MN1 in the capacitor amplifying unit together form an inverting amplifier circuit, the first capacitor C1 is connected to the input end and the output end of the inverting amplifier circuit, and it can be known from miller's theorem that the capacitor provided at the output end of the amplifier EA is equivalently amplified, and finally the equivalent capacitor Cc is obtained.
In some embodiments, the voltage V across the first capacitor C1 Y And V X Can be expressed by the formula five:
based on the same principle of the formula three, the small-signal equivalent impedance of the diode-connected sixth transistor MP2 is much smaller than that of the seventh transistor MN1, and the small-signal impedance of the seventh transistor MN1 can be omitted in the impedance of the common drain of the sixth transistor MP2 and the seventh transistor MN1. Similarly, the small signal impedance of the fourth transistor MP3 at the common drain terminal with the fifth transistor MN2 can be omitted.
G in equation five m(MN1) ，r 0(MP2) ，g m(MP3) ，r 0(MN2) ，g m(MN3) And r 0(MP4) Can be expressed by the following formulas respectively:
meanwhile, in the circuit shown in fig. 4, there is a relationship shown in the following formula twelve to formula fourteen between the second transistor MP4, the third transistor MN3, the fourth transistor MP3, the fifth transistor MN2, the sixth transistor MP2, and the seventh transistor MN1.
I d(MN1) ＝I d(MP2) ＝I d(MP3) ＝I d(MN2) ＝I d(MN3) ＝I d(MP4) Fourteen formula
The voltage V at the two sides of the first capacitor C1 can be obtained by combining the formula five-formula fourteen Y And V X Has a ratio Av of
Then, according to the miller theorem and the formula fifteen, a formula sixteenth for calculating the equivalent capacitance Cc can be obtained:
wherein, mu P Is the mobility of the electron carriers of the second transistor,
is the width-to-length ratio of the second transistor, mu N Is the mobility of the electron carriers of the seventh transistor,
is the aspect ratio of the seventh transistor.
It can be seen from the sixteenth formula that the compensation capacitor Cc provided by the compensation capacitor unit is related to the capacitance value of the first capacitor C1 and the width-to-length ratio of the seventh transistor MN1 and the second transistor MP4, so that the capacitance value of the first capacitor C1 can be amplified to obtain the compensation capacitor Cc, and the amplification factor can be determined according to the width-to-length ratio of the seventh transistor MN1 and the second transistor MP4 to reduce the capacitance value of the first capacitor C1, so that the compensation capacitor unit can still provide the compensation capacitor Cc with a large capacitance value under the condition that the first capacitor C1 is small.
Finally, in the circuit shown in fig. 4, the pole at the output terminal of the amplifier EA in the linear voltage stabilizing circuit can be represented by the following formula seventeen, and the zero can be represented by the following formula eighteen, through the compensation resistor Rc provided by the compensation resistor unit and the compensation capacitor Cc provided by the compensation capacitor unit:
wherein R is EA For the output impedance of the amplifier EA, the pole p can be seen from the seventeen equation 1 From R EA The width-to-length ratios of the first capacitor C1 and the seventh transistor MN1 and the width-to-length ratio of the second transistor MP4 are obtained, and it can be seen from the eighteenth formula that the zero point z 1 The first capacitor C1 outputs the current I of the interface d(MP1) The width-to-length ratio of the seventh transistor MN1, and the width-to-length ratio of the second transistor MP 4. Therefore, when the zero point is compensated and the current I of the output interface is d(MP1) The arithmetic square root of the voltage regulator is in direct proportion, so that the compensation zero point can change along with the current of the load, the dynamic frequency compensation is carried out on the zero point of the output end of the amplifier, and the loop stability of the linear voltage regulator circuit can still be ensured when the load current changes greatly。
In summary, the linear voltage stabilizing circuit provided by the present application can achieve the following technical effects: 1. because the compensation resistor of the linear voltage stabilizing circuit can be adjusted according to the current of the output interface, when the output interface is connected with different loads, different zero points can be subjected to frequency compensation under different conditions, so that the stability of the linear voltage stabilizing circuit can be ensured when the load current changes greatly, and a better frequency compensation effect which is more matched with the current load is realized. 2. The capacitance compensation unit is provided with the capacitance amplification unit to amplify the first capacitor, so that the compensation capacitor with a large capacitance value can be obtained by amplifying the first capacitor through the capacitance amplification unit under the condition that the first capacitor arranged in the capacitance compensation unit is small, the area of the first capacitor arranged in the capacitance compensation unit of the linear voltage stabilizing circuit is reduced, the area of a chip where the linear voltage stabilizing circuit is located is further reduced, and the cost of the chip is reduced. 3. The linear voltage stabilizing circuit has a simple circuit structure and therefore has high reliability. 4. Because the zero point is not adjusted by an output Equivalent Series Resistance (ESR), the ESR value of an output capacitor connected with the linear voltage stabilizing circuit is not required, the value of the ESR can be not limited, and the output is stable when the ESR is approximately equal to 0.
In some embodiments, as can be seen from formula four, formula sixteen, formula seventeen, and formula eighteen, when the width-to-length ratios of the second transistors MP4 are different, the amplification factors for the first capacitors are different, and the obtained compensation resistors are also different, so that, on the basis of the circuit shown in fig. 4, a plurality of candidate second transistors MP4 may be arranged in parallel according to the same connection relationship, and each candidate second transistor MP4 adopts a different width-to-length ratio. Then, one end of each of the candidate second transistors MP4 is connected to a selection switch, so that the selection switch selects one of the candidate second transistors MP4 with the aspect ratio as the second transistor MP4 in fig. 4 by switching the switch states, and then the second transistor MP4 is connected to the circuit shown in fig. 4 to operate. Therefore, the linear voltage stabilizing circuit provided by this embodiment can provide a plurality of different width-to-length ratios of the second transistor MP4, so that the linear voltage stabilizing circuit can adjust the compensation capacitor, the compensation resistor, the zero point, the pole, and the like of the linear voltage stabilizing circuit by selecting the second transistor MP4 with different width-to-length ratios. It can be understood that according to the same idea as described above, a plurality of candidate transistors may also be provided in the seventh transistor shown in fig. 4, and the candidate transistors are selected through the selection switch, and the specific implementation and principle thereof are the same and will not be described again.
In another embodiment of the present application, based on the foregoing embodiments, the present application further provides a frequency compensation method for a linear voltage regulator circuit, for example, the compensation capacitor Cc may be determined first (e.g., calculated according to formula sixteen), and the current I of the output interface may be collected d(MP1) And a feedback voltage V FB (ii) a Subsequently, the current I according to the output interface is calculated by the formula four d(MP1) Determining a compensation resistance Rc; finally according to the feedback voltage V FB The compensation capacitor Cc and the compensation resistor Rc are used for compensating the dynamic frequency of a voltage stabilizing loop of the linear voltage stabilizing circuit when the linear voltage stabilizing circuit adjusts the input voltage VDD of the input interface and outputs the voltage Vout from the output interface.
Finally, it should be noted that: the above embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and these modifications or substitutions do not depart from the scope of the technical solutions of the embodiments of the present application.
Claims (10)
1. A linear voltage regulator circuit, comprising:
an input interface for inputting a voltage;
an output interface for outputting a voltage;
the voltage adjusting unit is arranged between the input interface and the output interface and used for adjusting the voltage of the input interface according to the feedback voltage of the output interface and then outputting the voltage from the output interface;
the compensation resistance unit is connected with the voltage adjusting unit and is used for providing compensation resistance required by adjusting voltage to the voltage adjusting unit; wherein the compensation resistance is determined from a current of the output interface;
the compensation capacitor unit is connected with the voltage adjusting unit and is used for providing compensation capacitors required by voltage adjustment to the voltage adjusting unit; wherein the compensation capacitance unit includes: the capacitor amplifying unit is used for amplifying the capacitance value of the first capacitor to obtain the compensation capacitor.
2. The linear voltage regulating circuit of claim 1, wherein the voltage regulation unit comprises:
an amplifier, a first voltage-dividing resistor, a second voltage-dividing resistor, and a first transistor;
wherein the first transistor is disposed between the input interface and the output interface; a first end of the first voltage-dividing resistor is connected to the output interface, and a second end of the first voltage-dividing resistor is connected to a first end of the second voltage-dividing resistor and a first input end of the amplifier; a second terminal of the second voltage-dividing resistor is grounded, a second input terminal of the amplifier is configured to receive a reference voltage, and an output terminal of the amplifier is connected to the control terminal of the first transistor and the first terminal of the first capacitor.
3. The linear voltage regulating circuit of claim 1, wherein the compensation resistance unit comprises:
a second transistor and a third transistor; the second end of the first capacitor is connected to the second end and the control end of the second transistor and the first end of the third transistor, the first end of the second transistor is connected to the input interface, and the second end of the third transistor is grounded.
4. The linear voltage regulator circuit of claim 3, wherein the compensation resistor R provided by the compensation resistor unit c The method comprises the following steps:
wherein, mu P Is the mobility of the electron carrier of the second transistor, C ox Is the capacitance of the gate oxide layer in unit area,
is the width-to-length ratio of the second transistor, I d(MP4) Is the current of the second transistor, I d(MP1) For outputting the current of the interface, I d(MP4) ＝k·I d(MP1) 。
5. The linear voltage regulating circuit of any of claims 1-4, wherein the capacitive amplification unit comprises:
a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor;
a first terminal of the fourth transistor is connected to the input interface, a second terminal of the fourth transistor is connected to the first terminal and the control terminal of the fifth transistor and the control terminal of the third transistor, a second terminal of the fifth transistor is grounded, a first terminal of the sixth transistor is connected to the input interface, a second terminal and the control terminal of the sixth transistor are connected to the first terminal of the seventh transistor, and a second terminal of the seventh transistor is grounded.
6. The linear voltage regulating circuit of claim 5, wherein the capacitance amplifying unit is a compensation capacitor C obtained by amplifying the capacitance value C1 of the first capacitor c The method comprises the following steps:
wherein, mu P Is the mobility of the electron carriers of the second transistor,
is the width-to-length ratio, mu, of the second transistor N Is the mobility of the electron carriers of the seventh transistor,
is the width-to-length ratio of the seventh transistor.
7. The linear voltage regulating circuit of claim 6,
the pole of the output voltage of the amplifier is obtained by calculation through the compensation capacitor and the resistance of the amplifier;
and the zero point of the output voltage of the amplifier is obtained by calculation through the compensation capacitor and the compensation resistor.
8. The linear voltage regulating circuit of claim 7,
pole p of the amplifier output voltage 1 Is composed of
Zero z of the output voltage of the amplifier 1 Is composed of
9. The linear voltage regulating circuit according to any of claims 1-4,
the compensation capacitance unit further includes: a selection switch and a plurality of candidate second transistors; the width-to-length ratio of each of the candidate second transistors is different;
a first end of the candidate second transistor is connected with the input interface, and a second end of the first capacitor is connected with a second end and a control end of the candidate second transistor through the selection switch; or the first end of the candidate second transistor is connected with the input interface through the selection switch, and the second end of the first capacitor is connected with the second end and the control end of the candidate second transistor;
the selection switch is configured to determine one of the plurality of candidate second transistors as the second transistor.
10. A method for frequency compensation of a linear voltage regulator circuit, comprising:
determining a compensation capacitor, the current of an output interface and a feedback voltage;
determining a compensation resistor according to the current of the output interface;
and performing frequency compensation on the linear voltage stabilizing circuit according to the feedback voltage, the compensation capacitor and the compensation resistor.
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