CN115706140A - Fin manufacturing method, fin field effect transistor and fin field effect transistor manufacturing method - Google Patents

Abstract

The application discloses a fin preparation method, a fin field effect transistor and a fin preparation method, wherein the fin preparation method comprises the following steps: forming a plurality of polysilicon layers arranged in parallel at a preset interval on a semiconductor substrate; oxidizing the side wall of each polycrystalline silicon layer, and forming an oxide layer with a preset thickness extending inwards from the outer surface of the side wall on the side wall of each polycrystalline silicon layer; removing the residual polysilicon layer; etching the semiconductor substrate to form a fin by using the oxide layer as a mask; the critical dimension of the fin is adjusted according to the thickness of the oxide layer; the oxide layer that is preserved on the fin is removed. According to the method, firstly, the side wall of the polycrystalline silicon layer is oxidized to form an oxidation layer which extends inwards from the outer surface of the side wall to the preset thickness at the side wall, then the oxidation layer is used as a mask to etch the semiconductor substrate to form the fin, the key size of the fin can be controlled by controlling the thickness of the oxidation layer, the method is suitable for preparing fins with different key sizes, and the prepared fin has vertical side walls and good uniformity.

Description

Fin manufacturing method, fin field effect transistor and fin field effect transistor manufacturing method

Technical Field

The application relates to the technical field of semiconductor correlation, in particular to a fin preparation method, a fin field effect transistor and a fin field effect transistor preparation method.

Background

In a Complementary Metal Oxide Semiconductor (CMOS) device, the performance of the device is improved mainly by reducing the size of the device, and in order to adapt to a small-sized device, the channel length of the device needs to be adaptively reduced, which easily causes a short channel effect. In order to improve short channel effect and improve device performance, a fin field effect transistor is widely used.

The fin field effect transistor comprises a semiconductor substrate and a fin arranged on the semiconductor substrate, and when the size of the fin field effect transistor is reduced, the critical dimension of the fin is also correspondingly reduced. Conventional methods for manufacturing small-sized fins include self-aligned dual imaging (SADP) and dual lithography (LELE), both of which have some disadvantages, for example, the manufacturing process of the self-aligned dual imaging (SADP) is complicated, the obtained fins have an asymmetric structure, and the heights of the fins at different positions have large deviation and poor uniformity; the process of double lithography (LELE) is also complicated, and the requirement for photolithography and etching equipment is very high, which requires high cost.

Therefore, it is an urgent need in the art to provide a fin fabrication method to improve fin uniformity while simplifying the fabrication process and reducing the cost.

Disclosure of Invention

The present disclosure provides a method for fabricating a fin, in which a sidewall of a polysilicon layer is oxidized to form an oxide layer, and a semiconductor substrate is etched using the oxide layer as a mask to form a fin having a predetermined critical dimension, wherein the fin has a vertical sidewall and good uniformity.

Another objective is to provide a fin field effect transistor and a method for fabricating the same.

In a first aspect, an embodiment of the present application provides a method for manufacturing a fin, including:

forming a plurality of polysilicon layers arranged in parallel at a preset interval on a semiconductor substrate;

oxidizing the side wall of each polycrystalline silicon layer, and forming an oxide layer with a preset thickness extending inwards from the outer surface of the side wall on the side wall of each polycrystalline silicon layer;

removing the residual polysilicon layer; etching the semiconductor substrate to form a fin by taking the oxide layer as a mask; the critical dimension of the fin is adjusted according to the thickness of the oxide layer;

the oxide layer that is preserved on the fin is removed.

In a possible embodiment, before forming a plurality of polysilicon layers arranged in parallel at a predetermined pitch on a semiconductor substrate, the method further includes:

and forming a protective layer on the surface of the semiconductor substrate for forming the polycrystalline silicon layer, wherein the protective layer comprises a silicon dioxide layer.

In one possible embodiment, in the step of forming a plurality of polysilicon layers arranged in parallel at a predetermined pitch on the semiconductor substrate, a surface of each of the polysilicon layers remote from the semiconductor substrate includes a barrier layer.

In one possible embodiment, oxidizing sidewalls of each of the polysilicon layers and forming an oxide layer on the sidewalls of each of the polysilicon layers extending inward from outer surfaces of the sidewalls by a predetermined thickness includes:

oxidizing the side wall of each polycrystalline silicon layer by adopting an in-situ water vapor oxidation process;

and adjusting parameters of the in-situ water vapor oxidation process according to the target critical dimension of the fin, and forming an oxidation layer with a preset thickness extending inwards from the outer surface of the side wall on the side wall of each polycrystalline silicon layer.

In one possible embodiment, the thickness of the oxide layer at the sidewalls of each polysilicon layer is the same; the height of the oxide layer on the side wall of each polysilicon layer is the same and is greater than that of the polysilicon layer.

In one possible implementation, the thickness of the oxide layer is equal to the target critical dimension of the fin.

In one possible embodiment, the target critical dimension of the fin is 1 to 2nm; or the target key size of the fin is 2-10 nm; alternatively, the target critical dimension of the fin is 10-15 nm.

In one possible embodiment, the parameters of the in situ moisture oxidation process include oxidation temperature, oxidation time, and moisture content.

In one possible embodiment, the surface of the oxide layer away from the semiconductor substrate is parallel to the semiconductor substrate, and the sidewalls of the oxide layer are vertical sidewalls.

In one possible implementation, the sidewalls of the fins are vertical sidewalls, and the heights of the fins at different positions are the same.

In one possible embodiment, the barrier layer comprises silicon nitride.

In one possible embodiment, the semiconductor base comprises a single crystal silicon substrate or a silicon-on-insulator (SOI) substrate.

In a second aspect, an embodiment of the present application provides a method for manufacturing a fin field effect transistor, including:

forming a fin on the semiconductor substrate, wherein the fin is manufactured by adopting the preparation method of the fin in the embodiment; a groove is arranged between the adjacent fins;

forming a trench isolation layer at the trench between adjacent fins, the trench isolation layer having a height less than the height of the fins;

forming a stacked structure on the trench isolation layer, wherein the extending direction of the stacked structure is parallel to the arrangement direction of the fins, and the stacked structure exceeds the preset height of the fins;

forming a strained layer on the fins on opposite sides of the stacked structure;

and removing the stacked structure, and forming a gate stack on the trench isolation layer, wherein the extending direction of the gate stack is parallel to the arrangement direction of the fins, and the gate stack exceeds the fins by a preset height.

In a third aspect, embodiments of the present application provide a fin field effect transistor, where the fin field effect transistor is manufactured by using the method for manufacturing a fin field effect transistor in the foregoing embodiments.

Compared with the prior art, the application has at least the following beneficial effects:

the method comprises the steps of firstly oxidizing the side wall of a polycrystalline silicon layer to form an oxidation layer which extends inwards from the outer surface of the side wall to a preset thickness on the side wall, then etching a semiconductor substrate by using the oxidation layer as a mask to form a fin, controlling the key size of the fin by controlling the thickness of the oxidation layer, and being applicable to preparing fins with different key sizes. The oxide layer has good uniformity, the surface of the oxide layer far away from the semiconductor substrate is parallel to the semiconductor substrate, and the side wall of the oxide layer is a vertical side wall, so that the manufactured fin has the vertical side wall and good uniformity. The thickness of the oxide layer is determined by the target critical dimension of the fin, and can be obtained by adjusting the oxidation temperature, the oxidation time and the water vapor content parameters in the in-situ water vapor oxidation process.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained from the drawings without inventive effort.

Fig. 1 is a schematic diagram illustrating a method of fabricating a fin according to an embodiment of the present disclosure;

FIGS. 2-8 are schematic cross-sectional views of a fin shown at various stages of fabrication according to embodiments of the present application;

fig. 9 is a schematic perspective view of a finfet in accordance with an embodiment of the present application;

fig. 10-12 are schematic cross-sectional viewsbase:Sub>A-base:Sub>A of the finfet shown in fig. 9 at different stages of fabrication;

fig. 13 is a schematic cross-sectional B-B view of the finfet shown in fig. 9.

Illustration of the drawings:

100 a semiconductor substrate; 200 a protective layer; 300 a polysilicon layer; 310 an oxide layer; 400 a barrier layer; 500 fins; 510 a groove; 600 a trench isolation layer; 700 a stacked structure; 800 a strained layer; 900 gate stack.

Detailed Description

The following embodiments are provided to illustrate the present disclosure by way of specific examples, and other advantages and effects of the present disclosure will be apparent to those skilled in the art from the disclosure herein. The present application is capable of other and different embodiments and its several details are capable of modifications and variations in various respects, all without departing from the spirit of the present application.

In the description of the present application, it should be noted that the terms "upper" and "lower" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings or orientations or positional relationships that the products of the application usually place when using, and are only used for convenience in describing the present application and simplifying the description, but do not indicate or imply that the devices or elements that are referred to must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present application.

According to one aspect of the present application, a method of making a fin is provided. Referring to fig. 1, the method for manufacturing the fin includes the following steps:

s1, forming a plurality of polysilicon layers 300 arranged in parallel at a predetermined pitch on the semiconductor substrate 100.

By way of example, the semiconductor base 100 includes, but is not limited to, a single crystal silicon substrate or a silicon-on-insulator (SOI) substrate, and the semiconductor base 100 may be selected as a P-type single crystal silicon substrate having an N-well, or an N-type single crystal silicon substrate having a P-well, or a silicon-on-insulator (SOI) substrate. In this embodiment, the semiconductor substrate 100 is a silicon-on-insulator (SOI) substrate including a silicon substrate and an epitaxial silicon layer formed on the silicon substrate, the epitaxial silicon layer having a P-well region and an N-well region.

As an example, referring to fig. 2, a protective layer 200 is formed on a surface of the semiconductor substrate 100 for forming a polysilicon layer 300, the protective layer 200 serving to protect the semiconductor substrate 100. The material of the protection layer 200 includes, but is not limited to, silicon dioxide, which can be deposited on the upper surface of the semiconductor substrate 100 by atomic layer deposition, physical vapor deposition or chemical vapor deposition.

As an example, referring to fig. 3 and 4, a polysilicon layer 300 and a barrier layer 400 are sequentially formed on an upper surface of the protective layer 200, and the polysilicon layer 300 and the barrier layer 400 are etched to form a polysilicon layer array, wherein the polysilicon layer array includes a plurality of cells arranged in parallel at a predetermined interval on the protective layer 200, and each cell includes the polysilicon layer 300 and the barrier layer 400 formed on an upper surface of the polysilicon layer 300. The polysilicon layer 300 and the barrier layer 400 can be grown by atomic layer deposition, physical vapor deposition or chemical vapor deposition, and the material of the barrier layer 400 includes, but is not limited to, silicon nitride.

And S2, oxidizing the side wall of each polycrystalline silicon layer 300, and forming an oxidation layer 310 which extends inwards from the outer surface of the side wall by a preset thickness on the side wall of each polycrystalline silicon layer 300.

As an example, referring to fig. 5, the sidewalls of each polysilicon layer 300 are oxidized using an in-situ moisture oxidation process, parameters of the in-situ moisture oxidation process are adjusted according to a target critical dimension of the fin 500, and an oxide layer 310 is formed on the sidewalls of each polysilicon layer 300 to extend inward from the outer surface of the sidewalls by a predetermined thickness. Parameters of the in-situ water vapor oxidation process include an oxidation temperature, an oxidation time, and a water vapor content, and the oxide layer 310 having a thickness corresponding to the target critical dimension of the fin 500 can be obtained by selecting an appropriate oxidation temperature, oxidation time, and water vapor content. The oxide layer 310 is specifically a silicon dioxide layer.

During the formation of the oxide layer 310, the barrier layer 400 serves to protect the polysilicon layer 300 from being oxidized, and at the same time, to make the upper surface of the oxide layer 310 parallel to the semiconductor substrate 100. The oxide layer 310 formed by the above method has vertical sidewalls and good uniformity.

As an example, referring to fig. 5, the thickness of the oxide layer 310 at the sidewall of each polysilicon layer 300 is the same, the thickness of the oxide layer 310 is equal to the target critical dimension of the fin 500, and the target critical dimension of the fin 500 may be specifically selected to be 1-2 nm, or, 2-10 nm, or, 10-15 nm. The critical dimension of the fin 500 can be controlled by controlling the thickness of the oxide layer 310, which is suitable for manufacturing fins 500 with different critical dimensions.

The height of the oxide layer 310 at the sidewall of each polysilicon layer 300 is the same and is greater than the height of the polysilicon layer 300. In the process of oxidizing polysilicon into silicon dioxide, the volume of silicon dioxide is increased compared to polysilicon, and the height of the oxide layer 310 on the sidewall of each polysilicon layer 300 is greater than the height of the polysilicon layer 300, so the height of the barrier layer 400 above the oxide layer 310 is also increased.

As an example, after the oxide layer 310 is formed, the oxide layer 310 is annealed, and the annealing is plasma annealing at 950 to 1050 ℃ for 30 to 60 seconds.

S3, removing the residual polycrystalline silicon layer 300; etching the semiconductor substrate 100 to form a fin 500 by using the oxide layer 310 as a mask; the critical dimensions of fin 500 are adjusted according to the thickness of oxide layer 310.

As an example, referring to fig. 6, the remaining polysilicon layer 300 and the barrier layer 400 are removed by wet cleaning or dry cleaning. For example, the remaining polysilicon layer 300 and the barrier layer 400 are removed by wet etching using diluted potassium hydroxide or phosphoric acid; alternatively, the remaining polysilicon layer 300 and the barrier layer 400 are removed using a plasma etching method. In this embodiment, a wet cleaning process is preferably used to remove the remaining polysilicon layer 300 and the barrier layer 400, and the extremely high selectivity ratio can make the upper surface and the sidewalls of the oxide layer 310 have better flatness, which can also be described as better levelness of the upper surface of the oxide layer 310 and better verticality of the sidewalls of the oxide layer 310.

As an example, referring to fig. 7, the epitaxial silicon layer of the semiconductor substrate 100 and the protective layer 200 are etched until the inside of the epitaxial silicon layer is etched using the oxide layer 310 as a mask to form the fin 500. The critical dimension of fin 500 is the width of fin 500, which is adjusted according to the thickness of oxide layer 310.

Since the top surface of the oxide layer 310 is parallel to the semiconductor substrate 100, and the sidewalls are vertical sidewalls and have good uniformity, the sidewalls of the fin 500 obtained by using the oxide layer 310 as a mask are vertical sidewalls, and the heights of the fins 500 at different positions are the same, thereby effectively reducing the height deviation of the fin 500 and having good uniformity.

And S4, removing the oxide layer 310 which is preserved on the fin 500.

As an example, referring to fig. 8, the oxide layer 310, which is to be left on the fins 500, is removed by wet etching using diluted hydrofluoric acid, and trenches 510 are included between adjacent fins 500.

The method of the present embodiment can control the critical dimension of the fin 500 by controlling the thickness of the oxide layer 310, so as to be suitable for manufacturing fins 500 with different critical dimensions. Moreover, the oxide layer 310 has good uniformity, the upper surface of the oxide layer is parallel to the semiconductor substrate 100, and the sidewall is a vertical sidewall, so that the fin 500 obtained by using the oxide layer 310 as a mask has a vertical sidewall, and the heights of the fins 500 at different positions are the same, thereby effectively reducing the height deviation of the fin 500 and having good uniformity.

According to one aspect of the application, a method for manufacturing a fin field effect transistor is provided. Fig. 9 is a schematic perspective view of a finfet, which is fabricated by a method comprising:

s10, forming a fin 500 on the semiconductor substrate 100, where the fin 500 is manufactured by the fin manufacturing method in the above embodiment, and details of the fin manufacturing process are not repeated here. Trenches 510 are included between adjacent fins 500.

S20, a trench isolation layer 600 is formed at the trench 510 between the adjacent fins 500, and the height of the trench isolation layer 600 is less than the height of the fins 500.

As an example, referring to fig. 10, a trench isolation layer 600 is formed at the trench 510 between adjacent fins 500, and in particular, an isolation oxide layer is formed at the trench 510, the isolation oxide layer exceeding the fins 500 by a predetermined height and completely covering the fins 500. The isolation oxide layer is etched to remove the isolation oxide layer around the upper portion of the fin 500, exposing the upper portion of the fin 500, the remaining isolation oxide layer forms a trench isolation layer 600, and the trench isolation layer 600 has a height less than the height of the fin 500.

S30, a stacked structure 700 is formed on the trench isolation layer 600, an extending direction of the stacked structure 700 is parallel to an arrangement direction of the fins 500, and the stacked structure 700 exceeds the fins 500 by a predetermined height.

As an example, referring to fig. 11, a stacked structure 700 is formed on the trench isolation layer 600, wherein the extending direction of the stacked structure 700 is parallel to the arrangement direction of the fins 500, which can also be described as the stacked structure 700 crosses the trench 510 between adjacent fins 500. The stacked structure 700 exceeds the fin 500 by a predetermined height. In this embodiment, the stacked structure 700 includes a polysilicon strip and a hard mask strip over the polysilicon strip, the hard mask strip being formed of silicon nitride, silicon oxide, or a combination thereof. Sidewalls of the polysilicon strips and the hard mask strips include spacers.

S40, a strained layer 800 is formed on the fin 500 on opposite sides of the stacked structure 700.

As an example, referring to fig. 13, a strained layer 800 is formed on the fin 500 on opposite sides of the stacked structure 700, the strained layer 800 serving as a source region and a drain region, and the material of the strained layer 800 includes silicon germanium, silicon carbide, or silicon phosphide.

S50, removing the stacked structure 700, and forming a gate stack 900 on the trench isolation layer 600, wherein an extending direction of the gate stack 900 is parallel to an arrangement direction of the fins 500, and the gate stack 700 exceeds the fins 500 by a predetermined height.

By way of example, referring to fig. 12, the polysilicon strips and the hard mask strips in the stacked structure 700 are removed, and a gate stack 900 is formed within the recess defined by the spacers on the trench isolation layer 600, the gate stack 900 including a gate dielectric layer and a gate electrode layer, the gate dielectric layer being formed of silicon nitride, silicon oxide, or a combination thereof. The extending direction of the gate stack 900 is parallel to the arrangement direction of the fins 500, which can also be described as the gate stack 900 crossing the trenches 510 between adjacent fins 500. The stacked structure 700 exceeds the fin 500 by a predetermined height.

According to an aspect of the present application, a fin field effect transistor is provided, which is manufactured by the method for manufacturing the fin field effect transistor in the above embodiment. A detailed description thereof will be omitted.

As can be seen from the above technical solutions, the sidewall of the polysilicon layer 300 is first oxidized to form an oxide layer 310 extending inward from the outer surface of the sidewall by a predetermined thickness at the sidewall, and then the semiconductor substrate 100 is etched by using the oxide layer 310 as a mask to form the fin 500, so that the critical dimension of the fin 500 can be controlled by controlling the thickness of the oxide layer 310, and the method is suitable for preparing fins 500 with different critical dimensions. The surface of each polysilicon layer 300 away from the semiconductor substrate 100 includes a barrier layer 400, the barrier layer 400 ensures that the surface of the oxide layer 310 away from the semiconductor substrate 100 is parallel to the semiconductor substrate 100, and the sidewalls of the oxide layer 310 are vertical sidewalls, the oxide layer 310 has good uniformity, thereby ensuring that the fin 500 has vertical sidewalls and good uniformity. The thickness of the oxide layer 310 is determined by the target critical dimension of the fin 500, and can be obtained by adjusting the oxidation temperature, the oxidation time, and the moisture content parameters in the in-situ moisture oxidation process.

The foregoing is only a preferred embodiment of the present application, and it should be noted that, for those skilled in the art, many modifications and substitutions can be made without departing from the technical principle of the present application, and these modifications and substitutions should also be regarded as the protection scope of the present application.

Claims (14)

1. A method for preparing a fin, comprising:

forming a plurality of polysilicon layers arranged in parallel at a preset interval on a semiconductor substrate;

oxidizing the side wall of each polycrystalline silicon layer, and forming an oxide layer with a preset thickness extending inwards from the outer surface of the side wall on the side wall of each polycrystalline silicon layer;

removing the residual polysilicon layer; etching the semiconductor substrate to form a fin by taking the oxide layer as a mask; the critical dimension of the fin is adjusted according to the thickness of the oxide layer;

and removing the oxide layer reserved on the fin.

2. The method for preparing a fin according to claim 1, wherein before forming a plurality of polysilicon layers arranged in parallel at a predetermined pitch on the semiconductor substrate, the method further comprises:

and forming a protective layer on the surface of the semiconductor substrate for forming the polycrystalline silicon layer, wherein the protective layer comprises a silicon dioxide layer.

3. The method of claim 1, wherein in the step of forming a plurality of polysilicon layers arranged in parallel at a predetermined pitch on the semiconductor substrate, a surface of each of the polysilicon layers remote from the semiconductor substrate comprises a barrier layer.

4. The method of claim 1, wherein the step of oxidizing sidewalls of each polysilicon layer and forming an oxide layer on the sidewalls of each polysilicon layer extending inward from an outer surface of the sidewalls by a predetermined thickness comprises:

oxidizing the side wall of each polycrystalline silicon layer by adopting an in-situ water vapor oxidation process;

and adjusting parameters of the in-situ water vapor oxidation process according to the target critical dimension of the fin, and forming an oxidation layer with a preset thickness extending inwards from the outer surface of the side wall on the side wall of each polycrystalline silicon layer.

5. The method of fabricating fins according to claim 4, wherein the thickness of the oxide layer at the sidewalls of each of the polysilicon layers is the same; the height of the oxide layer on the side wall of each polycrystalline silicon layer is the same and is greater than that of the polycrystalline silicon layer.

6. The method of claim 4, wherein a thickness of the oxide layer is equal to a target critical dimension of the fin.

7. The method of claim 4, wherein the fin has a target critical dimension of 1-2 nm; or the target critical dimension of the fin is 2-10 nm; alternatively, the target critical dimension of the fin is 10-15 nm.

8. The method of manufacturing a fin according to claim 4, wherein the parameters of the in-situ moisture oxidation process include oxidation temperature, oxidation time, and moisture content.

9. The method of claim 4, wherein a surface of the oxide layer remote from the semiconductor substrate is parallel to the semiconductor substrate, and wherein sidewalls of the oxide layer are vertical sidewalls.

10. The method for manufacturing a fin according to any one of claims 1 to 9, wherein the sidewall of the fin is a vertical sidewall, and heights of the fins located at different positions are the same.

11. The method of fabricating a fin according to claim 1, wherein the barrier layer comprises silicon nitride.

12. The method of fabricating a fin according to claim 1, wherein the semiconductor base includes a single crystal silicon substrate or a silicon-on-insulator (SOI) substrate.

13. A method for manufacturing a fin field effect transistor is characterized by comprising the following steps:

forming a fin on a semiconductor substrate, wherein the fin is manufactured by the fin manufacturing method according to any one of claims 1 to 12; a groove is arranged between the adjacent fins;

forming a trench isolation layer at the trench between adjacent fins, a height of the trench isolation layer being less than a height of the fins;

forming a stacked structure on the trench isolation layer, wherein the extending direction of the stacked structure is parallel to the arrangement direction of the fins, and the stacked structure exceeds the fins by a preset height;

forming a strained layer on the fins on opposite sides of the stacked structure;

and removing the stacked structure, and forming a gate stack on the trench isolation layer, wherein the extending direction of the gate stack is parallel to the arrangement direction of the fins, and the gate stack exceeds the fins by a preset height.

14. The fin field effect transistor manufactured by the method of claim 13.

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