CN115705995A - Nitride epitaxial structure and preparation method thereof - Google Patents

Abstract

The invention relates to a nitride epitaxial structure and a preparation method thereof, wherein the preparation method of the nitride epitaxial structure comprises the steps of growing a nitride epitaxial layer and a first dielectric layer on the upper surface of a substrate in sequence, etching the edge area of at least one side of the first dielectric layer to expose part of the substrate, removing the edge area of at least one side of the nitride epitaxial layer while etching to expose the middle part area with lower stress, so that the stress between the edge area of the nitride epitaxial layer on the side and the substrate is released, and the edge area of the substrate on the side is exposed out of the nitride epitaxial layer, so that the edge area of the etched nitride epitaxial layer on the side can be protected from collision of objects from the side direction under certain conditions, and finally, the wafer warping and cracking caused by separation of the edge of the nitride epitaxial layer from the substrate are avoided.

Description

Nitride epitaxial structure and preparation method thereof

Technical Field

The invention relates to the technical field of semiconductors, in particular to a nitride epitaxial structure and a preparation method thereof.

Background

When a silicon device production line is used for researching and developing a silicon-based GaN power device at present, a GaN epitaxial layer and a Si substrate are of a heterostructure, so that a silicon-based GaN epitaxial layer has large stress, and a wafer is easy to warp or crack in a thermal process during wafer flowing and cannot continue to flow.

The warping and cracking of the wafer are usually avoided by increasing the thickness of the silicon-based substrate, but the method only reduces the probability of the problem to a certain extent, does not fundamentally solve the problem, and also influences the overall thickness of the GaN epitaxial wafer due to the increase of the thickness of the substrate.

Disclosure of Invention

In view of the above, there is a need for a nitride epitaxial structure and a method for fabricating the same, which can effectively improve the problems of wafer warpage and chipping.

A preparation method of a nitride epitaxial structure comprises the following steps:

providing a substrate;

growing a nitride epitaxial layer on the upper surface of the substrate;

growing a first dielectric layer on the upper surface of the nitride epitaxial layer;

and etching the edge area of at least one side of the first dielectric layer to expose part of the substrate.

In one embodiment, the etching depth of the edge region extends to the inside of the substrate.

In one embodiment, the method further comprises:

and growing a second dielectric layer on the first dielectric layer, wherein the second dielectric layer surrounds the first dielectric layer and at least covers the etched side wall of the nitride epitaxial layer.

In one embodiment, the etching the edge region of at least one side of the first dielectric layer includes:

forming a mask layer on the upper surface of the first dielectric layer;

patterning the mask layer to enable the mask layer to expose the edge area of at least one side of the first dielectric layer;

and etching the edge area of at least one side of the first dielectric layer by taking the patterned mask layer as a mask.

In one embodiment, the etching the edge region of at least one side of the first dielectric layer to expose part of the substrate includes:

and etching the edge area around the first dielectric layer to expose part of the substrate.

In one embodiment, the orthographic projection shape of the edge region around the first medium layer on the upper surface of the substrate is annular.

In one embodiment, the width of the loop ranges from 3mm to 7mm.

In one embodiment, the edge regions on the same side have a gradual size in a direction parallel to the upper surface of the substrate.

A nitride epitaxial structure is prepared by the preparation method of the nitride epitaxial structure.

In one embodiment, the nitride epitaxial structure includes:

a substrate;

the nitride epitaxial layer is positioned on the upper surface of the substrate and exposes the edge area of at least one side of the substrate;

and the first dielectric layer is positioned on the upper surface of the nitride epitaxial layer.

In one embodiment, the thickness of the exposed edge region of the substrate is less than the thickness of the region of the substrate covered by the nitride epitaxial layer.

According to the preparation method of the nitride epitaxial structure, the nitride epitaxial layer and the first dielectric layer are sequentially grown on the upper surface of the substrate, then the edge area of at least one side of the first dielectric layer is etched to expose part of the substrate, the edge area of at least one side of the nitride epitaxial layer is removed through etching to expose the middle part area with smaller stress because the stress between the edge area of the nitride epitaxial layer and the substrate is higher than that between the middle area of the nitride epitaxial layer and the substrate in the epitaxial growth process, so that the stress between the edge area of the nitride epitaxial layer and the substrate on the side is released, and the edge area of the substrate on the side is exposed out of the nitride epitaxial layer, so that the edge area of the etched nitride epitaxial layer on the side can be protected from collision of objects from the side direction, and finally the wafer warping and cracking caused by separation of the edge of the nitride epitaxial layer and the substrate are avoided.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments or the conventional technologies of the present application, the drawings used in the description of the embodiments or the conventional technologies will be briefly introduced below, it is obvious that the drawings in the description below are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.

Fig. 1 is a schematic flow chart illustrating a method for fabricating a nitride epitaxial structure according to an embodiment;

FIG. 2 is a top view of a nitride epitaxial structure before etching according to one embodiment;

FIG. 3 is a longitudinal sectional view of a nitride epitaxial structure before etching in accordance with one embodiment;

FIG. 4 is a top view of a nitride epitaxial structure before etching according to another embodiment;

FIG. 5 is a top view of an etched nitride epitaxial structure of an embodiment;

FIG. 6 is a longitudinal cross-sectional view of an etched nitride epitaxial structure of an embodiment;

FIG. 7 is a top view of an etched nitride epitaxial structure according to another embodiment;

FIG. 8 is a longitudinal sectional view of an etched nitride epitaxial structure according to another embodiment;

FIG. 9 is a longitudinal sectional view of an etched nitride epitaxial structure according to another embodiment;

FIG. 10 is a longitudinal sectional view of an etched nitride epitaxial structure according to another embodiment;

FIG. 11 is a top view of an etched nitride epitaxial structure according to another embodiment;

fig. 12 is a top view of an etched nitride epitaxial structure of another embodiment;

FIG. 13 is a top view of an etched nitride epitaxial structure according to another embodiment;

FIG. 14 is a top view of an etched nitride epitaxial structure of another embodiment;

fig. 15 is a longitudinal sectional view of an etched nitride epitaxial structure of another embodiment.

Description of the reference numerals:

101, a substrate; 102, a nitride epitaxial layer; 103, a first dielectric layer; 104, a second dielectric layer; w, width

Detailed Description

To facilitate an understanding of the present application, the present application will now be described more fully with reference to the accompanying drawings. Embodiments of the present application are given in the accompanying drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the present application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

It will be understood that, as used herein, the terms "first," "second," and the like may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another. For example, a first resistance may be referred to as a second resistance, and similarly, a second resistance may be referred to as a first resistance, without departing from the scope of the present application. The first resistance and the second resistance are both resistances, but they are not the same resistance.

It is to be understood that "connection" in the following embodiments is to be understood as "electrical connection", "communication connection", and the like if the connected circuits, modules, units, and the like have communication of electrical signals or data with each other.

As used herein, the singular forms "a", "an" and "the" may include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises/comprising," "includes" or "including," etc., specify the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. Also, as used in this specification, the term "and/or" includes any and all combinations of the associated listed items.

Fig. 1 is a schematic flow chart of a method for fabricating a nitride epitaxial structure according to an embodiment, as shown in fig. 1, the method includes steps S110 to S140.

In step S110, a substrate 101 is provided.

Alternatively, the substrate 101 may be a silicon-containing substrate 101, such as a monocrystalline silicon substrate 101, which may have a conventional thickness, such as about 675 um.

It can be understood that the nitride epitaxial structure mainly uses GaN material as epitaxial layer, the epitaxy is mainly heteroepitaxy, the substrate and epitaxial layer are heterostructure, and the material of the hetero-substrate 101 mainly includes sapphire, siC, si, etc. Most of the currently widely used blue LEDs are manufactured by growing GaN epitaxial layers on sapphire, and the silicon substrate 101 has the advantages of large size, good heat dissipation, low price, capability of being integrated with a traditional silicon circuit and the like compared with the sapphire substrate 101.

Wherein at least one surface of the substrate 101 is polished by a polishing process. It can be understood that during the processing of the substrate 101, a damaged layer may be formed on the surface of the silicon wafer by the multi-wire cutting, grinding, and the like, so that the surface of the substrate 101 has a certain roughness. Polishing is a process of further obtaining a smoother and smoother surface by a chemical mechanical grinding mode on the basis of grinding plates. The polishing can remove the damaged layer on the surface of the substrate 101 and reduce the roughness of the surface of the substrate 101, for example, the surface roughness of the substrate 101 before polishing can reach 10-20 microns, and the surface roughness of the substrate 101 after polishing can be reduced to timely nanometers, thereby facilitating the growth of subsequent material layers.

In step S120, a nitride epitaxial layer 102 is grown on the upper surface of the substrate 101.

Alternatively, the nitride epitaxial layer 102 may use a nitride material, such as AlGaN or GaN.

Among them, the nitride epitaxial layer 102 may be a gallium nitride (GaN) epitaxial layer, and gallium nitride (GaN) is used as a third generation wide bandgap semiconductor material, compared with a second generation semiconductor material represented by gallium arsenide (GaAs) and indium phosphide (InP), the nitride epitaxial layer has the advantages of large bandgap, high breakdown voltage, high two-dimensional electron gas concentration, high saturated electron velocity, and the like, and the second generation semiconductor material has scarce resources, is expensive, has toxicity, and may cause environmental pollution, so the gallium nitride material is widely used in semiconductor devices. The thickness of the nitride epitaxial layer 102 may be in the micron order.

The growth process of the nitride epitaxial layer 102 may be, for example, a vapor phase epitaxy growth process, a liquid phase epitaxy growth process, a molecular beam epitaxy growth process, or the like, and optionally, the nitride epitaxial layer 102 may be prepared by a Metal Organic Chemical Vapor Deposition (MOCVD) process, so that a crystal plane of the substrate 101 and a crystal plane of the nitride epitaxial layer 102 can be well matched.

In step S130, a first dielectric layer 103 is grown on the upper surface of the nitride epitaxial layer 102.

It is understood that the first dielectric layer 103 can be used to connect the nitride epitaxial layer 102 on its lower surface with the metal layer on its upper surface in the back-end process, which is generally performed by etching a via hole and filling aluminum in the first dielectric layer 103 between the nitride epitaxial layer 102 and the metal layer. In addition, the first dielectric layer 103 grown on the nitride epitaxial layer 102 can prevent the nitride epitaxial layer 102 from being directly exposed to cause the risk of contamination due to leakage of metal ions of the nitride epitaxial layer 102.

Alternatively, the nitride epitaxial structure may be a wafer, and the nitride epitaxial structure prepared in steps S110 to S130 may be a cylinder, and a top view and a longitudinal sectional view thereof may be respectively shown in fig. 2 and 3; after obtaining the cylindrical nitride epitaxial structure, the nitride epitaxial structure may also be cut to form a flat trench, as shown in fig. 4.

In step S140, the edge region of at least one side of the first dielectric layer 103 is etched to expose a portion of the substrate 101.

When the nitride epitaxial structure is etched, the edge region of one or more sides of the first dielectric layer 103 may be etched in a plurality of etching forms, and a portion of the nitride epitaxial layer 102 corresponding to the etched edge region of the first dielectric layer 103 is etched away, so that the substrate 101 is exposed. For example, taking the etching of the edge region on one side of the first dielectric layer 103 as an example, in one embodiment, the sidewalls of the etched first dielectric layer 103 and the nitride epitaxial layer 102 may be planar, and taking the nitride epitaxial structures in fig. 2 and fig. 3 as examples, the etched nitride epitaxial structures are as shown in fig. 5 to fig. 6; in another embodiment, the sidewalls of the etched first dielectric layer 103 and the nitride epitaxial layer 102 may also be curved, as shown in fig. 7 to 8. It should be understood that the etching pattern is not limited in this embodiment, and may be any regular or irregular pattern as long as the edge region can be removed.

By etching the first dielectric layer 103 to expose part of the substrate 101, the etching depth can extend to the upper surface of the substrate 101 or extend to the inside of the substrate 101.

It can be understood that since the substrate 101 and the nitride epitaxial layer 102 are of a hetero-structure, during the epitaxial growth of the nitride epitaxial layer 102 on the surface of the substrate 101, the stress of the edge region is greater than that of the middle region, so that the edge region of the nitride epitaxial layer 102 can be removed, the middle region except the edge region is exposed, and compared with the edge region before etching, the stress between the new edge region and the substrate 101 is smaller, and the adhesion capability is stronger; secondly, after etching, at least one side of the substrate 101 is exposed out of the nitride epitaxial layer 102, so that collision from an object on the side can be resisted, the edge area of the nitride epitaxial layer 102 on the side is protected, the adhesion stability of the edge of the nitride epitaxial layer 102 and the substrate 101 is finally improved, and the situation that the nitride epitaxial structure warps and cracks due to a subsequent thermal process during wafer flowing is avoided.

The etching process can adopt a dry etching process, and special etching equipment is adopted for etching, so that the contamination risk is avoided.

According to the preparation method of the nitride epitaxial structure, the nitride epitaxial layer 102 and the first dielectric layer 103 are sequentially grown on the upper surface of the substrate 101, then the edge area of at least one side of the first dielectric layer 103 is etched to expose part of the substrate 101, because the stress between the edge area of the nitride epitaxial layer 102 and the substrate 101 is higher than that between the middle area of the nitride epitaxial layer and the substrate 101 in the epitaxial growth process, the edge area of at least one side of the nitride epitaxial layer 102 is removed by etching to expose the middle area with smaller stress, so that the stress between the edge area of the nitride epitaxial layer 102 and the substrate 101 is released, and because the substrate 101 is exposed to the nitride epitaxial layer 102 in the edge area of the side, the etched edge area of the nitride epitaxial layer 102 can be protected from collision of objects from the direction of the substrate 101, and finally the situation that the wafer is warped and cracked due to separation of the edge of the nitride epitaxial layer 102 and the substrate 101 is avoided. In addition, the first dielectric layer 103 is grown on the upper surface of the nitride epitaxial layer 102 before etching, so that the functional requirements of the device are met, and the contamination risk caused by leakage of metal ions of the nitride epitaxial layer 102 in the etching process can be avoided.

In one embodiment, the etch depth of the edge region extends into the interior of the substrate 101.

It can be understood that, when etching the edge region of at least one side of the first dielectric layer 103, the etching depth may penetrate through the nitride epitaxial layer 102 and extend into the substrate 101, so that it can be ensured that the edge region of the nitride epitaxial layer 102 corresponding to the etched edge region in the stacking direction is removed at the same time when the edge region of the first dielectric layer 103 is etched. Wherein the stacking direction is the direction in which the substrate 101 points towards the first dielectric layer 103. Taking the nitride epitaxial structure in fig. 6 as an example, when the etching depth extends to the inside of the substrate 101, a longitudinal sectional view of the nitride epitaxial structure can be seen with reference to fig. 9.

In one embodiment, the method for fabricating the nitride epitaxial structure further includes growing a second dielectric layer on the first dielectric layer 103, wherein the second dielectric layer surrounds the first dielectric layer 103 and covers at least the etched sidewalls of the nitride epitaxial layer 102.

It can be understood that after etching the edge region of at least one side of the first dielectric layer 103, the edge region on the same side of the nitride epitaxial layer 102 is also correspondingly etched and removed, and in order to avoid the metal ions of the nitride epitaxial layer 102 from leaking from the etched sidewall and thereby causing the contamination risk, a second dielectric layer may be grown on the first dielectric layer 103, so that the second dielectric layer surrounds the first dielectric layer 103 and at least covers the etched sidewall of the nitride epitaxial layer 102, thereby preventing the contamination risk caused by the exposure of the nitride epitaxial layer 102.

In fact, since a specific growth region cannot be specified during the growth process, when the second dielectric layer is grown, the edge region of the substrate 101 exposed to the nitride epitaxial layer 102 is also covered by the second dielectric layer, and taking fig. 9 as an example, the nitride epitaxial structure after the second dielectric layer is grown can be referred to as shown in fig. 10 (in fig. 10, 104 is the second dielectric layer). In addition, the second dielectric layer can also cover the side wall of the nitride epitaxial layer which is not etched, so that the metal ions on the side wall are prevented from leaking to cause contamination risk to a production line.

In one embodiment, etching the edge region of at least one side of the first dielectric layer 103 includes steps S1401 to S1403.

In step S1401, a mask layer is formed on the upper surface of the first dielectric layer 103.

It is understood that the mask layer may be a photoresist layer, and may be formed on the upper surface of the first dielectric layer 103 through a coating process.

In step S1402, the mask layer is patterned to expose an edge region of at least one side of the first dielectric layer 103.

Specifically, after the mask layer is coated, the mask layer may be patterned through a mask, wherein the mask is formed with a pattern capable of partially transmitting light, and the mask layer is exposed through the mask, so that the pattern on the mask is projected on the mask layer to form the mask layer capable of exposing the edge region of at least one side of the first dielectric layer 103.

Step S1403, the edge region of at least one side of the first dielectric layer 103 is etched using the patterned mask layer as a mask.

It can be understood that, by forming a mask layer on the upper surface of the first dielectric layer 103, patterning the mask layer to expose the edge region of at least one side of the first dielectric layer 103, and etching with the mask layer as a mask, the region to be etched can be clarified, and the situation that the edge stress is still too large and is easily warped or cracked due to too large etching region or too small etching region can not be solved.

In one embodiment, if the edge region of at least one side of the first dielectric layer 103 is etched using the patterned mask layer as a mask, the step of removing the mask layer on the upper surface of the first dielectric layer 103 is further included before growing the second dielectric layer on the first dielectric layer 103, so as to prevent the etching apparatus from causing photoresist contamination during the subsequent etching process.

In one embodiment, etching the edge region of at least one side of the first dielectric layer 103 to expose a portion of the substrate 101 comprises: the edge region around the first dielectric layer 103 is etched to expose a portion of the substrate 101.

It is understood that to avoid warping or cracking of the edge regions on each side of the nitride epitaxial structure, the edge regions around the first dielectric layer 103 may be etched to remove the edge regions around the nitride epitaxial layer 102, so that the middle region with relatively low stress is exposed and serves as a new edge region.

Alternatively, the first dielectric layer 103 may be etched in a regular etching pattern, for example, as shown in fig. 11, 12 and 14, or the first dielectric layer 103 may be etched in an irregular etching pattern, for example, as shown in fig. 13.

In one embodiment, the orthographic shape of the edge region around the first dielectric layer 103 on the upper surface of the substrate 101 is a ring.

It can be understood that, in order to reduce the stress between the edge region around the nitride epitaxial layer 102 and the substrate 101 and ensure that the remaining functional region after etching is sufficiently large, the edge region around the first dielectric layer 103 may be designed to be annular, so that the orthographic projection shape of the edge region on the upper surface of the substrate 101 is annular, and the annular edge region around the removed nitride epitaxial layer 102 is etched, as shown in fig. 12; for a nitride epitaxial structure with a flat trench, a top view of the nitride epitaxial structure after etching the removed annular edge region around the nitride epitaxial layer 102 can be seen with reference to fig. 14.

In one embodiment, the width of the loop may range from 3mm to 7mm. In one embodiment, the width w of the ring may in particular be 5mm.

In one embodiment, the edge regions on the same side have a gradual size in a direction parallel to the upper surface of the substrate 101.

It is understood that, depending on the etching configuration, the etched first dielectric layer 103 and the nitride epitaxial layer 102 (including a portion of the substrate 101 if the etching depth extends to the inside of the substrate 101) may have unique dimensions, for example, the etched edge region has a ring shape with a unique width, and the etched nitride epitaxial structure may be as shown in fig. 12; the etched first dielectric layer 103 and the etched nitride epitaxial layer 102 (or a part of the substrate 101 if the etching depth extends to the inside of the substrate 101) may also have a gradually changing size, for example, the etched edge region is a partial circumferential region with a gradually changing width, specifically, taking the etching of the edge region on one side of the first dielectric layer 103 as an example, and as for the nitride epitaxial structure in the embodiment in fig. 2, the specific form after etching may be referred to as fig. 5.

The embodiment of the invention also provides a nitride epitaxial structure, which is prepared by the preparation method of the nitride epitaxial structure in any embodiment.

In one embodiment, the nitride epitaxial structure comprises a substrate 101, a nitride epitaxial layer 102 and a first dielectric layer 103, wherein the nitride epitaxial layer 102 is positioned on the upper surface of the substrate 101, and part of the edge area of at least one side of the substrate 101 is exposed; a first dielectric layer 103 is located on the upper surface of the nitride epitaxial layer 102.

The substrate 101 may be sapphire, siC or Si, the nitride epitaxial layer 102 may be AlGaN or GaN, and the first dielectric layer 103 may be selected according to the specific function of the device, and may be HfO, for example ₂ 、Al ₂ O ₃ For isolating the nitride epitaxial layer 102 from the metal layer on the upper layer of the nitride epitaxial layer 102, and then electrically connecting the nitride epitaxial layer 102 with the metal layer on the upper layer by etching a via hole on the first dielectric layer 103 and filling the aluminum material. In addition, the first dielectric layer 103 covering the upper surface of the nitride epitaxial layer 102 can prevent the nitride epitaxial layer 102 from being directly exposed, thereby causing the metal ions of the nitride epitaxial layer 102 to leak and causing contamination risks.

The first dielectric layer 103 may completely cover the upper surface of the nitride epitaxial layer 102, and the nitride epitaxial layer 102 covers a portion of the upper surface of the substrate 101 to expose a portion of the edge region of at least one side of the substrate 101. The nitride epitaxial structure of the embodiment can be prepared by an etching process, and the initial form of the nitride epitaxial structure to be etched is wholly cylindrical, as shown in fig. 2 and 3; the method may also be a columnar type with a cut flat groove, as shown in fig. 4, including a substrate 101, a nitride epitaxial layer 102 and a first dielectric layer 103 stacked in sequence, and then etching the edge region of one or more sides of the first dielectric layer 103 in various etching forms, and simultaneously etching and removing a portion of the nitride epitaxial layer 102 corresponding to the edge region of the first dielectric layer 103 to be etched, thereby exposing the substrate 101. Taking the edge area of the exposed part of the substrate 101 of the nitride epitaxial layer 102 as an example, the sidewalls of the first dielectric layer 103 and the nitride epitaxial layer 102 may be flat, and taking the nitride epitaxial structure of the embodiment of fig. 2 and 3 as an example, the specific structure after etching may refer to fig. 5 and 6; in another embodiment, the sidewalls of the first dielectric layer 103 and the nitride epitaxial layer 102 may also be curved, and taking the nitride epitaxial structure of the embodiments in fig. 2 and fig. 3 as an example, the specific structure after etching may be as shown in fig. 7 and fig. 8. It should be understood that the etching pattern is not limited in this embodiment, and may be any regular or irregular pattern as long as the edge region can be removed.

It can be understood that since the substrate 101 and the nitride epitaxial layer 102 are of a heterostructure, during the epitaxial growth of the nitride epitaxial layer 102 on the surface of the substrate 101, the stress of the edge region is greater than that of the middle region, so that the edge region of the nitride epitaxial layer 102 can be removed, the middle region except the edge region is exposed, and compared with the edge region before etching, the stress between the new edge region and the substrate 101 is smaller, and the adhesion capability is stronger; secondly, after etching, the substrate 101 is exposed out of the nitride epitaxial layer 102, so that collision of objects from an etching side can be resisted, the nitride epitaxial layer 102 is prevented from collision in the edge area of the side, the adhesion stability of the edge of the nitride epitaxial layer 102 and the substrate 101 is finally improved, and the condition that the nitride epitaxial structure is warped and cracked due to the subsequent thermal process during wafer flowing is avoided.

The nitride epitaxial structure of the present embodiment includes a substrate 101, a nitride epitaxial layer 102 and a first dielectric layer 103, wherein the nitride epitaxial layer 102 is located on the upper surface of the substrate 101, and a portion of an edge region of at least one side of the substrate 101 is exposed, and the first dielectric layer 103 is located on the upper surface of the nitride epitaxial layer 102, in the present embodiment, the structure of the edge region of the nitride epitaxial layer 102 exposed on at least one side of the substrate 101 exposes a portion of the substrate 101 by sequentially growing the nitride epitaxial layer 102 and the first dielectric layer 103 on the upper surface of the substrate 101, and then etching the edge region of at least one side of the first dielectric layer 103 to expose the portion of the substrate 101, so that the middle portion of the nitride epitaxial layer 102 with smaller stress is exposed, and the problem of too large stress of the edge region of the nitride epitaxial layer 102 and the edge region of the substrate 101 are solved, and in addition, because the substrate 101 is exposed on the edge region of the side of the nitride epitaxial layer 102, the edge region of the nitride epitaxial layer 102 can be protected from obstacles in the direction of the substrate 101, and finally, the wafer is prevented from warping and cracking caused by the separation of the edge region of the nitride epitaxial layer 102 from the substrate 101.

In one embodiment, the thickness of the exposed edge region of the substrate 101 may be less than the thickness of the region of the substrate 101 covered by the nitride epitaxial layer 102.

It is understood that, during the etching process, in order to ensure that the nitride epitaxial layer 102 corresponding to the edge region of the first dielectric layer 103 to be etched in the stacking direction is sufficiently removed, the etching depth may penetrate through the nitride epitaxial layer 102 and extend into the substrate 101, and taking the embodiment of fig. 6 as an example, a longitudinal sectional view of the nitride epitaxial structure when the etching depth extends into the substrate may be as shown in fig. 9. The difference between the thickness of the exposed edge region of the substrate 101 and the thickness of the region of the substrate 101 covered by the nitride epitaxial layer 102 may be smaller than a thickness threshold, so as to ensure that the exposed edge region of the substrate 101 is not easily broken. In another embodiment, the thickness of the exposed edge region of the substrate 101 may also be the same as the thickness of the region of the substrate 101 covered by the nitride epitaxial layer 102, i.e., the etching depth extends only to the surface of the substrate 101.

In one embodiment, the nitride epitaxial structure further comprises a second dielectric layer, wherein the second dielectric layer surrounds the first dielectric layer 103 and covers at least the etched sidewalls of the nitride epitaxial layer 102.

The second dielectric layer may be made of the same material as or different from the first dielectric layer 103, and is used to isolate the nitride epitaxial layer 102 from the first dielectric layer 103 and to connect the nitride epitaxial layer 102 and the metal layer formed on the nitride epitaxial layer 102 in the subsequent processing, and to implement the device function by connecting the metal layer to the nitride epitaxial layer 102 through the through hole.

In addition, the nitride epitaxial layer 102 is usually made of GaN or AlGaN, and since metal elements such as gallium ions are introduced, a certain risk of cross contamination may be caused to a wafer device production line. For the cross contamination of ions, the conventional method is that EBR solvent edge cleaning treatment is not carried out during each layer of photoetching glue coating, so that the photoresist is reserved on the medium at the edge of the wafer, and the GaN at the edge of the wafer is prevented from being exposed after an etching process; or after each processing step is finished, carefully checking whether the GaN wafer has abnormal conditions such as cracks and unfilled corners, and immediately cleaning the processing equipment once the abnormal conditions occur, so as to confirm that the concentration of metal ions is lower than the production line specification, however, the photoresist is retained to cause photoresist pollution in subsequent processing, and the checking after each step is finished can cause low efficiency and long time consumption. The second dielectric layer in this embodiment surrounds the first dielectric layer 103 and covers the nitride epitaxial layer 102, so that metal ions of the nitride epitaxial layer 102 can be prevented from leaking from the etched side wall, photoresist pollution can be avoided, the processing process can be smoothly performed, and influence on the processing efficiency due to intermediate pause is avoided.

In one embodiment, the nitride epitaxial layer 102 may expose an edge region around the substrate 101, as shown in fig. 11 to 14.

The structure of the peripheral region of the nitride epitaxial layer 102 exposed out of the substrate 101 may be formed by etching the peripheral region of the first dielectric layer 103, so as to remove the peripheral region of the nitride epitaxial layer 102. Alternatively, the first dielectric layer 103 may be etched in a regular etching pattern, for example, as shown in fig. 11 and fig. 12 and fig. 14, or the first dielectric layer 103 may be etched in an irregular etching pattern, for example, as shown in fig. 13.

It can be understood that the removal of the edge regions around the nitride epitaxial layer 102 can expose the middle region with relatively small stress and serve as a new edge region, thereby solving the problem of excessive stress between the edge regions of the nitride epitaxial layer 102 and the edge regions of the substrate 101, and avoiding the situation that the edge regions on each side of the nitride epitaxial structure are warped or cracked.

In one embodiment, the nitride epitaxial layer 102 may be ring-shaped with an edge region exposed around the substrate 101, as shown in fig. 12 and 14.

In order to make the peripheral area of the nitride epitaxial layer 102 exposed out of the substrate 101 be annular, the orthographic projection shape of the peripheral area of the first dielectric layer 103 to be etched on the upper surface of the substrate 101 can be designed to be annular, so that the peripheral area of the nitride epitaxial layer 102 corresponding to the annular shape is also etched and removed in the process of etching the first dielectric layer 103.

It can be understood that the orthographic projection shape of the edge region around the first dielectric layer 103 on the upper surface of the substrate 101 is designed to be annular, so that the annular edge region around the nitride epitaxial layer 102 is etched and removed, the stress between the edge region around the nitride epitaxial layer 102 and the substrate 101 is reduced, and the residual functional region after etching is ensured to be large enough. In addition, the rounded edges of nitride epitaxial layer 102 may also reduce the risk of edge warping and chipping.

In an embodiment, when the peripheral region of the nitride epitaxial layer 102 exposed out of the substrate 101 is annular, taking the nitride epitaxial structure in fig. 12 as an example, the specific structure of the second dielectric layer surrounding the first dielectric layer 103 and covering at least the etched sidewall of the nitride epitaxial layer 102 can be referred to as shown in fig. 15 (in fig. 15, 104 is the second dielectric layer).

In one embodiment, the width of the loop may range from 3mm to 7mm. Alternatively, the width w of the ring may be 5mm.

It is understood that, for example, the nitride epitaxial structure has a size of 6 inches, in order to ensure that sufficient functional area is reserved and to improve the warp resistance and the chipping resistance of the nitride epitaxial structure, the width w of the annular region of the etched nitride epitaxial layer 102 may be within 3mm to 7mm, for example, the width w may be 5mm.

In one embodiment, the edge region of the nitride epitaxial layer 102 exposed on the same side of the substrate 101 may have a graded dimension in a direction parallel to the upper surface of the substrate 101, as can be seen, for example, in fig. 5, 7, 11, and 13.

It should be understood that the present embodiment does not specifically limit the morphology of the edge region of the substrate exposed by nitride epitaxial layer 102 and the size in the direction parallel to the upper surface of substrate 101, and may have any morphology or size as long as part of the substrate can be exposed by etching.

In the description herein, references to "some embodiments," "other embodiments," "desired embodiments," or the like, mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, a schematic description of the above terminology may not necessarily refer to the same embodiment or example.

The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is specific and detailed, but not to be understood as limiting the scope of the invention. It should be noted that various changes and modifications can be made by those skilled in the art without departing from the spirit of the invention, and these changes and modifications are all within the scope of the invention. Therefore, the protection scope of the present patent should be subject to the appended claims.

Claims (11)

1. A method for preparing a nitride epitaxial structure is characterized by comprising the following steps:

providing a substrate;

growing a nitride epitaxial layer on the upper surface of the substrate;

growing a first dielectric layer on the upper surface of the nitride epitaxial layer;

and etching the edge area of at least one side of the first dielectric layer to expose part of the substrate.

2. The method of claim 1, wherein the etching depth of the edge region extends to an inside of the substrate.

3. The method of fabricating a nitride epitaxial structure according to claim 1, characterized in that the method of fabricating further comprises:

and growing a second dielectric layer on the first dielectric layer, wherein the second dielectric layer surrounds the first dielectric layer and at least covers the etched side wall of the nitride epitaxial layer.

4. The method of claim 1, wherein etching the edge region of at least one side of the first dielectric layer comprises:

forming a mask layer on the upper surface of the first dielectric layer;

patterning the mask layer to enable the mask layer to expose the edge area of at least one side of the first dielectric layer;

and etching the edge area of at least one side of the first dielectric layer by taking the patterned mask layer as a mask.

5. The method of claim 1, wherein said etching an edge region of at least one side of said first dielectric layer to expose a portion of said substrate comprises:

and etching the edge area around the first dielectric layer to expose part of the substrate.

6. The method of claim 5, wherein an orthographic shape of the edge region around the first dielectric layer on the upper surface of the substrate is a ring shape.

7. The method of claim 6, wherein the width of the ring is in the range of 3mm to 7mm.

8. The method of claim 1, wherein the edge regions on the same side have a gradual dimension in a direction parallel to the upper surface of the substrate.

9. A nitride epitaxial structure, characterized by being produced by the production method of a nitride epitaxial structure according to any one of claims 1 to 8.

10. The nitride epitaxial structure of claim 9, characterized in that it comprises:

a substrate;

the nitride epitaxial layer is positioned on the upper surface of the substrate and exposes the edge area of at least one side of the substrate;

and the first dielectric layer is positioned on the upper surface of the nitride epitaxial layer.

11. The nitride epitaxial structure of claim 9, wherein the thickness of the exposed edge region of the substrate is less than the thickness of the region of the substrate covered by the nitride epitaxial layer.

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