CN115696593A - Apparatus and method for wireless communication - Google Patents

Abstract

An apparatus and method of wireless communication are provided. The method is performed by a User Equipment (UE), comprising: one or more synchronization signal/Physical Broadcast Channel (PBCH) blocks (SSBs) are received at one or more reception occasions. This may solve the problems existing in the prior art, provide SSB design and/or synchronization grid design for frequency ranges, provide good communication performance and/or provide high reliability.

Description

Apparatus and method for wireless communication

This application claims priority from PCT application PCT/IB2021/000516 filed on 23/07/2021.

Technical Field

The present disclosure relates to the field of communication systems, and more particularly, to an apparatus and method for wireless communication, which can provide good communication performance and/or high reliability.

Background

In the unlicensed band, the unlicensed spectrum is a shared spectrum. Communication devices in different communication systems may use unlicensed spectrum as long as the unlicensed spectrum meets national or regional regulatory requirements for the spectrum. No special spectrum grants need to be applied to the government.

In order for various communication systems that use unlicensed spectrum for wireless communications to be able to coexist in the spectrum in a friendly manner, some countries or regions specify regulatory requirements that must be met using unlicensed spectrum. For example, the communication device follows a Listen Before Talk (LBT) or channel access procedure, i.e., the communication device needs to perform channel sensing before transmitting a signal on the channel. When the LBT result indicates that the channel is idle, the communication device may perform signaling; otherwise, the communication device cannot perform signal transmission. To ensure fairness, once a communication device successfully occupies a channel, the transmission duration cannot exceed the Maximum Channel Occupancy Time (MCOT). The LBT mechanism is also referred to as a channel access procedure. In New Radio (NR) release 16, there are different types of channel access procedures, for example, type 1, type 2A, type 2B, and type 2C channel access procedures described in TS 37.213.

Therefore, there is a need for an apparatus and method for wireless communication that can solve the problems in the prior art, provide SSB design and/or synchronization grid design for frequency ranges, provide good communication performance, and/or provide high reliability.

Disclosure of Invention

An object of the present disclosure is to provide an apparatus for wireless communication (e.g., a User Equipment (UE) and/or a base station) and a method for wireless communication, which can solve the problems existing in the prior art, provide SSB design and/or synchronization grid design for frequency ranges, provide good communication performance and/or provide high reliability.

According to a first aspect of the present disclosure, a method of wireless communication is provided, performed by a User Equipment (UE), the method comprising receiving one or more synchronization signal/Physical Broadcast Channel (PBCH) blocks (SSBs) at one or more reception occasions.

According to a first aspect, in an implementation form of the first aspect, the one or more reception occasions comprise at least one of: time domain location or frequency domain location.

According to the first aspect and the foregoing embodiments of the first aspect, in a further embodiment of the first aspect, the time-domain position includes at least one of: a first slot, a first set of symbols, a second set of symbols, a first burst of slots, or a second burst of slots.

According to the first aspect in combination with the above-described embodiments of the first aspect, in a further embodiment of the first aspect, the first slot is defined in a field, and the field comprises a duration of 5 ms.

In a further embodiment of the first aspect according to the first aspect and the previous embodiments of the first aspect, the half frame comprises a plurality of time slots (X time slots), the number (X) of the plurality of time slots being determined according to a subcarrier spacing (SCS).

According to the first aspect and the foregoing embodiments of the first aspect, in a further embodiment of the first aspect, the SCS comprises at least one of: 120kHz, 480kHz, 960kHz or 1920kHz.

According to the first aspect and the above-described embodiments of the first aspect, in a further embodiment of the first aspect, the X slots are indexed within the semi-frame in ascending order from index 0 to index X-1.

In accordance with the first aspect and the foregoing embodiments of the first aspect, in a further embodiment of the first aspect, the first slot includes 14 symbols, and the index of the symbols is from index 0 to index 13.

In accordance with the first aspect and the foregoing embodiments of the first aspect, in a further embodiment of the first aspect, the first symbol set is within the first time slot.

According to the first aspect and the respective embodiments of the first aspect, in a further embodiment of the first aspect, the first symbol set is four consecutive symbols.

According to the first aspect and the above-mentioned embodiments of the first aspect, in a further embodiment of the first aspect, a first symbol in the first symbol set is located at symbol index 1 or index 2, and the first symbol is the earliest symbol in the first symbol set.

In accordance with the first aspect and the foregoing embodiments of the first aspect, in a further embodiment of the first aspect, the second symbol set is within the first time slot.

According to the first aspect and the aforementioned embodiments of the first aspect, in a further embodiment of the first aspect, the second symbol set is four consecutive symbols.

According to the first aspect and the above-mentioned embodiments of the first aspect, in a further embodiment of the first aspect, the second symbol in the second symbol set is located at symbol index 8 or index 9, and the second symbol is the earliest symbol in the second symbol set.

According to the first aspect and the respective embodiments of the first aspect, in a further embodiment of the first aspect, the value of X comprises: x =80 when SCS =120kHz, X =160 when SCS =480kHz, X =320 when SCS =960kHz, and X =640 when SCS =1920 kHz.

In accordance with the first aspect and the above embodiments of the first aspect, in a further embodiment of the first aspect, the first slot has a slot index (n) that depends on the SCS value, and the slot index is at least one of the following index ranges: for SCS =120khz, n = 0-79; for SCS =480khz, n = (0-15) + i, where i =0, 20, 40, or 60; for SCS =480khz, n =0 to 63; for SCS =480khz, n = (0-7) + i, where i =0, 10, 20, 30, 40, 50, 60, or 70; for SCS =960khz, n = (0-31) + i, where i =0 or 40; for SCS =960khz, n =0 to 63; for SCS =960khz, n = (0-15) + i, where i =0, 10, 20, or 30; for SCS =960khz, n = (0-15) + i, where i =0, 24, 48, or 72.

In a further implementation form of the first aspect according to the first aspect as well as the above implementation forms of the first aspect, the first timeslot burst and/or the second timeslot burst are within a half frame, the first timeslot burst comprises a first number of consecutive SSB timeslots and/or the second timeslot burst comprises a second number of consecutive SSB timeslots.

According to the first aspect and the above-described embodiments of the first aspect, in a further embodiment of the first aspect, the first number is equal to or greater than the second number.

According to the first aspect and the foregoing embodiments of the first aspect, in a further embodiment of the first aspect, the SSB slot is a slot having at least one SSB reception opportunity.

In a further embodiment of the first aspect according to the first aspect as well as the above embodiments of the first aspect, the first number is defined according to SCS values, or when there is only one first SSB slot burst within the half-frame, the first number is determined according to the target total number of SSB candidates divided by the number of SSB candidates within the SSB slot.

According to the first aspect and the foregoing embodiments of the first aspect, in another embodiment of the first aspect, the first number includes: 8. 16, 32 or 64.

In a further implementation form of the first aspect according to the first aspect as well as the above implementation forms of the first aspect, the first time slot burst and the second time slot burst are consecutive bursts, and there are U time slots between the end of the first time slot burst and the beginning of the second time slot burst, wherein the value of U is defined according to the SCS value.

According to the first aspect and the foregoing respective embodiments of the first aspect, in a further embodiment of the first aspect, the value of U includes: 0,2,4,8 or 16.

According to the first aspect and the foregoing embodiments of the first aspect, in a further embodiment of the first aspect, the frequency domain locations comprise first frequency bins and/or second frequency bins.

According to the first aspect and the foregoing respective embodiments of the first aspect, in a further embodiment of the first aspect, the first frequency point and the second frequency point are Global Synchronization Channel Number (GSCN) points.

In accordance with the first aspect and the foregoing embodiments of the first aspect, in a further embodiment of the first aspect, the first frequency point and the second frequency point are two consecutive synchronous grid points.

According to the first aspect and the foregoing embodiments of the first aspect, in a further embodiment of the first aspect, a frequency interval exists between the first frequency point and the second frequency point.

In a further embodiment of the first aspect according to the first aspect as well as the above embodiments of the first aspect, the frequency spacing is defined according to SCS values.

According to the first aspect and the foregoing embodiments of the first aspect, in a further embodiment of the first aspect, the frequency interval is greater than 17.28MHz and less than or equal to the first bandwidth.

According to the first aspect and the foregoing embodiments of the first aspect, in a further embodiment of the first aspect, the first bandwidth is related to a transmission bandwidth and/or an SSB bandwidth, and the SSB bandwidth includes: SSB bandwidth of 28.8MHz when the SCS of SSB is 120 kHz; when the SCS of the SSB is 480kHz, the SSB bandwidth of 115.2MHz; SSB bandwidth of 230.4MHz when SCS of SSB is 960 kHz; or 460.8MHz SSB bandwidth when the SCS of the SSB is 1920kHz.

According to the first aspect and the foregoing embodiments of the first aspect, in a further embodiment of the first aspect, the transmission bandwidth is less than or equal to a channel bandwidth, and the channel bandwidth includes: channel bandwidth of 100MHz when SCS =120 kHz; channel bandwidth of 400MHz when SCS =480kHz, 960kHz, or 1920 kHz; or 800MHz channel bandwidth when SCS =480kHz or 960kHz or 1920kHz.

According to the first aspect and the foregoing embodiments of the first aspect, in a further embodiment of the first aspect, the transmission bandwidth is a portion of a channel bandwidth.

In accordance with the first aspect and the above-described embodiments of the first aspect, in a further embodiment of the first aspect, the portion comprises 95%.

According to the first aspect and the respective embodiments of the first aspect, in a further embodiment of the first aspect, the first bandwidth is at least one of: the transmission bandwidth minus the SSB bandwidth, or the transmission bandwidth minus (twice the SSB bandwidth).

In accordance with the first aspect and the foregoing embodiments of the first aspect, in a further embodiment of the first aspect, the frequency interval is equal to the second bandwidth.

According to the first aspect and the foregoing respective embodiments of the first aspect, in a further embodiment of the first aspect, the second bandwidth is an integer multiple of 17.28MHz.

In accordance with the first aspect and the above-described embodiments of the first aspect, in a further embodiment of the first aspect, the integer comprises an odd power or an even power of 2.

According to the first aspect and the foregoing embodiments of the first aspect, in a further embodiment of the first aspect, the second bandwidth is smaller than or equal to the first bandwidth.

In accordance with the first aspect and the foregoing embodiments of the first aspect, in a further embodiment of the first aspect, the method further comprises determining a first control resource set (CORESET) location and/or a second CORESET location in the timeslot, wherein the first CORESET is quasi co-located (QCL' ed) with the first SSB candidate and the second CORESET is quasi co-located with the second SSB candidate.

According to the first aspect and the foregoing respective embodiments of the first aspect, in a further embodiment of the first aspect, the first SSB candidate is located in the first symbol set, and the second SSB candidate is located in the second symbol set.

In a further implementation form of the first aspect according to the first aspect as well as the above implementation forms of the first aspect, the first CORESET is quasi co-located with the first SSB candidate, and a demodulation reference signal (DMRS) of a PBCH of the first SSB candidate is quasi co-located with a DMRS of the first CORESET of type D.

According to the first aspect and the foregoing respective embodiments of the first aspect, in a further embodiment of the first aspect, the second CORESET is quasi-co-located with the second SSB candidate, and the DMRS of the PBCH of the second SSB candidate and the DMRS of the second CORESET are quasi-co-located of type D.

According to the first aspect and the foregoing respective embodiments of the first aspect, in a further embodiment of the first aspect, the first CORESET position is a symbol index 0 of the slot, and the second CORESET position is a symbol index 7 of the slot.

According to the first aspect and the foregoing embodiments of the first aspect, in a further embodiment of the first aspect, the first core set and/or the second core set is associated with a Physical Downlink Control Channel (PDCCH) common search space set (CSS) of type 0.

According to the first aspect and the foregoing embodiments of the first aspect, in a further embodiment of the first aspect, a Physical Downlink Shared Channel (PDSCH) is scheduled in a Downlink Control Information (DCI) format transmitted in PDCCH CSS of type 0.

According to the first aspect and the foregoing embodiments of the first aspect, in a further embodiment of the first aspect, the PDSCH includes a length of 1 symbol.

According to the first aspect and the above-mentioned embodiments of the first aspect, in a further embodiment of the first aspect, the starting position of the PDSCH is at symbol index 1, 5, 8 or 12 in the slot.

According to the first aspect and the above-described embodiments of the first aspect, in a further embodiment of the first aspect, there is a time domain resource allocation Table (TDRA) in which there are rows corresponding to a starting position (S) and a PDSCH length (L).

According to the first aspect and the above embodiments of the first aspect, in a further embodiment of the first aspect, at least one of the following is satisfied: s =1, l =1; or S =5,l =1; or S =8,l =1; or S =12,l =1.

According to the first aspect and the foregoing embodiments of the first aspect, in a further embodiment of the first aspect, the TDRA table is predefined.

According to a second aspect of the present disclosure, there is provided a wireless communication method, performed by a base station, the method comprising transmitting one or more synchronization signal/Physical Broadcast Channel (PBCH) blocks (SSBs) to a User Equipment (UE) at one or more transmission occasions.

According to a second aspect, in an embodiment of the second aspect, the one or more transmission occasions comprise at least one of: time domain location or frequency domain location.

According to the second aspect and the foregoing embodiments of the second aspect, in a further embodiment of the second aspect, the time domain position includes at least one of: a first time slot, a first set of symbols, a second set of symbols, a first burst of time slots, or a second burst of time slots.

According to the second aspect and the above-mentioned embodiments of the second aspect, in a further embodiment of the second aspect, the first slot is defined in a field, and the field comprises a duration of 5 ms.

In a further embodiment of the second aspect, according to the second aspect and the above embodiments of the second aspect, the half frame comprises a plurality of time slots (X time slots), the number (X) of the plurality of time slots being determined according to a subcarrier spacing (SCS).

In accordance with the second aspect and the above-mentioned embodiments of the second aspect, in a further embodiment of the second aspect, the SCS comprises at least one of: 120kHz, 480kHz, 960kHz or 1920kHz.

According to the second aspect and the above-described embodiments of the second aspect, in a further embodiment of the second aspect, the X slots are indexed in ascending order from index 0 to index X-1 within the half-frame.

In accordance with the second aspect and the foregoing embodiments of the second aspect, in a further embodiment of the second aspect, the first slot comprises 14 symbols, the index of the symbols being from index 0 to index 13.

In accordance with the second aspect and the foregoing embodiments of the second aspect, in a further embodiment of the second aspect, the first symbol set is within the first time slot.

According to the second aspect and the above-described embodiments of the second aspect, in a further embodiment of the second aspect, the first symbol set is four consecutive symbols.

In accordance with the second aspect and the above-described embodiments of the second aspect, in a further embodiment of the second aspect, the first symbol of the first symbol set is located at symbol index 1 or index 2 and is the earliest symbol in the first symbol set.

In accordance with the second aspect and the foregoing embodiments of the second aspect, in a further embodiment of the second aspect, the second symbol set is within the first time slot.

According to the second aspect and the above-described embodiments of the second aspect, in a further embodiment of the second aspect, the second symbol set is four consecutive symbols.

In accordance with the second aspect and the above-mentioned embodiments of the second aspect, in a further embodiment of the second aspect, the second symbol in the second symbol set is located at symbol index 8 or index 9, and the second symbol is the earliest symbol in the second symbol set.

According to the second aspect and the foregoing embodiments of the second aspect, in a further embodiment of the second aspect, the value of X comprises: x =80 when SCS =120kHz, X =160 when SCS =480kHz, X =320 when SCS =960kHz, and X =640 when SCS =1920 kHz.

In accordance with the second aspect and the above embodiments of the second aspect, in a further embodiment of the second aspect, the first slot has a slot index (n) that depends on the SCS value, and the slot index is at least one of the following index ranges: for SCS =120khz, n =0 to 79; for SCS =480khz, n = (0-15) + i, where i =0, 20, 40, or 60; n =0 to 63 for SCS =480 kHz; for SCS =480khz, n = (0-7) + i, where i =0, 10, 20, 30, 40, 50, 60, or 70; for SCS =960khz, n = (0-31) + i, where i =0 or 40; n =0 to 63 for SCS =960 kHz; for SCS =960khz, n = (0-15) + i, where i =0, 10, 20, or 30; for SCS =960khz, n = (0-15) + i, where i =0, 24, 48, or 72.

In accordance with the second aspect and the foregoing embodiments of the second aspect, in a further embodiment of the second aspect, the first time slot burst and/or the second time slot burst are within the half frame, the first time slot burst includes a first number of consecutive SSB time slots, and/or the second time slot burst includes a second number of consecutive SSB time slots.

According to the second aspect and the above-described embodiments of the second aspect, in a further embodiment of the second aspect, the first number is equal to or greater than the second number.

According to the second aspect and the foregoing embodiments of the second aspect, in a further embodiment of the second aspect, the SSB slot is a slot with at least one SSB reception opportunity.

In a further embodiment of the second aspect, the first number is defined according to SCS values, or when there is only one first SSB slot burst in the half-frame, the first number is determined according to the target total number of SSB candidates divided by the number of SSB candidates in the SSB slot.

According to the second aspect and the foregoing embodiments of the second aspect, in a further embodiment of the second aspect, the first number comprises: 8. 16, 32 or 64.

In a further embodiment of the second aspect, the first and second bursts of time slots are consecutive bursts, and there are U time slots between the end of the first burst of time slots and the start of the second burst of time slots, wherein the U value is defined according to an SCS value.

According to the second aspect and the foregoing embodiments of the second aspect, in a further embodiment of the second aspect, the value of U comprises: 0. 2,4,8 or 16.

According to the second aspect and the foregoing embodiments of the second aspect, in a further embodiment of the second aspect, the frequency domain positions comprise first frequency bins and/or second frequency bins.

According to the second aspect and the foregoing embodiments of the second aspect, in another embodiment of the second aspect, the first frequency point and the second frequency point are Global Synchronization Channel Number (GSCN) points.

In one embodiment of the second aspect, the first frequency point and the second frequency point are two consecutive synchronous grid points.

According to the second aspect and the above-mentioned embodiments of the second aspect, in a further embodiment of the second aspect, a frequency interval exists between the first frequency point and the second frequency point.

In accordance with the second aspect and the above-described embodiments of the second aspect, in a further embodiment of the second aspect, the frequency spacing is defined in accordance with SCS values.

According to the second aspect and the above embodiments of the second aspect, in a further embodiment of the second aspect, the frequency separation is greater than 17.28MHz and less than or equal to the first bandwidth.

In accordance with the second aspect and the foregoing embodiments of the second aspect, in a further embodiment of the second aspect, the first bandwidth is related to a transmission bandwidth and/or an SSB bandwidth, and the SSB bandwidth includes: SSB bandwidth of 28.8MHz when the SCS of SSB is 120 kHz; when SCS of SSB is 480kHz, SSB bandwidth of 115.2MHz; SSB bandwidth of 230.4MHz when SCS of SSB is 960 kHz; or 460.8MHz SSB bandwidth when the SCS of the SSB is 1920kHz.

According to the second aspect and the above embodiments of the second aspect, in a further embodiment of the second aspect, the transmission bandwidth is less than or equal to the channel bandwidth, and the channel bandwidth comprises: channel bandwidth of 100MHz when SCS =120 kHz; channel bandwidth of 400MHz when SCS =480kHz, 960kHz, or 1920 kHz; or 800MHz channel bandwidth when SCS =480kHz or 960kHz or 1920kHz.

According to the second aspect and the foregoing embodiments of the second aspect, in a further embodiment of the second aspect, the transmission bandwidth is a portion of a channel bandwidth.

According to the second aspect and the above embodiments of the second aspect, in a further embodiment of the second aspect, the portion comprises 95%.

According to the second aspect and the above-mentioned embodiments of the second aspect, in a further embodiment of the second aspect, the first bandwidth is at least one of: the transmission bandwidth minus the SSB bandwidth or the transmission bandwidth minus (twice the SB bandwidth).

In accordance with the second aspect and the foregoing embodiments of the second aspect, in a further embodiment of the second aspect, the frequency interval is equal to the second bandwidth.

According to the second aspect and the foregoing embodiments of the second aspect, in a further embodiment of the second aspect, the second bandwidth is an integer multiple of 17.28MHz.

According to the second aspect and the above-mentioned embodiments of the second aspect, in a further embodiment of the second aspect, the integer comprises an odd power or an even power of 2.

According to the second aspect and the above-mentioned embodiments of the second aspect, in a further embodiment of the second aspect, the second bandwidth is smaller than or equal to the first bandwidth.

In accordance with the second aspect and the foregoing embodiments of the second aspect, in a further embodiment of the second aspect, the method further comprises controlling the UE to determine a first control resource set (CORESET) location and/or a second CORESET location in a timeslot, wherein the first CORESET is quasi co-located (QCL' ed) with a first SSB candidate and the second CORESET is quasi co-located with a second SSB candidate.

According to the second aspect and the foregoing embodiments of the second aspect, in a further embodiment of the second aspect, the first SSB candidate is located in the first symbol set and the second SSB candidate is located in the second symbol set.

In accordance with the second aspect and the foregoing embodiments of the second aspect, in a further embodiment of the second aspect, the first CORESET is quasi co-located with the first SSB candidate, and a demodulation reference signal (DMRS) of a PBCH of the first SSB candidate is quasi co-located with a DMRS of the first CORESET of type D.

In a further implementation form of the second aspect according to the second aspect and the previous implementation forms of the second aspect, the second CORESET is quasi co-located with the second SSB candidate, and the DMRS of the PBCH of the second SSB candidate is quasi co-located with the DMRS of the second CORESET of type D.

According to the second aspect and the foregoing embodiments of the second aspect, in a further embodiment of the second aspect, the first CORESET position is a symbol index 0 of the slot, and the second CORESET position is a symbol index 7 of the slot.

According to the second aspect and the foregoing embodiments of the second aspect, in a further embodiment of the second aspect, the first core set and/or the second core set are associated with a type 0 Physical Downlink Control Channel (PDCCH) common search space set (CSS).

According to the second aspect and the foregoing embodiments of the second aspect, in a further embodiment of the second aspect, the Physical Downlink Shared Channel (PDSCH) is scheduled by a Downlink Control Information (DCI) format transmitted in the PDCCH CSS of type 0.

According to the second aspect and the above-mentioned embodiments of the second aspect, in a further embodiment of the second aspect, the PDSCH comprises a length of 1 symbol.

According to the second aspect and the above-described embodiments of the second aspect, in a further embodiment of the second aspect, the starting position of the PDSCH is at symbol index 1, 5, 8 or 12 in the slot.

According to the second aspect and the above-described embodiments of the second aspect, in a further embodiment of the second aspect, there is a time domain resource allocation Table (TDRA) in which there are rows corresponding to the starting position (S) and the PDSCH length (L).

According to the second aspect and the above embodiments of the second aspect, in a further embodiment of the second aspect, at least one of the following is satisfied: s =1, l =1; or S =5,l =1; or S =8,l =1; or S =12,l =1.

According to the second aspect and the foregoing embodiments of the second aspect, in a further embodiment of the second aspect, the TDRA table is predefined.

According to a third aspect of the present disclosure, there is provided a user equipment comprising a memory, a transceiver, and a processor coupled to the memory and the transceiver. The transceiver is configured to receive one or more synchronization signal/Physical Broadcast Channel (PBCH) blocks (SSBs) at one or more receive occasions.

According to a fourth aspect of the present disclosure, there is provided a base station comprising a memory, a transceiver, and a processor coupled to the memory and the transceiver. The transceiver is configured to transmit one or more synchronization signal/Physical Broadcast Channel (PBCH) blocks (SSBs) to a User Equipment (UE) at one or more transmit occasions.

In a fifth aspect of the disclosure, a non-transitory machine-readable storage medium stores instructions which, when executed by a computer, cause the computer to perform the above-described method.

In a sixth aspect of the disclosure, a chip includes a processor configured to invoke and execute a computer program stored in a memory to cause an apparatus in which the chip is installed to perform the above-described method.

In a seventh aspect of the present disclosure, a computer-readable storage medium stores a computer program to cause a computer to execute the above-described method.

In an eighth aspect of the disclosure, a computer program product comprises a computer program which causes a computer to perform the above method.

In a ninth aspect of the present disclosure, a computer program causes a computer to execute the above method.

Drawings

In order to explain the embodiments of the present disclosure or the related art, the following drawings described in the embodiments will be briefly introduced. It is to be understood that these drawings are merely exemplary of the disclosure and that other drawings may be derived by those skilled in the art without inventive faculty.

Fig. 1 is a block diagram of one or more User Equipments (UEs) and a base station (e.g., a gNB) in a communication network system according to an embodiment of the present disclosure.

Fig. 2 is a flowchart of a method of a User Equipment (UE) performing wireless communication according to an embodiment of the present disclosure.

Fig. 3 is a flow chart of a method of a base station performing wireless communication according to an embodiment of the present disclosure.

Fig. 4 illustrates an example of a synchronization grid for a frequency range according to an embodiment of the disclosure.

Fig. 5 illustrates an example of synchronization grid granularity for a frequency range in accordance with an embodiment of the present disclosure.

Fig. 6 illustrates an example where the starting synchronization grid in the frequency range may be an R15 legacy GSCN according to an embodiment of the present disclosure.

Fig. 7 illustrates an example of a slot including an SSB according to an embodiment of the present disclosure.

Fig. 8 illustrates an example of an SSB slot defined within a field according to an embodiment of the present disclosure.

Fig. 9 shows an example of a 1ms duration containing 32 slots in accordance with an embodiment of the disclosure.

Fig. 10 illustrates an example of a SSB slot burst containing a set of consecutive SSB slots in accordance with an embodiment of the disclosure.

Fig. 11 shows an example of a SSB slot burst containing a set of consecutive SSB slots in accordance with an embodiment of the disclosure.

Fig. 12 illustrates an example of a SSB slot burst containing a set of consecutive SSB slots in accordance with an embodiment of the disclosure.

Fig. 13 shows an example of a SSB slot burst containing a set of consecutive SSB slots in accordance with an embodiment of the disclosure.

Fig. 14 shows an example of a SSB slot burst containing a set of consecutive SSB slots in accordance with an embodiment of the disclosure.

Fig. 15 is a block diagram of a system for wireless communication according to an embodiment of the disclosure.

Detailed Description

Technical points, structural features, objects, and effects achieved by the embodiments of the present disclosure are described in detail below with reference to the accompanying drawings. In particular, the terminology used in the embodiments of the disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure.

For uplink or downlink transmissions in the shared spectrum, a User Equipment (UE) or a gNB may perform a channel access procedure before transmitting one or more uplink transmissions or one or more downlink transmissions in a channel. The channel access procedure includes sensing the channel to determine whether the channel is free or busy. Optionally, the channel access procedure may at least comprise a type 1 channel access according to TS37.213 chapter 4.2.1.1, or a type 2A channel access according to TS37.213 chapter 4.2.1.2.1, or a type 2B channel access according to TS37.213 chapter 4.2.1.2.2, or a type 2C channel access according to TS37.213 chapter 4.2.1.2.3.

Fig. 1 illustrates that in some embodiments, one or more User Equipments (UEs) 10 and base stations (e.g., gnbs) 20 for transmission adaptation in a communication network system 30 according to embodiments of the present disclosure are provided. The communication network system 30 includes a base station 20 and one or more UEs 10. One or more UEs 10 may include a memory 12, a transceiver 13, and a processor 11 coupled to the memory 12 and the transceiver 13. The base station 20 may include a memory 22, a transceiver 23, and a processor 21 coupled to the memory 22 and the transceiver 23. The processor 11 or 21 may be configured to implement the functions, processes and/or methods set forth in this specification. The layers of the radio interface protocol may be implemented in the processor 11 or 21. The memory 12 or 22 is operatively coupled with the processor 11 or 21 and stores various information for operating the processor 11 or 21. The transceiver 13 or 23 is operatively coupled with the processor 11 or 21, and the transceiver 13 or 23 transmits and/or receives radio signals.

The processor 11 or 21 may comprise an Application Specific Integrated Circuit (ASIC), other chipset, logic circuit and/or data processing device. The memory 12 or 22 may include Read Only Memory (ROM), random Access Memory (RAM), flash memory, memory cards, storage media, and/or other storage devices. The transceiver 13 or 23 may comprise a baseband circuit that processes radio frequency signals. When the embodiments are implemented in software, the techniques described herein may be implemented with modules (e.g., procedures, functions, and so on) that perform the functions described herein. The modules may be stored in the memory 12 or 22 and executed by the processor 11 or 21. The memory 12 or 22 may be implemented within the processor 11 or 21 or external to the processor 11 or 21, in which case the memory 12 or 22 may be communicatively coupled to the processor 11 or 21 via various means as is known in the art.

In some embodiments, the transceiver 13 is configured to receive one or more synchronization signal/Physical Broadcast Channel (PBCH) blocks (SSBs) at one or more reception occasions. This may solve the problems in the prior art, provide SSB design and/or synchronization grid design for frequency ranges, provide good communication performance and/or provide high reliability.

In some embodiments, the transceiver 23 is configured to transmit one or more synchronization signal/Physical Broadcast Channel (PBCH) blocks (SSBs) to the UE 10 at one or more transmission occasions. This may solve the problems in the prior art, provide SSB design and/or synchronization grid design for frequency ranges, provide good communication performance, and/or provide high reliability.

Fig. 2 illustrates a wireless communication method 200 performed by a User Equipment (UE) in accordance with an embodiment of the disclosure. In some embodiments, the method 200 includes: at block 202, one or more synchronization signal/Physical Broadcast Channel (PBCH) blocks (SSBs) are received at one or more receive opportunities. This may solve the problems in the prior art, provide SSB design and/or synchronization grid design for frequency ranges, provide good communication performance and/or provide high reliability.

Fig. 3 illustrates a wireless communication method 300 performed by a base station in accordance with an embodiment of the disclosure. In some embodiments, the method 300 includes: block 302, one or more synchronization signal/Physical Broadcast Channel (PBCH) blocks (SSBs) are transmitted to a User Equipment (UE) at one or more transmit occasions. This may solve the problems in the prior art, provide SSB design and/or synchronization grid design for frequency ranges, provide good communication performance and/or provide high reliability.

In some embodiments, the one or more receive opportunities comprise at least one of: time domain location or frequency domain location. In some embodiments, the temporal location comprises at least one of: a first slot, a first set of symbols, a second set of symbols, a first burst of slots, or a second burst of slots. In some embodiments, the first slot is defined in a field, and the field comprises a duration of 5 ms. In some embodiments, the field includes a plurality of time slots (X time slots), and the number (X) of the plurality of time slots is determined according to a subcarrier spacing (SCS). In some embodiments, the SCS comprises at least one of: 120kHz, 480kHz, 960kHz or 1920kHz. In some embodiments, the X slots are indexed within a field in ascending order from index 0 to index X-1. In some embodiments, the first slot includes 14 symbols, and the indices of the symbols are from index 0 to index 13. In some embodiments, the first set of symbols is within the first slot. In some embodiments, the first symbol set is four consecutive symbols.

In some embodiments, the first symbol in the first set of symbols is located at symbol index 1 or index 2, and the first symbol is the earliest symbol in the first set of symbols. In some embodiments, the second set of symbols is within the first slot. In some embodiments, the second symbol set is four consecutive symbols. In some embodiments, the second symbol of the second symbol set is located at symbol index 8 or index 9, and the second symbol is the earliest symbol of the second symbol set. In some embodiments, the values of X include: x =80 when SCS =120kHz, X =160 when SCS =480kHz, X =320 when SCS =960kHz, and X =640 when SCS =1920 kHz. In some embodiments, the first slot has a slot index (n) that depends on the SCS value, and the slot index is at least one of the following index ranges: for SCS =120khz, n =0 to 79; for SCS =480khz, n = (0-15) + i, where i =0, 20, 40, or 60; for SCS =480khz, n =0 to 63; for SCS =480khz, n = (0-7) + i, where i =0, 10, 20, 30, 40, 50, 60, or 70; for SCS =960khz, n = (0-31) + i, where i =0 or 40; for SCS =960khz, n =0 to 63; for SCS =960khz, n = (0-15) + i, where i =0, 10, 20, or 30; for SCS =960khz, n = (0-15) + i, where i =0, 24, 48, or 72. In some embodiments, the first and/or second bursts of time slots are within a half frame, the first burst of time slots includes a first number of consecutive SSB time slots, and the second burst of time slots includes a second number of consecutive SSB time slots.

In some embodiments, the first number is equal to or greater than the second number. In some embodiments, an SSB slot is a slot in which there is at least one SSB reception opportunity. In some embodiments, the first number is defined in terms of SCS values, or when there is only one first SSB slot burst within a half-frame, the first number is determined in terms of the target total number of SSB candidates divided by the number of SSB candidates within the SSB slot. In some embodiments, the first number comprises: 8. 16, 32 or 64. In some embodiments, the first time slot burst and the second time slot burst are consecutive bursts, with U time slots between the end of the first time slot burst and the beginning of the second time slot burst, wherein the value of U is defined in terms of the SCS value. In some embodiments, the value of U includes 0,2,4,8, or 16. In some embodiments, the frequency domain locations include the first frequency bin and/or the second frequency bin. In some embodiments, the first and second bins are Global Synchronization Channel Number (GSCN) points. In some embodiments, the first frequency point and the second frequency point are two consecutive synchronized grid points. In some embodiments, there is a frequency separation between the first frequency bin and the second frequency bin. In some embodiments, the frequency spacing is defined according to SCS values.

In some embodiments, the frequency separation is greater than 17.28MHz and less than or equal to the first bandwidth. In some embodiments, the first bandwidth is related to a transmission bandwidth and/or an SSB bandwidth, and the SSB bandwidth includes: SSB bandwidth of 28.8MHz when the SCS of the SSB is 120 kHz; when the SCS of the SSB is 480kHz, the SSB bandwidth of 115.2MHz; SSB bandwidth of 230.4MHz when SCS of SSB is 960 kHz; or 460.8MHz SSB bandwidth when the SCS of the SSB is 1920kHz. In some embodiments, the transmission bandwidth is less than or equal to the channel bandwidth, and the channel bandwidth comprises: channel bandwidth of 100MHz when SCS =120 kHz; channel bandwidth of 400MHz when SCS =480kHz, 960kHz, or 1920 kHz; or 800MHz channel bandwidth when SCS =480kHz or 960kHz or 1920kHz. In some embodiments, the transmission bandwidth is a portion of the channel bandwidth. In some embodiments, the portion comprises 95%. In some embodiments, the first bandwidth is at least one of: the transmission bandwidth minus the SSB bandwidth, or the transmission bandwidth minus (twice the SSB bandwidth). In some embodiments, the frequency spacing is equal to the second bandwidth.

In some embodiments, the second bandwidth is an integer multiple of 17.28MHz. In some embodiments, the integer includes an odd power of 2 or an even power of 2. In some embodiments, the second bandwidth is less than or equal to the first bandwidth. In some embodiments, the method further includes determining a first control resource set (CORESET) location and/or a second CORESET location in the timeslot, wherein the first CORESET is quasi co-located (QCL' ed) with the first SSB candidate and the second CORESET is quasi co-located with the second SSB candidate. In some embodiments, the first SSB candidate is located in a first set of symbols and the second SSB candidate is located in a second set of symbols. In some embodiments, the first CORESET is quasi co-located with the first SSB candidate, and a demodulation reference signal (DMRS) of a PBCH of the first SSB candidate is quasi co-located with a DMRS of the first CORESET of type D. In some embodiments, the second CORESET is quasi co-located with the second SSB candidate, and the DMRS of the PBCH of the second SSB candidate is quasi co-located with the DMRS of the second CORESET by type D.

In some embodiments, the first core set position is symbol index 0 of the slot and the second core set position is symbol index 7 of the slot. In some embodiments, the first core set and/or the second core set are associated with a Physical Downlink Control Channel (PDCCH) common search space set (CSS) of type 0. In some embodiments, a Physical Downlink Shared Channel (PDSCH) is scheduled through a Downlink Control Information (DCI) format transmitted in the PDCCH CSS of type 0. In some embodiments, the PDSCH comprises 1 symbol length. In some embodiments, the starting position of the PDSCH is in symbol index 1, 5, 8, or 12 in the slot. In some embodiments, there is a time domain resource allocation Table (TDRA) in which there is a row corresponding to the starting position (S) and PDSCH length (L). In some embodiments, at least one of the following is satisfied: s =1,l =1; or S =5,l =1; or S =8,l =1; or S =12,l =1. In some embodiments, the TDRA table is predefined.

Fig. 4 illustrates an example of a synchronization grid for a frequency range in accordance with an embodiment of the present disclosure. As shown in fig. 4, in some embodiments, in R15, the synchronization grid is designed for the frequency range 2, i.e., from 24.2GHz to 100GHz, with the grid granularity being 17.28MHz as shown in fig. 1.

In some embodiments, the synchronization grid may be adapted according to the subcarrier spacing (SCS) for the frequency range from 52.6GHz to 71GHz, the SCS being equal to 120kHz, 480kHz and 960kHz, respectively. For this purpose, the design is based on SCS and minimum channel bandwidth (min CBW). In some embodiments, the minimum CBW for different SCS is as follows: SCS = minimum CBW of 120kHz =100MHz, and SCS = minimum CBW of 480kHz or 960kHz =400MHz. Furthermore, for a given minimum CBW, the effective number of RBs for transmission (or effective transmission BW) is defined. Some embodiments of the present disclosure assume that the effective transmission BW is about 95% of the minimum CBW, which corresponds to 95MHz with SCS =120kHz and 380MHz with SCS =480kHz or 960kHz. It is converted into a plurality of RBs: 66 RBs for SCS =120kHz or 480kHz, 33 RBs for SCS =960kHz, where 1RB contains 12 subcarriers each having a frequency domain spacing according to the SCS value.

Using the above parameters, the upper limit synchronization grid granularity is designed according to (effective transmission BW minus a × SSB BW), where a is an integer and takes the value of 1 or 2, and for SCS =120khz, SSB BW is 28.8MHz; for SCS =480khz, ssb BW 115.2MHz; and 230.4MHz for SCS =960khz, ssb BW. The upper grid granularity is calculated as follows (taking a =1 as an example):

SCS	efficient transport BW	SSB BW	Upper limit synchronous grid granularity
				120kHz	95MHz	28.8MHz	66.2MHz
480kHz	380MHz	115.2MHz	264.8MHz
				960kHz	380MHz	230.4MHz	149.6MHz

Comparing the upper-bound synchronization grid granularity with the conventional synchronization grid granularity, it can be understood that:

SCS	upper limit of particle size	Particle size R15	Factor(s)
				120kHz	66.2MHz	17.28MHz	Factor 3.83
480kHz	264.8MHz	17.28MHz	Factor 15.32
				960kHz	149.6MHz	17.28MHz	Factor 8.66

In some embodiments, it is assumed that the synchronization grid granularity for the frequency range between 52.6GHz and 71GHz is an integer multiple of the conventional granularity of 17.28MHz. In some embodiments, a rounding operation is performed to obtain an integer factor, where the rounding operation may round up or round down.

Fig. 5 illustrates an example of synchronization grid granularity for a frequency range in accordance with an embodiment of the present disclosure. As shown in fig. 5, in some embodiments, for rounding up, the upper limit synchronization grid granularity becomes 4 × 17.28mhz for SCS =120 kHz; for SCS =480kHz, the upper limit synchronization grid granularity becomes 16 × 17.28mhz; for SCS =960kHz, the upper limit synchronization grid granularity becomes 9 × 17.28mhz. Thus, the actual synchronization grid granularity may be selected from L x 17.28MHz as shown in fig. 5, for SCS =120khz, L =2 and/or 3 and/or 4; for SCS =480khz, l =2 and/or 3 and/or 4 and/or 5 and/or 6 and/or 7 and/or 8 and/or 9 and/or 10 and/or 11 and/or 12 and/or 13 and/or 14 and/or 15 and/or 16; for SCS =960khz, l =2 and/or 3 and/or 4. Alternatively, the value of L may be limited to an even number, in which case the actual synchronization grid granularity may be chosen to be L × 17.28MHz, for SCS =120khz, L =2 and/or 4; for SCS =480khz, l =2 and/or 4 and/or 6 and/or 8 and/or 10 and/or 12 and/or 14 and/or 16; for SCS =960khz, l =2 and/or 4. Optionally, in some examples, only one value of L is selected for a given SCS. In some embodiments, L comprises an odd power or an even power of 2.

Fig. 6 illustrates an example where the starting synchronization grid may be an R15 legacy GSCN in a frequency range according to an embodiment of the present disclosure. Notably, the starting synchronization grid may be an R15 legacy GSCN in the frequency range between 52.6GHz and 71GHz as shown in fig. 6.

In some examples, for a group of GSCNs defined for a frequency range between 52.6GHz and 71GHz, there is at least one GSCN used only for shared spectrum or unlicensed spectrum.

Fig. 7 illustrates an example of a slot including an SSB according to an embodiment of the present disclosure. In some examples, the slots that include SSBs are referred to as SSB slots. The SSB slot includes 14 symbols, the SSB slot includes a first SSB and/or a second SSB, wherein the first SSB includes 4 consecutive symbols and the second SSB includes 4 consecutive symbols. As illustrated in fig. 7, the first SSB is located at symbol index # 1, 2, 3, 4 or #2, 3, 4, 5 of the SSB slot. In some examples, the second SSB is located at symbol index # 8, 9, 10, 11 or #9, 10, 11, 12.

Fig. 8 illustrates an example of an SSB slot defined within a half-frame according to an embodiment of the present disclosure. In some examples, the SSB slots are defined in half-frames as shown in fig. 8, which contain a duration of 5 ms.

Fig. 9 shows an example of a 1ms duration containing 32 slots in accordance with an embodiment of the disclosure. For SCS =480khz, the 1ms duration contains 32 slots, while for SCS =960kHz, the 1ms duration contains 64 slots as shown in fig. 6.

Fig. 10 illustrates an example of a SSB slot burst containing a set of consecutive SSB slots in accordance with an embodiment of the disclosure. The SSB slots are defined from the first slot of the first 1ms of a field. In some examples, we can define an SSB slot burst that contains a set of consecutive SSB slots. As shown in fig. 10, where SSBs are transmitted in 4 consecutive time slots (SSB slots), the SSB slot burst thus includes 4 consecutive SSB slots. Between two SSB slot bursts, there are 2 slots without SSB transmission.

Fig. 11 shows an example of a SSB slot burst containing a set of consecutive SSB slots in accordance with an embodiment of the disclosure. In the case of SCS =480kHz, an SSB slot burst may contain 16 SSB slots, and between two consecutive SSB slot bursts, there is a gap of 4 slots as shown in fig. 11, the total number of SSB slot bursts depending on the target total number of SSB candidates within a half-frame. For example, if 1 SSB slot contains 2 SSB candidates, as described in the previous example, and the target total number of SSB candidates is 128, the number of SSB slot bursts is (target total number of SSB candidates)/(number of SSB slots within an SSB slot burst ×) number of SSB candidates within an SSB slot) = 128/(16 × 2) =4. In this example, the SSB slot is an index n, where n = l + (0-15), where l =0, 20, 40, 60. Note that, as shown in fig. 8 and 9, the slot index is defined in a field. Fig. 12 illustrates an example of a SSB slot burst containing a set of consecutive SSB slots in accordance with an embodiment of the disclosure. As shown in fig. 12, in another example, there is only one SSB slot burst within a half frame, and the SSB slot burst includes M SSB slots. The value of M is calculated as M = target total number of SSB candidates/number of SSB candidates within the SSB slot. For example, if the target total number of SSB candidates is 128 and there are 2 SSB candidates in one SSB slot, then the value of M =64. In this example, the SSB slot has an index n, where n = 0-63.

Fig. 13 illustrates an example of a SSB slot burst containing a set of consecutive SSB slots in accordance with an embodiment of the disclosure. Alternatively, the SSB slot burst includes 8 SSB slots, as shown in fig. 13, with 2 slots between 2 consecutive SSB slot bursts. The time slots between consecutive SSB time slot bursts may be viewed as gaps in which the network may schedule an emergency uplink transmission. If the target total number of SSB candidates is 128, there are 8 SSB slot bursts, each SSB slot including 2 SSB candidates. In this example, the SSB slot is an index n, where n = l + (0-7), where l =0, 10, 20, 30, 40, 50, 60, 70.

Fig. 14 shows an example of a burst of timeslots including a set of consecutive SSB timeslots in accordance with an embodiment of the present disclosure. A similar approach can be applied to SCS =960kHz. As shown in fig. 14, for SCS =960kHz, assuming a target total number of SSB candidates within a half-frame of 128, one example is that the SSB slot burst includes 32 SSB slots, each containing 2 SSB candidates. Between two consecutive SSB slot bursts, there are 8 slots. Thus, there are 2 SSB slot bursts, with the SSB slot index in a half frame being n = l + (0-31), where l =0, 40. Optionally, there are 4 SSB slot bursts. Between two consecutive SSB slot bursts, there are 4 slots, and each SSB slot burst includes 16 SSB slots, each SSB slot including 2 SSB candidates. The SSB slot index in the field becomes n = l + (0-15), where l =0, 20, 40, 60. Optionally, there are four SSB slot bursts. Between two consecutive SSB slot bursts, there are 8 slots, and each SSB slot burst includes 16 SSB slots, each SSB slot including 2 SSB candidates. The SSB slot index in the field becomes n = l + (0-15), where l =0, 24, 48, 72.

In some examples, for a frequency range between 52.6GHz and 71GHz (denoted as FR 2-1), for a half frame with SSB/PBCH blocks, a first symbol index of a candidate SSB/PBCH block (SSB) is determined from the SCS of the SSB/PBCH block as follows, where index 0 corresponds to the first symbol of the first slot in the half frame: {1,8} +14 xn, or {2,8} +14 xn, or {1,9} +14 xn or {2,9} +14 xn, where n is defined according to SCS. For example, for SCS =480khz, n = l + (0 to 15), where l =0, 20, 40, 60. Optionally, n = l + (0-7), wherein l =0, 10, 20, 30, 40, 50, 60, 70. For SCS =960khz, n = l + (0 to 31), where l =0, 40. Optionally, n = l + (0-15), where l =0, 20, 40, 60. Optionally, n = l + (0-15), where l =0, 24, 48, 72.

It should be noted that the above example assumes that the total target number of SSB candidates in a half frame is 128. As the target number increases or decreases, the number of SSB slots increases or decreases accordingly. No further examples are illustrated in this disclosure. In some examples, in an SSB slot, there may be a first SSB and/or a second SSB, where the first SSB includes an SSB index or an SSB candidate index. In some examples, the SSB index or SSB candidate index of the second SSB is an even number. In some examples, a first coreest associated with a PDCCH common search space set (CSS) of type 0 corresponding to a second SSB is located at symbol index #0 in the SSB slot. In some examples, CORESET is 1 symbol in length. In some examples, the second SSB includes an SSB index or an SSB candidate index. In some examples, the SSB index or SSB candidate index of the second SSB is an odd number. In some examples, a first coreest associated with a PDCCH common search space set (CSS) of type 0 corresponding to a first SSB is located at symbol index #7 in the SSB slot. In some examples, the length of CORESET is 1 symbol. In some embodiments, the first CORESET is quasi co-located with the first SSB candidate (QCL' ed) and the second CORESET is quasi co-located with the second SSB candidate. In some embodiments, the first SSB candidate is located in a first set of symbols and the second SSB candidate is located in a second set of symbols. In some embodiments, the first CORESET is quasi co-located with the first SSB candidate, and a demodulation reference signal (DMRS) of a PBCH of the first SSB candidate is quasi co-located of type D with a DMRS of the first CORESET. In some embodiments, the second CORESET is quasi co-located with the second SSB candidate, and the DMRS of the PBCH of the second SSB candidate is quasi co-located with the DMRS of the second CORESET by type D. In some embodiments, the first core set position is symbol index 0 of the slot and the second core set position is symbol index 7 of the slot. In some embodiments, the first core set and/or the second core set are associated with a Physical Downlink Control Channel (PDCCH) common search space set (CSS) of type 0. In some embodiments, the Physical Downlink Shared Channel (PDSCH) is scheduled through a Downlink Control Information (DCI) format transmitted in PDCCH CSS of type 0.

In some examples, the network may schedule the PDSCH through a DCI format transmitted in PDCCH CSS of type 0, where the PDSCH may include a 1 symbol length and a starting position at symbol index #1, #5, or #8, or # 12. This translates into a time domain resource allocation Table (TDRA) where there are rows corresponding to a starting location (S) and a PDSCH length (L), satisfying at least one of: s =1, l =1; or S =5,l =1; or S =8,l =1; or S =12,l =1, wherein the TDRA table is predefined.

The commercial interest of some embodiments is as follows. 1. The problems in the prior art are solved. 2. SSB designs and/or synchronization grid designs are provided for the frequency range. 3. Providing good communication performance. 4. High reliability of communication is provided. 5. The users of some embodiments of the present disclosure are: 5G-NR chipset vendor; V2X communication system developers; automobile manufacturers, including automobiles, trains, trucks, buses, bicycles, motorcycles, helmets, and the like; unmanned aerial vehicles (unmanned aerial vehicles), smart phone manufacturers; communication devices for public safety purposes, AR/VR device manufacturers, AR/VR devices for e.g. gaming, conference/seminar, educational purposes. Some embodiments of the present disclosure are a combination of "technologies/processes" that may be employed in 3GPP specifications to create an end product. Some embodiments of the present disclosure may be employed in 5G NR licensed spectrum and unlicensed or shared spectrum communications. Some embodiments of the present disclosure propose technical mechanisms.

Fig. 15 is a block diagram of an example system 700 for wireless communication in accordance with an embodiment of the disclosure. The embodiments described herein may be implemented in a system using any suitably configured hardware and/or software. Fig. 15 shows a system 700 comprising: radio Frequency (RF) circuitry 710, baseband circuitry 720, application circuitry 730, memory/storage 740, display 750, camera 760, sensors 770, and input/output (I/O) interface 780, coupled to each other at least as shown. The application circuitry 730 may include circuitry such as, but not limited to, one or more single-core or multi-core processors. The processor may include any combination of general purpose processors and special purpose processors, such as a graphics processor, an application processor. The processor may be coupled with the memory/storage and configured to execute instructions stored in the memory/storage to enable various applications and/or operating systems running on the system.

The baseband circuitry 720 may include circuitry such as, but not limited to, one or more single-core or multi-core processors. The processor may comprise a baseband processor. The baseband circuitry may handle various radio control functions that enable communication with one or more radio networks through the RF circuitry. The radio control functions may include, but are not limited to, signal modulation, encoding, decoding, radio frequency shifting, and the like. In some embodiments, the baseband circuitry may provide communications compatible with one or more radio technologies. For example, in some embodiments, the baseband circuitry may support communication with an Evolved Universal Terrestrial Radio Access Network (EUTRAN) and/or other Wireless Metropolitan Area Networks (WMANs), wireless Local Area Networks (WLANs), and Wireless Personal Area Networks (WPANs). Embodiments in which the baseband circuitry is configured to support radio communications of more than one wireless protocol may be referred to as multi-mode baseband circuitry.

In various embodiments, the baseband circuitry 720 may include circuitry that operates with signals that are not considered to be in the baseband frequency in the strict sense. For example, in some embodiments, the baseband circuitry may include circuitry that operates with signals having an intermediate frequency between the baseband frequency and the radio frequency. The RF circuitry 710 may enable communication with a wireless network using modulated electromagnetic radiation through a non-solid medium. In various embodiments, the RF circuitry may include switches, filters, amplifiers, etc. to facilitate communication with the wireless network. In various embodiments, the RF circuitry 710 may include circuitry that operates with signals that are not considered to be at radio frequencies in the strict sense of the word. For example, in some embodiments, the RF circuitry may include circuitry to operate with signals having an intermediate frequency between baseband and radio frequencies.

In various embodiments, the transmitter circuitry, control circuitry, or receiver circuitry discussed above with respect to the user equipment, eNB, or gNB may be embodied in whole or in part in one or more RF circuits, the baseband circuitry, and/or the application circuitry. As used herein, "circuitry" may refer to a portion of or include: an Application Specific Integrated Circuit (ASIC), an electronic circuit, a processor (shared, dedicated, or group) and/or memory that executes one or more software or firmware programs (shared, dedicated, or group), a combinational logic circuit, and/or other suitable hardware components that provide the described functionality. In some embodiments, the electronic device circuitry may be implemented in, or functions associated with, one or more software or firmware modules. In some embodiments, some or all of the constituent components of the baseband circuitry, the application circuitry, and/or the memory/storage may be implemented together on a system on a chip (SOC). The memory/storage 740 may be used to load and store data and/or instructions, for example, for a system. Memory/storage for one embodiment may comprise any combination of suitable volatile memory (e.g., dynamic Random Access Memory (DRAM)) and/or non-volatile memory (e.g., flash memory).

In various embodiments, the I/O interface 780 may include one or more user interfaces designed to enable user interaction with the system and/or peripheral component interfaces designed to enable peripheral component interaction with the system. The user interface may include, but is not limited to, a physical keyboard or keypad, a touchpad, a speaker, a microphone, and the like. The peripheral component interfaces may include, but are not limited to, a non-volatile memory port, a Universal Serial Bus (USB) port, an audio jack, and a power interface. In various embodiments, the sensor 770 may include one or more sensing devices to determine environmental conditions and/or location information associated with the system. In some embodiments, the sensors may include, but are not limited to, a gyroscope sensor, an accelerometer, a proximity sensor, an ambient light sensor, and a positioning unit. The positioning unit may also be part of, or interact with, the baseband circuitry and/or RF circuitry to communicate with components of a positioning network, such as Global Positioning System (GPS) satellites.

In various embodiments, the display 750 may include a display, such as a liquid crystal display and a touch screen display. In various embodiments, the system 700 may be a mobile computing device, such as but not limited to a laptop device, a tablet device, a netbook, an ultrabook, a smartphone, AR/VR glasses, and the like. In various embodiments, the system may have more or fewer components and/or different architectures. Where appropriate, the methods described herein may be implemented as a computer program. The computer program may be stored on a storage medium, such as a non-transitory storage medium.

Those of ordinary skill in the art will appreciate that each of the units, algorithms, and steps described and disclosed in the embodiments of the present disclosure is implemented using electronic hardware or a combination of software and electronic hardware for a computer. Whether the function is a hardware or software operation depends on the application conditions and the design requirements of the solution. Skilled artisans may implement the functionality in varying ways for each particular application, and such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure. A person skilled in the art will understand that since the working processes of the above-described systems, devices and units are substantially the same, he/she may refer to the working processes of the systems, devices and units in the above-described embodiments. For ease of description and simplicity, these operations will not be described in detail.

The elements of a single component used for illustration may or may not be physically separate. The unit for displaying is a physical unit or not, i.e. located in one place or distributed over a plurality of network units. Some or all of the units are used according to the purpose of the embodiment. Furthermore, each functional unit in each embodiment may be integrated into one processing unit, the each unit being physically independent, or two or more units may be integrated into one processing unit.

If the software functional unit is implemented and used and sold as a product, it may be stored in a readable storage medium in a computer. Based on this understanding, the technical solutions proposed by the present disclosure can be implemented essentially or partially in the form of software products. Alternatively, a portion of the technical plan that facilitates conventional techniques may be implemented in the form of a software product. A software product in a computer is stored in a storage medium and includes instructions for causing a computing device (e.g., a personal computer, server, or network device) to perform all or some of the steps disclosed in the embodiments of the present disclosure. The storage medium includes a USB disk, a removable hard disk, a Read Only Memory (ROM), a Random Access Memory (RAM), a floppy disk or other type of medium capable of storing program code.

While the present disclosure has been described in connection with what is presently considered to be the most practical and preferred embodiment, it is to be understood that the present disclosure is not limited to the disclosed embodiments, but is intended to cover various arrangements without departing from the scope of the broadest interpretation of the appended claims.

Claims (9)

1. A method of wireless communication, performed by a User Equipment (UE), the method comprising:

one or more synchronization signal/Physical Broadcast Channel (PBCH) blocks (SSBs) are received at one or more reception occasions.

2. A wireless communication method, performed by a base station, the method comprising:

one or more synchronization signal/Physical Broadcast Channel (PBCH) blocks (SSBs) are transmitted to a User Equipment (UE) at one or more transmission occasions.

3. A User Equipment (UE), comprising:

a memory;

a transceiver; and

a processor coupled to the memory and the transceiver;

wherein the processor is configured to perform the method of claim 1.

4. A base station, comprising:

a memory;

a transceiver; and

a processor coupled to the memory and the transceiver;

wherein the processor is configured to perform the method of claim 2.

5. A non-transitory machine-readable storage medium storing instructions which, when executed by a computer, cause the computer to perform the method of claim 1 or 2.

6. A chip, comprising:

a processor configured to invoke and execute a computer program stored in the memory to cause the chip-mounted device to perform the method according to claim 1 or 2.

7. A computer-readable storage medium having stored thereon a computer program for causing a computer to execute the method according to claim 1 or 2.

8. A computer program product, comprising: computer program, wherein the computer program causes a computer to perform the method according to claim 1 or 2.

9. A computer program, wherein the computer program causes a computer to perform the method according to claim 1 or 2.

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