CN115696433A

CN115696433A - Information processing method, device and network equipment

Info

Publication number: CN115696433A
Application number: CN202110869658.6A
Authority: CN
Inventors: 刘塬
Original assignee: China Mobile Communications Group Co Ltd; China Mobile IoT Co Ltd
Current assignee: China Mobile Communications Group Co Ltd; China Mobile IoT Co Ltd
Priority date: 2021-07-30
Filing date: 2021-07-30
Publication date: 2023-02-03

Abstract

The application provides an information processing method, an information processing device and network equipment, and relates to the technical field of communication. The method performed by the first node comprises: acquiring a first transmission frame to be transmitted; the first transmission frame comprises a target identification code and a preset protocol target address, wherein the target identification code comprises a preset protocol interface identification code and a core number identification code; under the condition that the preset protocol interface identification code in the first transmission frame is consistent with the preset protocol interface identification code of the sending end, sending the first transmission frame according to the buffer area state of a second node receiving the first transmission frame; and under the condition that the preset protocol interface identification code in the first transmission frame is inconsistent with the preset protocol interface identification code of the sending end, sending the first transmission frame to a target node corresponding to the core number identification code. According to the technical scheme, the protocol interface identification code and the core number identification code are preset in the first transmission frame, so that the method and the device can be applied to various bottom layer architectures, and the reliability of information communication is guaranteed.

Description

Information processing method, device and network equipment

Technical Field

The present application relates to the field of communications technologies, and in particular, to an information processing method, an information processing apparatus, and a network device.

Background

Currently, communication middleware is widely applied to various distributed application systems. For example, in a parallel signal processing system employing a multi-Digital Signal Processor (DSP) array architecture, message middleware plays a significant role. The application development of the parallel signal processing system is mainly multiprocessor development and a parallel task distribution method. In the prior multiprocessor development and debugging, the problems of compact combination of software and hardware, simple software supporting function, insufficient system openness, insufficient communication flexibility and the like finally cause the limitation of system function and performance and the rise of development period and development cost. In order to meet the requirements of the array signal processing system on networking and integration in a new period, message middleware is configured inside the array signal processing system and used for shielding details and heterogeneity of an internal data network and a network protocol, complex bottom layer processing work is separated from specific engineering application, and information and control channels are established through simple interface functions, so that engineering technicians can concentrate on design and implementation of an application layer, and the dilemma that deep research has to be carried out on a bottom layer hardware system is eliminated.

In some large distributed systems, processors with various architectures and different models are provided, and the mainstream operating systems of the processors are different from each other, so that in order to reduce the development difficulty and increase the performability of service codes, a general communication framework is developed for node management and thread management, and a unified communication interface which can be compatible with a standard RapidIO standard protocol and support DSP inter-core communication is developed.

In summary, a large distributed system usually has processors with multiple architectures and different models, and mainstream operating systems between different processors are different, so that it is difficult to implement unified communication, that is, the architectures of the underlying layers of the multi-core processors are not unified, and it is difficult to simultaneously consider the problems of reliability, real-time performance, and CPU processing capability.

Disclosure of Invention

The embodiment of the application provides an information processing method, an information processing device and network equipment, and aims to solve the problem that communication cannot be realized under a multi-core processor with non-uniform underlying architecture in the information processing method in the prior art.

In order to solve the technical problem, the following technical scheme is adopted in the application:

an embodiment of the present application provides an information processing method, which is performed by a first node, and includes:

acquiring a first transmission frame to be transmitted; the first transmission frame comprises a destination identification code and a preset protocol destination address, wherein the destination identification code comprises a preset protocol interface identification code and a core number identification code;

under the condition that a preset protocol interface identification code in the first transmission frame is consistent with a preset protocol interface identification code of a sending end, sending the first transmission frame according to the buffer area state of a second node receiving the first transmission frame;

and sending the first transmission frame to a target node corresponding to the core number identification code under the condition that the preset protocol interface identification code in the first transmission frame is inconsistent with the preset protocol interface identification code of the sending end.

Optionally, the sending the first transmission frame according to the buffer status of the second node receiving the first transmission frame includes:

determining the buffer zone flag bit state of a second node receiving the first transmission frame from the preset protocol destination address through a first transaction packet format;

and sending the first transmission frame according to the flag bit state of the buffer area.

Optionally, the sending the first transmission frame according to the status of the flag bit of the buffer area includes:

if the status of the zone bit of the cache zone is a receivable data status, sending the first transmission frame to a second node receiving the first transmission frame through a second transaction packet format, and determining that the status of the zone bit of the cache zone of the second node is a non-receivable data status;

and if the status of the zone bit of the cache region is in a data unreceivable status, circularly inquiring the status of the zone bit of the cache region until the status of the zone bit of the cache region is in a data receivable status, and sending the first transmission frame.

Optionally, when the first node is a master node, the method further includes:

initializing slave nodes connected with the first node, and endowing each slave node with a preset protocol interface identification code;

and respectively establishing a cache zone bit for the first node and the slave node connected with the first node according to the preset protocol interface identification code and the type of a processor corresponding to the slave node.

Optionally, when the first node is a slave node, the method further includes:

and periodically sending heartbeat data to a main node connected with the sending end.

An embodiment of the present application further provides an information processing method, which is executed by a second node, and the method includes:

receiving a first transmission frame sent by a first node; the first transmission frame comprises a destination identification code and a preset protocol destination address, wherein the destination identification code comprises a preset protocol interface identification code and a core number identification code;

and determining whether the first transmission frame needs to be subjected to inter-core communication transmission according to the core number identification code in the first transmission frame.

Optionally, the determining whether the first transmission frame needs to be inter-core communication transmitted includes:

if the core number identification code of the first node is first preset information, determining to perform inter-core communication transmission;

and if the core number identification code of the first node is second preset information, interrupting the second node and analyzing the first transmission frame by the inter-process communication IPC, and determining to perform inter-core communication transmission.

Optionally, the performing inter-core communication transmission includes:

and copying the first transmission frame to a target application layer in a Direct Memory Access (DMA) mode, and clearing the buffer area state of the second node.

Optionally, when the second node is a master node, the method further includes:

periodically receiving heartbeat data sent by a first node connected with the sending end;

and if the received heartbeat data fails, determining that the first node is in a fault state.

Optionally, when the second node is a slave node, after receiving the first transmission frame sent by the first node, the method further includes:

determining whether the core number identification code of the first transmission frame is consistent with the core number identification code of the second node;

if yes, executing a step of determining whether the first transmission frame needs to be subjected to inter-core communication transmission; and if the first transmission frame is inconsistent with the second transmission frame, interrupting the second node through IPC, and sending the first transmission frame to a cache region of a target node corresponding to the first transmission frame.

An embodiment of the present application further provides an information processing apparatus, including:

an obtaining module, configured to obtain a first transmission frame to be transmitted; the first transmission frame comprises a destination identification code and a preset protocol destination address, wherein the destination identification code comprises a preset protocol interface identification code and a core number identification code;

a sending module, configured to send the first transmission frame according to a buffer status of a second node that receives the first transmission frame when a preset protocol interface identification code in the first transmission frame is consistent with a preset protocol interface identification code of a sending end;

and the processing module is used for sending the first transmission frame to a target node corresponding to the core number identification code under the condition that the preset protocol interface identification code in the first transmission frame is inconsistent with the preset protocol interface identification code of the sending end.

a first receiving module, configured to receive a first transmission frame sent by a first node; the first transmission frame comprises a destination identification code and a preset protocol destination address, wherein the destination identification code comprises a preset protocol interface identification code and a core number identification code;

and the first determining module is used for determining whether the first transmission frame needs to be subjected to inter-core communication transmission according to the core number identification code in the first transmission frame.

An embodiment of the present application further provides a network device, including: a transceiver, a memory, a processor, and a program stored on the memory and executable on the processor, wherein,

the transceiver is used for receiving a first transmission frame sent by a first node; the first transmission frame comprises a destination identification code and a preset protocol destination address, wherein the destination identification code comprises a preset protocol interface identification code and a core number identification code;

the processor implements the following steps when executing the program:

An embodiment of the present application also provides a readable storage medium, on which a program is stored, and the program, when executed by a processor, implements the steps in the information processing method as described above.

The beneficial effect of this application is:

in the above technical solution, an information processing method executed by a first node includes: acquiring a first transmission frame to be transmitted; the first transmission frame comprises a destination identification code and a preset protocol destination address, wherein the destination identification code comprises a preset protocol interface identification code and a core number identification code; under the condition that a preset protocol interface identification code in the first transmission frame is consistent with a preset protocol interface identification code of a sending end, sending the first transmission frame according to the buffer area state of a second node receiving the first transmission frame; and sending the first transmission frame to a target node corresponding to the core number identification code under the condition that the preset protocol interface identification code in the first transmission frame is inconsistent with the preset protocol interface identification code of the sending end. According to the technical scheme, the protocol interface identification code and the core number identification code are preset, the preset protocols of different processor frames are compatible, the hardware redundancy characteristic of a unified communication interface is guaranteed, later-stage expansion driving is facilitated, and data communication is carried out on frames compatible with more equipment types.

Drawings

FIG. 1 is a schematic flow chart of an information processing method according to an embodiment of the present disclosure;

FIG. 2 is a second flowchart of an information processing method according to an embodiment of the present disclosure;

FIG. 3 is a system diagram illustrating various processors provided by an embodiment of the present application;

fig. 4 is a diagram illustrating a first transmission frame according to an embodiment of the present application;

FIG. 5 is a block diagram of an information processing apparatus according to an embodiment of the present disclosure;

fig. 6 shows a second block diagram of an information processing apparatus according to a second embodiment of the present disclosure;

fig. 7 shows a block diagram of a network device according to an embodiment of the present application.

Detailed Description

To make the technical problems, technical solutions and advantages to be solved by the present application clearer, the following detailed description is made with reference to the accompanying drawings and specific embodiments. In the following description, specific details such as specific configurations and components are provided only to help the embodiments of the present application be fully understood. Accordingly, it will be apparent to those skilled in the art that various changes and modifications may be made to the embodiments described herein without departing from the scope and spirit of the present application. In addition, descriptions of well-known functions and constructions are omitted for clarity and conciseness.

It should be appreciated that reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present application. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

In various embodiments of the present application, it should be understood that the sequence numbers of the following processes do not mean the execution sequence, and the execution sequence of each process should be determined by the function and the inherent logic of the process, and should not constitute any limitation to the implementation process of the embodiments of the present application.

It should be appreciated that RapidIO is an interconnection communication technology mainly applied to a high-performance embedded system, and data transmission is performed in a switching interconnection manner, that is, a traditional single point-to-point connection manner is not adopted, so that a switching mechanism is added, and flexibility of the system is enhanced. Serial RapidIO (SRIO) can adopt modes of 1X, 4X and the like, and the transmission rate can reach dozens of gigabits. RapidIO technology has a complete consideration for routing, switching, and fault tolerance and error correction, and is therefore being applied to more and more high-performance reliable data transmission systems.

Prior art Asymmetric Multiprocessing (AMP) architecture processors are mostly Digital Signal Processor (DSP) chips. A Symmetrical Multiprocessing (SMP) structure processor in the prior art is internally integrated with a RapidIO controller which accords with RapidIO Interconnect Specification, and the controller consists of a RapidIO port and a RapidIO message transmission unit. Each SMP structure processor integrates two RapidIO ports, both support 1x or 4x physical links, and the maximum support rate of a single link is 3.125Gbps. The message transmission unit supports 2 data message sending controllers, 2 data message receiving controllers, 1 doorbell message sending controller, 1 doorbell message receiving controller and one port receiving controller.

The communication middleware (message oriented middleware) refers to middleware that supports and guarantees synchronous/asynchronous transceiving of data between distributed applications. The communication interface between the distributed applications is provided by an API provided by the middleware. In particular, the communication middleware is data communication middleware between processes or threads.

The application provides an information processing method, an information processing device and network equipment, aiming at the problem that communication cannot be realized under a multi-core processor with non-uniform underlying architecture in the information processing method in the prior art.

As shown in fig. 3, a system framework of various processors provided by the embodiments of the present application is schematically illustrated; the processors of the system described herein include various types of processors, and may include Symmetric Multiprocessing (SMP) architecture processors and Asymmetric Multiprocessing (AMP) architecture processors, each coupled to a processing chip. In order to realize the advantage of the computing speed, the AMP architecture processor is preferably a high-performance 8-core DSP of the TMS320C6678, and the SMP architecture processor is preferably a P2020 type processor. The processor under the system framework of the application can be of the same-core processor type, and certainly can also be a different-core processor, and is selected according to actual requirements. The system framework provided by the present application is applicable to the following steps of the information processing method.

As further shown in fig. 1, an alternative embodiment of the present application provides an information processing method, which is performed by a first node, and includes:

step 100, acquiring a first transmission frame to be transmitted; the first transmission frame comprises a target identification code (target ID) and a preset protocol target address (RapidIO target address), wherein the target identification code (target ID) comprises a preset protocol interface identification code (SRIO ID) and a CORE number identification code (CORE ID);

specifically, as shown in fig. 4, the first transmission frame is composed of 3 parts, which are respectively a destination ID (4 bytes), a RapidIO destination address (8 bytes), and a transmission data length (8 bytes); the meaning of each part is as follows:

destination ID: the lower 16 bits are composed of SRIO ID unique to each device, the upper 16 bits are composed of core number of the receiving end, and when the opposite end is an SMP architecture processor, the 16 bits default to 0, and the opposite end is an AMP architecture processor, the 16 bits are corresponding to the core number of the data to be received. Destination RaidIO address: and resolving a destination RapidIO address corresponding to the node (or core) to be sent from the destination ID specified by the application layer, and sending the data to a data cache region of the corresponding node (or core).

Length of transmission data: is the length of data to be sent by the application layer.

In this embodiment, the first transport frame may be suitable for a C-language-based generic task management POSIX interface, which is convenient for compatibility with other operating system task management interfaces, and improves portability of an application program. The first transmission frame may also be adapted to an AMP multi-core architecture of the DSP, and is compatible with an inter-core approach for inter-process communication (IPC) based on a Queue Manager (QMSS).

200, under the condition that a preset protocol interface identification code (SRIO ID) in the first transmission frame is consistent with a preset protocol interface identification code of a sending end, sending the first transmission frame according to a buffer area state of a second node receiving the first transmission frame;

here, when the SRIO ID in the first transmission frame matches the SRIO ID of the transmitting end, the current communication type may be considered to be the SRIO communication type. And sending the first transmission frame under the condition of the SRIO communication type.

Step 300, sending the first transmission frame to a target node corresponding to the core number identification code under the condition that the preset protocol interface identification code in the first transmission frame is inconsistent with the preset protocol interface identification code of the sending end.

Here, when the SRIO ID in the first transmission frame is inconsistent with the SRIO ID of the sending end, it may be considered that the current communication type is a non-SRIO communication type, and sending the first transmission frame to the target node corresponding to the core number identifier may be understood as: the first node firstly puts the data to be sent into a sending queue of a Queue Manager (QMSS), the data is sent to a cache address corresponding to a core number in the first transmission frame through the QMSS, then a target node to receive the data is notified through IPC inter-core interruption, and the target node receiving the IPC inter-core interruption takes the data from the received cache address.

Optionally, the step 200 includes:

step 210, determining the buffer zone flag bit state of the second node receiving the first transmission frame from the RapidIO destination address through a first transaction packet format;

step 220, sending the first transmission frame according to the status of the buffer zone flag bit.

It should be appreciated that in order to reduce the number of messages and enable the processor to process multiple transactions in parallel to improve the processing efficiency of the system on information, the concept of "transaction packing" is introduced in the RapidIO destination address. The "transaction packaging" is to combine the transactions into a transaction request message when the RapidIO destination address has a plurality of prepared transactions such as request primitive, and the like to be initiated, namely to form a transaction package. The processor may or may not process the transactions in the order they were received.

In this embodiment, the buffer flag bit status of the second node that receives the first transmission frame is determined from the RapidIO destination address by a first transaction packet format (NREAD transaction packet format); the buffer zone flag bit states include a receivable data state and a non-receivable data state.

Optionally, the step 220 includes:

and if the status of the zone bit of the cache area is in a data unreceivable status, circularly inquiring the status of the zone bit of the cache area until the status of the zone bit of the cache area is in a data receivable status, and sending the first transmission frame.

In this embodiment, if the status of the flag bit in the cache area is a data receivable status, the first transmission frame is sent to a second node that receives the first transmission frame in a second transaction packet format (NWRITE transaction packet format), and if the status of the flag bit in the cache area is not data receivable, the first transmission frame is sent when the status of the flag bit in the cache area is circularly queried to be a data receivable status.

Of course, the message type of the message data packet to be sent can also be determined: if the transmission frame is the RTPS protocol message, replacing the RapidIO target address of the first transmission frame with the data; and if the transmission frame is the service message, writing the service message data into the RapidIO destination address of the first transmission frame.

Optionally, when the first node is a master node, the method further includes:

initializing slave nodes connected with the first node, and endowing a preset protocol interface identification code for each slave node;

in this embodiment, the first transmission frame is sent by a communication middleware, and before the first node obtains the first transmission frame to be transmitted, the first node initializes a slave node connected to the first node, and assigns a preset protocol interface identification code (SRIO ID) to each slave node; for example, using an SMP processor as a master node, blocking all slave nodes in the system of fig. 3 (the term "blocking mode" means that when attempting to read or write the file descriptor, if nothing is readable at that time or the file descriptor is temporarily unwritable, the program enters a waiting state until something is readable or writable), and the master node scans and gives the SRIO ID of the first node and the slave nodes connected to the first node in the network as a unique identifier for each node.

And respectively establishing cache zone bits for the first node and the slave node connected with the first node according to the preset protocol interface identification code and the type of the processor corresponding to the slave node.

In this embodiment, the slave master node may observe all node types and SRIO IDs of the entire SRIO network. And respectively establishing a cache flag bit according to the SRIO ID and the type network of the processor corresponding to the slave node, namely each core of each SMP structure processor and each core of the AMP structure processor, and setting whether the cache region can accept data. According to the method and the device, the cache flag bit is established according to the SRIO ID and the processor type, and the problem that communication cannot be achieved under a multi-core processor with non-uniform underlying architecture is solved.

Optionally, when the first node is a slave node, the method further includes:

In this embodiment, if there are four processors and one processing chip, that is, the system framework in fig. 3, the data writer and the data reader that transmit heartbeat messages to each other through the DDS mechanism monitor the active states of the other processors. Here, when the first node is a slave node, the first node periodically sends a heartbeat message to a participant (which may be a master node of the receiving end) at the receiving end through a multicast transmission manner, so as to refresh its own active state.

As shown in fig. 2, an embodiment of the present application further provides an information processing method, which is executed by a second node, and the method includes:

step 400, receiving a first transmission frame sent by a first node; the first transmission frame comprises a destination identification code and a preset protocol destination address, wherein the destination identification code comprises a preset protocol interface identification code and a core number identification code;

here, the destination identifier is a destination ID, the destination address is a RapidIO destination address, the preset protocol interface identifier is an SRIO ID, and the CORE number identifier is a CORE ID, which is consistent with the content of the first transmission frame described in fig. 4.

Step 500, determining whether inter-core communication transmission needs to be performed on the first transmission frame according to the core number identification code in the first transmission frame.

In this embodiment, it may be determined whether the second node is a node requiring inter-CORE communication transmission through a CORE number identifier (CORE ID) in the first transmission frame, and when the second node is a node not requiring inter-CORE communication transmission, the content of the first transmission frame is transmitted to a required target node. For example, the node a needs inter-core communication for the first transmission frame, but the node B receives the information at this time, and the node a needs inter-core communication for the first transmission frame is transferred to the node B. The method increases the diversity and accuracy of inter-core communication.

Optionally, the determining whether the inter-core communication transmission needs to be performed on the first transmission frame includes:

In this embodiment, the first preset information is preferably 0, the second preset information is preferably not 0,

optionally, the performing inter-core communication transmission includes:

and copying the first transmission frame to a target application layer in a Direct Memory Access (DMA) mode, and emptying the buffer area state of the second node.

In this embodiment, the receiving end task receives the information of the first transmission frame, performs parsing, and if the parsing core number is 0, copies the data to the cache region of the target application layer where the data is to be received in a DMA manner, and clears the SRIO data cache region, and sets the receiving flag bit of the cache region as data that can be received.

If the analyzed core number is not 0 and the data receiving node is an AMP architecture processor, the second node firstly puts the data to be sent into a sending queue of the QMSS, sends the data to a cache address corresponding to the core number through the QMSS, then informs the core to receive the data through IPC inter-core interruption, after the core receiving the inter-core interruption takes the data from the received cache address, analyzes the content of the transmission frame, copies the data to a cache region to receive the data on an application layer on the corresponding core in a DMA mode, clears an SRIO data cache region, and sets a cache region receiving flag bit as data receivable.

Optionally, when the second node is a master node, the method further includes:

In this embodiment, each sender sends a heartbeat message to the second node through a built-in data writer, and the second node is configured to discover information of the sending node itself or other nodes connected to the sending node; and the second nodes monitor the activity period of the second nodes, if the received heartbeat data fails, the node (the first node) at the sending end is proved to have abnormity, and the first node is determined to be in a fault state at the moment.

Certainly, the second node may also analyze the packet of the first node through the heartbeat data sent by the first node, and determine whether the first node has a power failure. The method and the device support node management, can give a judgment result for the condition of reset of the independent node or power failure of the independent node, and can prompt relevant personnel to perform corresponding maintenance operation based on the judgment result; and judging whether the slave node is in a normal working state or not, thereby updating the node state.

In this embodiment, determining whether the core number identifier of the first transmission frame is consistent with the core number identifier of the second node may be understood as: the core number identification code of the first transmission frame is A, the core number identification code of the second node is B, and when A is consistent with B, the step of determining whether the first transmission frame needs to be subjected to inter-core communication transmission is executed; when A is inconsistent with B, the second node firstly puts the data to be sent into a sending queue of a Queue Manager (QMSS), the data is sent to a cache address corresponding to a core number through the QMSS, then a core which needs to receive the data is informed through IPC inter-core interruption, and the core which receives the inter-core interruption takes the data from the received cache address.

To sum up, the method supports a universal communication framework of a redundant multiple architecture, and is compatible with a communication mode of a standard RapidIO protocol and inter-core communication based on an AMP framework; on the basis of a protocol, a specific transmission frame definition aiming at the middleware is added, wherein the transmission frame consists of 3 parts, namely a target ID (4 bytes), a RapidIO target address (8 bytes) and a sending data length (8 bytes), namely the first transmission frame comprises a target identification code (target ID) and a preset protocol target address (RapidIO target address), and the target identification code (target ID) comprises a preset protocol interface identification code (SRIO ID) and a CORE number identification code (CORE ID); the receiving end judges whether inter-core communication is needed, the processing flow that the core number is not 0 is added, and the diversity of inter-core communication is increased.

As shown in fig. 5, an embodiment of the present application further provides an information processing apparatus, where the apparatus includes:

an obtaining module 10, configured to obtain a first transmission frame to be transmitted; the first transmission frame comprises a destination identification code and a preset protocol destination address, wherein the destination identification code comprises a preset protocol interface identification code and a core number identification code;

a sending module 20, configured to send the first transmission frame according to a buffer status of a second node that receives the first transmission frame when a preset protocol interface identifier in the first transmission frame is consistent with a preset protocol interface identifier of a sending end;

and the processing module 30 is configured to send the first transmission frame to a target node corresponding to the core number identifier when a preset protocol interface identifier in the first transmission frame is inconsistent with a preset protocol interface identifier of the sending end.

Optionally, the sending module 20 includes:

a first determining unit, configured to determine, from the preset protocol destination address, a buffer flag bit state of a second node that receives the first transmission frame through a first transaction packet format;

and the sending unit is used for sending the first transmission frame according to the state of the zone bit of the buffer area.

Optionally, the sending unit includes:

a first determining subunit, configured to send the first transmission frame to a second node that receives the first transmission frame through a second transaction packet format if the status of the buffer zone flag bit is a receivable data status, and determine that the status of the buffer zone flag bit of the second node is a non-receivable data status;

and the sending subunit is configured to send the first transmission frame when the status of the buffer flag bit is circularly queried to the status of data receivable if the status of the buffer flag bit is in the status of data unreceivable.

Optionally, the apparatus further comprises:

the giving module is used for initializing the slave nodes connected with the first node and giving a preset protocol interface identification code to each slave node;

and the establishing module is used for respectively establishing cache zone bits for the first node and the slave node connected with the first node according to the preset protocol interface identification code and the type of the processor corresponding to the slave node.

Optionally, the apparatus further comprises:

and the second sending module is used for periodically sending heartbeat data to the main node connected with the sending end.

As shown in fig. 6, an embodiment of the present application further provides an information processing apparatus, including:

a first receiving module 40, configured to receive a first transmission frame sent by a first node; the first transmission frame comprises a destination identification code and a preset protocol destination address, wherein the destination identification code comprises a preset protocol interface identification code and a core number identification code;

a first determining module 50, configured to determine whether inter-core communication transmission needs to be performed on the first transmission frame according to the core number identifier in the first transmission frame.

Optionally, the first determining module 50 includes:

a second determining unit, configured to determine to perform inter-core communication transmission if the core number identification code of the first node is first preset information;

and the third determining unit is used for interrupting the second node and analyzing the first transmission frame by the inter-process communication IPC if the core number identification code of the first node is second preset information, and determining to perform inter-core communication transmission.

It should be noted that the first determining unit or the second determining unit performs inter-core communication transmission, and is configured to copy the first transmission frame to a target application layer in a direct memory access DMA manner, and clear a buffer status of the second node.

Optionally, the apparatus further comprises:

the second receiving module is used for periodically receiving heartbeat data sent by a first node connected with the sending end;

and the third receiving module is configured to determine that the first node is in a failure state if the received heartbeat data fails.

Optionally, the apparatus further comprises:

a second determining module, configured to determine whether a core number identifier of the first transmission frame is consistent with a core number identifier of the second node;

a second processing module, configured to, if yes, perform a step of determining whether inter-core communication transmission is required for the first transmission frame; and if the first transmission frame is inconsistent with the second transmission frame, interrupting the second node through IPC, and sending the first transmission frame to a cache region of a target node corresponding to the first transmission frame.

As shown in fig. 7, an embodiment of the present application further provides a network device, including: a transceiver 61, a memory 62, a processor 63 and a program stored on the memory 62 and executable on the processor 63,

the transceiver 61 is configured to receive a first transmission frame sent by a first node; the first transmission frame comprises a destination identification code and a preset protocol destination address, wherein the destination identification code comprises a preset protocol interface identification code and a core number identification code;

the processor 63, when executing the program, implements the following steps:

Wherein in fig. 7 the bus architecture may include any number of interconnected buses and bridges, with one or more processors, represented by processor 63, and various circuits, represented by memory 62, being linked together. The bus architecture may also link together various other circuits such as peripherals, voltage regulators, power management circuits, and the like, which are well known in the art, and therefore, will not be described any further herein. The bus interface provides an interface. The transceiver 61 may be a number of elements including a transmitter and a receiver providing a means for communicating with various other apparatus over a transmission medium. The processor 63 is responsible for managing the bus architecture and general processing, and the memory 62 may store data used by the processor 63 in performing operations.

It should be noted that the network device may be the second node described above.

Optionally, the processor 63 is further configured to:

An embodiment of the present application further provides a readable storage medium, where a program is stored, and when the program is executed by a processor, the program implements each process of the embodiment of the information processing method described above, and can achieve the same technical effect, and details are not described here to avoid repetition. The readable storage medium may be a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk.

Finally, it should also be noted that, in this document, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or terminal apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising a … …" does not exclude the presence of another identical element in a process, method, article, or apparatus that comprises the element.

While the foregoing is directed to the preferred embodiment of the present application, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the principles of the disclosure and, therefore, the scope of the disclosure is to be defined by the appended claims.

Claims

1. An information processing method performed by a first node, the method comprising:

2. The method of claim 1, wherein the sending the first transmission frame according to the buffer status of the second node receiving the first transmission frame comprises:

determining a buffer zone flag bit state of a second node receiving the first transmission frame from the preset protocol destination address through a first transaction packet format;

and sending the first transmission frame according to the state of the zone bit of the buffer area.

3. The method of claim 2, wherein sending the first transmission frame according to the buffer flag state comprises:

if the status of the zone bit of the cache zone is a data receivable status, sending the first transmission frame to a second node receiving the first transmission frame through a second transaction packet format, and determining that the status of the zone bit of the cache zone of the second node is a data unreceivable status;

4. The method of claim 1, wherein when the first node is a master node, the method further comprises:

5. The method of claim 1, wherein when the first node is a slave node, the method further comprises:

6. An information processing method performed by a second node, the method comprising:

7. The method of claim 6, wherein the determining whether the first transmission frame requires inter-core communication transmission comprises:

8. The method of claim 7, wherein the performing inter-core communication transmissions comprises:

9. The method of claim 6, wherein when the second node is a master node, the method further comprises:

10. The method of claim 6, wherein after receiving the first transmission frame sent by the first node when the second node is a slave node, the method further comprises:

11. An information processing apparatus characterized in that the apparatus comprises:

the device comprises an acquisition module, a transmission module and a transmission module, wherein the acquisition module is used for acquiring a first transmission frame to be transmitted; the first transmission frame comprises a destination identification code and a preset protocol destination address, wherein the destination identification code comprises a preset protocol interface identification code and a core number identification code;

12. An information processing apparatus, characterized in that the apparatus comprises:

13. A network device, comprising: a transceiver, a memory, a processor, and a program stored on the memory and executable on the processor, wherein,

the processor implements the following steps when executing the program:

14. A readable storage medium on which a program is stored, characterized in that the program realizes the steps in the information processing method according to any one of claims 1 to 5 when executed by a processor; alternatively, the first and second electrodes may be,

the program, when executed by a processor, implements the steps in the information processing method of any one of claims 6 to 10.